| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | /* include/asm-arm/arch-lh7a40x/irqs.h |
| 2 | * |
| 3 | * Copyright (C) 2004 Coastal Environmental Systems |
| 4 | * Copyright (C) 2004 Logic Product Development |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * version 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | /* It is to be seen whether or not we can build a kernel for more than |
| 13 | * one board. For the time being, these macros assume that we cannot. |
| 14 | * Thus, it is OK to ifdef machine/board specific IRQ assignments. |
| 15 | */ |
| 16 | |
| 17 | |
| 18 | #ifndef __ASM_ARCH_IRQS_H |
| 19 | #define __ASM_ARCH_IRQS_H |
| 20 | |
| 21 | #include <linux/config.h> |
| 22 | |
| 23 | #define FIQ_START 80 |
| 24 | |
| 25 | #if defined (CONFIG_ARCH_LH7A400) |
| 26 | |
| 27 | /* FIQs */ |
| 28 | |
| 29 | # define IRQ_GPIO0FIQ 0 /* GPIO External FIQ Interrupt on F0 */ |
| 30 | # define IRQ_BLINT 1 /* Battery Low */ |
| 31 | # define IRQ_WEINT 2 /* Watchdog Timer, WDT overflow */ |
| 32 | # define IRQ_MCINT 3 /* Media Change, MEDCHG pin rising */ |
| 33 | |
| 34 | /* IRQs */ |
| 35 | |
| 36 | # define IRQ_CSINT 4 /* Audio Codec (ACI) */ |
| 37 | # define IRQ_GPIO1INTR 5 /* GPIO External IRQ Interrupt on F1 */ |
| 38 | # define IRQ_GPIO2INTR 6 /* GPIO External IRQ Interrupt on F2 */ |
| 39 | # define IRQ_GPIO3INTR 7 /* GPIO External IRQ Interrupt on F3 */ |
| 40 | # define IRQ_T1UI 8 /* Timer 1 underflow */ |
| 41 | # define IRQ_T2UI 9 /* Timer 2 underflow */ |
| 42 | # define IRQ_RTCMI 10 |
| 43 | # define IRQ_TINTR 11 /* Clock State Controller 64 Hz tick (CSC) */ |
| 44 | # define IRQ_UART1INTR 12 |
| 45 | # define IRQ_UART2INTR 13 |
| 46 | # define IRQ_LCDINTR 14 |
| 47 | # define IRQ_SSIEOT 15 /* Synchronous Serial Interface (SSI) */ |
| 48 | # define IRQ_UART3INTR 16 |
| 49 | # define IRQ_SCIINTR 17 /* Smart Card Interface (SCI) */ |
| 50 | # define IRQ_AACINTR 18 /* Advanced Audio Codec (AAC) */ |
| 51 | # define IRQ_MMCINTR 19 /* Multimedia Card (MMC) */ |
| 52 | # define IRQ_USBINTR 20 |
| 53 | # define IRQ_DMAINTR 21 |
| 54 | # define IRQ_T3UI 22 /* Timer 3 underflow */ |
| 55 | # define IRQ_GPIO4INTR 23 /* GPIO External IRQ Interrupt on F4 */ |
| 56 | # define IRQ_GPIO5INTR 24 /* GPIO External IRQ Interrupt on F5 */ |
| 57 | # define IRQ_GPIO6INTR 25 /* GPIO External IRQ Interrupt on F6 */ |
| 58 | # define IRQ_GPIO7INTR 26 /* GPIO External IRQ Interrupt on F7 */ |
| 59 | # define IRQ_BMIINTR 27 /* Battery Monitor Interface (BMI) */ |
| 60 | |
| 61 | # define NR_IRQ_CPU 28 /* IRQs directly recognized by CPU */ |
| 62 | |
| 63 | /* Given IRQ, return GPIO interrupt number 0-7 */ |
| 64 | # define IRQ_TO_GPIO(i) ((i) \ |
| 65 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ |
| 66 | - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0)) |
| 67 | |
| 68 | #endif |
| 69 | |
| 70 | #if defined (CONFIG_ARCH_LH7A404) |
| 71 | |
| 72 | # define IRQ_BROWN 0 /* Brownout */ |
| 73 | # define IRQ_WDTINTR 1 /* Watchdog Timer */ |
| 74 | # define IRQ_COMMRX 2 /* ARM Comm Rx for Debug */ |
| 75 | # define IRQ_COMMTX 3 /* ARM Comm Tx for Debug */ |
| 76 | # define IRQ_T1UI 4 /* Timer 1 underflow */ |
| 77 | # define IRQ_T2UI 5 /* Timer 2 underflow */ |
| 78 | # define IRQ_CSINT 6 /* Codec Interrupt (shared by AAC on 404) */ |
| 79 | # define IRQ_DMAM2P0 7 /* -- DMA Memory to Peripheral */ |
| 80 | # define IRQ_DMAM2P1 8 |
| 81 | # define IRQ_DMAM2P2 9 |
| 82 | # define IRQ_DMAM2P3 10 |
| 83 | # define IRQ_DMAM2P4 11 |
| 84 | # define IRQ_DMAM2P5 12 |
| 85 | # define IRQ_DMAM2P6 13 |
| 86 | # define IRQ_DMAM2P7 14 |
| 87 | # define IRQ_DMAM2P8 15 |
| 88 | # define IRQ_DMAM2P9 16 |
| 89 | # define IRQ_DMAM2M0 17 /* -- DMA Memory to Memory */ |
| 90 | # define IRQ_DMAM2M1 18 |
| 91 | # define IRQ_GPIO0INTR 19 /* -- GPIOF Interrupt */ |
| 92 | # define IRQ_GPIO1INTR 20 |
| 93 | # define IRQ_GPIO2INTR 21 |
| 94 | # define IRQ_GPIO3INTR 22 |
| 95 | # define IRQ_SOFT_V1_23 23 /* -- Unassigned */ |
| 96 | # define IRQ_SOFT_V1_24 24 |
| 97 | # define IRQ_SOFT_V1_25 25 |
| 98 | # define IRQ_SOFT_V1_26 26 |
| 99 | # define IRQ_SOFT_V1_27 27 |
| 100 | # define IRQ_SOFT_V1_28 28 |
| 101 | # define IRQ_SOFT_V1_29 29 |
| 102 | # define IRQ_SOFT_V1_30 30 |
| 103 | # define IRQ_SOFT_V1_31 31 |
| 104 | |
| 105 | # define IRQ_BLINT 32 /* Battery Low */ |
| 106 | # define IRQ_BMIINTR 33 /* Battery Monitor */ |
| 107 | # define IRQ_MCINTR 34 /* Media Change */ |
| 108 | # define IRQ_TINTR 35 /* 64Hz Tick */ |
| 109 | # define IRQ_WEINT 36 /* Watchdog Expired */ |
| 110 | # define IRQ_RTCMI 37 /* Real-time Clock Match */ |
| 111 | # define IRQ_UART1INTR 38 /* UART1 Interrupt (including error) */ |
| 112 | # define IRQ_UART1ERR 39 /* UART1 Error */ |
| 113 | # define IRQ_UART2INTR 40 /* UART2 Interrupt (including error) */ |
| 114 | # define IRQ_UART2ERR 41 /* UART2 Error */ |
| 115 | # define IRQ_UART3INTR 42 /* UART3 Interrupt (including error) */ |
| 116 | # define IRQ_UART3ERR 43 /* UART3 Error */ |
| 117 | # define IRQ_SCIINTR 44 /* Smart Card */ |
| 118 | # define IRQ_TSCINTR 45 /* Touchscreen */ |
| 119 | # define IRQ_KMIINTR 46 /* Keyboard/Mouse (PS/2) */ |
| 120 | # define IRQ_GPIO4INTR 47 /* -- GPIOF Interrupt */ |
| 121 | # define IRQ_GPIO5INTR 48 |
| 122 | # define IRQ_GPIO6INTR 49 |
| 123 | # define IRQ_GPIO7INTR 50 |
| 124 | # define IRQ_T3UI 51 /* Timer 3 underflow */ |
| 125 | # define IRQ_LCDINTR 52 /* LCD Controller */ |
| 126 | # define IRQ_SSPINTR 53 /* Synchronous Serial Port */ |
| 127 | # define IRQ_SDINTR 54 /* Secure Digital Port (MMC) */ |
| 128 | # define IRQ_USBINTR 55 /* USB Device Port */ |
| 129 | # define IRQ_USHINTR 56 /* USB Host Port */ |
| 130 | # define IRQ_SOFT_V2_25 57 /* -- Unassigned */ |
| 131 | # define IRQ_SOFT_V2_26 58 |
| 132 | # define IRQ_SOFT_V2_27 59 |
| 133 | # define IRQ_SOFT_V2_28 60 |
| 134 | # define IRQ_SOFT_V2_29 61 |
| 135 | # define IRQ_SOFT_V2_30 62 |
| 136 | # define IRQ_SOFT_V2_31 63 |
| 137 | |
| 138 | # define NR_IRQ_CPU 64 /* IRQs directly recognized by CPU */ |
| 139 | |
| 140 | /* Given IRQ, return GPIO interrupt number 0-7 */ |
| 141 | # define IRQ_TO_GPIO(i) ((i) \ |
| 142 | - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\ |
| 143 | - IRQ_GPIO0INTR) |
| 144 | |
| 145 | /* Vector Address constants */ |
| 146 | # define VA_VECTORED 0x100 /* Set for vectored interrupt */ |
| 147 | # define VA_VIC1DEFAULT 0x200 /* Set as default VECTADDR for VIC1 */ |
| 148 | # define VA_VIC2DEFAULT 0x400 /* Set as default VECTADDR for VIC2 */ |
| 149 | |
| 150 | #endif |
| 151 | |
| 152 | /* IRQ aliases */ |
| 153 | |
| 154 | #if !defined (IRQ_GPIO0INTR) |
| 155 | # define IRQ_GPIO0INTR IRQ_GPIO0FIQ |
| 156 | #endif |
| 157 | #define IRQ_TICK IRQ_TINTR |
| 158 | #define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ |
| 159 | #define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ |
| 160 | |
| 161 | #ifdef CONFIG_MACH_KEV7A400 |
| 162 | # define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ |
| 163 | # define IRQ_CPLD IRQ_GPIO1INTR /* CPLD cascade */ |
| 164 | # define IRQ_PCC1_CD IRQ_GPIO_F2 /* PCCard 1 card detect */ |
| 165 | # define IRQ_PCC2_CD IRQ_GPIO_F3 /* PCCard 2 card detect */ |
| 166 | #endif |
| 167 | |
| 168 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) |
| 169 | # define IRQ_CPLD_V28 IRQ_GPIO7INTR /* CPLD cascade through GPIO_PF7 */ |
| 170 | # define IRQ_CPLD_V34 IRQ_GPIO3INTR /* CPLD cascade through GPIO_PF3 */ |
| 171 | #endif |
| 172 | |
| 173 | /* System specific IRQs */ |
| 174 | |
| 175 | #define IRQ_BOARD_START NR_IRQ_CPU |
| 176 | |
| 177 | #ifdef CONFIG_MACH_KEV7A400 |
| 178 | # define IRQ_KEV7A400_CPLD IRQ_BOARD_START |
| 179 | # define NR_IRQ_BOARD 5 |
| 180 | # define IRQ_KEV7A400_MMC_CD IRQ_KEV7A400_CPLD + 0 /* MMC Card Detect */ |
| 181 | # define IRQ_KEV7A400_RI2 IRQ_KEV7A400_CPLD + 1 /* Ring Indicator 2 */ |
| 182 | # define IRQ_KEV7A400_IDE_CF IRQ_KEV7A400_CPLD + 2 /* Compact Flash (?) */ |
| 183 | # define IRQ_KEV7A400_ETH_INT IRQ_KEV7A400_CPLD + 3 /* Ethernet chip */ |
| 184 | # define IRQ_KEV7A400_INT IRQ_KEV7A400_CPLD + 4 |
| 185 | #endif |
| 186 | |
| 187 | #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) |
| 188 | # define IRQ_LPD7A40X_CPLD IRQ_BOARD_START |
| 189 | # define NR_IRQ_BOARD 2 |
| 190 | # define IRQ_LPD7A40X_ETH_INT IRQ_LPD7A40X_CPLD + 0 /* Ethernet chip */ |
| 191 | # define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ |
| 192 | #endif |
| 193 | |
| 194 | #define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) |
| 195 | |
| 196 | #endif |