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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* dma.h: FRV DMA controller management
2 *
3 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_DMA_H
13#define _ASM_DMA_H
14
15//#define DMA_DEBUG 1
16
17#include <linux/config.h>
18#include <linux/interrupt.h>
19
20#undef MAX_DMA_CHANNELS /* don't use kernel/dma.c */
21
22/* under 2.4 this is actually needed by the new bootmem allocator */
23#define MAX_DMA_ADDRESS PAGE_OFFSET
24
25/*
26 * FRV DMA controller management
27 */
28struct pt_regs;
29
30typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data,
31 struct pt_regs *regs);
32
33extern void frv_dma_init(void);
34
35extern int frv_dma_open(const char *devname,
36 unsigned long dmamask,
37 int dmacap,
38 dma_irq_handler_t handler,
39 unsigned long irq_flags,
40 void *data);
41
42/* channels required */
43#define FRV_DMA_MASK_ANY ULONG_MAX /* any channel */
44
45/* capabilities required */
46#define FRV_DMA_CAP_DREQ 0x01 /* DMA request pin */
47#define FRV_DMA_CAP_DACK 0x02 /* DMA ACK pin */
48#define FRV_DMA_CAP_DONE 0x04 /* DMA done pin */
49
50extern void frv_dma_close(int dma);
51
52extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
53
54extern void frv_dma_start(int dma,
55 unsigned long sba, unsigned long dba,
56 unsigned long pix, unsigned long six, unsigned long bcl);
57
58extern void frv_dma_restart_circular(int dma, unsigned long six);
59
60extern void frv_dma_stop(int dma);
61
62extern int is_frv_dma_interrupting(int dma);
63
64extern void frv_dma_dump(int dma);
65
66extern void frv_dma_status_clear(int dma);
67
68#define FRV_DMA_NCHANS 8
69#define FRV_DMA_4CHANS 4
70#define FRV_DMA_8CHANS 8
71
72#define DMAC_CCFRx 0x00 /* channel configuration reg */
73#define DMAC_CCFRx_CM_SHIFT 16
74#define DMAC_CCFRx_CM_DA 0x00000000
75#define DMAC_CCFRx_CM_SCA 0x00010000
76#define DMAC_CCFRx_CM_DCA 0x00020000
77#define DMAC_CCFRx_CM_2D 0x00030000
78#define DMAC_CCFRx_ATS_SHIFT 8
79#define DMAC_CCFRx_RS_INTERN 0x00000000
80#define DMAC_CCFRx_RS_EXTERN 0x00000001
81#define DMAC_CCFRx_RS_SHIFT 0
82
83#define DMAC_CSTRx 0x08 /* channel status reg */
84#define DMAC_CSTRx_FS 0x0000003f
85#define DMAC_CSTRx_NE 0x00000100
86#define DMAC_CSTRx_FED 0x00000200
87#define DMAC_CSTRx_WER 0x00000800
88#define DMAC_CSTRx_RER 0x00001000
89#define DMAC_CSTRx_CE 0x00002000
90#define DMAC_CSTRx_INT 0x00800000
91#define DMAC_CSTRx_BUSY 0x80000000
92
93#define DMAC_CCTRx 0x10 /* channel control reg */
94#define DMAC_CCTRx_DSIZ_1 0x00000000
95#define DMAC_CCTRx_DSIZ_2 0x00000001
96#define DMAC_CCTRx_DSIZ_4 0x00000002
97#define DMAC_CCTRx_DSIZ_32 0x00000005
98#define DMAC_CCTRx_DAU_HOLD 0x00000000
99#define DMAC_CCTRx_DAU_INC 0x00000010
100#define DMAC_CCTRx_DAU_DEC 0x00000020
101#define DMAC_CCTRx_SSIZ_1 0x00000000
102#define DMAC_CCTRx_SSIZ_2 0x00000100
103#define DMAC_CCTRx_SSIZ_4 0x00000200
104#define DMAC_CCTRx_SSIZ_32 0x00000500
105#define DMAC_CCTRx_SAU_HOLD 0x00000000
106#define DMAC_CCTRx_SAU_INC 0x00001000
107#define DMAC_CCTRx_SAU_DEC 0x00002000
108#define DMAC_CCTRx_FC 0x08000000
109#define DMAC_CCTRx_ICE 0x10000000
110#define DMAC_CCTRx_IE 0x40000000
111#define DMAC_CCTRx_ACT 0x80000000
112
113#define DMAC_SBAx 0x18 /* source base address reg */
114#define DMAC_DBAx 0x20 /* data base address reg */
115#define DMAC_PIXx 0x28 /* primary index reg */
116#define DMAC_SIXx 0x30 /* secondary index reg */
117#define DMAC_BCLx 0x38 /* byte count limit reg */
118#define DMAC_APRx 0x40 /* alternate pointer reg */
119
120/*
121 * required for PCI + MODULES
122 */
123#ifdef CONFIG_PCI
124extern int isa_dma_bridge_buggy;
125#else
126#define isa_dma_bridge_buggy (0)
127#endif
128
129#endif /* _ASM_DMA_H */