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Russell Kingc41b16f2011-01-19 15:32:15 +00001/*
2 * Support for Versatile FPGA-based IRQ controllers
3 */
Linus Walleij3a6ca8c2012-10-27 01:05:06 +02004#include <linux/bitops.h>
Russell Kingc41b16f2011-01-19 15:32:15 +00005#include <linux/irq.h>
6#include <linux/io.h>
Linus Walleij2389d502012-10-31 22:04:31 +01007#include <linux/irqchip/versatile-fpga.h>
Linus Walleij3108e6a2012-04-28 14:33:47 +01008#include <linux/irqdomain.h>
9#include <linux/module.h>
Linus Walleij9bc15032012-09-06 09:07:57 +010010#include <linux/of.h>
11#include <linux/of_address.h>
Linus Walleijbdd272c2013-10-04 15:15:35 +020012#include <linux/of_irq.h>
Russell Kingc41b16f2011-01-19 15:32:15 +000013
Linus Walleij3108e6a2012-04-28 14:33:47 +010014#include <asm/exception.h>
Russell Kingc41b16f2011-01-19 15:32:15 +000015#include <asm/mach/irq.h>
Russell Kingc41b16f2011-01-19 15:32:15 +000016
Rob Herring2920bc92014-05-29 16:39:43 -050017#include "irqchip.h"
18
Russell Kingc41b16f2011-01-19 15:32:15 +000019#define IRQ_STATUS 0x00
20#define IRQ_RAW_STATUS 0x04
21#define IRQ_ENABLE_SET 0x08
22#define IRQ_ENABLE_CLEAR 0x0c
Linus Walleij9bc15032012-09-06 09:07:57 +010023#define INT_SOFT_SET 0x10
24#define INT_SOFT_CLEAR 0x14
25#define FIQ_STATUS 0x20
26#define FIQ_RAW_STATUS 0x24
27#define FIQ_ENABLE 0x28
28#define FIQ_ENABLE_SET 0x28
29#define FIQ_ENABLE_CLEAR 0x2C
Russell Kingc41b16f2011-01-19 15:32:15 +000030
Rob Herring59318462014-03-03 09:15:18 -060031#define PIC_ENABLES 0x20 /* set interrupt pass through bits */
32
Linus Walleij3108e6a2012-04-28 14:33:47 +010033/**
34 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
35 * @base: memory offset in virtual memory
Linus Walleij3108e6a2012-04-28 14:33:47 +010036 * @chip: chip container for this instance
37 * @domain: IRQ domain for this instance
38 * @valid: mask for valid IRQs on this controller
39 * @used_irqs: number of active IRQs on this controller
40 */
41struct fpga_irq_data {
42 void __iomem *base;
Linus Walleij3108e6a2012-04-28 14:33:47 +010043 struct irq_chip chip;
44 u32 valid;
45 struct irq_domain *domain;
46 u8 used_irqs;
47};
48
49/* we cannot allocate memory when the controllers are initially registered */
Linus Walleij2389d502012-10-31 22:04:31 +010050static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
Linus Walleij3108e6a2012-04-28 14:33:47 +010051static int fpga_irq_id;
52
Russell Kingc41b16f2011-01-19 15:32:15 +000053static void fpga_irq_mask(struct irq_data *d)
54{
55 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
Linus Walleij3108e6a2012-04-28 14:33:47 +010056 u32 mask = 1 << d->hwirq;
Russell Kingc41b16f2011-01-19 15:32:15 +000057
58 writel(mask, f->base + IRQ_ENABLE_CLEAR);
59}
60
61static void fpga_irq_unmask(struct irq_data *d)
62{
63 struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
Linus Walleij3108e6a2012-04-28 14:33:47 +010064 u32 mask = 1 << d->hwirq;
Russell Kingc41b16f2011-01-19 15:32:15 +000065
66 writel(mask, f->base + IRQ_ENABLE_SET);
67}
68
69static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
70{
Thomas Gleixner6845664a2011-03-24 13:25:22 +010071 struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
Russell Kingc41b16f2011-01-19 15:32:15 +000072 u32 status = readl(f->base + IRQ_STATUS);
73
74 if (status == 0) {
75 do_bad_IRQ(irq, desc);
76 return;
77 }
78
79 do {
80 irq = ffs(status) - 1;
81 status &= ~(1 << irq);
Linus Walleij3108e6a2012-04-28 14:33:47 +010082 generic_handle_irq(irq_find_mapping(f->domain, irq));
Russell Kingc41b16f2011-01-19 15:32:15 +000083 } while (status);
84}
85
Linus Walleij3108e6a2012-04-28 14:33:47 +010086/*
87 * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
88 * if we've handled at least one interrupt. This does a single read of the
89 * status register and handles all interrupts in order from LSB first.
90 */
91static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
Russell Kingc41b16f2011-01-19 15:32:15 +000092{
Linus Walleij3108e6a2012-04-28 14:33:47 +010093 int handled = 0;
94 int irq;
95 u32 status;
Russell Kingc41b16f2011-01-19 15:32:15 +000096
Linus Walleij3108e6a2012-04-28 14:33:47 +010097 while ((status = readl(f->base + IRQ_STATUS))) {
98 irq = ffs(status) - 1;
Marc Zyngier84bc7392014-08-26 11:03:29 +010099 handle_domain_irq(f->domain, irq, regs);
Linus Walleij3108e6a2012-04-28 14:33:47 +0100100 handled = 1;
101 }
102
103 return handled;
104}
105
106/*
107 * Keep iterating over all registered FPGA IRQ controllers until there are
108 * no pending interrupts.
109 */
110asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
111{
112 int i, handled;
113
114 do {
115 for (i = 0, handled = 0; i < fpga_irq_id; ++i)
116 handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
117 } while (handled);
118}
119
120static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
121 irq_hw_number_t hwirq)
122{
123 struct fpga_irq_data *f = d->host_data;
124
125 /* Skip invalid IRQs, only register handlers for the real ones */
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200126 if (!(f->valid & BIT(hwirq)))
Grant Likelyd94ea3f2013-06-06 14:11:38 +0100127 return -EPERM;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100128 irq_set_chip_data(irq, f);
129 irq_set_chip_and_handler(irq, &f->chip,
130 handle_level_irq);
131 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
Linus Walleij3108e6a2012-04-28 14:33:47 +0100132 return 0;
133}
134
135static struct irq_domain_ops fpga_irqdomain_ops = {
136 .map = fpga_irqdomain_map,
137 .xlate = irq_domain_xlate_onetwocell,
138};
139
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200140void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
141 int parent_irq, u32 valid, struct device_node *node)
142{
Linus Walleij3108e6a2012-04-28 14:33:47 +0100143 struct fpga_irq_data *f;
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200144 int i;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100145
146 if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
Paul Bollee6423f82013-03-25 10:34:46 +0100147 pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200148 return;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100149 }
Linus Walleij3108e6a2012-04-28 14:33:47 +0100150 f = &fpga_irq_devices[fpga_irq_id];
151 f->base = base;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100152 f->chip.name = name;
Russell Kingc41b16f2011-01-19 15:32:15 +0000153 f->chip.irq_ack = fpga_irq_mask;
154 f->chip.irq_mask = fpga_irq_mask;
155 f->chip.irq_unmask = fpga_irq_unmask;
Linus Walleij3108e6a2012-04-28 14:33:47 +0100156 f->valid = valid;
Russell Kingc41b16f2011-01-19 15:32:15 +0000157
158 if (parent_irq != -1) {
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100159 irq_set_handler_data(parent_irq, f);
160 irq_set_chained_handler(parent_irq, fpga_irq_handle);
Russell Kingc41b16f2011-01-19 15:32:15 +0000161 }
162
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200163 /* This will also allocate irq descriptors */
164 f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
Linus Walleij3108e6a2012-04-28 14:33:47 +0100165 &fpga_irqdomain_ops, f);
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200166
167 /* This will allocate all valid descriptors in the linear case */
168 for (i = 0; i < fls(valid); i++)
169 if (valid & BIT(i)) {
170 if (!irq_start)
171 irq_create_mapping(f->domain, i);
172 f->used_irqs++;
173 }
174
Linus Walleijbdd272c2013-10-04 15:15:35 +0200175 pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
Linus Walleij3108e6a2012-04-28 14:33:47 +0100176 fpga_irq_id, name, base, f->used_irqs);
Linus Walleijbdd272c2013-10-04 15:15:35 +0200177 if (parent_irq != -1)
178 pr_cont(", parent IRQ: %d\n", parent_irq);
179 else
180 pr_cont("\n");
Linus Walleij3a6ca8c2012-10-27 01:05:06 +0200181
182 fpga_irq_id++;
Russell Kingc41b16f2011-01-19 15:32:15 +0000183}
Linus Walleij9bc15032012-09-06 09:07:57 +0100184
185#ifdef CONFIG_OF
186int __init fpga_irq_of_init(struct device_node *node,
187 struct device_node *parent)
188{
Linus Walleij9bc15032012-09-06 09:07:57 +0100189 void __iomem *base;
190 u32 clear_mask;
191 u32 valid_mask;
Linus Walleijbdd272c2013-10-04 15:15:35 +0200192 int parent_irq;
Linus Walleij9bc15032012-09-06 09:07:57 +0100193
194 if (WARN_ON(!node))
195 return -ENODEV;
196
197 base = of_iomap(node, 0);
198 WARN(!base, "unable to map fpga irq registers\n");
199
200 if (of_property_read_u32(node, "clear-mask", &clear_mask))
201 clear_mask = 0;
202
203 if (of_property_read_u32(node, "valid-mask", &valid_mask))
204 valid_mask = 0;
205
Linus Walleijbdd272c2013-10-04 15:15:35 +0200206 /* Some chips are cascaded from a parent IRQ */
207 parent_irq = irq_of_parse_and_map(node, 0);
Rob Herring2920bc92014-05-29 16:39:43 -0500208 if (!parent_irq) {
209 set_handle_irq(fpga_handle_irq);
Linus Walleijbdd272c2013-10-04 15:15:35 +0200210 parent_irq = -1;
Rob Herring2920bc92014-05-29 16:39:43 -0500211 }
Linus Walleijbdd272c2013-10-04 15:15:35 +0200212
213 fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
Linus Walleij9bc15032012-09-06 09:07:57 +0100214
215 writel(clear_mask, base + IRQ_ENABLE_CLEAR);
216 writel(clear_mask, base + FIQ_ENABLE_CLEAR);
217
Rob Herring59318462014-03-03 09:15:18 -0600218 /*
219 * On Versatile AB/PB, some secondary interrupts have a direct
220 * pass-thru to the primary controller for IRQs 20 and 22-31 which need
221 * to be enabled. See section 3.10 of the Versatile AB user guide.
222 */
223 if (of_device_is_compatible(node, "arm,versatile-sic"))
224 writel(0xffd00000, base + PIC_ENABLES);
225
Linus Walleij9bc15032012-09-06 09:07:57 +0100226 return 0;
227}
Rob Herring2920bc92014-05-29 16:39:43 -0500228IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
Rob Herring59318462014-03-03 09:15:18 -0600229IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
Linus Walleij9bc15032012-09-06 09:07:57 +0100230#endif