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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22
23
24 Linux kernel changelog:
25 -----------------------
26
27 LK1.1.1 (jgarzik): Port to 2.4 kernel
28
29 LK1.1.2 (jgarzik):
30 * Merge in becker version 1.05
31
32 LK1.1.3 (jgarzik):
33 * Various cleanups
34 * Update yellowfin_timer to correctly calculate duplex.
35 (suggested by Manfred Spraul)
36
37 LK1.1.4 (val@nmt.edu):
38 * Fix three endian-ness bugs
39 * Support dual function SYM53C885E ethernet chip
40
41 LK1.1.5 (val@nmt.edu):
42 * Fix forced full-duplex bug I introduced
43
44 LK1.1.6 (val@nmt.edu):
45 * Only print warning on truly "oversized" packets
46 * Fix theoretical bug on gigabit cards - return to 1.1.3 behavior
47
48*/
49
50#define DRV_NAME "yellowfin"
51#define DRV_VERSION "1.05+LK1.1.6"
52#define DRV_RELDATE "Feb 11, 2002"
53
54#define PFX DRV_NAME ": "
55
56/* The user-configurable values.
57 These may be modified when a driver module is loaded.*/
58
59static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
60/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
61static int max_interrupt_work = 20;
62static int mtu;
63#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
64/* System-wide count of bogus-rx frames. */
65static int bogus_rx;
66static int dma_ctrl = 0x004A0263; /* Constrained by errata */
67static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
68#elif defined(YF_NEW) /* A future perfect board :->. */
69static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
70static int fifo_cfg = 0x0028;
71#else
Arjan van de Venf71e1302006-03-03 21:33:57 -050072static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
73static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070074#endif
75
76/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
77 Setting to > 1514 effectively disables this feature. */
78static int rx_copybreak;
79
80/* Used to pass the media type, etc.
81 No media types are currently defined. These exist for driver
82 interoperability.
83*/
84#define MAX_UNITS 8 /* More are supported, limit only on options */
85static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
86static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
87
88/* Do ugly workaround for GX server chipset errata. */
89static int gx_fix;
90
91/* Operational parameters that are set at compile time. */
92
93/* Keep the ring sizes a power of two for efficiency.
94 Making the Tx ring too long decreases the effectiveness of channel
95 bonding and packet priority.
96 There are no ill effects from too-large receive rings. */
97#define TX_RING_SIZE 16
98#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
99#define RX_RING_SIZE 64
100#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
101#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
102#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
103
104/* Operational parameters that usually are not changed. */
105/* Time in jiffies before concluding the transmitter is hung. */
106#define TX_TIMEOUT (2*HZ)
107#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
108
109#define yellowfin_debug debug
110
111#include <linux/module.h>
112#include <linux/kernel.h>
113#include <linux/string.h>
114#include <linux/timer.h>
115#include <linux/errno.h>
116#include <linux/ioport.h>
117#include <linux/slab.h>
118#include <linux/interrupt.h>
119#include <linux/pci.h>
120#include <linux/init.h>
121#include <linux/mii.h>
122#include <linux/netdevice.h>
123#include <linux/etherdevice.h>
124#include <linux/skbuff.h>
125#include <linux/ethtool.h>
126#include <linux/crc32.h>
127#include <linux/bitops.h>
128#include <asm/uaccess.h>
129#include <asm/processor.h> /* Processor type for cache alignment. */
130#include <asm/unaligned.h>
131#include <asm/io.h>
132
133/* These identify the driver base version and may not be removed. */
134static char version[] __devinitdata =
135KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
136KERN_INFO " http://www.scyld.com/network/yellowfin.html\n"
137KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
138
139MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
140MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
141MODULE_LICENSE("GPL");
142
143module_param(max_interrupt_work, int, 0);
144module_param(mtu, int, 0);
145module_param(debug, int, 0);
146module_param(rx_copybreak, int, 0);
147module_param_array(options, int, NULL, 0);
148module_param_array(full_duplex, int, NULL, 0);
149module_param(gx_fix, int, 0);
150MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
151MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
152MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
153MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
154MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
155MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
156MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
157
158/*
159 Theory of Operation
160
161I. Board Compatibility
162
163This device driver is designed for the Packet Engines "Yellowfin" Gigabit
164Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
165Symbios 53C885E dual function chip.
166
167II. Board-specific settings
168
169PCI bus devices are configured by the system at boot time, so no jumpers
170need to be set on the board. The system BIOS preferably should assign the
171PCI INTA signal to an otherwise unused system IRQ line.
172Note: Kernel versions earlier than 1.3.73 do not support shared PCI
173interrupt lines.
174
175III. Driver operation
176
177IIIa. Ring buffers
178
179The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
180This is a descriptor list scheme similar to that used by the EEPro100 and
181Tulip. This driver uses two statically allocated fixed-size descriptor lists
182formed into rings by a branch from the final descriptor to the beginning of
183the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
184
185The driver allocates full frame size skbuffs for the Rx ring buffers at
186open() time and passes the skb->data field to the Yellowfin as receive data
187buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
188a fresh skbuff is allocated and the frame is copied to the new skbuff.
189When the incoming frame is larger, the skbuff is passed directly up the
190protocol stack and replaced by a newly allocated skbuff.
191
192The RX_COPYBREAK value is chosen to trade-off the memory wasted by
193using a full-sized skbuff for small frames vs. the copying costs of larger
194frames. For small frames the copying cost is negligible (esp. considering
195that we are pre-loading the cache with immediately useful header
196information). For large frames the copying cost is non-trivial, and the
197larger copy might flush the cache of useful data.
198
199IIIC. Synchronization
200
201The driver runs as two independent, single-threaded flows of control. One
202is the send-packet routine, which enforces single-threaded use by the
203dev->tbusy flag. The other thread is the interrupt handler, which is single
204threaded by the hardware and other software.
205
206The send packet thread has partial control over the Tx ring and 'dev->tbusy'
207flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
208queue slot is empty, it clears the tbusy flag when finished otherwise it sets
209the 'yp->tx_full' flag.
210
211The interrupt handler has exclusive control over the Rx ring and records stats
212from the Tx ring. After reaping the stats, it marks the Tx queue entry as
213empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
214clears both the tx_full and tbusy flags.
215
216IV. Notes
217
218Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
219Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
220and an AlphaStation to verifty the Alpha port!
221
222IVb. References
223
224Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
225Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
226 Data Manual v3.0
227http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
228http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
229
230IVc. Errata
231
232See Packet Engines confidential appendix (prototype chips only).
233*/
234
235
236
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237enum capability_flags {
238 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
239 HasMACAddrBug=32, /* Only on early revs. */
240 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
241};
242/* The PCI I/O space extent. */
243#define YELLOWFIN_SIZE 0x100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244
245struct pci_id_info {
246 const char *name;
247 struct match_info {
248 int pci, pci_mask, subsystem, subsystem_mask;
249 int revision, revision_mask; /* Only 8 bits. */
250 } id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 int io_size; /* Needed for I/O region check or ioremap(). */
252 int drv_flags; /* Driver use, intended as capability flags. */
253};
254
Arjan van de Venf71e1302006-03-03 21:33:57 -0500255static const struct pci_id_info pci_id_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
Jeff Garzik1f1bd5f2006-06-26 23:47:50 -0400257 YELLOWFIN_SIZE,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
259 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
Jeff Garzik1f1bd5f2006-06-26 23:47:50 -0400260 YELLOWFIN_SIZE, HasMII | DontUseEeprom },
261 { }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262};
263
Jeff Garzik1f1bd5f2006-06-26 23:47:50 -0400264static const struct pci_device_id yellowfin_pci_tbl[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
266 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
Jeff Garzik1f1bd5f2006-06-26 23:47:50 -0400267 { }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268};
269MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
270
271
272/* Offsets to the Yellowfin registers. Various sizes and alignments. */
273enum yellowfin_offsets {
274 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
275 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
276 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
277 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
278 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
279 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
280 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
281 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
282 MII_Status=0xAE,
283 RxDepth=0xB8, FlowCtrl=0xBC,
284 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
285 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
286 EEFeature=0xF5,
287};
288
289/* The Yellowfin Rx and Tx buffer descriptors.
290 Elements are written as 32 bit for endian portability. */
291struct yellowfin_desc {
292 u32 dbdma_cmd;
293 u32 addr;
294 u32 branch_addr;
295 u32 result_status;
296};
297
298struct tx_status_words {
299#ifdef __BIG_ENDIAN
300 u16 tx_errs;
301 u16 tx_cnt;
302 u16 paused;
303 u16 total_tx_cnt;
304#else /* Little endian chips. */
305 u16 tx_cnt;
306 u16 tx_errs;
307 u16 total_tx_cnt;
308 u16 paused;
309#endif /* __BIG_ENDIAN */
310};
311
312/* Bits in yellowfin_desc.cmd */
313enum desc_cmd_bits {
314 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
315 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
316 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
317 BRANCH_IFTRUE=0x040000,
318};
319
320/* Bits in yellowfin_desc.status */
321enum desc_status_bits { RX_EOP=0x0040, };
322
323/* Bits in the interrupt status/mask registers. */
324enum intr_status_bits {
325 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
326 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
327 IntrEarlyRx=0x100, IntrWakeup=0x200, };
328
329#define PRIV_ALIGN 31 /* Required alignment mask */
330#define MII_CNT 4
331struct yellowfin_private {
332 /* Descriptor rings first for alignment.
333 Tx requires a second descriptor for status. */
334 struct yellowfin_desc *rx_ring;
335 struct yellowfin_desc *tx_ring;
336 struct sk_buff* rx_skbuff[RX_RING_SIZE];
337 struct sk_buff* tx_skbuff[TX_RING_SIZE];
338 dma_addr_t rx_ring_dma;
339 dma_addr_t tx_ring_dma;
340
341 struct tx_status_words *tx_status;
342 dma_addr_t tx_status_dma;
343
344 struct timer_list timer; /* Media selection timer. */
345 struct net_device_stats stats;
346 /* Frequently used and paired value: keep adjacent for cache effect. */
347 int chip_id, drv_flags;
348 struct pci_dev *pci_dev;
349 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
350 unsigned int rx_buf_sz; /* Based on MTU+slack. */
351 struct tx_status_words *tx_tail_desc;
352 unsigned int cur_tx, dirty_tx;
353 int tx_threshold;
354 unsigned int tx_full:1; /* The Tx queue is full. */
355 unsigned int full_duplex:1; /* Full-duplex operation requested. */
356 unsigned int duplex_lock:1;
357 unsigned int medialock:1; /* Do not sense media. */
358 unsigned int default_port:4; /* Last dev->if_port value. */
359 /* MII transceiver section. */
360 int mii_cnt; /* MII device addresses. */
361 u16 advertising; /* NWay media advertisement */
362 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
363 spinlock_t lock;
364 void __iomem *base;
365};
366
367static int read_eeprom(void __iomem *ioaddr, int location);
368static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
369static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
370static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
371static int yellowfin_open(struct net_device *dev);
372static void yellowfin_timer(unsigned long data);
373static void yellowfin_tx_timeout(struct net_device *dev);
374static void yellowfin_init_ring(struct net_device *dev);
375static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
376static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
377static int yellowfin_rx(struct net_device *dev);
378static void yellowfin_error(struct net_device *dev, int intr_status);
379static int yellowfin_close(struct net_device *dev);
380static struct net_device_stats *yellowfin_get_stats(struct net_device *dev);
381static void set_rx_mode(struct net_device *dev);
382static struct ethtool_ops ethtool_ops;
383
384
385static int __devinit yellowfin_init_one(struct pci_dev *pdev,
386 const struct pci_device_id *ent)
387{
388 struct net_device *dev;
389 struct yellowfin_private *np;
390 int irq;
391 int chip_idx = ent->driver_data;
392 static int find_cnt;
393 void __iomem *ioaddr;
394 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
395 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
396 void *ring_space;
397 dma_addr_t ring_dma;
398#ifdef USE_IO_OPS
399 int bar = 0;
400#else
401 int bar = 1;
402#endif
403
404/* when built into the kernel, we only print version if device is found */
405#ifndef MODULE
406 static int printed_version;
407 if (!printed_version++)
408 printk(version);
409#endif
410
411 i = pci_enable_device(pdev);
412 if (i) return i;
413
414 dev = alloc_etherdev(sizeof(*np));
415 if (!dev) {
416 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
417 return -ENOMEM;
418 }
419 SET_MODULE_OWNER(dev);
420 SET_NETDEV_DEV(dev, &pdev->dev);
421
422 np = netdev_priv(dev);
423
424 if (pci_request_regions(pdev, DRV_NAME))
425 goto err_out_free_netdev;
426
427 pci_set_master (pdev);
428
429 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
430 if (!ioaddr)
431 goto err_out_free_res;
432
433 irq = pdev->irq;
434
435 if (drv_flags & DontUseEeprom)
436 for (i = 0; i < 6; i++)
437 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
438 else {
439 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
440 for (i = 0; i < 6; i++)
441 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
442 }
443
444 /* Reset the chip. */
445 iowrite32(0x80000000, ioaddr + DMACtrl);
446
447 dev->base_addr = (unsigned long)ioaddr;
448 dev->irq = irq;
449
450 pci_set_drvdata(pdev, dev);
451 spin_lock_init(&np->lock);
452
453 np->pci_dev = pdev;
454 np->chip_id = chip_idx;
455 np->drv_flags = drv_flags;
456 np->base = ioaddr;
457
458 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
459 if (!ring_space)
460 goto err_out_cleardev;
461 np->tx_ring = (struct yellowfin_desc *)ring_space;
462 np->tx_ring_dma = ring_dma;
463
464 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
465 if (!ring_space)
466 goto err_out_unmap_tx;
467 np->rx_ring = (struct yellowfin_desc *)ring_space;
468 np->rx_ring_dma = ring_dma;
469
470 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
471 if (!ring_space)
472 goto err_out_unmap_rx;
473 np->tx_status = (struct tx_status_words *)ring_space;
474 np->tx_status_dma = ring_dma;
475
476 if (dev->mem_start)
477 option = dev->mem_start;
478
479 /* The lower four bits are the media type. */
480 if (option > 0) {
481 if (option & 0x200)
482 np->full_duplex = 1;
483 np->default_port = option & 15;
484 if (np->default_port)
485 np->medialock = 1;
486 }
487 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
488 np->full_duplex = 1;
489
490 if (np->full_duplex)
491 np->duplex_lock = 1;
492
493 /* The Yellowfin-specific entries in the device structure. */
494 dev->open = &yellowfin_open;
495 dev->hard_start_xmit = &yellowfin_start_xmit;
496 dev->stop = &yellowfin_close;
497 dev->get_stats = &yellowfin_get_stats;
498 dev->set_multicast_list = &set_rx_mode;
499 dev->do_ioctl = &netdev_ioctl;
500 SET_ETHTOOL_OPS(dev, &ethtool_ops);
501 dev->tx_timeout = yellowfin_tx_timeout;
502 dev->watchdog_timeo = TX_TIMEOUT;
503
504 if (mtu)
505 dev->mtu = mtu;
506
507 i = register_netdev(dev);
508 if (i)
509 goto err_out_unmap_status;
510
511 printk(KERN_INFO "%s: %s type %8x at %p, ",
512 dev->name, pci_id_tbl[chip_idx].name,
513 ioread32(ioaddr + ChipRev), ioaddr);
514 for (i = 0; i < 5; i++)
515 printk("%2.2x:", dev->dev_addr[i]);
516 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
517
518 if (np->drv_flags & HasMII) {
519 int phy, phy_idx = 0;
520 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
521 int mii_status = mdio_read(ioaddr, phy, 1);
522 if (mii_status != 0xffff && mii_status != 0x0000) {
523 np->phys[phy_idx++] = phy;
524 np->advertising = mdio_read(ioaddr, phy, 4);
525 printk(KERN_INFO "%s: MII PHY found at address %d, status "
526 "0x%4.4x advertising %4.4x.\n",
527 dev->name, phy, mii_status, np->advertising);
528 }
529 }
530 np->mii_cnt = phy_idx;
531 }
532
533 find_cnt++;
534
535 return 0;
536
537err_out_unmap_status:
538 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
539 np->tx_status_dma);
540err_out_unmap_rx:
541 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
542err_out_unmap_tx:
543 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
544err_out_cleardev:
545 pci_set_drvdata(pdev, NULL);
546 pci_iounmap(pdev, ioaddr);
547err_out_free_res:
548 pci_release_regions(pdev);
549err_out_free_netdev:
550 free_netdev (dev);
551 return -ENODEV;
552}
553
554static int __devinit read_eeprom(void __iomem *ioaddr, int location)
555{
556 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
557
558 iowrite8(location, ioaddr + EEAddr);
559 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
560 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
561 ;
562 return ioread8(ioaddr + EERead);
563}
564
565/* MII Managemen Data I/O accesses.
566 These routines assume the MDIO controller is idle, and do not exit until
567 the command is finished. */
568
569static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
570{
571 int i;
572
573 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
574 iowrite16(1, ioaddr + MII_Cmd);
575 for (i = 10000; i >= 0; i--)
576 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
577 break;
578 return ioread16(ioaddr + MII_Rd_Data);
579}
580
581static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
582{
583 int i;
584
585 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
586 iowrite16(value, ioaddr + MII_Wr_Data);
587
588 /* Wait for the command to finish. */
589 for (i = 10000; i >= 0; i--)
590 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
591 break;
592 return;
593}
594
595
596static int yellowfin_open(struct net_device *dev)
597{
598 struct yellowfin_private *yp = netdev_priv(dev);
599 void __iomem *ioaddr = yp->base;
600 int i;
601
602 /* Reset the chip. */
603 iowrite32(0x80000000, ioaddr + DMACtrl);
604
Thomas Gleixner1fb9df52006-07-01 19:29:39 -0700605 i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606 if (i) return i;
607
608 if (yellowfin_debug > 1)
609 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
610 dev->name, dev->irq);
611
612 yellowfin_init_ring(dev);
613
614 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
615 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
616
617 for (i = 0; i < 6; i++)
618 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
619
620 /* Set up various condition 'select' registers.
621 There are no options here. */
622 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
623 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
624 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
625 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
626 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
627 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
628
629 /* Initialize other registers: with so many this eventually this will
630 converted to an offset/value list. */
631 iowrite32(dma_ctrl, ioaddr + DMACtrl);
632 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
633 /* Enable automatic generation of flow control frames, period 0xffff. */
634 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
635
636 yp->tx_threshold = 32;
637 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
638
639 if (dev->if_port == 0)
640 dev->if_port = yp->default_port;
641
642 netif_start_queue(dev);
643
644 /* Setting the Rx mode will start the Rx process. */
645 if (yp->drv_flags & IsGigabit) {
646 /* We are always in full-duplex mode with gigabit! */
647 yp->full_duplex = 1;
648 iowrite16(0x01CF, ioaddr + Cnfg);
649 } else {
650 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
651 iowrite16(0x1018, ioaddr + FrameGap1);
652 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
653 }
654 set_rx_mode(dev);
655
656 /* Enable interrupts by setting the interrupt mask. */
657 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
658 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
659 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
660 iowrite32(0x80008000, ioaddr + TxCtrl);
661
662 if (yellowfin_debug > 2) {
663 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
664 dev->name);
665 }
666
667 /* Set the timer to check for link beat. */
668 init_timer(&yp->timer);
669 yp->timer.expires = jiffies + 3*HZ;
670 yp->timer.data = (unsigned long)dev;
671 yp->timer.function = &yellowfin_timer; /* timer handler */
672 add_timer(&yp->timer);
673
674 return 0;
675}
676
677static void yellowfin_timer(unsigned long data)
678{
679 struct net_device *dev = (struct net_device *)data;
680 struct yellowfin_private *yp = netdev_priv(dev);
681 void __iomem *ioaddr = yp->base;
682 int next_tick = 60*HZ;
683
684 if (yellowfin_debug > 3) {
685 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
686 dev->name, ioread16(ioaddr + IntrStatus));
687 }
688
689 if (yp->mii_cnt) {
690 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
691 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
692 int negotiated = lpa & yp->advertising;
693 if (yellowfin_debug > 1)
694 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
695 "link partner capability %4.4x.\n",
696 dev->name, yp->phys[0], bmsr, lpa);
697
698 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
699
700 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
701
702 if (bmsr & BMSR_LSTATUS)
703 next_tick = 60*HZ;
704 else
705 next_tick = 3*HZ;
706 }
707
708 yp->timer.expires = jiffies + next_tick;
709 add_timer(&yp->timer);
710}
711
712static void yellowfin_tx_timeout(struct net_device *dev)
713{
714 struct yellowfin_private *yp = netdev_priv(dev);
715 void __iomem *ioaddr = yp->base;
716
717 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
718 "status %4.4x, Rx status %4.4x, resetting...\n",
719 dev->name, yp->cur_tx, yp->dirty_tx,
720 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
721
722 /* Note: these should be KERN_DEBUG. */
723 if (yellowfin_debug) {
724 int i;
725 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
726 for (i = 0; i < RX_RING_SIZE; i++)
727 printk(" %8.8x", yp->rx_ring[i].result_status);
728 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
729 for (i = 0; i < TX_RING_SIZE; i++)
730 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
731 yp->tx_ring[i].result_status);
732 printk("\n");
733 }
734
735 /* If the hardware is found to hang regularly, we will update the code
736 to reinitialize the chip here. */
737 dev->if_port = 0;
738
739 /* Wake the potentially-idle transmit channel. */
740 iowrite32(0x10001000, yp->base + TxCtrl);
741 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
742 netif_wake_queue (dev); /* Typical path */
743
744 dev->trans_start = jiffies;
745 yp->stats.tx_errors++;
746}
747
748/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
749static void yellowfin_init_ring(struct net_device *dev)
750{
751 struct yellowfin_private *yp = netdev_priv(dev);
752 int i;
753
754 yp->tx_full = 0;
755 yp->cur_rx = yp->cur_tx = 0;
756 yp->dirty_tx = 0;
757
758 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
759
760 for (i = 0; i < RX_RING_SIZE; i++) {
761 yp->rx_ring[i].dbdma_cmd =
762 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
763 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
764 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
765 }
766
767 for (i = 0; i < RX_RING_SIZE; i++) {
768 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
769 yp->rx_skbuff[i] = skb;
770 if (skb == NULL)
771 break;
772 skb->dev = dev; /* Mark as being used by this device. */
773 skb_reserve(skb, 2); /* 16 byte align the IP header. */
774 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
David S. Miller689be432005-06-28 15:25:31 -0700775 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 }
777 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
778 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
779
780#define NO_TXSTATS
781#ifdef NO_TXSTATS
782 /* In this mode the Tx ring needs only a single descriptor. */
783 for (i = 0; i < TX_RING_SIZE; i++) {
784 yp->tx_skbuff[i] = NULL;
785 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
786 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
787 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
788 }
789 /* Wrap ring */
790 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
791#else
792{
793 int j;
794
795 /* Tx ring needs a pair of descriptors, the second for the status. */
796 for (i = 0; i < TX_RING_SIZE; i++) {
797 j = 2*i;
798 yp->tx_skbuff[i] = 0;
799 /* Branch on Tx error. */
800 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
801 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
802 (j+1)*sizeof(struct yellowfin_desc);
803 j++;
804 if (yp->flags & FullTxStatus) {
805 yp->tx_ring[j].dbdma_cmd =
806 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
807 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
808 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
809 i*sizeof(struct tx_status_words);
810 } else {
811 /* Symbios chips write only tx_errs word. */
812 yp->tx_ring[j].dbdma_cmd =
813 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
814 yp->tx_ring[j].request_cnt = 2;
815 /* Om pade ummmmm... */
816 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
817 i*sizeof(struct tx_status_words) +
818 &(yp->tx_status[0].tx_errs) -
819 &(yp->tx_status[0]));
820 }
821 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
822 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
823 }
824 /* Wrap ring */
825 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
826}
827#endif
828 yp->tx_tail_desc = &yp->tx_status[0];
829 return;
830}
831
832static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
833{
834 struct yellowfin_private *yp = netdev_priv(dev);
835 unsigned entry;
836 int len = skb->len;
837
838 netif_stop_queue (dev);
839
840 /* Note: Ordering is important here, set the field with the
841 "ownership" bit last, and only then increment cur_tx. */
842
843 /* Calculate the next Tx descriptor entry. */
844 entry = yp->cur_tx % TX_RING_SIZE;
845
846 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
847 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
848 /* Fix GX chipset errata. */
849 if (cacheline_end > 24 || cacheline_end == 0) {
850 len = skb->len + 32 - cacheline_end + 1;
Herbert Xu5b057c62006-06-23 02:06:41 -0700851 if (skb_padto(skb, len)) {
852 yp->tx_skbuff[entry] = NULL;
853 netif_wake_queue(dev);
854 return 0;
855 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 }
857 }
858 yp->tx_skbuff[entry] = skb;
859
860#ifdef NO_TXSTATS
861 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
862 skb->data, len, PCI_DMA_TODEVICE));
863 yp->tx_ring[entry].result_status = 0;
864 if (entry >= TX_RING_SIZE-1) {
865 /* New stop command. */
866 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
867 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
868 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
869 } else {
870 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
871 yp->tx_ring[entry].dbdma_cmd =
872 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
873 }
874 yp->cur_tx++;
875#else
876 yp->tx_ring[entry<<1].request_cnt = len;
877 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
878 skb->data, len, PCI_DMA_TODEVICE));
879 /* The input_last (status-write) command is constant, but we must
880 rewrite the subsequent 'stop' command. */
881
882 yp->cur_tx++;
883 {
884 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
885 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
886 }
887 /* Final step -- overwrite the old 'stop' command. */
888
889 yp->tx_ring[entry<<1].dbdma_cmd =
890 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
891 CMD_TX_PKT | BRANCH_IFTRUE) | len);
892#endif
893
894 /* Non-x86 Todo: explicitly flush cache lines here. */
895
896 /* Wake the potentially-idle transmit channel. */
897 iowrite32(0x10001000, yp->base + TxCtrl);
898
899 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
900 netif_start_queue (dev); /* Typical path */
901 else
902 yp->tx_full = 1;
903 dev->trans_start = jiffies;
904
905 if (yellowfin_debug > 4) {
906 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
907 dev->name, yp->cur_tx, entry);
908 }
909 return 0;
910}
911
912/* The interrupt handler does all of the Rx thread work and cleans up
913 after the Tx thread. */
914static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
915{
916 struct net_device *dev = dev_instance;
917 struct yellowfin_private *yp;
918 void __iomem *ioaddr;
919 int boguscnt = max_interrupt_work;
920 unsigned int handled = 0;
921
922#ifndef final_version /* Can never occur. */
923 if (dev == NULL) {
924 printk (KERN_ERR "yellowfin_interrupt(): irq %d for unknown device.\n", irq);
925 return IRQ_NONE;
926 }
927#endif
928
929 yp = netdev_priv(dev);
930 ioaddr = yp->base;
931
932 spin_lock (&yp->lock);
933
934 do {
935 u16 intr_status = ioread16(ioaddr + IntrClear);
936
937 if (yellowfin_debug > 4)
938 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
939 dev->name, intr_status);
940
941 if (intr_status == 0)
942 break;
943 handled = 1;
944
945 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
946 yellowfin_rx(dev);
947 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
948 }
949
950#ifdef NO_TXSTATS
951 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
952 int entry = yp->dirty_tx % TX_RING_SIZE;
953 struct sk_buff *skb;
954
955 if (yp->tx_ring[entry].result_status == 0)
956 break;
957 skb = yp->tx_skbuff[entry];
958 yp->stats.tx_packets++;
959 yp->stats.tx_bytes += skb->len;
960 /* Free the original skb. */
961 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
962 skb->len, PCI_DMA_TODEVICE);
963 dev_kfree_skb_irq(skb);
964 yp->tx_skbuff[entry] = NULL;
965 }
966 if (yp->tx_full
967 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
968 /* The ring is no longer full, clear tbusy. */
969 yp->tx_full = 0;
970 netif_wake_queue(dev);
971 }
972#else
973 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
974 unsigned dirty_tx = yp->dirty_tx;
975
976 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
977 dirty_tx++) {
978 /* Todo: optimize this. */
979 int entry = dirty_tx % TX_RING_SIZE;
980 u16 tx_errs = yp->tx_status[entry].tx_errs;
981 struct sk_buff *skb;
982
983#ifndef final_version
984 if (yellowfin_debug > 5)
985 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
986 "%4.4x %4.4x %4.4x %4.4x.\n",
987 dev->name, entry,
988 yp->tx_status[entry].tx_cnt,
989 yp->tx_status[entry].tx_errs,
990 yp->tx_status[entry].total_tx_cnt,
991 yp->tx_status[entry].paused);
992#endif
993 if (tx_errs == 0)
994 break; /* It still hasn't been Txed */
995 skb = yp->tx_skbuff[entry];
996 if (tx_errs & 0xF810) {
997 /* There was an major error, log it. */
998#ifndef final_version
999 if (yellowfin_debug > 1)
1000 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
1001 dev->name, tx_errs);
1002#endif
1003 yp->stats.tx_errors++;
1004 if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++;
1005 if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++;
1006 if (tx_errs & 0x2000) yp->stats.tx_window_errors++;
1007 if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++;
1008 } else {
1009#ifndef final_version
1010 if (yellowfin_debug > 4)
1011 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
1012 dev->name, tx_errs);
1013#endif
1014 yp->stats.tx_bytes += skb->len;
1015 yp->stats.collisions += tx_errs & 15;
1016 yp->stats.tx_packets++;
1017 }
1018 /* Free the original skb. */
1019 pci_unmap_single(yp->pci_dev,
1020 yp->tx_ring[entry<<1].addr, skb->len,
1021 PCI_DMA_TODEVICE);
1022 dev_kfree_skb_irq(skb);
1023 yp->tx_skbuff[entry] = 0;
1024 /* Mark status as empty. */
1025 yp->tx_status[entry].tx_errs = 0;
1026 }
1027
1028#ifndef final_version
1029 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1030 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1031 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1032 dirty_tx += TX_RING_SIZE;
1033 }
1034#endif
1035
1036 if (yp->tx_full
1037 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1038 /* The ring is no longer full, clear tbusy. */
1039 yp->tx_full = 0;
1040 netif_wake_queue(dev);
1041 }
1042
1043 yp->dirty_tx = dirty_tx;
1044 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1045 }
1046#endif
1047
1048 /* Log errors and other uncommon events. */
1049 if (intr_status & 0x2ee) /* Abnormal error summary. */
1050 yellowfin_error(dev, intr_status);
1051
1052 if (--boguscnt < 0) {
1053 printk(KERN_WARNING "%s: Too much work at interrupt, "
1054 "status=0x%4.4x.\n",
1055 dev->name, intr_status);
1056 break;
1057 }
1058 } while (1);
1059
1060 if (yellowfin_debug > 3)
1061 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1062 dev->name, ioread16(ioaddr + IntrStatus));
1063
1064 spin_unlock (&yp->lock);
1065 return IRQ_RETVAL(handled);
1066}
1067
1068/* This routine is logically part of the interrupt handler, but separated
1069 for clarity and better register allocation. */
1070static int yellowfin_rx(struct net_device *dev)
1071{
1072 struct yellowfin_private *yp = netdev_priv(dev);
1073 int entry = yp->cur_rx % RX_RING_SIZE;
1074 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1075
1076 if (yellowfin_debug > 4) {
1077 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1078 entry, yp->rx_ring[entry].result_status);
1079 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1080 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1081 yp->rx_ring[entry].result_status);
1082 }
1083
1084 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1085 while (1) {
1086 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1087 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1088 s16 frame_status;
1089 u16 desc_status;
1090 int data_size;
1091 u8 *buf_addr;
1092
1093 if(!desc->result_status)
1094 break;
1095 pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr,
1096 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1097 desc_status = le32_to_cpu(desc->result_status) >> 16;
David S. Miller689be432005-06-28 15:25:31 -07001098 buf_addr = rx_skb->data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1100 le32_to_cpu(desc->result_status)) & 0xffff;
1101 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1102 if (yellowfin_debug > 4)
1103 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1104 frame_status);
1105 if (--boguscnt < 0)
1106 break;
1107 if ( ! (desc_status & RX_EOP)) {
1108 if (data_size != 0)
1109 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1110 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1111 yp->stats.rx_length_errors++;
1112 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1113 /* There was a error. */
1114 if (yellowfin_debug > 3)
1115 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1116 frame_status);
1117 yp->stats.rx_errors++;
1118 if (frame_status & 0x0060) yp->stats.rx_length_errors++;
1119 if (frame_status & 0x0008) yp->stats.rx_frame_errors++;
1120 if (frame_status & 0x0010) yp->stats.rx_crc_errors++;
1121 if (frame_status < 0) yp->stats.rx_dropped++;
1122 } else if ( !(yp->drv_flags & IsGigabit) &&
1123 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1124 u8 status1 = buf_addr[data_size-2];
1125 u8 status2 = buf_addr[data_size-1];
1126 yp->stats.rx_errors++;
1127 if (status1 & 0xC0) yp->stats.rx_length_errors++;
1128 if (status2 & 0x03) yp->stats.rx_frame_errors++;
1129 if (status2 & 0x04) yp->stats.rx_crc_errors++;
1130 if (status2 & 0x80) yp->stats.rx_dropped++;
1131#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1132 } else if ((yp->flags & HasMACAddrBug) &&
1133 memcmp(le32_to_cpu(yp->rx_ring_dma +
1134 entry*sizeof(struct yellowfin_desc)),
1135 dev->dev_addr, 6) != 0 &&
1136 memcmp(le32_to_cpu(yp->rx_ring_dma +
1137 entry*sizeof(struct yellowfin_desc)),
1138 "\377\377\377\377\377\377", 6) != 0) {
1139 if (bogus_rx++ == 0)
1140 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1141 "%2.2x:%2.2x.\n",
1142 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1143 buf_addr[3], buf_addr[4], buf_addr[5]);
1144#endif
1145 } else {
1146 struct sk_buff *skb;
1147 int pkt_len = data_size -
1148 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1149 /* To verify: Yellowfin Length should omit the CRC! */
1150
1151#ifndef final_version
1152 if (yellowfin_debug > 4)
1153 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1154 " of %d, bogus_cnt %d.\n",
1155 pkt_len, data_size, boguscnt);
1156#endif
1157 /* Check if the packet is long enough to just pass up the skbuff
1158 without copying to a properly sized skbuff. */
1159 if (pkt_len > rx_copybreak) {
1160 skb_put(skb = rx_skb, pkt_len);
1161 pci_unmap_single(yp->pci_dev,
1162 yp->rx_ring[entry].addr,
1163 yp->rx_buf_sz,
1164 PCI_DMA_FROMDEVICE);
1165 yp->rx_skbuff[entry] = NULL;
1166 } else {
1167 skb = dev_alloc_skb(pkt_len + 2);
1168 if (skb == NULL)
1169 break;
1170 skb->dev = dev;
1171 skb_reserve(skb, 2); /* 16 byte align the IP header */
David S. Miller689be432005-06-28 15:25:31 -07001172 eth_copy_and_sum(skb, rx_skb->data, pkt_len, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173 skb_put(skb, pkt_len);
1174 pci_dma_sync_single_for_device(yp->pci_dev, desc->addr,
1175 yp->rx_buf_sz,
1176 PCI_DMA_FROMDEVICE);
1177 }
1178 skb->protocol = eth_type_trans(skb, dev);
1179 netif_rx(skb);
1180 dev->last_rx = jiffies;
1181 yp->stats.rx_packets++;
1182 yp->stats.rx_bytes += pkt_len;
1183 }
1184 entry = (++yp->cur_rx) % RX_RING_SIZE;
1185 }
1186
1187 /* Refill the Rx ring buffers. */
1188 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1189 entry = yp->dirty_rx % RX_RING_SIZE;
1190 if (yp->rx_skbuff[entry] == NULL) {
1191 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1192 if (skb == NULL)
1193 break; /* Better luck next round. */
1194 yp->rx_skbuff[entry] = skb;
1195 skb->dev = dev; /* Mark as being used by this device. */
1196 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1197 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
David S. Miller689be432005-06-28 15:25:31 -07001198 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001199 }
1200 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1201 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1202 if (entry != 0)
1203 yp->rx_ring[entry - 1].dbdma_cmd =
1204 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1205 else
1206 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1207 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1208 | yp->rx_buf_sz);
1209 }
1210
1211 return 0;
1212}
1213
1214static void yellowfin_error(struct net_device *dev, int intr_status)
1215{
1216 struct yellowfin_private *yp = netdev_priv(dev);
1217
1218 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1219 dev->name, intr_status);
1220 /* Hmmmmm, it's not clear what to do here. */
1221 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1222 yp->stats.tx_errors++;
1223 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1224 yp->stats.rx_errors++;
1225}
1226
1227static int yellowfin_close(struct net_device *dev)
1228{
1229 struct yellowfin_private *yp = netdev_priv(dev);
1230 void __iomem *ioaddr = yp->base;
1231 int i;
1232
1233 netif_stop_queue (dev);
1234
1235 if (yellowfin_debug > 1) {
1236 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1237 "Rx %4.4x Int %2.2x.\n",
1238 dev->name, ioread16(ioaddr + TxStatus),
1239 ioread16(ioaddr + RxStatus),
1240 ioread16(ioaddr + IntrStatus));
1241 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1242 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1243 }
1244
1245 /* Disable interrupts by clearing the interrupt mask. */
1246 iowrite16(0x0000, ioaddr + IntrEnb);
1247
1248 /* Stop the chip's Tx and Rx processes. */
1249 iowrite32(0x80000000, ioaddr + RxCtrl);
1250 iowrite32(0x80000000, ioaddr + TxCtrl);
1251
1252 del_timer(&yp->timer);
1253
1254#if defined(__i386__)
1255 if (yellowfin_debug > 2) {
1256 printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n",
1257 (unsigned long long)yp->tx_ring_dma);
1258 for (i = 0; i < TX_RING_SIZE*2; i++)
1259 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1260 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1261 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1262 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1263 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1264 for (i = 0; i < TX_RING_SIZE; i++)
1265 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1266 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1267 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1268
1269 printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n",
1270 (unsigned long long)yp->rx_ring_dma);
1271 for (i = 0; i < RX_RING_SIZE; i++) {
1272 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1273 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1274 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1275 yp->rx_ring[i].result_status);
1276 if (yellowfin_debug > 6) {
1277 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1278 int j;
1279 for (j = 0; j < 0x50; j++)
1280 printk(" %4.4x",
1281 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1282 printk("\n");
1283 }
1284 }
1285 }
1286 }
1287#endif /* __i386__ debugging only */
1288
1289 free_irq(dev->irq, dev);
1290
1291 /* Free all the skbuffs in the Rx queue. */
1292 for (i = 0; i < RX_RING_SIZE; i++) {
1293 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1294 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1295 if (yp->rx_skbuff[i]) {
1296 dev_kfree_skb(yp->rx_skbuff[i]);
1297 }
1298 yp->rx_skbuff[i] = NULL;
1299 }
1300 for (i = 0; i < TX_RING_SIZE; i++) {
1301 if (yp->tx_skbuff[i])
1302 dev_kfree_skb(yp->tx_skbuff[i]);
1303 yp->tx_skbuff[i] = NULL;
1304 }
1305
1306#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1307 if (yellowfin_debug > 0) {
1308 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1309 dev->name, bogus_rx);
1310 }
1311#endif
1312
1313 return 0;
1314}
1315
1316static struct net_device_stats *yellowfin_get_stats(struct net_device *dev)
1317{
1318 struct yellowfin_private *yp = netdev_priv(dev);
1319 return &yp->stats;
1320}
1321
1322/* Set or clear the multicast filter for this adaptor. */
1323
1324static void set_rx_mode(struct net_device *dev)
1325{
1326 struct yellowfin_private *yp = netdev_priv(dev);
1327 void __iomem *ioaddr = yp->base;
1328 u16 cfg_value = ioread16(ioaddr + Cnfg);
1329
1330 /* Stop the Rx process to change any value. */
1331 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1332 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1333 /* Unconditionally log net taps. */
1334 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1335 iowrite16(0x000F, ioaddr + AddrMode);
1336 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1337 /* Too many to filter well, or accept all multicasts. */
1338 iowrite16(0x000B, ioaddr + AddrMode);
1339 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1340 struct dev_mc_list *mclist;
1341 u16 hash_table[4];
1342 int i;
1343 memset(hash_table, 0, sizeof(hash_table));
1344 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1345 i++, mclist = mclist->next) {
1346 unsigned int bit;
1347
1348 /* Due to a bug in the early chip versions, multiple filter
1349 slots must be set for each address. */
1350 if (yp->drv_flags & HasMulticastBug) {
1351 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1352 hash_table[bit >> 4] |= (1 << bit);
1353 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1354 hash_table[bit >> 4] |= (1 << bit);
1355 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1356 hash_table[bit >> 4] |= (1 << bit);
1357 }
1358 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1359 hash_table[bit >> 4] |= (1 << bit);
1360 }
1361 /* Copy the hash table to the chip. */
1362 for (i = 0; i < 4; i++)
1363 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1364 iowrite16(0x0003, ioaddr + AddrMode);
1365 } else { /* Normal, unicast/broadcast-only mode. */
1366 iowrite16(0x0001, ioaddr + AddrMode);
1367 }
1368 /* Restart the Rx process. */
1369 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1370}
1371
1372static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1373{
1374 struct yellowfin_private *np = netdev_priv(dev);
1375 strcpy(info->driver, DRV_NAME);
1376 strcpy(info->version, DRV_VERSION);
1377 strcpy(info->bus_info, pci_name(np->pci_dev));
1378}
1379
1380static struct ethtool_ops ethtool_ops = {
1381 .get_drvinfo = yellowfin_get_drvinfo
1382};
1383
1384static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1385{
1386 struct yellowfin_private *np = netdev_priv(dev);
1387 void __iomem *ioaddr = np->base;
1388 struct mii_ioctl_data *data = if_mii(rq);
1389
1390 switch(cmd) {
1391 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1392 data->phy_id = np->phys[0] & 0x1f;
1393 /* Fall Through */
1394
1395 case SIOCGMIIREG: /* Read MII PHY register. */
1396 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1397 return 0;
1398
1399 case SIOCSMIIREG: /* Write MII PHY register. */
1400 if (!capable(CAP_NET_ADMIN))
1401 return -EPERM;
1402 if (data->phy_id == np->phys[0]) {
1403 u16 value = data->val_in;
1404 switch (data->reg_num) {
1405 case 0:
1406 /* Check for autonegotiation on or reset. */
1407 np->medialock = (value & 0x9000) ? 0 : 1;
1408 if (np->medialock)
1409 np->full_duplex = (value & 0x0100) ? 1 : 0;
1410 break;
1411 case 4: np->advertising = value; break;
1412 }
1413 /* Perhaps check_duplex(dev), depending on chip semantics. */
1414 }
1415 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1416 return 0;
1417 default:
1418 return -EOPNOTSUPP;
1419 }
1420}
1421
1422
1423static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1424{
1425 struct net_device *dev = pci_get_drvdata(pdev);
1426 struct yellowfin_private *np;
1427
Eric Sesterhenn5d9428d2006-04-02 13:52:48 +02001428 BUG_ON(!dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 np = netdev_priv(dev);
1430
1431 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1432 np->tx_status_dma);
1433 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1434 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1435 unregister_netdev (dev);
1436
1437 pci_iounmap(pdev, np->base);
1438
1439 pci_release_regions (pdev);
1440
1441 free_netdev (dev);
1442 pci_set_drvdata(pdev, NULL);
1443}
1444
1445
1446static struct pci_driver yellowfin_driver = {
1447 .name = DRV_NAME,
1448 .id_table = yellowfin_pci_tbl,
1449 .probe = yellowfin_init_one,
1450 .remove = __devexit_p(yellowfin_remove_one),
1451};
1452
1453
1454static int __init yellowfin_init (void)
1455{
1456/* when a module, this is printed whether or not devices are found in probe */
1457#ifdef MODULE
1458 printk(version);
1459#endif
1460 return pci_module_init (&yellowfin_driver);
1461}
1462
1463
1464static void __exit yellowfin_cleanup (void)
1465{
1466 pci_unregister_driver (&yellowfin_driver);
1467}
1468
1469
1470module_init(yellowfin_init);
1471module_exit(yellowfin_cleanup);
1472
1473/*
1474 * Local variables:
1475 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1476 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1477 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"
1478 * c-indent-level: 4
1479 * c-basic-offset: 4
1480 * tab-width: 4
1481 * End:
1482 */