blob: 53d2a5d61baf4fe1d35b756edc43b418db32bdad [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31#define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32#define DRIVER_NAME "Maestro3"
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/io.h>
35#include <linux/delay.h>
36#include <linux/interrupt.h>
37#include <linux/init.h>
38#include <linux/pci.h>
Tobias Klauser9d2f9282006-03-22 10:53:19 +010039#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/slab.h>
41#include <linux/vmalloc.h>
42#include <linux/moduleparam.h>
Clemens Ladisch81d77242006-11-06 09:26:41 +010043#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070044#include <sound/core.h>
45#include <sound/info.h>
46#include <sound/control.h>
47#include <sound/pcm.h>
48#include <sound/mpu401.h>
49#include <sound/ac97_codec.h>
50#include <sound/initval.h>
Clemens Ladisch81d77242006-11-06 09:26:41 +010051#include <asm/byteorder.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54MODULE_DESCRIPTION("ESS Maestro3 PCI");
55MODULE_LICENSE("GPL");
56MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,ES1988},"
58 "{ESS,Allegro PCI},"
59 "{ESS,Allegro-1 PCI},"
60 "{ESS,Canyon3D-2/LE PCI}}");
Clemens Ladisch7e0af292007-05-03 17:59:54 +020061MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
62MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
64static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
67static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
68static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
69
70module_param_array(index, int, NULL, 0444);
71MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
72module_param_array(id, charp, NULL, 0444);
73MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
74module_param_array(enable, bool, NULL, 0444);
75MODULE_PARM_DESC(enable, "Enable this soundcard.");
76module_param_array(external_amp, bool, NULL, 0444);
77MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
78module_param_array(amp_gpio, int, NULL, 0444);
79MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
80
81#define MAX_PLAYBACKS 2
82#define MAX_CAPTURES 1
83#define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
84
85
86/*
87 * maestro3 registers
88 */
89
90/* Allegro PCI configuration registers */
91#define PCI_LEGACY_AUDIO_CTRL 0x40
92#define SOUND_BLASTER_ENABLE 0x00000001
93#define FM_SYNTHESIS_ENABLE 0x00000002
94#define GAME_PORT_ENABLE 0x00000004
95#define MPU401_IO_ENABLE 0x00000008
96#define MPU401_IRQ_ENABLE 0x00000010
97#define ALIAS_10BIT_IO 0x00000020
98#define SB_DMA_MASK 0x000000C0
99#define SB_DMA_0 0x00000040
100#define SB_DMA_1 0x00000040
101#define SB_DMA_R 0x00000080
102#define SB_DMA_3 0x000000C0
103#define SB_IRQ_MASK 0x00000700
104#define SB_IRQ_5 0x00000000
105#define SB_IRQ_7 0x00000100
106#define SB_IRQ_9 0x00000200
107#define SB_IRQ_10 0x00000300
108#define MIDI_IRQ_MASK 0x00003800
109#define SERIAL_IRQ_ENABLE 0x00004000
110#define DISABLE_LEGACY 0x00008000
111
112#define PCI_ALLEGRO_CONFIG 0x50
113#define SB_ADDR_240 0x00000004
114#define MPU_ADDR_MASK 0x00000018
115#define MPU_ADDR_330 0x00000000
116#define MPU_ADDR_300 0x00000008
117#define MPU_ADDR_320 0x00000010
118#define MPU_ADDR_340 0x00000018
119#define USE_PCI_TIMING 0x00000040
120#define POSTED_WRITE_ENABLE 0x00000080
121#define DMA_POLICY_MASK 0x00000700
122#define DMA_DDMA 0x00000000
123#define DMA_TDMA 0x00000100
124#define DMA_PCPCI 0x00000200
125#define DMA_WBDMA16 0x00000400
126#define DMA_WBDMA4 0x00000500
127#define DMA_WBDMA2 0x00000600
128#define DMA_WBDMA1 0x00000700
129#define DMA_SAFE_GUARD 0x00000800
130#define HI_PERF_GP_ENABLE 0x00001000
131#define PIC_SNOOP_MODE_0 0x00002000
132#define PIC_SNOOP_MODE_1 0x00004000
133#define SOUNDBLASTER_IRQ_MASK 0x00008000
134#define RING_IN_ENABLE 0x00010000
135#define SPDIF_TEST_MODE 0x00020000
136#define CLK_MULT_MODE_SELECT_2 0x00040000
137#define EEPROM_WRITE_ENABLE 0x00080000
138#define CODEC_DIR_IN 0x00100000
139#define HV_BUTTON_FROM_GD 0x00200000
140#define REDUCED_DEBOUNCE 0x00400000
141#define HV_CTRL_ENABLE 0x00800000
142#define SPDIF_ENABLE 0x01000000
143#define CLK_DIV_SELECT 0x06000000
144#define CLK_DIV_BY_48 0x00000000
145#define CLK_DIV_BY_49 0x02000000
146#define CLK_DIV_BY_50 0x04000000
147#define CLK_DIV_RESERVED 0x06000000
148#define PM_CTRL_ENABLE 0x08000000
149#define CLK_MULT_MODE_SELECT 0x30000000
150#define CLK_MULT_MODE_SHIFT 28
151#define CLK_MULT_MODE_0 0x00000000
152#define CLK_MULT_MODE_1 0x10000000
153#define CLK_MULT_MODE_2 0x20000000
154#define CLK_MULT_MODE_3 0x30000000
155#define INT_CLK_SELECT 0x40000000
156#define INT_CLK_MULT_RESET 0x80000000
157
158/* M3 */
159#define INT_CLK_SRC_NOT_PCI 0x00100000
160#define INT_CLK_MULT_ENABLE 0x80000000
161
162#define PCI_ACPI_CONTROL 0x54
163#define PCI_ACPI_D0 0x00000000
164#define PCI_ACPI_D1 0xB4F70000
165#define PCI_ACPI_D2 0xB4F7B4F7
166
167#define PCI_USER_CONFIG 0x58
168#define EXT_PCI_MASTER_ENABLE 0x00000001
169#define SPDIF_OUT_SELECT 0x00000002
170#define TEST_PIN_DIR_CTRL 0x00000004
171#define AC97_CODEC_TEST 0x00000020
172#define TRI_STATE_BUFFER 0x00000080
173#define IN_CLK_12MHZ_SELECT 0x00000100
174#define MULTI_FUNC_DISABLE 0x00000200
175#define EXT_MASTER_PAIR_SEL 0x00000400
176#define PCI_MASTER_SUPPORT 0x00000800
177#define STOP_CLOCK_ENABLE 0x00001000
178#define EAPD_DRIVE_ENABLE 0x00002000
179#define REQ_TRI_STATE_ENABLE 0x00004000
180#define REQ_LOW_ENABLE 0x00008000
181#define MIDI_1_ENABLE 0x00010000
182#define MIDI_2_ENABLE 0x00020000
183#define SB_AUDIO_SYNC 0x00040000
184#define HV_CTRL_TEST 0x00100000
185#define SOUNDBLASTER_TEST 0x00400000
186
187#define PCI_USER_CONFIG_C 0x5C
188
189#define PCI_DDMA_CTRL 0x60
190#define DDMA_ENABLE 0x00000001
191
192
193/* Allegro registers */
194#define HOST_INT_CTRL 0x18
195#define SB_INT_ENABLE 0x0001
196#define MPU401_INT_ENABLE 0x0002
197#define ASSP_INT_ENABLE 0x0010
198#define RING_INT_ENABLE 0x0020
199#define HV_INT_ENABLE 0x0040
200#define CLKRUN_GEN_ENABLE 0x0100
201#define HV_CTRL_TO_PME 0x0400
202#define SOFTWARE_RESET_ENABLE 0x8000
203
204/*
205 * should be using the above defines, probably.
206 */
207#define REGB_ENABLE_RESET 0x01
208#define REGB_STOP_CLOCK 0x10
209
210#define HOST_INT_STATUS 0x1A
211#define SB_INT_PENDING 0x01
212#define MPU401_INT_PENDING 0x02
213#define ASSP_INT_PENDING 0x10
214#define RING_INT_PENDING 0x20
215#define HV_INT_PENDING 0x40
216
217#define HARDWARE_VOL_CTRL 0x1B
218#define SHADOW_MIX_REG_VOICE 0x1C
219#define HW_VOL_COUNTER_VOICE 0x1D
220#define SHADOW_MIX_REG_MASTER 0x1E
221#define HW_VOL_COUNTER_MASTER 0x1F
222
223#define CODEC_COMMAND 0x30
224#define CODEC_READ_B 0x80
225
226#define CODEC_STATUS 0x30
227#define CODEC_BUSY_B 0x01
228
229#define CODEC_DATA 0x32
230
231#define RING_BUS_CTRL_A 0x36
232#define RAC_PME_ENABLE 0x0100
233#define RAC_SDFS_ENABLE 0x0200
234#define LAC_PME_ENABLE 0x0400
235#define LAC_SDFS_ENABLE 0x0800
236#define SERIAL_AC_LINK_ENABLE 0x1000
237#define IO_SRAM_ENABLE 0x2000
238#define IIS_INPUT_ENABLE 0x8000
239
240#define RING_BUS_CTRL_B 0x38
241#define SECOND_CODEC_ID_MASK 0x0003
242#define SPDIF_FUNC_ENABLE 0x0010
243#define SECOND_AC_ENABLE 0x0020
244#define SB_MODULE_INTF_ENABLE 0x0040
245#define SSPE_ENABLE 0x0040
246#define M3I_DOCK_ENABLE 0x0080
247
248#define SDO_OUT_DEST_CTRL 0x3A
249#define COMMAND_ADDR_OUT 0x0003
250#define PCM_LR_OUT_LOCAL 0x0000
251#define PCM_LR_OUT_REMOTE 0x0004
252#define PCM_LR_OUT_MUTE 0x0008
253#define PCM_LR_OUT_BOTH 0x000C
254#define LINE1_DAC_OUT_LOCAL 0x0000
255#define LINE1_DAC_OUT_REMOTE 0x0010
256#define LINE1_DAC_OUT_MUTE 0x0020
257#define LINE1_DAC_OUT_BOTH 0x0030
258#define PCM_CLS_OUT_LOCAL 0x0000
259#define PCM_CLS_OUT_REMOTE 0x0040
260#define PCM_CLS_OUT_MUTE 0x0080
261#define PCM_CLS_OUT_BOTH 0x00C0
262#define PCM_RLF_OUT_LOCAL 0x0000
263#define PCM_RLF_OUT_REMOTE 0x0100
264#define PCM_RLF_OUT_MUTE 0x0200
265#define PCM_RLF_OUT_BOTH 0x0300
266#define LINE2_DAC_OUT_LOCAL 0x0000
267#define LINE2_DAC_OUT_REMOTE 0x0400
268#define LINE2_DAC_OUT_MUTE 0x0800
269#define LINE2_DAC_OUT_BOTH 0x0C00
270#define HANDSET_OUT_LOCAL 0x0000
271#define HANDSET_OUT_REMOTE 0x1000
272#define HANDSET_OUT_MUTE 0x2000
273#define HANDSET_OUT_BOTH 0x3000
274#define IO_CTRL_OUT_LOCAL 0x0000
275#define IO_CTRL_OUT_REMOTE 0x4000
276#define IO_CTRL_OUT_MUTE 0x8000
277#define IO_CTRL_OUT_BOTH 0xC000
278
279#define SDO_IN_DEST_CTRL 0x3C
280#define STATUS_ADDR_IN 0x0003
281#define PCM_LR_IN_LOCAL 0x0000
282#define PCM_LR_IN_REMOTE 0x0004
283#define PCM_LR_RESERVED 0x0008
284#define PCM_LR_IN_BOTH 0x000C
285#define LINE1_ADC_IN_LOCAL 0x0000
286#define LINE1_ADC_IN_REMOTE 0x0010
287#define LINE1_ADC_IN_MUTE 0x0020
288#define MIC_ADC_IN_LOCAL 0x0000
289#define MIC_ADC_IN_REMOTE 0x0040
290#define MIC_ADC_IN_MUTE 0x0080
291#define LINE2_DAC_IN_LOCAL 0x0000
292#define LINE2_DAC_IN_REMOTE 0x0400
293#define LINE2_DAC_IN_MUTE 0x0800
294#define HANDSET_IN_LOCAL 0x0000
295#define HANDSET_IN_REMOTE 0x1000
296#define HANDSET_IN_MUTE 0x2000
297#define IO_STATUS_IN_LOCAL 0x0000
298#define IO_STATUS_IN_REMOTE 0x4000
299
300#define SPDIF_IN_CTRL 0x3E
301#define SPDIF_IN_ENABLE 0x0001
302
303#define GPIO_DATA 0x60
304#define GPIO_DATA_MASK 0x0FFF
305#define GPIO_HV_STATUS 0x3000
306#define GPIO_PME_STATUS 0x4000
307
308#define GPIO_MASK 0x64
309#define GPIO_DIRECTION 0x68
310#define GPO_PRIMARY_AC97 0x0001
311#define GPI_LINEOUT_SENSE 0x0004
312#define GPO_SECONDARY_AC97 0x0008
313#define GPI_VOL_DOWN 0x0010
314#define GPI_VOL_UP 0x0020
315#define GPI_IIS_CLK 0x0040
316#define GPI_IIS_LRCLK 0x0080
317#define GPI_IIS_DATA 0x0100
318#define GPI_DOCKING_STATUS 0x0100
319#define GPI_HEADPHONE_SENSE 0x0200
320#define GPO_EXT_AMP_SHUTDOWN 0x1000
321
322#define GPO_EXT_AMP_M3 1 /* default m3 amp */
323#define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
324
325/* M3 */
326#define GPO_M3_EXT_AMP_SHUTDN 0x0002
327
328#define ASSP_INDEX_PORT 0x80
329#define ASSP_MEMORY_PORT 0x82
330#define ASSP_DATA_PORT 0x84
331
332#define MPU401_DATA_PORT 0x98
333#define MPU401_STATUS_PORT 0x99
334
335#define CLK_MULT_DATA_PORT 0x9C
336
337#define ASSP_CONTROL_A 0xA2
338#define ASSP_0_WS_ENABLE 0x01
339#define ASSP_CTRL_A_RESERVED1 0x02
340#define ASSP_CTRL_A_RESERVED2 0x04
341#define ASSP_CLK_49MHZ_SELECT 0x08
342#define FAST_PLU_ENABLE 0x10
343#define ASSP_CTRL_A_RESERVED3 0x20
344#define DSP_CLK_36MHZ_SELECT 0x40
345
346#define ASSP_CONTROL_B 0xA4
347#define RESET_ASSP 0x00
348#define RUN_ASSP 0x01
349#define ENABLE_ASSP_CLOCK 0x00
350#define STOP_ASSP_CLOCK 0x10
351#define RESET_TOGGLE 0x40
352
353#define ASSP_CONTROL_C 0xA6
354#define ASSP_HOST_INT_ENABLE 0x01
355#define FM_ADDR_REMAP_DISABLE 0x02
356#define HOST_WRITE_PORT_ENABLE 0x08
357
358#define ASSP_HOST_INT_STATUS 0xAC
359#define DSP2HOST_REQ_PIORECORD 0x01
360#define DSP2HOST_REQ_I2SRATE 0x02
361#define DSP2HOST_REQ_TIMER 0x04
362
363/* AC97 registers */
364/* XXX fix this crap up */
365/*#define AC97_RESET 0x00*/
366
367#define AC97_VOL_MUTE_B 0x8000
368#define AC97_VOL_M 0x1F
369#define AC97_LEFT_VOL_S 8
370
371#define AC97_MASTER_VOL 0x02
372#define AC97_LINE_LEVEL_VOL 0x04
373#define AC97_MASTER_MONO_VOL 0x06
374#define AC97_PC_BEEP_VOL 0x0A
375#define AC97_PC_BEEP_VOL_M 0x0F
376#define AC97_SROUND_MASTER_VOL 0x38
377#define AC97_PC_BEEP_VOL_S 1
378
379/*#define AC97_PHONE_VOL 0x0C
380#define AC97_MIC_VOL 0x0E*/
381#define AC97_MIC_20DB_ENABLE 0x40
382
383/*#define AC97_LINEIN_VOL 0x10
384#define AC97_CD_VOL 0x12
385#define AC97_VIDEO_VOL 0x14
386#define AC97_AUX_VOL 0x16*/
387#define AC97_PCM_OUT_VOL 0x18
388/*#define AC97_RECORD_SELECT 0x1A*/
389#define AC97_RECORD_MIC 0x00
390#define AC97_RECORD_CD 0x01
391#define AC97_RECORD_VIDEO 0x02
392#define AC97_RECORD_AUX 0x03
393#define AC97_RECORD_MONO_MUX 0x02
394#define AC97_RECORD_DIGITAL 0x03
395#define AC97_RECORD_LINE 0x04
396#define AC97_RECORD_STEREO 0x05
397#define AC97_RECORD_MONO 0x06
398#define AC97_RECORD_PHONE 0x07
399
400/*#define AC97_RECORD_GAIN 0x1C*/
401#define AC97_RECORD_VOL_M 0x0F
402
403/*#define AC97_GENERAL_PURPOSE 0x20*/
404#define AC97_POWER_DOWN_CTRL 0x26
405#define AC97_ADC_READY 0x0001
406#define AC97_DAC_READY 0x0002
407#define AC97_ANALOG_READY 0x0004
408#define AC97_VREF_ON 0x0008
409#define AC97_PR0 0x0100
410#define AC97_PR1 0x0200
411#define AC97_PR2 0x0400
412#define AC97_PR3 0x0800
413#define AC97_PR4 0x1000
414
415#define AC97_RESERVED1 0x28
416
417#define AC97_VENDOR_TEST 0x5A
418
419#define AC97_CLOCK_DELAY 0x5C
420#define AC97_LINEOUT_MUX_SEL 0x0001
421#define AC97_MONO_MUX_SEL 0x0002
422#define AC97_CLOCK_DELAY_SEL 0x1F
423#define AC97_DAC_CDS_SHIFT 6
424#define AC97_ADC_CDS_SHIFT 11
425
426#define AC97_MULTI_CHANNEL_SEL 0x74
427
428/*#define AC97_VENDOR_ID1 0x7C
429#define AC97_VENDOR_ID2 0x7E*/
430
431/*
432 * ASSP control regs
433 */
434#define DSP_PORT_TIMER_COUNT 0x06
435
436#define DSP_PORT_MEMORY_INDEX 0x80
437
438#define DSP_PORT_MEMORY_TYPE 0x82
439#define MEMTYPE_INTERNAL_CODE 0x0002
440#define MEMTYPE_INTERNAL_DATA 0x0003
441#define MEMTYPE_MASK 0x0003
442
443#define DSP_PORT_MEMORY_DATA 0x84
444
445#define DSP_PORT_CONTROL_REG_A 0xA2
446#define DSP_PORT_CONTROL_REG_B 0xA4
447#define DSP_PORT_CONTROL_REG_C 0xA6
448
449#define REV_A_CODE_MEMORY_BEGIN 0x0000
450#define REV_A_CODE_MEMORY_END 0x0FFF
451#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
452#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
453
454#define REV_B_CODE_MEMORY_BEGIN 0x0000
455#define REV_B_CODE_MEMORY_END 0x0BFF
456#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
457#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
458
459#define REV_A_DATA_MEMORY_BEGIN 0x1000
460#define REV_A_DATA_MEMORY_END 0x2FFF
461#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
462#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
463
464#define REV_B_DATA_MEMORY_BEGIN 0x1000
465#define REV_B_DATA_MEMORY_END 0x2BFF
466#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
467#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
468
469
470#define NUM_UNITS_KERNEL_CODE 16
471#define NUM_UNITS_KERNEL_DATA 2
472
473#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
474#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
475
476/*
477 * Kernel data layout
478 */
479
480#define DP_SHIFT_COUNT 7
481
482#define KDATA_BASE_ADDR 0x1000
483#define KDATA_BASE_ADDR2 0x1080
484
485#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
486#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
487#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
488#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
489#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
490#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
491#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
492#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
493#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
494
495#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
496#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
497
498#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
499#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
500#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
501#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
502#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
503#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
504#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
505#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
506#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
507#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
508
509#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
510#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
511
512#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
513#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
514
515#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
516#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
517
518#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
519#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
520#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
521
522#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
523#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
524#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
525#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
526#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
527
528#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
529#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
530#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
531
532#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
533#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
534#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
535
536#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
537#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
538#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
539#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
540#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
541#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
542#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
543#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
544#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
545#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
546
547#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
548#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
549#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
550
551#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
552#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
553
554#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
555#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
556#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
557
558#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
559#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
560#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
561#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
562#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
563#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
564
565#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
566#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
567#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
568#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
569#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
570#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
571
572#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
573#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
574#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
575#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
576#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
577#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
578
579#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
580#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
581#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
582#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
583
584#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
585#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
586
587#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
588#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
589
590#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
591#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
592#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
593#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
594#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
595
596#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
597#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
598
599#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
600#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
601#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
602
603#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
604#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
605
606#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
607
608#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
609#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
610#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
611#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
612#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
613#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
614#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
615#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
616#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
617#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
618#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
619#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
620
621#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
622#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
623#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
624#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
625
626#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
627#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
628
629#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
630#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
631#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
632#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
633
634#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
635#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
636#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
637#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
638#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
639
640/*
641 * second 'segment' (?) reserved for mixer
642 * buffers..
643 */
644
645#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
646#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
647#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
648#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
649#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
650#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
651#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
652#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
653#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
654#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
655#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
656#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
657#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
658#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
659#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
660#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
661
662#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
663#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
664#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
665#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
666#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
667#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
668#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
669#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
670#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
671#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
672#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
673
674#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
675#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
676#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
677#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
678#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
679#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
680
681#define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
682#define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
683#define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
684#define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
685
686/*
687 * client data area offsets
688 */
689#define CDATA_INSTANCE_READY 0x00
690
691#define CDATA_HOST_SRC_ADDRL 0x01
692#define CDATA_HOST_SRC_ADDRH 0x02
693#define CDATA_HOST_SRC_END_PLUS_1L 0x03
694#define CDATA_HOST_SRC_END_PLUS_1H 0x04
695#define CDATA_HOST_SRC_CURRENTL 0x05
696#define CDATA_HOST_SRC_CURRENTH 0x06
697
698#define CDATA_IN_BUF_CONNECT 0x07
699#define CDATA_OUT_BUF_CONNECT 0x08
700
701#define CDATA_IN_BUF_BEGIN 0x09
702#define CDATA_IN_BUF_END_PLUS_1 0x0A
703#define CDATA_IN_BUF_HEAD 0x0B
704#define CDATA_IN_BUF_TAIL 0x0C
705#define CDATA_OUT_BUF_BEGIN 0x0D
706#define CDATA_OUT_BUF_END_PLUS_1 0x0E
707#define CDATA_OUT_BUF_HEAD 0x0F
708#define CDATA_OUT_BUF_TAIL 0x10
709
710#define CDATA_DMA_CONTROL 0x11
711#define CDATA_RESERVED 0x12
712
713#define CDATA_FREQUENCY 0x13
714#define CDATA_LEFT_VOLUME 0x14
715#define CDATA_RIGHT_VOLUME 0x15
716#define CDATA_LEFT_SUR_VOL 0x16
717#define CDATA_RIGHT_SUR_VOL 0x17
718
719#define CDATA_HEADER_LEN 0x18
720
721#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
722#define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
723#define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
724#define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
725#define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
726#define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
727#define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
728#define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
729
730#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
731#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733#define MINISRC_BIQUAD_STAGE 2
734#define MINISRC_COEF_LOC 0x175
735
736#define DMACONTROL_BLOCK_MASK 0x000F
737#define DMAC_BLOCK0_SELECTOR 0x0000
738#define DMAC_BLOCK1_SELECTOR 0x0001
739#define DMAC_BLOCK2_SELECTOR 0x0002
740#define DMAC_BLOCK3_SELECTOR 0x0003
741#define DMAC_BLOCK4_SELECTOR 0x0004
742#define DMAC_BLOCK5_SELECTOR 0x0005
743#define DMAC_BLOCK6_SELECTOR 0x0006
744#define DMAC_BLOCK7_SELECTOR 0x0007
745#define DMAC_BLOCK8_SELECTOR 0x0008
746#define DMAC_BLOCK9_SELECTOR 0x0009
747#define DMAC_BLOCKA_SELECTOR 0x000A
748#define DMAC_BLOCKB_SELECTOR 0x000B
749#define DMAC_BLOCKC_SELECTOR 0x000C
750#define DMAC_BLOCKD_SELECTOR 0x000D
751#define DMAC_BLOCKE_SELECTOR 0x000E
752#define DMAC_BLOCKF_SELECTOR 0x000F
753#define DMACONTROL_PAGE_MASK 0x00F0
754#define DMAC_PAGE0_SELECTOR 0x0030
755#define DMAC_PAGE1_SELECTOR 0x0020
756#define DMAC_PAGE2_SELECTOR 0x0010
757#define DMAC_PAGE3_SELECTOR 0x0000
758#define DMACONTROL_AUTOREPEAT 0x1000
759#define DMACONTROL_STOPPED 0x2000
760#define DMACONTROL_DIRECTION 0x0100
761
762/*
763 * an arbitrary volume we set the internal
764 * volume settings to so that the ac97 volume
765 * range is a little less insane. 0x7fff is
766 * max.
767 */
768#define ARB_VOLUME ( 0x6800 )
769
770/*
771 */
772
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773struct m3_list {
774 int curlen;
775 int mem_addr;
776 int max;
777};
778
Takashi Iwai3470c292005-11-17 15:05:09 +0100779struct m3_dma {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700780
781 int number;
Takashi Iwai3470c292005-11-17 15:05:09 +0100782 struct snd_pcm_substream *substream;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783
784 struct assp_instance {
785 unsigned short code, data;
786 } inst;
787
788 int running;
789 int opened;
790
791 unsigned long buffer_addr;
792 int dma_size;
793 int period_size;
794 unsigned int hwptr;
795 int count;
796
797 int index[3];
798 struct m3_list *index_list[3];
799
800 int in_lists;
801
802 struct list_head list;
803
804};
805
806struct snd_m3 {
807
Takashi Iwai3470c292005-11-17 15:05:09 +0100808 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809
810 unsigned long iobase;
811
812 int irq;
813 unsigned int allegro_flag : 1;
814
Takashi Iwai3470c292005-11-17 15:05:09 +0100815 struct snd_ac97 *ac97;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816
Takashi Iwai3470c292005-11-17 15:05:09 +0100817 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818
819 struct pci_dev *pci;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820
821 int dacs_active;
822 int timer_users;
823
824 struct m3_list msrc_list;
825 struct m3_list mixer_list;
826 struct m3_list adc1_list;
827 struct m3_list dma_list;
828
829 /* for storing reset state..*/
830 u8 reset_state;
831
832 int external_amp;
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100833 int amp_gpio; /* gpio pin # for external amp, -1 = default */
834 unsigned int hv_config; /* hardware-volume config bits */
835 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
836 (e.g. for IrDA on Dell Inspirons) */
837 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838
839 /* midi */
Takashi Iwai3470c292005-11-17 15:05:09 +0100840 struct snd_rawmidi *rmidi;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841
842 /* pcm streams */
843 int num_substreams;
Takashi Iwai3470c292005-11-17 15:05:09 +0100844 struct m3_dma *substreams;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845
846 spinlock_t reg_lock;
Ville Syrjaladb68d152005-05-12 14:19:32 +0200847 spinlock_t ac97_lock;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
Takashi Iwai3470c292005-11-17 15:05:09 +0100849 struct snd_kcontrol *master_switch;
850 struct snd_kcontrol *master_volume;
Ville Syrjaladb68d152005-05-12 14:19:32 +0200851 struct tasklet_struct hwvol_tq;
Hans de Goede715aa672010-04-21 11:04:08 -0400852 unsigned int in_suspend;
Ville Syrjala82f008c2005-05-20 18:40:38 +0200853
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854#ifdef CONFIG_PM
855 u16 *suspend_mem;
856#endif
Clemens Ladisch81d77242006-11-06 09:26:41 +0100857
858 const struct firmware *assp_kernel_image;
859 const struct firmware *assp_minisrc_image;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860};
861
862/*
863 * pci ids
864 */
Alexey Dobriyancebe41d2010-02-06 00:21:03 +0200865static DEFINE_PCI_DEVICE_TABLE(snd_m3_ids) = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700866 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
867 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
868 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
869 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
870 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
871 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
872 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
873 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
874 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
875 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
876 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
877 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
878 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
879 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
880 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
881 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
882 {0,},
883};
884
885MODULE_DEVICE_TABLE(pci, snd_m3_ids);
886
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100887static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
Hans de Goede7efbfd12010-04-21 11:04:06 -0400888 SND_PCI_QUIRK(0x0E11, 0x0094, "Compaq Evo N600c", 0x0c),
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100889 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
890 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
891 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
892 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
893 { } /* END */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894};
895
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100896static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
897 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
898 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
899 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
900 { } /* END */
901};
902
903/* hardware volume quirks */
904static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
Ville Syrjala82f008c2005-05-20 18:40:38 +0200905 /* Allegro chips */
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100906 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
932 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
954 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
955 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
956 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
957 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
958 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
959 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
Ville Syrjala82f008c2005-05-20 18:40:38 +0200960 /* Maestro3 chips */
Takashi Iwai1061eeb2006-11-24 15:36:46 +0100961 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
977 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
978 { } /* END */
979};
980
981/* HP Omnibook quirks */
982static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
983 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
984 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
985 { } /* END */
Ville Syrjala82f008c2005-05-20 18:40:38 +0200986};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987
988/*
989 * lowlevel functions
990 */
991
Takashi Iwai3470c292005-11-17 15:05:09 +0100992static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993{
994 outw(value, chip->iobase + reg);
995}
996
Takashi Iwai3470c292005-11-17 15:05:09 +0100997static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998{
999 return inw(chip->iobase + reg);
1000}
1001
Takashi Iwai3470c292005-11-17 15:05:09 +01001002static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003{
1004 outb(value, chip->iobase + reg);
1005}
1006
Takashi Iwai3470c292005-11-17 15:05:09 +01001007static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001008{
1009 return inb(chip->iobase + reg);
1010}
1011
1012/*
1013 * access 16bit words to the code or data regions of the dsp's memory.
1014 * index addresses 16bit words.
1015 */
Takashi Iwai3470c292005-11-17 15:05:09 +01001016static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017{
1018 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1019 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1020 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1021}
1022
Takashi Iwai3470c292005-11-17 15:05:09 +01001023static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024{
1025 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1026 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1027 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1028}
1029
Takashi Iwai3470c292005-11-17 15:05:09 +01001030static void snd_m3_assp_halt(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031{
1032 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02001033 msleep(10);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1035}
1036
Takashi Iwai3470c292005-11-17 15:05:09 +01001037static void snd_m3_assp_continue(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038{
1039 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1040}
1041
1042
1043/*
1044 * This makes me sad. the maestro3 has lists
1045 * internally that must be packed.. 0 terminates,
1046 * apparently, or maybe all unused entries have
1047 * to be 0, the lists have static lengths set
1048 * by the binary code images.
1049 */
1050
Takashi Iwai3470c292005-11-17 15:05:09 +01001051static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052{
1053 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1054 list->mem_addr + list->curlen,
1055 val);
1056 return list->curlen++;
1057}
1058
Takashi Iwai3470c292005-11-17 15:05:09 +01001059static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060{
1061 u16 val;
1062 int lastindex = list->curlen - 1;
1063
1064 if (index != lastindex) {
1065 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1066 list->mem_addr + lastindex);
1067 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068 list->mem_addr + index,
1069 val);
1070 }
1071
1072 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073 list->mem_addr + lastindex,
1074 0);
1075
1076 list->curlen--;
1077}
1078
Takashi Iwai3470c292005-11-17 15:05:09 +01001079static void snd_m3_inc_timer_users(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080{
1081 chip->timer_users++;
1082 if (chip->timer_users != 1)
1083 return;
1084
1085 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1086 KDATA_TIMER_COUNT_RELOAD,
1087 240);
1088
1089 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1090 KDATA_TIMER_COUNT_CURRENT,
1091 240);
1092
1093 snd_m3_outw(chip,
1094 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1095 HOST_INT_CTRL);
1096}
1097
Takashi Iwai3470c292005-11-17 15:05:09 +01001098static void snd_m3_dec_timer_users(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099{
1100 chip->timer_users--;
1101 if (chip->timer_users > 0)
1102 return;
1103
1104 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1105 KDATA_TIMER_COUNT_RELOAD,
1106 0);
1107
1108 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1109 KDATA_TIMER_COUNT_CURRENT,
1110 0);
1111
1112 snd_m3_outw(chip,
1113 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1114 HOST_INT_CTRL);
1115}
1116
1117/*
1118 * start/stop
1119 */
1120
1121/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001122static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1123 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124{
1125 if (! s || ! subs)
1126 return -EINVAL;
1127
1128 snd_m3_inc_timer_users(chip);
1129 switch (subs->stream) {
1130 case SNDRV_PCM_STREAM_PLAYBACK:
1131 chip->dacs_active++;
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 s->inst.data + CDATA_INSTANCE_READY, 1);
1134 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135 KDATA_MIXER_TASK_NUMBER,
1136 chip->dacs_active);
1137 break;
1138 case SNDRV_PCM_STREAM_CAPTURE:
Takashi Iwai3470c292005-11-17 15:05:09 +01001139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 KDATA_ADC1_REQUEST, 1);
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 s->inst.data + CDATA_INSTANCE_READY, 1);
1143 break;
1144 }
1145 return 0;
1146}
1147
1148/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001149static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1150 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151{
1152 if (! s || ! subs)
1153 return -EINVAL;
1154
1155 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1156 s->inst.data + CDATA_INSTANCE_READY, 0);
1157 snd_m3_dec_timer_users(chip);
1158 switch (subs->stream) {
1159 case SNDRV_PCM_STREAM_PLAYBACK:
1160 chip->dacs_active--;
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 KDATA_MIXER_TASK_NUMBER,
1163 chip->dacs_active);
1164 break;
1165 case SNDRV_PCM_STREAM_CAPTURE:
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 KDATA_ADC1_REQUEST, 0);
1168 break;
1169 }
1170 return 0;
1171}
1172
1173static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001174snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175{
Takashi Iwai3470c292005-11-17 15:05:09 +01001176 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1177 struct m3_dma *s = subs->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001178 int err = -EINVAL;
1179
Takashi Iwaida3cec32008-08-08 17:12:14 +02001180 if (snd_BUG_ON(!s))
1181 return -ENXIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001182
1183 spin_lock(&chip->reg_lock);
1184 switch (cmd) {
1185 case SNDRV_PCM_TRIGGER_START:
1186 case SNDRV_PCM_TRIGGER_RESUME:
1187 if (s->running)
1188 err = -EBUSY;
1189 else {
1190 s->running = 1;
1191 err = snd_m3_pcm_start(chip, s, subs);
1192 }
1193 break;
1194 case SNDRV_PCM_TRIGGER_STOP:
1195 case SNDRV_PCM_TRIGGER_SUSPEND:
1196 if (! s->running)
1197 err = 0; /* should return error? */
1198 else {
1199 s->running = 0;
1200 err = snd_m3_pcm_stop(chip, s, subs);
1201 }
1202 break;
1203 }
1204 spin_unlock(&chip->reg_lock);
1205 return err;
1206}
1207
1208/*
1209 * setup
1210 */
1211static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001212snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213{
1214 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
Takashi Iwai3470c292005-11-17 15:05:09 +01001215 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216
1217 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1218 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1219 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1220 } else {
1221 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1222 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1223 }
1224 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1225 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1226
1227 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1228 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1229 s->hwptr = 0;
1230 s->count = 0;
1231
1232#define LO(x) ((x) & 0xffff)
1233#define HI(x) LO((x) >> 16)
1234
1235 /* host dma buffer pointers */
1236 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1237 s->inst.data + CDATA_HOST_SRC_ADDRL,
1238 LO(s->buffer_addr));
1239
1240 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1241 s->inst.data + CDATA_HOST_SRC_ADDRH,
1242 HI(s->buffer_addr));
1243
1244 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1245 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1246 LO(s->buffer_addr + s->dma_size));
1247
1248 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1249 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1250 HI(s->buffer_addr + s->dma_size));
1251
1252 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1253 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1254 LO(s->buffer_addr));
1255
1256 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1257 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1258 HI(s->buffer_addr));
1259#undef LO
1260#undef HI
1261
1262 /* dsp buffers */
1263
1264 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1265 s->inst.data + CDATA_IN_BUF_BEGIN,
1266 dsp_in_buffer);
1267
1268 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1269 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1270 dsp_in_buffer + (dsp_in_size / 2));
1271
1272 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1273 s->inst.data + CDATA_IN_BUF_HEAD,
1274 dsp_in_buffer);
1275
1276 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1277 s->inst.data + CDATA_IN_BUF_TAIL,
1278 dsp_in_buffer);
1279
1280 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1281 s->inst.data + CDATA_OUT_BUF_BEGIN,
1282 dsp_out_buffer);
1283
1284 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1285 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1286 dsp_out_buffer + (dsp_out_size / 2));
1287
1288 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1289 s->inst.data + CDATA_OUT_BUF_HEAD,
1290 dsp_out_buffer);
1291
1292 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1293 s->inst.data + CDATA_OUT_BUF_TAIL,
1294 dsp_out_buffer);
1295}
1296
Takashi Iwai3470c292005-11-17 15:05:09 +01001297static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1298 struct snd_pcm_runtime *runtime)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001299{
1300 u32 freq;
1301
1302 /*
1303 * put us in the lists if we're not already there
1304 */
1305 if (! s->in_lists) {
1306 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1307 s->inst.data >> DP_SHIFT_COUNT);
1308 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1309 s->inst.data >> DP_SHIFT_COUNT);
1310 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1311 s->inst.data >> DP_SHIFT_COUNT);
1312 s->in_lists = 1;
1313 }
1314
1315 /* write to 'mono' word */
1316 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1317 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1318 runtime->channels == 2 ? 0 : 1);
1319 /* write to '8bit' word */
1320 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1321 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1322 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1323
1324 /* set up dac/adc rate */
1325 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1326 if (freq)
1327 freq--;
1328
1329 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1330 s->inst.data + CDATA_FREQUENCY,
1331 freq);
1332}
1333
1334
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001335static const struct play_vals {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001336 u16 addr, val;
1337} pv[] = {
1338 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1339 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1340 {SRC3_DIRECTION_OFFSET, 0} ,
1341 /* +1, +2 are stereo/16 bit */
1342 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1343 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1344 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1345 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1346 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1347 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1348 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1349 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1350 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1351 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1352 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1353 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1354 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1355 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1356 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1357 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1358 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1359};
1360
1361
1362/* the mode passed should be already shifted and masked */
1363static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001364snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1365 struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366{
1367 unsigned int i;
1368
1369 /*
1370 * some per client initializers
1371 */
1372
1373 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1374 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1375 s->inst.data + 40 + 8);
1376
1377 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1378 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1379 s->inst.code + MINISRC_COEF_LOC);
1380
1381 /* enable or disable low pass filter? */
1382 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1383 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1384 subs->runtime->rate > 45000 ? 0xff : 0);
1385
1386 /* tell it which way dma is going? */
1387 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1388 s->inst.data + CDATA_DMA_CONTROL,
1389 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1390
1391 /*
1392 * set an armload of static initializers
1393 */
1394 for (i = 0; i < ARRAY_SIZE(pv); i++)
1395 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1396 s->inst.data + pv[i].addr, pv[i].val);
1397}
1398
1399/*
1400 * Native record driver
1401 */
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001402static const struct rec_vals {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403 u16 addr, val;
1404} rv[] = {
1405 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1406 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1407 {SRC3_DIRECTION_OFFSET, 1} ,
1408 /* +1, +2 are stereo/16 bit */
1409 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1410 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1411 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1412 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1413 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1414 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1415 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1416 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1417 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1418 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1419 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1420 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1421 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1422 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1423 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1424 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1425 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1426 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1427 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1428};
1429
1430static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001431snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432{
1433 unsigned int i;
1434
1435 /*
1436 * some per client initializers
1437 */
1438
1439 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1440 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1441 s->inst.data + 40 + 8);
1442
1443 /* tell it which way dma is going? */
1444 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1445 s->inst.data + CDATA_DMA_CONTROL,
1446 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1447 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1448
1449 /*
1450 * set an armload of static initializers
1451 */
1452 for (i = 0; i < ARRAY_SIZE(rv); i++)
1453 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1454 s->inst.data + rv[i].addr, rv[i].val);
1455}
1456
Takashi Iwai3470c292005-11-17 15:05:09 +01001457static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1458 struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459{
Takashi Iwai3470c292005-11-17 15:05:09 +01001460 struct m3_dma *s = substream->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461 int err;
1462
1463 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1464 return err;
1465 /* set buffer address */
1466 s->buffer_addr = substream->runtime->dma_addr;
1467 if (s->buffer_addr & 0x3) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02001468 snd_printk(KERN_ERR "oh my, not aligned\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001469 s->buffer_addr = s->buffer_addr & ~0x3;
1470 }
1471 return 0;
1472}
1473
Takashi Iwai3470c292005-11-17 15:05:09 +01001474static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001475{
Takashi Iwai3470c292005-11-17 15:05:09 +01001476 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477
1478 if (substream->runtime->private_data == NULL)
1479 return 0;
Takashi Iwai3470c292005-11-17 15:05:09 +01001480 s = substream->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481 snd_pcm_lib_free_pages(substream);
1482 s->buffer_addr = 0;
1483 return 0;
1484}
1485
1486static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001487snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001488{
Takashi Iwai3470c292005-11-17 15:05:09 +01001489 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1490 struct snd_pcm_runtime *runtime = subs->runtime;
1491 struct m3_dma *s = runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492
Takashi Iwaida3cec32008-08-08 17:12:14 +02001493 if (snd_BUG_ON(!s))
1494 return -ENXIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495
1496 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1497 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1498 return -EINVAL;
1499 if (runtime->rate > 48000 ||
1500 runtime->rate < 8000)
1501 return -EINVAL;
1502
1503 spin_lock_irq(&chip->reg_lock);
1504
1505 snd_m3_pcm_setup1(chip, s, subs);
1506
1507 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1508 snd_m3_playback_setup(chip, s, subs);
1509 else
1510 snd_m3_capture_setup(chip, s, subs);
1511
1512 snd_m3_pcm_setup2(chip, s, runtime);
1513
1514 spin_unlock_irq(&chip->reg_lock);
1515
1516 return 0;
1517}
1518
1519/*
1520 * get current pointer
1521 */
1522static unsigned int
Takashi Iwai3470c292005-11-17 15:05:09 +01001523snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524{
1525 u16 hi = 0, lo = 0;
1526 int retry = 10;
1527 u32 addr;
1528
1529 /*
1530 * try and get a valid answer
1531 */
1532 while (retry--) {
1533 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1534 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1535
1536 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1537 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1538
1539 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1540 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1541 break;
1542 }
1543 addr = lo | ((u32)hi<<16);
1544 return (unsigned int)(addr - s->buffer_addr);
1545}
1546
1547static snd_pcm_uframes_t
Takashi Iwai3470c292005-11-17 15:05:09 +01001548snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549{
Takashi Iwai3470c292005-11-17 15:05:09 +01001550 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551 unsigned int ptr;
Takashi Iwai3470c292005-11-17 15:05:09 +01001552 struct m3_dma *s = subs->runtime->private_data;
Takashi Iwaida3cec32008-08-08 17:12:14 +02001553
1554 if (snd_BUG_ON(!s))
1555 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556
1557 spin_lock(&chip->reg_lock);
1558 ptr = snd_m3_get_pointer(chip, s, subs);
1559 spin_unlock(&chip->reg_lock);
1560 return bytes_to_frames(subs->runtime, ptr);
1561}
1562
1563
1564/* update pointer */
1565/* spinlock held! */
Takashi Iwai3470c292005-11-17 15:05:09 +01001566static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001567{
Takashi Iwai3470c292005-11-17 15:05:09 +01001568 struct snd_pcm_substream *subs = s->substream;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569 unsigned int hwptr;
1570 int diff;
1571
1572 if (! s->running)
1573 return;
1574
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001575 hwptr = snd_m3_get_pointer(chip, s, subs);
1576
1577 /* try to avoid expensive modulo divisions */
1578 if (hwptr >= s->dma_size)
1579 hwptr %= s->dma_size;
1580
1581 diff = s->dma_size + hwptr - s->hwptr;
1582 if (diff >= s->dma_size)
1583 diff %= s->dma_size;
1584
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585 s->hwptr = hwptr;
1586 s->count += diff;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001587
Linus Torvalds1da177e2005-04-16 15:20:36 -07001588 if (s->count >= (signed)s->period_size) {
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001589
1590 if (s->count < 2 * (signed)s->period_size)
1591 s->count -= (signed)s->period_size;
1592 else
1593 s->count %= s->period_size;
1594
Linus Torvalds1da177e2005-04-16 15:20:36 -07001595 spin_unlock(&chip->reg_lock);
1596 snd_pcm_period_elapsed(subs);
1597 spin_lock(&chip->reg_lock);
1598 }
1599}
1600
Hans de Goede20133d42010-04-21 11:04:07 -04001601/* The m3's hardware volume works by incrementing / decrementing 2 counters
1602 (without wrap around) in response to volume button presses and then
1603 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1604 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001605static void snd_m3_update_hw_volume(unsigned long private_data)
1606{
Takashi Iwai3470c292005-11-17 15:05:09 +01001607 struct snd_m3 *chip = (struct snd_m3 *) private_data;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001608 int x, val;
1609 unsigned long flags;
1610
1611 /* Figure out which volume control button was pushed,
1612 based on differences from the default register
1613 values. */
1614 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1615
Hans de Goede20133d42010-04-21 11:04:07 -04001616 /* Reset the volume counters to 4. Tests on the allegro integrated
1617 into a Compaq N600C laptop, have revealed that:
1618 1) Writing any value will result in the 2 counters being reset to
1619 4 so writing 0x88 is not strictly necessary
1620 2) Writing to any of the 4 involved registers will reset all 4
1621 of them (and reading them always returns the same value for all
1622 of them)
1623 It could be that a maestro deviates from this, so leave the code
1624 as is. */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001625 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1626 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1627 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1628 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1629
Hans de Goede715aa672010-04-21 11:04:08 -04001630 /* Ignore spurious HV interrupts during suspend / resume, this avoids
1631 mistaking them for a mute button press. */
1632 if (chip->in_suspend)
1633 return;
1634
Ville Syrjaladb68d152005-05-12 14:19:32 +02001635 if (!chip->master_switch || !chip->master_volume)
1636 return;
1637
1638 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1639 spin_lock_irqsave(&chip->ac97_lock, flags);
1640
1641 val = chip->ac97->regs[AC97_MASTER_VOL];
1642 switch (x) {
1643 case 0x88:
Hans de Goede20133d42010-04-21 11:04:07 -04001644 /* The counters have not changed, yet we've received a HV
1645 interrupt. According to tests run by various people this
1646 happens when pressing the mute button. */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001647 val ^= 0x8000;
1648 chip->ac97->regs[AC97_MASTER_VOL] = val;
1649 outw(val, chip->iobase + CODEC_DATA);
1650 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1651 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1652 &chip->master_switch->id);
1653 break;
1654 case 0xaa:
Hans de Goede20133d42010-04-21 11:04:07 -04001655 /* counters increased by 1 -> volume up */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001656 if ((val & 0x7f) > 0)
1657 val--;
1658 if ((val & 0x7f00) > 0)
1659 val -= 0x0100;
1660 chip->ac97->regs[AC97_MASTER_VOL] = val;
1661 outw(val, chip->iobase + CODEC_DATA);
1662 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1663 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1664 &chip->master_volume->id);
1665 break;
1666 case 0x66:
Hans de Goede20133d42010-04-21 11:04:07 -04001667 /* counters decreased by 1 -> volume down */
Ville Syrjaladb68d152005-05-12 14:19:32 +02001668 if ((val & 0x7f) < 0x1f)
1669 val++;
1670 if ((val & 0x7f00) < 0x1f00)
1671 val += 0x0100;
1672 chip->ac97->regs[AC97_MASTER_VOL] = val;
1673 outw(val, chip->iobase + CODEC_DATA);
1674 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1675 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1676 &chip->master_volume->id);
1677 break;
1678 }
1679 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1680}
1681
David Howells7d12e782006-10-05 14:55:46 +01001682static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683{
Takashi Iwai3470c292005-11-17 15:05:09 +01001684 struct snd_m3 *chip = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685 u8 status;
1686 int i;
1687
1688 status = inb(chip->iobase + HOST_INT_STATUS);
1689
1690 if (status == 0xff)
1691 return IRQ_NONE;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001692
1693 if (status & HV_INT_PENDING)
Takashi Iwai1f041282008-12-18 12:17:55 +01001694 tasklet_schedule(&chip->hwvol_tq);
Ville Syrjaladb68d152005-05-12 14:19:32 +02001695
Linus Torvalds1da177e2005-04-16 15:20:36 -07001696 /*
1697 * ack an assp int if its running
1698 * and has an int pending
1699 */
1700 if (status & ASSP_INT_PENDING) {
1701 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1702 if (!(ctl & STOP_ASSP_CLOCK)) {
1703 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1704 if (ctl & DSP2HOST_REQ_TIMER) {
1705 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1706 /* update adc/dac info if it was a timer int */
1707 spin_lock(&chip->reg_lock);
1708 for (i = 0; i < chip->num_substreams; i++) {
Takashi Iwai3470c292005-11-17 15:05:09 +01001709 struct m3_dma *s = &chip->substreams[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710 if (s->running)
1711 snd_m3_update_ptr(chip, s);
1712 }
1713 spin_unlock(&chip->reg_lock);
1714 }
1715 }
1716 }
1717
1718#if 0 /* TODO: not supported yet */
1719 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1720 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1721#endif
1722
1723 /* ack ints */
Ville Syrjala88491382005-05-12 14:14:28 +02001724 outb(status, chip->iobase + HOST_INT_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725
1726 return IRQ_HANDLED;
1727}
1728
1729
1730/*
1731 */
1732
Takashi Iwai3470c292005-11-17 15:05:09 +01001733static struct snd_pcm_hardware snd_m3_playback =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001734{
1735 .info = (SNDRV_PCM_INFO_MMAP |
1736 SNDRV_PCM_INFO_INTERLEAVED |
1737 SNDRV_PCM_INFO_MMAP_VALID |
1738 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1739 /*SNDRV_PCM_INFO_PAUSE |*/
1740 SNDRV_PCM_INFO_RESUME),
1741 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1742 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1743 .rate_min = 8000,
1744 .rate_max = 48000,
1745 .channels_min = 1,
1746 .channels_max = 2,
1747 .buffer_bytes_max = (512*1024),
1748 .period_bytes_min = 64,
1749 .period_bytes_max = (512*1024),
1750 .periods_min = 1,
1751 .periods_max = 1024,
1752};
1753
Takashi Iwai3470c292005-11-17 15:05:09 +01001754static struct snd_pcm_hardware snd_m3_capture =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001755{
1756 .info = (SNDRV_PCM_INFO_MMAP |
1757 SNDRV_PCM_INFO_INTERLEAVED |
1758 SNDRV_PCM_INFO_MMAP_VALID |
1759 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1760 /*SNDRV_PCM_INFO_PAUSE |*/
1761 SNDRV_PCM_INFO_RESUME),
1762 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1763 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1764 .rate_min = 8000,
1765 .rate_max = 48000,
1766 .channels_min = 1,
1767 .channels_max = 2,
1768 .buffer_bytes_max = (512*1024),
1769 .period_bytes_min = 64,
1770 .period_bytes_max = (512*1024),
1771 .periods_min = 1,
1772 .periods_max = 1024,
1773};
1774
1775
1776/*
1777 */
1778
1779static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001780snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001781{
1782 int i;
Takashi Iwai3470c292005-11-17 15:05:09 +01001783 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784
1785 spin_lock_irq(&chip->reg_lock);
1786 for (i = 0; i < chip->num_substreams; i++) {
1787 s = &chip->substreams[i];
1788 if (! s->opened)
1789 goto __found;
1790 }
1791 spin_unlock_irq(&chip->reg_lock);
1792 return -ENOMEM;
1793__found:
1794 s->opened = 1;
1795 s->running = 0;
1796 spin_unlock_irq(&chip->reg_lock);
1797
1798 subs->runtime->private_data = s;
1799 s->substream = subs;
1800
1801 /* set list owners */
1802 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1803 s->index_list[0] = &chip->mixer_list;
1804 } else
1805 s->index_list[0] = &chip->adc1_list;
1806 s->index_list[1] = &chip->msrc_list;
1807 s->index_list[2] = &chip->dma_list;
1808
1809 return 0;
1810}
1811
1812static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001813snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814{
Takashi Iwai3470c292005-11-17 15:05:09 +01001815 struct m3_dma *s = subs->runtime->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816
1817 if (s == NULL)
1818 return; /* not opened properly */
1819
1820 spin_lock_irq(&chip->reg_lock);
1821 if (s->substream && s->running)
1822 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1823 if (s->in_lists) {
1824 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1825 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1826 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1827 s->in_lists = 0;
1828 }
1829 s->running = 0;
1830 s->opened = 0;
1831 spin_unlock_irq(&chip->reg_lock);
1832}
1833
1834static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001835snd_m3_playback_open(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836{
Takashi Iwai3470c292005-11-17 15:05:09 +01001837 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1838 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839 int err;
1840
1841 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1842 return err;
1843
1844 runtime->hw = snd_m3_playback;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845
1846 return 0;
1847}
1848
1849static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001850snd_m3_playback_close(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851{
Takashi Iwai3470c292005-11-17 15:05:09 +01001852 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001853
1854 snd_m3_substream_close(chip, subs);
1855 return 0;
1856}
1857
1858static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001859snd_m3_capture_open(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001860{
Takashi Iwai3470c292005-11-17 15:05:09 +01001861 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1862 struct snd_pcm_runtime *runtime = subs->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863 int err;
1864
1865 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1866 return err;
1867
1868 runtime->hw = snd_m3_capture;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001869
1870 return 0;
1871}
1872
1873static int
Takashi Iwai3470c292005-11-17 15:05:09 +01001874snd_m3_capture_close(struct snd_pcm_substream *subs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875{
Takashi Iwai3470c292005-11-17 15:05:09 +01001876 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877
1878 snd_m3_substream_close(chip, subs);
1879 return 0;
1880}
1881
1882/*
1883 * create pcm instance
1884 */
1885
Takashi Iwai3470c292005-11-17 15:05:09 +01001886static struct snd_pcm_ops snd_m3_playback_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001887 .open = snd_m3_playback_open,
1888 .close = snd_m3_playback_close,
1889 .ioctl = snd_pcm_lib_ioctl,
1890 .hw_params = snd_m3_pcm_hw_params,
1891 .hw_free = snd_m3_pcm_hw_free,
1892 .prepare = snd_m3_pcm_prepare,
1893 .trigger = snd_m3_pcm_trigger,
1894 .pointer = snd_m3_pcm_pointer,
1895};
1896
Takashi Iwai3470c292005-11-17 15:05:09 +01001897static struct snd_pcm_ops snd_m3_capture_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898 .open = snd_m3_capture_open,
1899 .close = snd_m3_capture_close,
1900 .ioctl = snd_pcm_lib_ioctl,
1901 .hw_params = snd_m3_pcm_hw_params,
1902 .hw_free = snd_m3_pcm_hw_free,
1903 .prepare = snd_m3_pcm_prepare,
1904 .trigger = snd_m3_pcm_trigger,
1905 .pointer = snd_m3_pcm_pointer,
1906};
1907
1908static int __devinit
Takashi Iwai3470c292005-11-17 15:05:09 +01001909snd_m3_pcm(struct snd_m3 * chip, int device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910{
Takashi Iwai3470c292005-11-17 15:05:09 +01001911 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912 int err;
1913
1914 err = snd_pcm_new(chip->card, chip->card->driver, device,
1915 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1916 if (err < 0)
1917 return err;
1918
1919 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1920 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1921
1922 pcm->private_data = chip;
1923 pcm->info_flags = 0;
1924 strcpy(pcm->name, chip->card->driver);
1925 chip->pcm = pcm;
1926
1927 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1928 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1929
1930 return 0;
1931}
1932
1933
1934/*
1935 * ac97 interface
1936 */
1937
1938/*
1939 * Wait for the ac97 serial bus to be free.
1940 * return nonzero if the bus is still busy.
1941 */
Takashi Iwai3470c292005-11-17 15:05:09 +01001942static int snd_m3_ac97_wait(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001943{
1944 int i = 10000;
1945
1946 do {
1947 if (! (snd_m3_inb(chip, 0x30) & 1))
1948 return 0;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001949 cpu_relax();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001950 } while (i-- > 0);
1951
Takashi Iwai99b359b2005-10-20 18:26:44 +02001952 snd_printk(KERN_ERR "ac97 serial bus busy\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001953 return 1;
1954}
1955
1956static unsigned short
Takashi Iwai3470c292005-11-17 15:05:09 +01001957snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001958{
Takashi Iwai3470c292005-11-17 15:05:09 +01001959 struct snd_m3 *chip = ac97->private_data;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001960 unsigned long flags;
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001961 unsigned short data = 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962
1963 if (snd_m3_ac97_wait(chip))
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001964 goto fail;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001965 spin_lock_irqsave(&chip->ac97_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001966 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1967 if (snd_m3_ac97_wait(chip))
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001968 goto fail_unlock;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001969 data = snd_m3_inw(chip, CODEC_DATA);
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001970fail_unlock:
Ville Syrjaladb68d152005-05-12 14:19:32 +02001971 spin_unlock_irqrestore(&chip->ac97_lock, flags);
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02001972fail:
Ville Syrjaladb68d152005-05-12 14:19:32 +02001973 return data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001974}
1975
1976static void
Takashi Iwai3470c292005-11-17 15:05:09 +01001977snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001978{
Takashi Iwai3470c292005-11-17 15:05:09 +01001979 struct snd_m3 *chip = ac97->private_data;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001980 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001981
1982 if (snd_m3_ac97_wait(chip))
1983 return;
Ville Syrjaladb68d152005-05-12 14:19:32 +02001984 spin_lock_irqsave(&chip->ac97_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985 snd_m3_outw(chip, val, CODEC_DATA);
1986 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
Ville Syrjaladb68d152005-05-12 14:19:32 +02001987 spin_unlock_irqrestore(&chip->ac97_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001988}
1989
1990
1991static void snd_m3_remote_codec_config(int io, int isremote)
1992{
1993 isremote = isremote ? 1 : 0;
1994
1995 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1996 io + RING_BUS_CTRL_B);
1997 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1998 io + SDO_OUT_DEST_CTRL);
1999 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
2000 io + SDO_IN_DEST_CTRL);
2001}
2002
2003/*
2004 * hack, returns non zero on err
2005 */
Takashi Iwai3470c292005-11-17 15:05:09 +01002006static int snd_m3_try_read_vendor(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007{
2008 u16 ret;
2009
2010 if (snd_m3_ac97_wait(chip))
2011 return 1;
2012
2013 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
2014
2015 if (snd_m3_ac97_wait(chip))
2016 return 1;
2017
2018 ret = snd_m3_inw(chip, 0x32);
2019
2020 return (ret == 0) || (ret == 0xffff);
2021}
2022
Takashi Iwai3470c292005-11-17 15:05:09 +01002023static void snd_m3_ac97_reset(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002024{
2025 u16 dir;
2026 int delay1 = 0, delay2 = 0, i;
2027 int io = chip->iobase;
2028
2029 if (chip->allegro_flag) {
2030 /*
2031 * the onboard codec on the allegro seems
2032 * to want to wait a very long time before
2033 * coming back to life
2034 */
2035 delay1 = 50;
2036 delay2 = 800;
2037 } else {
2038 /* maestro3 */
2039 delay1 = 20;
2040 delay2 = 500;
2041 }
2042
2043 for (i = 0; i < 5; i++) {
2044 dir = inw(io + GPIO_DIRECTION);
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002045 if (!chip->irda_workaround)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002046 dir |= 0x10; /* assuming pci bus master? */
2047
2048 snd_m3_remote_codec_config(io, 0);
2049
2050 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2051 udelay(20);
2052
2053 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2054 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2055 outw(0, io + GPIO_DATA);
2056 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2057
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002058 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002059
2060 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2061 udelay(5);
2062 /* ok, bring back the ac-link */
2063 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2064 outw(~0, io + GPIO_MASK);
2065
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002066 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067
2068 if (! snd_m3_try_read_vendor(chip))
2069 break;
2070
2071 delay1 += 10;
2072 delay2 += 100;
2073
2074 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2075 delay1, delay2);
2076 }
2077
2078#if 0
2079 /* more gung-ho reset that doesn't
2080 * seem to work anywhere :)
2081 */
2082 tmp = inw(io + RING_BUS_CTRL_A);
2083 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002084 msleep(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085 outw(tmp, io + RING_BUS_CTRL_A);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002086 msleep(50);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087#endif
2088}
2089
Takashi Iwai3470c292005-11-17 15:05:09 +01002090static int __devinit snd_m3_mixer(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002091{
Takashi Iwai3470c292005-11-17 15:05:09 +01002092 struct snd_ac97_bus *pbus;
2093 struct snd_ac97_template ac97;
Harvey Harrisone37273d2008-02-28 11:56:37 +01002094 struct snd_ctl_elem_id elem_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095 int err;
Takashi Iwai3470c292005-11-17 15:05:09 +01002096 static struct snd_ac97_bus_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002097 .write = snd_m3_ac97_write,
2098 .read = snd_m3_ac97_read,
2099 };
2100
2101 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2102 return err;
2103
2104 memset(&ac97, 0, sizeof(ac97));
2105 ac97.private_data = chip;
2106 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2107 return err;
2108
2109 /* seems ac97 PCM needs initialization.. hack hack.. */
2110 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
Nishanth Aravamudan8433a502005-10-24 15:02:37 +02002111 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002112 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2113
Harvey Harrisone37273d2008-02-28 11:56:37 +01002114 memset(&elem_id, 0, sizeof(elem_id));
2115 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2116 strcpy(elem_id.name, "Master Playback Switch");
2117 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2118 memset(&elem_id, 0, sizeof(elem_id));
2119 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2120 strcpy(elem_id.name, "Master Playback Volume");
2121 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
Ville Syrjaladb68d152005-05-12 14:19:32 +02002122
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123 return 0;
2124}
2125
2126
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127/*
2128 * initialize ASSP
2129 */
2130
2131#define MINISRC_LPF_LEN 10
Takashi Iwaif40b6892006-07-05 16:51:05 +02002132static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002133 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2134 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2135};
2136
Takashi Iwaif40b6892006-07-05 16:51:05 +02002137static void snd_m3_assp_init(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002138{
2139 unsigned int i;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002140 const u16 *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141
2142 /* zero kernel data */
2143 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2144 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2145 KDATA_BASE_ADDR + i, 0);
2146
2147 /* zero mixer data? */
2148 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2149 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2150 KDATA_BASE_ADDR2 + i, 0);
2151
2152 /* init dma pointer */
2153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2154 KDATA_CURRENT_DMA,
2155 KDATA_DMA_XFER0);
2156
2157 /* write kernel into code memory.. */
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002158 data = (const u16 *)chip->assp_kernel_image->data;
Clemens Ladisch81d77242006-11-06 09:26:41 +01002159 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002160 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002161 REV_B_CODE_MEMORY_BEGIN + i,
2162 le16_to_cpu(data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002163 }
2164
2165 /*
2166 * We only have this one client and we know that 0x400
2167 * is free in our kernel's mem map, so lets just
2168 * drop it there. It seems that the minisrc doesn't
2169 * need vectors, so we won't bother with them..
2170 */
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002171 data = (const u16 *)chip->assp_minisrc_image->data;
Clemens Ladisch81d77242006-11-06 09:26:41 +01002172 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002174 0x400 + i, le16_to_cpu(data[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175 }
2176
2177 /*
2178 * write the coefficients for the low pass filter?
2179 */
2180 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2181 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2182 0x400 + MINISRC_COEF_LOC + i,
2183 minisrc_lpf[i]);
2184 }
2185
2186 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2187 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2188 0x8000);
2189
2190 /*
2191 * the minisrc is the only thing on
2192 * our task list..
2193 */
2194 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2195 KDATA_TASK0,
2196 0x400);
2197
2198 /*
2199 * init the mixer number..
2200 */
2201
2202 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2203 KDATA_MIXER_TASK_NUMBER,0);
2204
2205 /*
2206 * EXTREME KERNEL MASTER VOLUME
2207 */
2208 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2209 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2210 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2211 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2212
2213 chip->mixer_list.curlen = 0;
2214 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2215 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2216 chip->adc1_list.curlen = 0;
2217 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2218 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2219 chip->dma_list.curlen = 0;
2220 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2221 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2222 chip->msrc_list.curlen = 0;
2223 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2224 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2225}
2226
2227
Takashi Iwai3470c292005-11-17 15:05:09 +01002228static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229{
2230 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2231 MINISRC_IN_BUFFER_SIZE / 2 +
2232 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2233 int address, i;
2234
2235 /*
2236 * the revb memory map has 0x1100 through 0x1c00
2237 * free.
2238 */
2239
2240 /*
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002241 * align instance address to 256 bytes so that its
Linus Torvalds1da177e2005-04-16 15:20:36 -07002242 * shifted list address is aligned.
2243 * list address = (mem address >> 1) >> 7;
2244 */
Clemens Ladisch7ab39922006-10-09 08:13:32 +02002245 data_bytes = ALIGN(data_bytes, 256);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246 address = 0x1100 + ((data_bytes/2) * index);
2247
2248 if ((address + (data_bytes/2)) >= 0x1c00) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002249 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002250 data_bytes, index, address);
2251 return -ENOMEM;
2252 }
2253
2254 s->number = index;
2255 s->inst.code = 0x400;
2256 s->inst.data = address;
2257
2258 for (i = data_bytes / 2; i > 0; address++, i--) {
2259 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2260 address, 0);
2261 }
2262
2263 return 0;
2264}
2265
2266
2267/*
2268 * this works for the reference board, have to find
2269 * out about others
2270 *
2271 * this needs more magic for 4 speaker, but..
2272 */
2273static void
Takashi Iwai3470c292005-11-17 15:05:09 +01002274snd_m3_amp_enable(struct snd_m3 *chip, int enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002275{
2276 int io = chip->iobase;
2277 u16 gpo, polarity;
2278
2279 if (! chip->external_amp)
2280 return;
2281
2282 polarity = enable ? 0 : 1;
2283 polarity = polarity << chip->amp_gpio;
2284 gpo = 1 << chip->amp_gpio;
2285
2286 outw(~gpo, io + GPIO_MASK);
2287
2288 outw(inw(io + GPIO_DIRECTION) | gpo,
2289 io + GPIO_DIRECTION);
2290
2291 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2292 io + GPIO_DATA);
2293
2294 outw(0xffff, io + GPIO_MASK);
2295}
2296
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002297static void
2298snd_m3_hv_init(struct snd_m3 *chip)
2299{
2300 unsigned long io = chip->iobase;
2301 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2302
2303 if (!chip->is_omnibook)
2304 return;
2305
2306 /*
2307 * Volume buttons on some HP OmniBook laptops
2308 * require some GPIO magic to work correctly.
2309 */
2310 outw(0xffff, io + GPIO_MASK);
2311 outw(0x0000, io + GPIO_DATA);
2312
2313 outw(~val, io + GPIO_MASK);
2314 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2315 outw(val, io + GPIO_MASK);
2316
2317 outw(0xffff, io + GPIO_MASK);
2318}
2319
Linus Torvalds1da177e2005-04-16 15:20:36 -07002320static int
Takashi Iwai3470c292005-11-17 15:05:09 +01002321snd_m3_chip_init(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002322{
2323 struct pci_dev *pcidev = chip->pci;
Ville Syrjaladb68d152005-05-12 14:19:32 +02002324 unsigned long io = chip->iobase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002325 u32 n;
2326 u16 w;
2327 u8 t; /* makes as much sense as 'n', no? */
2328
2329 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2330 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2331 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2332 DISABLE_LEGACY);
2333 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2334
2335 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
Ville Syrjala82f008c2005-05-20 18:40:38 +02002336 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002337 n |= chip->hv_config;
Ville Syrjala82f008c2005-05-20 18:40:38 +02002338 /* For some reason we must always use reduced debounce. */
2339 n |= REDUCED_DEBOUNCE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002340 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2341 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2342
2343 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2344 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2345 n &= ~INT_CLK_SELECT;
2346 if (!chip->allegro_flag) {
2347 n &= ~INT_CLK_MULT_ENABLE;
2348 n |= INT_CLK_SRC_NOT_PCI;
2349 }
2350 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2351 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2352
2353 if (chip->allegro_flag) {
2354 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2355 n |= IN_CLK_12MHZ_SELECT;
2356 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2357 }
2358
2359 t = inb(chip->iobase + ASSP_CONTROL_A);
2360 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2361 t |= ASSP_CLK_49MHZ_SELECT;
2362 t |= ASSP_0_WS_ENABLE;
2363 outb(t, chip->iobase + ASSP_CONTROL_A);
2364
Charles R. Anderson051b5162005-10-18 18:04:36 +02002365 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002366 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2367
Ville Syrjaladb68d152005-05-12 14:19:32 +02002368 outb(0x00, io + HARDWARE_VOL_CTRL);
2369 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2370 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2371 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2372 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2373
Linus Torvalds1da177e2005-04-16 15:20:36 -07002374 return 0;
2375}
2376
2377static void
Takashi Iwai3470c292005-11-17 15:05:09 +01002378snd_m3_enable_ints(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002379{
2380 unsigned long io = chip->iobase;
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002381 unsigned short val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382
2383 /* TODO: MPU401 not supported yet */
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002384 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002385 if (chip->hv_config & HV_CTRL_ENABLE)
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002386 val |= HV_INT_ENABLE;
2387 outw(val, io + HOST_INT_CTRL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002388 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2389 io + ASSP_CONTROL_C);
2390}
2391
2392
2393/*
2394 */
2395
Takashi Iwai3470c292005-11-17 15:05:09 +01002396static int snd_m3_free(struct snd_m3 *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002397{
Takashi Iwai3470c292005-11-17 15:05:09 +01002398 struct m3_dma *s;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002399 int i;
2400
2401 if (chip->substreams) {
2402 spin_lock_irq(&chip->reg_lock);
2403 for (i = 0; i < chip->num_substreams; i++) {
2404 s = &chip->substreams[i];
2405 /* check surviving pcms; this should not happen though.. */
2406 if (s->substream && s->running)
2407 snd_m3_pcm_stop(chip, s, s->substream);
2408 }
2409 spin_unlock_irq(&chip->reg_lock);
2410 kfree(chip->substreams);
2411 }
2412 if (chip->iobase) {
Ville Syrjala88491382005-05-12 14:14:28 +02002413 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002414 }
2415
2416#ifdef CONFIG_PM
2417 vfree(chip->suspend_mem);
2418#endif
2419
Jeff Garzikf000fd82008-04-22 13:50:34 +02002420 if (chip->irq >= 0)
Takashi Iwai3470c292005-11-17 15:05:09 +01002421 free_irq(chip->irq, chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002422
2423 if (chip->iobase)
2424 pci_release_regions(chip->pci);
2425
Takashi Iwaib7dd2b32007-04-26 14:13:44 +02002426 release_firmware(chip->assp_kernel_image);
2427 release_firmware(chip->assp_minisrc_image);
Clemens Ladisch81d77242006-11-06 09:26:41 +01002428
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429 pci_disable_device(chip->pci);
2430 kfree(chip);
2431 return 0;
2432}
2433
2434
2435/*
2436 * APM support
2437 */
2438#ifdef CONFIG_PM
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002439static int m3_suspend(struct pci_dev *pci, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002440{
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002441 struct snd_card *card = pci_get_drvdata(pci);
2442 struct snd_m3 *chip = card->private_data;
Harvey Harrisone37273d2008-02-28 11:56:37 +01002443 int i, dsp_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002444
2445 if (chip->suspend_mem == NULL)
2446 return 0;
2447
Hans de Goede715aa672010-04-21 11:04:08 -04002448 chip->in_suspend = 1;
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002449 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002450 snd_pcm_suspend_all(chip->pcm);
2451 snd_ac97_suspend(chip->ac97);
2452
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002453 msleep(10); /* give the assp a chance to idle.. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454
2455 snd_m3_assp_halt(chip);
2456
2457 /* save dsp image */
Harvey Harrisone37273d2008-02-28 11:56:37 +01002458 dsp_index = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
Harvey Harrisone37273d2008-02-28 11:56:37 +01002460 chip->suspend_mem[dsp_index++] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07002461 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2462 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
Harvey Harrisone37273d2008-02-28 11:56:37 +01002463 chip->suspend_mem[dsp_index++] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07002464 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2465
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002466 pci_disable_device(pci);
2467 pci_save_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002468 pci_set_power_state(pci, pci_choose_state(pci, state));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002469 return 0;
2470}
2471
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002472static int m3_resume(struct pci_dev *pci)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473{
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002474 struct snd_card *card = pci_get_drvdata(pci);
2475 struct snd_m3 *chip = card->private_data;
Harvey Harrisone37273d2008-02-28 11:56:37 +01002476 int i, dsp_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002477
2478 if (chip->suspend_mem == NULL)
2479 return 0;
2480
Takashi Iwai30b35392006-10-11 18:52:53 +02002481 pci_set_power_state(pci, PCI_D0);
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002482 pci_restore_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02002483 if (pci_enable_device(pci) < 0) {
2484 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2485 "disabling device\n");
2486 snd_card_disconnect(card);
2487 return -EIO;
2488 }
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002489 pci_set_master(pci);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002490
2491 /* first lets just bring everything back. .*/
2492 snd_m3_outw(chip, 0, 0x54);
2493 snd_m3_outw(chip, 0, 0x56);
2494
2495 snd_m3_chip_init(chip);
2496 snd_m3_assp_halt(chip);
2497 snd_m3_ac97_reset(chip);
2498
2499 /* restore dsp image */
Harvey Harrisone37273d2008-02-28 11:56:37 +01002500 dsp_index = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002501 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2502 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
Harvey Harrisone37273d2008-02-28 11:56:37 +01002503 chip->suspend_mem[dsp_index++]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2505 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
Harvey Harrisone37273d2008-02-28 11:56:37 +01002506 chip->suspend_mem[dsp_index++]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002507
2508 /* tell the dma engine to restart itself */
2509 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2510 KDATA_DMA_ACTIVE, 0);
2511
2512 /* restore ac97 registers */
2513 snd_ac97_resume(chip->ac97);
2514
2515 snd_m3_assp_continue(chip);
2516 snd_m3_enable_ints(chip);
2517 snd_m3_amp_enable(chip, 1);
2518
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002519 snd_m3_hv_init(chip);
2520
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002521 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Hans de Goede715aa672010-04-21 11:04:08 -04002522 chip->in_suspend = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002523 return 0;
2524}
2525#endif /* CONFIG_PM */
2526
2527
2528/*
2529 */
2530
Takashi Iwai3470c292005-11-17 15:05:09 +01002531static int snd_m3_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002532{
Takashi Iwai3470c292005-11-17 15:05:09 +01002533 struct snd_m3 *chip = device->device_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002534 return snd_m3_free(chip);
2535}
2536
2537static int __devinit
Takashi Iwai3470c292005-11-17 15:05:09 +01002538snd_m3_create(struct snd_card *card, struct pci_dev *pci,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002539 int enable_amp,
2540 int amp_gpio,
Takashi Iwai3470c292005-11-17 15:05:09 +01002541 struct snd_m3 **chip_ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002542{
Takashi Iwai3470c292005-11-17 15:05:09 +01002543 struct snd_m3 *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544 int i, err;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002545 const struct snd_pci_quirk *quirk;
Takashi Iwai3470c292005-11-17 15:05:09 +01002546 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002547 .dev_free = snd_m3_dev_free,
2548 };
2549
2550 *chip_ret = NULL;
2551
2552 if (pci_enable_device(pci))
2553 return -EIO;
2554
2555 /* check, if we can restrict PCI DMA transfers to 28 bits */
Yang Hongyangce0b6202009-04-06 19:01:17 -07002556 if (pci_set_dma_mask(pci, DMA_BIT_MASK(28)) < 0 ||
2557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(28)) < 0) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002558 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002559 pci_disable_device(pci);
2560 return -ENXIO;
2561 }
2562
Takashi Iwaie560d8d2005-09-09 14:21:46 +02002563 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002564 if (chip == NULL) {
2565 pci_disable_device(pci);
2566 return -ENOMEM;
2567 }
2568
2569 spin_lock_init(&chip->reg_lock);
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002570 spin_lock_init(&chip->ac97_lock);
2571
Linus Torvalds1da177e2005-04-16 15:20:36 -07002572 switch (pci->device) {
2573 case PCI_DEVICE_ID_ESS_ALLEGRO:
2574 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2575 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2576 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2577 chip->allegro_flag = 1;
2578 break;
2579 }
2580
2581 chip->card = card;
2582 chip->pci = pci;
2583 chip->irq = -1;
2584
Linus Torvalds1da177e2005-04-16 15:20:36 -07002585 chip->external_amp = enable_amp;
2586 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2587 chip->amp_gpio = amp_gpio;
Takashi Iwai1061eeb2006-11-24 15:36:46 +01002588 else {
2589 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2590 if (quirk) {
2591 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2592 "for '%s'\n", quirk->name);
2593 chip->amp_gpio = quirk->value;
2594 } else if (chip->allegro_flag)
2595 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2596 else /* presumably this is for all 'maestro3's.. */
2597 chip->amp_gpio = GPO_EXT_AMP_M3;
2598 }
2599
2600 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2601 if (quirk) {
2602 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2603 "for '%s'\n", quirk->name);
2604 chip->irda_workaround = 1;
2605 }
2606 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2607 if (quirk)
2608 chip->hv_config = quirk->value;
2609 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2610 chip->is_omnibook = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002611
2612 chip->num_substreams = NR_DSPS;
Takashi Iwai3470c292005-11-17 15:05:09 +01002613 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2614 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002615 if (chip->substreams == NULL) {
2616 kfree(chip);
2617 pci_disable_device(pci);
2618 return -ENOMEM;
2619 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620
Clemens Ladisch81d77242006-11-06 09:26:41 +01002621 err = request_firmware(&chip->assp_kernel_image,
2622 "ess/maestro3_assp_kernel.fw", &pci->dev);
2623 if (err < 0) {
Clemens Ladisch81d77242006-11-06 09:26:41 +01002624 snd_m3_free(chip);
2625 return err;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002626 }
Clemens Ladisch81d77242006-11-06 09:26:41 +01002627
2628 err = request_firmware(&chip->assp_minisrc_image,
2629 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2630 if (err < 0) {
Clemens Ladisch81d77242006-11-06 09:26:41 +01002631 snd_m3_free(chip);
2632 return err;
David Woodhousefa6e1cb2008-05-29 11:58:27 +03002633 }
Clemens Ladisch81d77242006-11-06 09:26:41 +01002634
Linus Torvalds1da177e2005-04-16 15:20:36 -07002635 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2636 snd_m3_free(chip);
2637 return err;
2638 }
2639 chip->iobase = pci_resource_start(pci, 0);
2640
2641 /* just to be sure */
2642 pci_set_master(pci);
2643
2644 snd_m3_chip_init(chip);
2645 snd_m3_assp_halt(chip);
2646
2647 snd_m3_ac97_reset(chip);
2648
Linus Torvalds1da177e2005-04-16 15:20:36 -07002649 snd_m3_amp_enable(chip, 1);
2650
Ville Syrjälä8b83afe2008-06-03 20:52:10 +03002651 snd_m3_hv_init(chip);
2652
Takashi Iwai5ba1e7b2005-06-30 13:47:58 +02002653 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2654
Takashi Iwai437a5a42006-11-21 12:14:23 +01002655 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
Takashi Iwai3470c292005-11-17 15:05:09 +01002656 card->driver, chip)) {
Takashi Iwai99b359b2005-10-20 18:26:44 +02002657 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002658 snd_m3_free(chip);
2659 return -ENOMEM;
2660 }
2661 chip->irq = pci->irq;
2662
2663#ifdef CONFIG_PM
2664 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2665 if (chip->suspend_mem == NULL)
2666 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002667#endif
2668
2669 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2670 snd_m3_free(chip);
2671 return err;
2672 }
2673
2674 if ((err = snd_m3_mixer(chip)) < 0)
2675 return err;
2676
2677 for (i = 0; i < chip->num_substreams; i++) {
Takashi Iwai3470c292005-11-17 15:05:09 +01002678 struct m3_dma *s = &chip->substreams[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002679 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2680 return err;
2681 }
2682
2683 if ((err = snd_m3_pcm(chip, 0)) < 0)
2684 return err;
2685
2686 snd_m3_enable_ints(chip);
2687 snd_m3_assp_continue(chip);
2688
2689 snd_card_set_dev(card, &pci->dev);
2690
2691 *chip_ret = chip;
2692
2693 return 0;
2694}
2695
2696/*
2697 */
2698static int __devinit
2699snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2700{
2701 static int dev;
Takashi Iwai3470c292005-11-17 15:05:09 +01002702 struct snd_card *card;
2703 struct snd_m3 *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002704 int err;
2705
2706 /* don't pick up modems */
2707 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2708 return -ENODEV;
2709
2710 if (dev >= SNDRV_CARDS)
2711 return -ENODEV;
2712 if (!enable[dev]) {
2713 dev++;
2714 return -ENOENT;
2715 }
2716
Takashi Iwaie58de7b2008-12-28 16:44:30 +01002717 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2718 if (err < 0)
2719 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002720
2721 switch (pci->device) {
2722 case PCI_DEVICE_ID_ESS_ALLEGRO:
2723 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2724 strcpy(card->driver, "Allegro");
2725 break;
2726 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2727 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2728 strcpy(card->driver, "Canyon3D-2");
2729 break;
2730 default:
2731 strcpy(card->driver, "Maestro3");
2732 break;
2733 }
2734
2735 if ((err = snd_m3_create(card, pci,
2736 external_amp[dev],
2737 amp_gpio[dev],
2738 &chip)) < 0) {
2739 snd_card_free(card);
2740 return err;
2741 }
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002742 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002743
2744 sprintf(card->shortname, "ESS %s PCI", card->driver);
2745 sprintf(card->longname, "%s at 0x%lx, irq %d",
2746 card->shortname, chip->iobase, chip->irq);
2747
2748 if ((err = snd_card_register(card)) < 0) {
2749 snd_card_free(card);
2750 return err;
2751 }
2752
2753#if 0 /* TODO: not supported yet */
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002754 /* TODO enable MIDI IRQ and I/O */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002755 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
Takashi Iwai302e4c22006-05-23 13:24:30 +02002756 chip->iobase + MPU401_DATA_PORT,
2757 MPU401_INFO_INTEGRATED,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002758 chip->irq, 0, &chip->rmidi);
2759 if (err < 0)
Andreas Mohr0b2dcd52006-03-28 12:56:14 +02002760 printk(KERN_WARNING "maestro3: no MIDI support.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002761#endif
2762
2763 pci_set_drvdata(pci, card);
2764 dev++;
2765 return 0;
2766}
2767
2768static void __devexit snd_m3_remove(struct pci_dev *pci)
2769{
2770 snd_card_free(pci_get_drvdata(pci));
2771 pci_set_drvdata(pci, NULL);
2772}
2773
2774static struct pci_driver driver = {
2775 .name = "Maestro3",
2776 .id_table = snd_m3_ids,
2777 .probe = snd_m3_probe,
2778 .remove = __devexit_p(snd_m3_remove),
Takashi Iwai0e2364a2005-11-17 16:10:19 +01002779#ifdef CONFIG_PM
2780 .suspend = m3_suspend,
2781 .resume = m3_resume,
2782#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783};
2784
2785static int __init alsa_card_m3_init(void)
2786{
Takashi Iwai01d25d42005-04-11 16:58:24 +02002787 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002788}
2789
2790static void __exit alsa_card_m3_exit(void)
2791{
2792 pci_unregister_driver(&driver);
2793}
2794
2795module_init(alsa_card_m3_init)
2796module_exit(alsa_card_m3_exit)