Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 1 | /* |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 2 | * Designware SPI core controller driver (refer pxa2xx_spi.c) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2009, Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <linux/dma-mapping.h> |
| 17 | #include <linux/interrupt.h> |
Paul Gortmaker | d7614de | 2011-07-03 15:44:29 -0400 | [diff] [blame] | 18 | #include <linux/module.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 19 | #include <linux/highmem.h> |
| 20 | #include <linux/delay.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 22 | #include <linux/spi/spi.h> |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 23 | #include <linux/gpio.h> |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 24 | |
Grant Likely | ca632f5 | 2011-06-06 01:16:30 -0600 | [diff] [blame] | 25 | #include "spi-dw.h" |
Grant Likely | 568a60e | 2011-02-28 12:47:12 -0700 | [diff] [blame] | 26 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 27 | #ifdef CONFIG_DEBUG_FS |
| 28 | #include <linux/debugfs.h> |
| 29 | #endif |
| 30 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 31 | /* Slave spi_dev related */ |
| 32 | struct chip_data { |
| 33 | u16 cr0; |
| 34 | u8 cs; /* chip select pin */ |
| 35 | u8 n_bytes; /* current is a 1/2/4 byte op */ |
| 36 | u8 tmode; /* TR/TO/RO/EEPROM */ |
| 37 | u8 type; /* SPI/SSP/MicroWire */ |
| 38 | |
| 39 | u8 poll_mode; /* 1 means use poll mode */ |
| 40 | |
| 41 | u32 dma_width; |
| 42 | u32 rx_threshold; |
| 43 | u32 tx_threshold; |
| 44 | u8 enable_dma; |
| 45 | u8 bits_per_word; |
| 46 | u16 clk_div; /* baud rate divider */ |
| 47 | u32 speed_hz; /* baud rate */ |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 48 | void (*cs_control)(u32 command); |
| 49 | }; |
| 50 | |
| 51 | #ifdef CONFIG_DEBUG_FS |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 52 | #define SPI_REGS_BUFSIZE 1024 |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 53 | static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, |
| 54 | size_t count, loff_t *ppos) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 55 | { |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 56 | struct dw_spi *dws = file->private_data; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 57 | char *buf; |
| 58 | u32 len = 0; |
| 59 | ssize_t ret; |
| 60 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 61 | buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL); |
| 62 | if (!buf) |
| 63 | return 0; |
| 64 | |
| 65 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 66 | "%s registers:\n", dev_name(&dws->master->dev)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 67 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
| 68 | "=================================\n"); |
| 69 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 70 | "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 71 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 72 | "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 73 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 74 | "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 75 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 76 | "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 77 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 78 | "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 79 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 80 | "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 81 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 82 | "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 83 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 84 | "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 85 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 86 | "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 87 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 88 | "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 89 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 90 | "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 91 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 92 | "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 93 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 94 | "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 95 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 96 | "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 97 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
H Hartley Sweeten | 7eb187b | 2011-09-20 11:06:17 -0700 | [diff] [blame] | 98 | "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 99 | len += snprintf(buf + len, SPI_REGS_BUFSIZE - len, |
| 100 | "=================================\n"); |
| 101 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 102 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 103 | kfree(buf); |
| 104 | return ret; |
| 105 | } |
| 106 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 107 | static const struct file_operations dw_spi_regs_ops = { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 108 | .owner = THIS_MODULE, |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 109 | .open = simple_open, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 110 | .read = dw_spi_show_regs, |
Arnd Bergmann | 6038f37 | 2010-08-15 18:52:59 +0200 | [diff] [blame] | 111 | .llseek = default_llseek, |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 112 | }; |
| 113 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 114 | static int dw_spi_debugfs_init(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 115 | { |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 116 | dws->debugfs = debugfs_create_dir("dw_spi", NULL); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 117 | if (!dws->debugfs) |
| 118 | return -ENOMEM; |
| 119 | |
| 120 | debugfs_create_file("registers", S_IFREG | S_IRUGO, |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 121 | dws->debugfs, (void *)dws, &dw_spi_regs_ops); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 122 | return 0; |
| 123 | } |
| 124 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 125 | static void dw_spi_debugfs_remove(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 126 | { |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 127 | debugfs_remove_recursive(dws->debugfs); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | #else |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 131 | static inline int dw_spi_debugfs_init(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 132 | { |
George Shore | 20a588f | 2010-01-21 11:40:49 +0000 | [diff] [blame] | 133 | return 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 134 | } |
| 135 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 136 | static inline void dw_spi_debugfs_remove(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 137 | { |
| 138 | } |
| 139 | #endif /* CONFIG_DEBUG_FS */ |
| 140 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 141 | static void dw_spi_set_cs(struct spi_device *spi, bool enable) |
| 142 | { |
| 143 | struct dw_spi *dws = spi_master_get_devdata(spi->master); |
| 144 | struct chip_data *chip = spi_get_ctldata(spi); |
| 145 | |
| 146 | /* Chip select logic is inverted from spi_set_cs() */ |
Andy Shevchenko | 207cda9 | 2015-03-25 20:26:26 +0200 | [diff] [blame^] | 147 | if (chip && chip->cs_control) |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 148 | chip->cs_control(!enable); |
| 149 | |
| 150 | if (!enable) |
| 151 | dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); |
| 152 | } |
| 153 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 154 | /* Return the max entries we can fill into tx fifo */ |
| 155 | static inline u32 tx_max(struct dw_spi *dws) |
| 156 | { |
| 157 | u32 tx_left, tx_room, rxtx_gap; |
| 158 | |
| 159 | tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 160 | tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 161 | |
| 162 | /* |
| 163 | * Another concern is about the tx/rx mismatch, we |
| 164 | * though to use (dws->fifo_len - rxflr - txflr) as |
| 165 | * one maximum value for tx, but it doesn't cover the |
| 166 | * data which is out of tx/rx fifo and inside the |
| 167 | * shift registers. So a control from sw point of |
| 168 | * view is taken. |
| 169 | */ |
| 170 | rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx)) |
| 171 | / dws->n_bytes; |
| 172 | |
| 173 | return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap)); |
| 174 | } |
| 175 | |
| 176 | /* Return the max entries we should read out of rx fifo */ |
| 177 | static inline u32 rx_max(struct dw_spi *dws) |
| 178 | { |
| 179 | u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; |
| 180 | |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 181 | return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR)); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 182 | } |
| 183 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 184 | static void dw_writer(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 185 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 186 | u32 max = tx_max(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 187 | u16 txw = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 188 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 189 | while (max--) { |
| 190 | /* Set the tx word if the transfer's original "tx" is not null */ |
| 191 | if (dws->tx_end - dws->len) { |
| 192 | if (dws->n_bytes == 1) |
| 193 | txw = *(u8 *)(dws->tx); |
| 194 | else |
| 195 | txw = *(u16 *)(dws->tx); |
| 196 | } |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 197 | dw_writel(dws, DW_SPI_DR, txw); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 198 | dws->tx += dws->n_bytes; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 199 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 200 | } |
| 201 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 202 | static void dw_reader(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 203 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 204 | u32 max = rx_max(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 205 | u16 rxw; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 206 | |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 207 | while (max--) { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 208 | rxw = dw_readl(dws, DW_SPI_DR); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 209 | /* Care rx only if the transfer's original "rx" is not null */ |
| 210 | if (dws->rx_end - dws->len) { |
| 211 | if (dws->n_bytes == 1) |
| 212 | *(u8 *)(dws->rx) = rxw; |
| 213 | else |
| 214 | *(u16 *)(dws->rx) = rxw; |
| 215 | } |
| 216 | dws->rx += dws->n_bytes; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 217 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 218 | } |
| 219 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 220 | static void int_error_stop(struct dw_spi *dws, const char *msg) |
| 221 | { |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 222 | spi_reset_chip(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 223 | |
| 224 | dev_err(&dws->master->dev, "%s\n", msg); |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 225 | dws->master->cur_msg->status = -EIO; |
| 226 | spi_finalize_current_transfer(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 227 | } |
| 228 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 229 | static irqreturn_t interrupt_transfer(struct dw_spi *dws) |
| 230 | { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 231 | u16 irq_status = dw_readl(dws, DW_SPI_ISR); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 232 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 233 | /* Error handling */ |
| 234 | if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 235 | dw_readl(dws, DW_SPI_ICR); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 236 | int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 237 | return IRQ_HANDLED; |
| 238 | } |
| 239 | |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 240 | dw_reader(dws); |
| 241 | if (dws->rx_end == dws->rx) { |
| 242 | spi_mask_intr(dws, SPI_INT_TXEI); |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 243 | spi_finalize_current_transfer(dws->master); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 244 | return IRQ_HANDLED; |
| 245 | } |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 246 | if (irq_status & SPI_INT_TXEI) { |
| 247 | spi_mask_intr(dws, SPI_INT_TXEI); |
Alek Du | 3b8a4dd | 2011-03-30 23:09:55 +0800 | [diff] [blame] | 248 | dw_writer(dws); |
| 249 | /* Enable TX irq always, it will be disabled when RX finished */ |
| 250 | spi_umask_intr(dws, SPI_INT_TXEI); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 251 | } |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 252 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 253 | return IRQ_HANDLED; |
| 254 | } |
| 255 | |
| 256 | static irqreturn_t dw_spi_irq(int irq, void *dev_id) |
| 257 | { |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 258 | struct spi_master *master = dev_id; |
| 259 | struct dw_spi *dws = spi_master_get_devdata(master); |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 260 | u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; |
Yong Wang | cbcc062 | 2010-09-07 15:27:27 +0800 | [diff] [blame] | 261 | |
Yong Wang | cbcc062 | 2010-09-07 15:27:27 +0800 | [diff] [blame] | 262 | if (!irq_status) |
| 263 | return IRQ_NONE; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 264 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 265 | if (!master->cur_msg) { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 266 | spi_mask_intr(dws, SPI_INT_TXEI); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 267 | return IRQ_HANDLED; |
| 268 | } |
| 269 | |
| 270 | return dws->transfer_handler(dws); |
| 271 | } |
| 272 | |
| 273 | /* Must be called inside pump_transfers() */ |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 274 | static int poll_transfer(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 275 | { |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 276 | do { |
| 277 | dw_writer(dws); |
Feng Tang | de6efe0 | 2011-03-30 23:09:52 +0800 | [diff] [blame] | 278 | dw_reader(dws); |
Alek Du | 2ff271b | 2011-03-30 23:09:54 +0800 | [diff] [blame] | 279 | cpu_relax(); |
| 280 | } while (dws->rx_end > dws->rx); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 281 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 282 | return 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 283 | } |
| 284 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 285 | static int dw_spi_transfer_one(struct spi_master *master, |
| 286 | struct spi_device *spi, struct spi_transfer *transfer) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 287 | { |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 288 | struct dw_spi *dws = spi_master_get_devdata(master); |
| 289 | struct chip_data *chip = spi_get_ctldata(spi); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 290 | u8 imask = 0; |
Andy Shevchenko | ea11370 | 2015-02-24 13:32:11 +0200 | [diff] [blame] | 291 | u16 txlevel = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 292 | u16 clk_div = 0; |
| 293 | u32 speed = 0; |
| 294 | u32 cr0 = 0; |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 295 | int ret; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 296 | |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 297 | dws->dma_mapped = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 298 | dws->n_bytes = chip->n_bytes; |
| 299 | dws->dma_width = chip->dma_width; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 300 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 301 | dws->tx = (void *)transfer->tx_buf; |
| 302 | dws->tx_end = dws->tx + transfer->len; |
| 303 | dws->rx = transfer->rx_buf; |
| 304 | dws->rx_end = dws->rx + transfer->len; |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 305 | dws->len = transfer->len; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 306 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 307 | spi_enable_chip(dws, 0); |
| 308 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 309 | cr0 = chip->cr0; |
| 310 | |
| 311 | /* Handle per transfer options for bpw and speed */ |
| 312 | if (transfer->speed_hz) { |
| 313 | speed = chip->speed_hz; |
| 314 | |
Andy Shevchenko | 341c7dc | 2015-02-24 13:32:12 +0200 | [diff] [blame] | 315 | if ((transfer->speed_hz != speed) || !chip->clk_div) { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 316 | speed = transfer->speed_hz; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 317 | |
| 318 | /* clk_div doesn't support odd number */ |
Andy Shevchenko | 341c7dc | 2015-02-24 13:32:12 +0200 | [diff] [blame] | 319 | clk_div = (dws->max_freq / speed + 1) & 0xfffe; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 320 | |
| 321 | chip->speed_hz = speed; |
| 322 | chip->clk_div = clk_div; |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 323 | |
| 324 | spi_set_clk(dws, chip->clk_div); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 325 | } |
| 326 | } |
| 327 | if (transfer->bits_per_word) { |
Andy Shevchenko | e31abce | 2015-03-09 16:48:45 +0200 | [diff] [blame] | 328 | if (transfer->bits_per_word == 8) { |
| 329 | dws->n_bytes = 1; |
| 330 | dws->dma_width = 1; |
| 331 | } else if (transfer->bits_per_word == 16) { |
| 332 | dws->n_bytes = 2; |
| 333 | dws->dma_width = 2; |
| 334 | } |
| 335 | cr0 = (transfer->bits_per_word - 1) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 336 | | (chip->type << SPI_FRF_OFFSET) |
| 337 | | (spi->mode << SPI_MODE_OFFSET) |
| 338 | | (chip->tmode << SPI_TMOD_OFFSET); |
| 339 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 340 | |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 341 | /* |
| 342 | * Adjust transfer mode if necessary. Requires platform dependent |
| 343 | * chipselect mechanism. |
| 344 | */ |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 345 | if (chip->cs_control) { |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 346 | if (dws->rx && dws->tx) |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 347 | chip->tmode = SPI_TMOD_TR; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 348 | else if (dws->rx) |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 349 | chip->tmode = SPI_TMOD_RO; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 350 | else |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 351 | chip->tmode = SPI_TMOD_TO; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 352 | |
Feng Tang | e3e55ff | 2010-09-07 15:52:06 +0800 | [diff] [blame] | 353 | cr0 &= ~SPI_TMOD_MASK; |
George Shore | 052dc7c | 2010-01-21 11:40:52 +0000 | [diff] [blame] | 354 | cr0 |= (chip->tmode << SPI_TMOD_OFFSET); |
| 355 | } |
| 356 | |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 357 | dw_writel(dws, DW_SPI_CTRL0, cr0); |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 358 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 359 | /* Check if current transfer is a DMA transaction */ |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 360 | if (master->can_dma && master->can_dma(master, spi, transfer)) |
| 361 | dws->dma_mapped = master->cur_msg_mapped; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 362 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 363 | /* For poll mode just disable all interrupts */ |
| 364 | spi_mask_intr(dws, 0xff); |
| 365 | |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 366 | /* |
| 367 | * Interrupt mode |
| 368 | * we only need set the TXEI IRQ, as TX/RX always happen syncronizely |
| 369 | */ |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 370 | if (dws->dma_mapped) { |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 371 | ret = dws->dma_ops->dma_setup(dws, transfer); |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 372 | if (ret < 0) { |
| 373 | spi_enable_chip(dws, 1); |
| 374 | return ret; |
| 375 | } |
| 376 | } else if (!chip->poll_mode) { |
Andy Shevchenko | ea11370 | 2015-02-24 13:32:11 +0200 | [diff] [blame] | 377 | txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 378 | dw_writel(dws, DW_SPI_TXFLTR, txlevel); |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 379 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 380 | /* Set the interrupt mask */ |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 381 | imask |= SPI_INT_TXEI | SPI_INT_TXOI | |
| 382 | SPI_INT_RXUI | SPI_INT_RXOI; |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 383 | spi_umask_intr(dws, imask); |
| 384 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 385 | dws->transfer_handler = interrupt_transfer; |
| 386 | } |
| 387 | |
Andy Shevchenko | 0b2e891 | 2015-03-02 14:58:56 +0200 | [diff] [blame] | 388 | spi_enable_chip(dws, 1); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 389 | |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 390 | if (dws->dma_mapped) { |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 391 | ret = dws->dma_ops->dma_transfer(dws, transfer); |
Andy Shevchenko | 9f14538 | 2015-03-09 16:48:46 +0200 | [diff] [blame] | 392 | if (ret < 0) |
| 393 | return ret; |
| 394 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 395 | |
| 396 | if (chip->poll_mode) |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 397 | return poll_transfer(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 398 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 399 | return 1; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 400 | } |
| 401 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 402 | static void dw_spi_handle_err(struct spi_master *master, |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 403 | struct spi_message *msg) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 404 | { |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 405 | struct dw_spi *dws = spi_master_get_devdata(master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 406 | |
Andy Shevchenko | 4d5ac1e | 2015-03-09 16:48:48 +0200 | [diff] [blame] | 407 | if (dws->dma_mapped) |
| 408 | dws->dma_ops->dma_stop(dws); |
| 409 | |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 410 | spi_reset_chip(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | /* This may be called twice for each spi dev */ |
| 414 | static int dw_spi_setup(struct spi_device *spi) |
| 415 | { |
| 416 | struct dw_spi_chip *chip_info = NULL; |
| 417 | struct chip_data *chip; |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 418 | int ret; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 419 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 420 | /* Only alloc on first setup */ |
| 421 | chip = spi_get_ctldata(spi); |
| 422 | if (!chip) { |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 423 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 424 | if (!chip) |
| 425 | return -ENOMEM; |
Baruch Siach | 43f627a | 2013-12-30 20:30:46 +0200 | [diff] [blame] | 426 | spi_set_ctldata(spi, chip); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | /* |
| 430 | * Protocol drivers may change the chip settings, so... |
| 431 | * if chip_info exists, use it |
| 432 | */ |
| 433 | chip_info = spi->controller_data; |
| 434 | |
| 435 | /* chip_info doesn't always exist */ |
| 436 | if (chip_info) { |
| 437 | if (chip_info->cs_control) |
| 438 | chip->cs_control = chip_info->cs_control; |
| 439 | |
| 440 | chip->poll_mode = chip_info->poll_mode; |
| 441 | chip->type = chip_info->type; |
| 442 | |
| 443 | chip->rx_threshold = 0; |
| 444 | chip->tx_threshold = 0; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 445 | } |
| 446 | |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 447 | if (spi->bits_per_word == 8) { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 448 | chip->n_bytes = 1; |
| 449 | chip->dma_width = 1; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 450 | } else if (spi->bits_per_word == 16) { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 451 | chip->n_bytes = 2; |
| 452 | chip->dma_width = 2; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 453 | } |
| 454 | chip->bits_per_word = spi->bits_per_word; |
| 455 | |
Feng Tang | 552e450 | 2010-01-20 13:49:45 -0700 | [diff] [blame] | 456 | if (!spi->max_speed_hz) { |
| 457 | dev_err(&spi->dev, "No max speed HZ parameter\n"); |
| 458 | return -EINVAL; |
| 459 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 460 | |
| 461 | chip->tmode = 0; /* Tx & Rx */ |
| 462 | /* Default SPI mode is SCPOL = 0, SCPH = 0 */ |
| 463 | chip->cr0 = (chip->bits_per_word - 1) |
| 464 | | (chip->type << SPI_FRF_OFFSET) |
| 465 | | (spi->mode << SPI_MODE_OFFSET) |
| 466 | | (chip->tmode << SPI_TMOD_OFFSET); |
| 467 | |
Andy Shevchenko | c3ce15b | 2014-09-18 20:08:56 +0300 | [diff] [blame] | 468 | if (spi->mode & SPI_LOOP) |
| 469 | chip->cr0 |= 1 << SPI_SRL_OFFSET; |
| 470 | |
Baruch Siach | d9c73bb | 2014-01-31 12:07:47 +0200 | [diff] [blame] | 471 | if (gpio_is_valid(spi->cs_gpio)) { |
| 472 | ret = gpio_direction_output(spi->cs_gpio, |
| 473 | !(spi->mode & SPI_CS_HIGH)); |
| 474 | if (ret) |
| 475 | return ret; |
| 476 | } |
| 477 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 478 | return 0; |
| 479 | } |
| 480 | |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 481 | static void dw_spi_cleanup(struct spi_device *spi) |
| 482 | { |
| 483 | struct chip_data *chip = spi_get_ctldata(spi); |
| 484 | |
| 485 | kfree(chip); |
| 486 | spi_set_ctldata(spi, NULL); |
| 487 | } |
| 488 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 489 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 490 | static void spi_hw_init(struct device *dev, struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 491 | { |
Andy Shevchenko | 45746e8 | 2015-03-02 14:58:55 +0200 | [diff] [blame] | 492 | spi_reset_chip(dws); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 493 | |
| 494 | /* |
| 495 | * Try to detect the FIFO depth if not set by interface driver, |
| 496 | * the depth could be from 2 to 256 from HW spec |
| 497 | */ |
| 498 | if (!dws->fifo_len) { |
| 499 | u32 fifo; |
Jingoo Han | fadcace | 2014-09-02 11:49:24 +0900 | [diff] [blame] | 500 | |
Andy Shevchenko | 9d239d3 | 2015-02-25 11:39:36 +0200 | [diff] [blame] | 501 | for (fifo = 1; fifo < 256; fifo++) { |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 502 | dw_writel(dws, DW_SPI_TXFLTR, fifo); |
| 503 | if (fifo != dw_readl(dws, DW_SPI_TXFLTR)) |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 504 | break; |
| 505 | } |
Thor Thayer | dd11444 | 2015-03-12 14:19:31 -0500 | [diff] [blame] | 506 | dw_writel(dws, DW_SPI_TXFLTR, 0); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 507 | |
Andy Shevchenko | 9d239d3 | 2015-02-25 11:39:36 +0200 | [diff] [blame] | 508 | dws->fifo_len = (fifo == 1) ? 0 : fifo; |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 509 | dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); |
Feng Tang | c587b6f | 2010-01-21 10:41:10 +0800 | [diff] [blame] | 510 | } |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 511 | } |
| 512 | |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 513 | int dw_spi_add_host(struct device *dev, struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 514 | { |
| 515 | struct spi_master *master; |
| 516 | int ret; |
| 517 | |
| 518 | BUG_ON(dws == NULL); |
| 519 | |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 520 | master = spi_alloc_master(dev, 0); |
| 521 | if (!master) |
| 522 | return -ENOMEM; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 523 | |
| 524 | dws->master = master; |
| 525 | dws->type = SSI_MOTO_SPI; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 526 | dws->dma_inited = 0; |
| 527 | dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); |
Andy Shevchenko | c3c6e23 | 2014-09-18 20:08:57 +0300 | [diff] [blame] | 528 | snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 529 | |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 530 | ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 531 | dws->name, master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 532 | if (ret < 0) { |
| 533 | dev_err(&master->dev, "can not get IRQ\n"); |
| 534 | goto err_free_master; |
| 535 | } |
| 536 | |
Andy Shevchenko | c3ce15b | 2014-09-18 20:08:56 +0300 | [diff] [blame] | 537 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 538 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 539 | master->bus_num = dws->bus_num; |
| 540 | master->num_chipselect = dws->num_cs; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 541 | master->setup = dw_spi_setup; |
Axel Lin | a97c883 | 2014-08-31 12:47:06 +0800 | [diff] [blame] | 542 | master->cleanup = dw_spi_cleanup; |
Andy Shevchenko | c22c62d | 2015-03-02 14:58:57 +0200 | [diff] [blame] | 543 | master->set_cs = dw_spi_set_cs; |
| 544 | master->transfer_one = dw_spi_transfer_one; |
| 545 | master->handle_err = dw_spi_handle_err; |
Axel Lin | 765ee70 | 2014-02-20 21:37:56 +0800 | [diff] [blame] | 546 | master->max_speed_hz = dws->max_freq; |
Thor Thayer | 9c6de47 | 2014-10-08 13:51:34 -0500 | [diff] [blame] | 547 | master->dev.of_node = dev->of_node; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 548 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 549 | /* Basic HW init */ |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 550 | spi_hw_init(dev, dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 551 | |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 552 | if (dws->dma_ops && dws->dma_ops->dma_init) { |
| 553 | ret = dws->dma_ops->dma_init(dws); |
| 554 | if (ret) { |
Andy Shevchenko | 3dbb3b9 | 2015-01-07 16:56:54 +0200 | [diff] [blame] | 555 | dev_warn(dev, "DMA init failed\n"); |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 556 | dws->dma_inited = 0; |
Andy Shevchenko | f89a6d8 | 2015-03-09 16:48:49 +0200 | [diff] [blame] | 557 | } else { |
| 558 | master->can_dma = dws->dma_ops->can_dma; |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 559 | } |
| 560 | } |
| 561 | |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 562 | spi_master_set_devdata(master, dws); |
Baruch Siach | 04f421e | 2013-12-30 20:30:44 +0200 | [diff] [blame] | 563 | ret = devm_spi_register_master(dev, master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 564 | if (ret) { |
| 565 | dev_err(&master->dev, "problem registering spi master\n"); |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 566 | goto err_dma_exit; |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 567 | } |
| 568 | |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 569 | dw_spi_debugfs_init(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 570 | return 0; |
| 571 | |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 572 | err_dma_exit: |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 573 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
| 574 | dws->dma_ops->dma_exit(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 575 | spi_enable_chip(dws, 0); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 576 | err_free_master: |
| 577 | spi_master_put(master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 578 | return ret; |
| 579 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 580 | EXPORT_SYMBOL_GPL(dw_spi_add_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 581 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 582 | void dw_spi_remove_host(struct dw_spi *dws) |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 583 | { |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 584 | if (!dws) |
| 585 | return; |
Andy Shevchenko | 53288fe | 2014-09-12 15:11:56 +0300 | [diff] [blame] | 586 | dw_spi_debugfs_remove(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 587 | |
Feng Tang | 7063c0d | 2010-12-24 13:59:11 +0800 | [diff] [blame] | 588 | if (dws->dma_ops && dws->dma_ops->dma_exit) |
| 589 | dws->dma_ops->dma_exit(dws); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 590 | spi_enable_chip(dws, 0); |
| 591 | /* Disable clk */ |
| 592 | spi_set_clk(dws, 0); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 593 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 594 | EXPORT_SYMBOL_GPL(dw_spi_remove_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 595 | |
| 596 | int dw_spi_suspend_host(struct dw_spi *dws) |
| 597 | { |
| 598 | int ret = 0; |
| 599 | |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 600 | ret = spi_master_suspend(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 601 | if (ret) |
| 602 | return ret; |
| 603 | spi_enable_chip(dws, 0); |
| 604 | spi_set_clk(dws, 0); |
| 605 | return ret; |
| 606 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 607 | EXPORT_SYMBOL_GPL(dw_spi_suspend_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 608 | |
| 609 | int dw_spi_resume_host(struct dw_spi *dws) |
| 610 | { |
| 611 | int ret; |
| 612 | |
Andy Shevchenko | 30b4b70 | 2015-01-07 16:56:55 +0200 | [diff] [blame] | 613 | spi_hw_init(&dws->master->dev, dws); |
Baruch Siach | ec37e8e | 2014-01-31 12:07:44 +0200 | [diff] [blame] | 614 | ret = spi_master_resume(dws->master); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 615 | if (ret) |
| 616 | dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret); |
| 617 | return ret; |
| 618 | } |
Feng Tang | 79290a2 | 2010-12-24 13:59:10 +0800 | [diff] [blame] | 619 | EXPORT_SYMBOL_GPL(dw_spi_resume_host); |
Feng Tang | e24c745 | 2009-12-14 14:20:22 -0800 | [diff] [blame] | 620 | |
| 621 | MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>"); |
| 622 | MODULE_DESCRIPTION("Driver for DesignWare SPI controller core"); |
| 623 | MODULE_LICENSE("GPL v2"); |