Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 13 | #include "sde_hwio.h" |
| 14 | #include "sde_hw_catalog.h" |
| 15 | #include "sde_hw_lm.h" |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 16 | #include "sde_hw_sspp.h" |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 17 | #include "sde_hw_color_processing.h" |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 18 | #include "sde_dbg.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 19 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 20 | #define SDE_FETCH_CONFIG_RESET_VALUE 0x00000087 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 21 | |
| 22 | /* SDE_SSPP_SRC */ |
| 23 | #define SSPP_SRC_SIZE 0x00 |
| 24 | #define SSPP_SRC_XY 0x08 |
| 25 | #define SSPP_OUT_SIZE 0x0c |
| 26 | #define SSPP_OUT_XY 0x10 |
| 27 | #define SSPP_SRC0_ADDR 0x14 |
| 28 | #define SSPP_SRC1_ADDR 0x18 |
| 29 | #define SSPP_SRC2_ADDR 0x1C |
| 30 | #define SSPP_SRC3_ADDR 0x20 |
| 31 | #define SSPP_SRC_YSTRIDE0 0x24 |
| 32 | #define SSPP_SRC_YSTRIDE1 0x28 |
| 33 | #define SSPP_SRC_FORMAT 0x30 |
| 34 | #define SSPP_SRC_UNPACK_PATTERN 0x34 |
| 35 | #define SSPP_SRC_OP_MODE 0x38 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 36 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 37 | /* SSPP_MULTIRECT*/ |
| 38 | #define SSPP_SRC_SIZE_REC1 0x16C |
| 39 | #define SSPP_SRC_XY_REC1 0x168 |
| 40 | #define SSPP_OUT_SIZE_REC1 0x160 |
| 41 | #define SSPP_OUT_XY_REC1 0x164 |
| 42 | #define SSPP_SRC_FORMAT_REC1 0x174 |
| 43 | #define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 |
| 44 | #define SSPP_SRC_OP_MODE_REC1 0x17C |
| 45 | #define SSPP_MULTIRECT_OPMODE 0x170 |
| 46 | #define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 |
| 47 | #define SSPP_EXCL_REC_SIZE_REC1 0x184 |
| 48 | #define SSPP_EXCL_REC_XY_REC1 0x188 |
| 49 | |
| 50 | #define MDSS_MDP_OP_DEINTERLACE BIT(22) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 51 | #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) |
| 52 | #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) |
| 53 | #define MDSS_MDP_OP_IGC_ROM_0 BIT(17) |
| 54 | #define MDSS_MDP_OP_IGC_EN BIT(16) |
| 55 | #define MDSS_MDP_OP_FLIP_UD BIT(14) |
| 56 | #define MDSS_MDP_OP_FLIP_LR BIT(13) |
| 57 | #define MDSS_MDP_OP_BWC_EN BIT(0) |
| 58 | #define MDSS_MDP_OP_PE_OVERRIDE BIT(31) |
| 59 | #define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) |
| 60 | #define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) |
| 61 | #define MDSS_MDP_OP_BWC_Q_MED (2 << 1) |
| 62 | |
| 63 | #define SSPP_SRC_CONSTANT_COLOR 0x3c |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 64 | #define SSPP_EXCL_REC_CTL 0x40 |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame] | 65 | #define SSPP_UBWC_STATIC_CTRL 0x44 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 66 | #define SSPP_FETCH_CONFIG 0x048 |
| 67 | #define SSPP_DANGER_LUT 0x60 |
| 68 | #define SSPP_SAFE_LUT 0x64 |
| 69 | #define SSPP_CREQ_LUT 0x68 |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 70 | #define SSPP_QOS_CTRL 0x6C |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 71 | #define SSPP_DECIMATION_CONFIG 0xB4 |
| 72 | #define SSPP_SRC_ADDR_SW_STATUS 0x70 |
| 73 | #define SSPP_SW_PIX_EXT_C0_LR 0x100 |
| 74 | #define SSPP_SW_PIX_EXT_C0_TB 0x104 |
| 75 | #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 |
| 76 | #define SSPP_SW_PIX_EXT_C1C2_LR 0x110 |
| 77 | #define SSPP_SW_PIX_EXT_C1C2_TB 0x114 |
| 78 | #define SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS 0x118 |
| 79 | #define SSPP_SW_PIX_EXT_C3_LR 0x120 |
| 80 | #define SSPP_SW_PIX_EXT_C3_TB 0x124 |
| 81 | #define SSPP_SW_PIX_EXT_C3_REQ_PIXELS 0x128 |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 82 | #define SSPP_TRAFFIC_SHAPER 0x130 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 83 | #define SSPP_UBWC_ERROR_STATUS 0x138 |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 84 | #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 |
| 85 | #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 |
| 86 | #define SSPP_TRAFFIC_SHAPER_REC1 0x158 |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 87 | #define SSPP_EXCL_REC_SIZE 0x1B4 |
| 88 | #define SSPP_EXCL_REC_XY 0x1B8 |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 89 | #define SSPP_VIG_OP_MODE 0x0 |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 90 | #define SSPP_VIG_CSC_10_OP_MODE 0x0 |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 91 | #define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 92 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 93 | /* SSPP_QOS_CTRL */ |
| 94 | #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) |
| 95 | #define SSPP_QOS_CTRL_DANGER_SAFE_EN BIT(0) |
| 96 | #define SSPP_QOS_CTRL_DANGER_VBLANK_MASK 0x3 |
| 97 | #define SSPP_QOS_CTRL_DANGER_VBLANK_OFF 4 |
| 98 | #define SSPP_QOS_CTRL_CREQ_VBLANK_MASK 0x3 |
| 99 | #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 |
| 100 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 101 | #define SSPP_SYS_CACHE_MODE 0x1BC |
| 102 | #define SSPP_SBUF_STATUS_PLANE0 0x1C0 |
| 103 | #define SSPP_SBUF_STATUS_PLANE1 0x1C4 |
| 104 | #define SSPP_SBUF_STATUS_PLANE_EMPTY BIT(16) |
| 105 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 106 | /* SDE_SSPP_SCALER_QSEED2 */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 107 | #define SCALE_CONFIG 0x04 |
| 108 | #define COMP0_3_PHASE_STEP_X 0x10 |
| 109 | #define COMP0_3_PHASE_STEP_Y 0x14 |
| 110 | #define COMP1_2_PHASE_STEP_X 0x18 |
| 111 | #define COMP1_2_PHASE_STEP_Y 0x1c |
| 112 | #define COMP0_3_INIT_PHASE_X 0x20 |
| 113 | #define COMP0_3_INIT_PHASE_Y 0x24 |
| 114 | #define COMP1_2_INIT_PHASE_X 0x28 |
| 115 | #define COMP1_2_INIT_PHASE_Y 0x2C |
| 116 | #define VIG_0_QSEED2_SHARP 0x30 |
| 117 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 118 | /* SDE_SSPP_SCALER_QSEED3 */ |
| 119 | #define QSEED3_HW_VERSION 0x00 |
| 120 | #define QSEED3_OP_MODE 0x04 |
| 121 | #define QSEED3_RGB2Y_COEFF 0x08 |
| 122 | #define QSEED3_PHASE_INIT 0x0C |
| 123 | #define QSEED3_PHASE_STEP_Y_H 0x10 |
| 124 | #define QSEED3_PHASE_STEP_Y_V 0x14 |
| 125 | #define QSEED3_PHASE_STEP_UV_H 0x18 |
| 126 | #define QSEED3_PHASE_STEP_UV_V 0x1C |
| 127 | #define QSEED3_PRELOAD 0x20 |
| 128 | #define QSEED3_DE_SHARPEN 0x24 |
| 129 | #define QSEED3_DE_SHARPEN_CTL 0x28 |
| 130 | #define QSEED3_DE_SHAPE_CTL 0x2C |
| 131 | #define QSEED3_DE_THRESHOLD 0x30 |
| 132 | #define QSEED3_DE_ADJUST_DATA_0 0x34 |
| 133 | #define QSEED3_DE_ADJUST_DATA_1 0x38 |
| 134 | #define QSEED3_DE_ADJUST_DATA_2 0x3C |
| 135 | #define QSEED3_SRC_SIZE_Y_RGB_A 0x40 |
| 136 | #define QSEED3_SRC_SIZE_UV 0x44 |
| 137 | #define QSEED3_DST_SIZE 0x48 |
| 138 | #define QSEED3_COEF_LUT_CTRL 0x4C |
| 139 | #define QSEED3_COEF_LUT_SWAP_BIT 0 |
| 140 | #define QSEED3_COEF_LUT_DIR_BIT 1 |
| 141 | #define QSEED3_COEF_LUT_Y_CIR_BIT 2 |
| 142 | #define QSEED3_COEF_LUT_UV_CIR_BIT 3 |
| 143 | #define QSEED3_COEF_LUT_Y_SEP_BIT 4 |
| 144 | #define QSEED3_COEF_LUT_UV_SEP_BIT 5 |
| 145 | #define QSEED3_BUFFER_CTRL 0x50 |
| 146 | #define QSEED3_CLK_CTRL0 0x54 |
| 147 | #define QSEED3_CLK_CTRL1 0x58 |
| 148 | #define QSEED3_CLK_STATUS 0x5C |
| 149 | #define QSEED3_MISR_CTRL 0x70 |
| 150 | #define QSEED3_MISR_SIGNATURE_0 0x74 |
| 151 | #define QSEED3_MISR_SIGNATURE_1 0x78 |
| 152 | #define QSEED3_PHASE_INIT_Y_H 0x90 |
| 153 | #define QSEED3_PHASE_INIT_Y_V 0x94 |
| 154 | #define QSEED3_PHASE_INIT_UV_H 0x98 |
| 155 | #define QSEED3_PHASE_INIT_UV_V 0x9C |
| 156 | #define QSEED3_COEF_LUT 0x100 |
| 157 | #define QSEED3_FILTERS 5 |
| 158 | #define QSEED3_LUT_REGIONS 4 |
| 159 | #define QSEED3_CIRCULAR_LUTS 9 |
| 160 | #define QSEED3_SEPARABLE_LUTS 10 |
| 161 | #define QSEED3_LUT_SIZE 60 |
| 162 | #define QSEED3_ENABLE 2 |
| 163 | #define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32)) |
| 164 | #define QSEED3_CIR_LUT_SIZE \ |
| 165 | (QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32)) |
| 166 | #define QSEED3_SEP_LUT_SIZE \ |
| 167 | (QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32)) |
| 168 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 169 | /* |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 170 | * Definitions for ViG op modes |
| 171 | */ |
| 172 | #define VIG_OP_CSC_DST_DATAFMT BIT(19) |
| 173 | #define VIG_OP_CSC_SRC_DATAFMT BIT(18) |
| 174 | #define VIG_OP_CSC_EN BIT(17) |
| 175 | #define VIG_OP_MEM_PROT_CONT BIT(15) |
| 176 | #define VIG_OP_MEM_PROT_VAL BIT(14) |
| 177 | #define VIG_OP_MEM_PROT_SAT BIT(13) |
| 178 | #define VIG_OP_MEM_PROT_HUE BIT(12) |
| 179 | #define VIG_OP_HIST BIT(8) |
| 180 | #define VIG_OP_SKY_COL BIT(7) |
| 181 | #define VIG_OP_FOIL BIT(6) |
| 182 | #define VIG_OP_SKIN_COL BIT(5) |
| 183 | #define VIG_OP_PA_EN BIT(4) |
| 184 | #define VIG_OP_PA_SAT_ZERO_EXP BIT(2) |
| 185 | #define VIG_OP_MEM_PROT_BLEND BIT(1) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 186 | |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 187 | /* |
| 188 | * Definitions for CSC 10 op modes |
| 189 | */ |
| 190 | #define VIG_CSC_10_SRC_DATAFMT BIT(1) |
| 191 | #define VIG_CSC_10_EN BIT(0) |
| 192 | #define CSC_10BIT_OFFSET 4 |
| 193 | |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 194 | /* traffic shaper clock in Hz */ |
| 195 | #define TS_CLK 19200000 |
| 196 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 197 | static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx, |
| 198 | int s_id, |
| 199 | u32 *idx) |
| 200 | { |
| 201 | int rc = 0; |
| 202 | const struct sde_sspp_sub_blks *sblk = ctx->cap->sblk; |
| 203 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 204 | if (!ctx) |
| 205 | return -EINVAL; |
| 206 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 207 | switch (s_id) { |
| 208 | case SDE_SSPP_SRC: |
| 209 | *idx = sblk->src_blk.base; |
| 210 | break; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 211 | case SDE_SSPP_SCALER_QSEED2: |
| 212 | case SDE_SSPP_SCALER_QSEED3: |
| 213 | case SDE_SSPP_SCALER_RGB: |
| 214 | *idx = sblk->scaler_blk.base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 215 | break; |
| 216 | case SDE_SSPP_CSC: |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 217 | case SDE_SSPP_CSC_10BIT: |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 218 | *idx = sblk->csc_blk.base; |
| 219 | break; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 220 | case SDE_SSPP_HSIC: |
Benet Clark | 37809e6 | 2016-10-24 10:14:00 -0700 | [diff] [blame] | 221 | *idx = sblk->hsic_blk.base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 222 | break; |
| 223 | case SDE_SSPP_PCC: |
| 224 | *idx = sblk->pcc_blk.base; |
| 225 | break; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 226 | case SDE_SSPP_MEMCOLOR: |
Benet Clark | 37809e6 | 2016-10-24 10:14:00 -0700 | [diff] [blame] | 227 | *idx = sblk->memcolor_blk.base; |
Gopikrishnaiah Anandan | e3842f3 | 2015-11-05 12:18:41 -0800 | [diff] [blame] | 228 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 229 | default: |
| 230 | rc = -EINVAL; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | return rc; |
| 234 | } |
| 235 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 236 | static void sde_hw_sspp_setup_multirect(struct sde_hw_pipe *ctx, |
| 237 | enum sde_sspp_multirect_index index, |
| 238 | enum sde_sspp_multirect_mode mode) |
| 239 | { |
| 240 | u32 mode_mask; |
| 241 | u32 idx; |
| 242 | |
| 243 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 244 | return; |
| 245 | |
| 246 | if (index == SDE_SSPP_RECT_SOLO) { |
| 247 | /** |
| 248 | * if rect index is RECT_SOLO, we cannot expect a |
| 249 | * virtual plane sharing the same SSPP id. So we go |
| 250 | * and disable multirect |
| 251 | */ |
| 252 | mode_mask = 0; |
| 253 | } else { |
| 254 | mode_mask = SDE_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); |
| 255 | mode_mask |= index; |
| 256 | mode_mask |= (mode == SDE_SSPP_MULTIRECT_TIME_MX) ? 0x4 : 0x0; |
| 257 | } |
| 258 | |
| 259 | SDE_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); |
| 260 | } |
| 261 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 262 | static void _sspp_setup_opmode(struct sde_hw_pipe *ctx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 263 | u32 mask, u8 en) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 264 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 265 | u32 idx; |
| 266 | u32 opmode; |
| 267 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 268 | if (!test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features) || |
| 269 | _sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || |
| 270 | !test_bit(SDE_SSPP_CSC, &ctx->cap->features)) |
| 271 | return; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 272 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 273 | opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_OP_MODE + idx); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 274 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 275 | if (en) |
| 276 | opmode |= mask; |
| 277 | else |
| 278 | opmode &= ~mask; |
| 279 | |
| 280 | SDE_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 281 | } |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 282 | |
| 283 | static void _sspp_setup_csc10_opmode(struct sde_hw_pipe *ctx, |
| 284 | u32 mask, u8 en) |
| 285 | { |
| 286 | u32 idx; |
| 287 | u32 opmode; |
| 288 | |
| 289 | if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC_10BIT, &idx)) |
| 290 | return; |
| 291 | |
| 292 | opmode = SDE_REG_READ(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx); |
| 293 | if (en) |
| 294 | opmode |= mask; |
| 295 | else |
| 296 | opmode &= ~mask; |
| 297 | |
| 298 | SDE_REG_WRITE(&ctx->hw, SSPP_VIG_CSC_10_OP_MODE + idx, opmode); |
| 299 | } |
| 300 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 301 | /** |
| 302 | * Setup source pixel format, flip, |
| 303 | */ |
| 304 | static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 305 | const struct sde_format *fmt, u32 flags, |
| 306 | enum sde_sspp_multirect_index rect_mode) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 307 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 308 | struct sde_hw_blk_reg_map *c; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 309 | u32 chroma_samp, unpack, src_format; |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 310 | u32 secure = 0, secure_bit_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 311 | u32 opmode = 0; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 312 | u32 op_mode_off, unpack_pat_off, format_off; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 313 | u32 idx; |
| 314 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 315 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !fmt) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 316 | return; |
| 317 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 318 | if (rect_mode == SDE_SSPP_RECT_SOLO || rect_mode == SDE_SSPP_RECT_0) { |
| 319 | op_mode_off = SSPP_SRC_OP_MODE; |
| 320 | unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; |
| 321 | format_off = SSPP_SRC_FORMAT; |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 322 | secure_bit_mask = (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 323 | } else { |
| 324 | op_mode_off = SSPP_SRC_OP_MODE_REC1; |
| 325 | unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; |
| 326 | format_off = SSPP_SRC_FORMAT_REC1; |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 327 | secure_bit_mask = 0xA; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 328 | } |
| 329 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 330 | c = &ctx->hw; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 331 | opmode = SDE_REG_READ(c, op_mode_off + idx); |
Clarence Ip | 5e2a922 | 2016-06-26 22:38:24 -0400 | [diff] [blame] | 332 | opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | |
| 333 | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 334 | |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 335 | secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx); |
| 336 | if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION) |
| 337 | secure |= secure_bit_mask; |
| 338 | else |
| 339 | secure &= ~secure_bit_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 340 | |
| 341 | if (flags & SDE_SSPP_FLIP_LR) |
| 342 | opmode |= MDSS_MDP_OP_FLIP_LR; |
| 343 | if (flags & SDE_SSPP_FLIP_UD) |
| 344 | opmode |= MDSS_MDP_OP_FLIP_UD; |
| 345 | |
| 346 | chroma_samp = fmt->chroma_sample; |
| 347 | if (flags & SDE_SSPP_SOURCE_ROTATED_90) { |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 348 | if (chroma_samp == SDE_CHROMA_H2V1) |
| 349 | chroma_samp = SDE_CHROMA_H1V2; |
| 350 | else if (chroma_samp == SDE_CHROMA_H1V2) |
| 351 | chroma_samp = SDE_CHROMA_H2V1; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | |
| 355 | (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 356 | (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 357 | |
| 358 | if (flags & SDE_SSPP_ROT_90) |
| 359 | src_format |= BIT(11); /* ROT90 */ |
| 360 | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 361 | if (fmt->alpha_enable && fmt->fetch_planes == SDE_PLANE_INTERLEAVED) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 362 | src_format |= BIT(8); /* SRCC3_EN */ |
| 363 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 364 | if (flags & SDE_SSPP_SOLID_FILL) |
| 365 | src_format |= BIT(22); |
| 366 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 367 | unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | |
| 368 | (fmt->element[1] << 8) | (fmt->element[0] << 0); |
| 369 | src_format |= ((fmt->unpack_count - 1) << 12) | |
| 370 | (fmt->unpack_tight << 17) | |
| 371 | (fmt->unpack_align_msb << 18) | |
| 372 | ((fmt->bpp - 1) << 9); |
| 373 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 374 | if (fmt->fetch_mode != SDE_FETCH_LINEAR) { |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 375 | if (SDE_FORMAT_IS_UBWC(fmt)) |
| 376 | opmode |= MDSS_MDP_OP_BWC_EN; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 377 | src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ |
| 378 | SDE_REG_WRITE(c, SSPP_FETCH_CONFIG, |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 379 | SDE_FETCH_CONFIG_RESET_VALUE | |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame] | 380 | ctx->mdp->highest_bank_bit << 18); |
| 381 | if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version)) |
| 382 | SDE_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, |
| 383 | BIT(31) | (ctx->mdp->ubwc_swizzle) | |
| 384 | (ctx->mdp->highest_bank_bit << 4)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 385 | } |
| 386 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 387 | opmode |= MDSS_MDP_OP_PE_OVERRIDE; |
| 388 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 389 | /* if this is YUV pixel format, enable CSC */ |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 390 | if (SDE_FORMAT_IS_YUV(fmt)) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 391 | src_format |= BIT(15); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 392 | |
abeykun | 5ed42e1 | 2016-08-24 17:09:26 -0400 | [diff] [blame] | 393 | if (SDE_FORMAT_IS_DX(fmt)) |
| 394 | src_format |= BIT(14); |
| 395 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 396 | /* update scaler opmode, if appropriate */ |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 397 | if (test_bit(SDE_SSPP_CSC, &ctx->cap->features)) |
| 398 | _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, |
| 399 | SDE_FORMAT_IS_YUV(fmt)); |
| 400 | else if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features)) |
| 401 | _sspp_setup_csc10_opmode(ctx, |
| 402 | VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, |
| 403 | SDE_FORMAT_IS_YUV(fmt)); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 404 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 405 | SDE_REG_WRITE(c, format_off + idx, src_format); |
| 406 | SDE_REG_WRITE(c, unpack_pat_off + idx, unpack); |
| 407 | SDE_REG_WRITE(c, op_mode_off + idx, opmode); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 408 | SDE_REG_WRITE(c, SSPP_SRC_ADDR_SW_STATUS + idx, secure); |
| 409 | |
| 410 | /* clear previous UBWC error */ |
| 411 | SDE_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); |
| 412 | } |
| 413 | |
| 414 | static void sde_hw_sspp_setup_pe_config(struct sde_hw_pipe *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 415 | struct sde_hw_pixel_ext *pe_ext) |
| 416 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 417 | struct sde_hw_blk_reg_map *c; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 418 | u8 color; |
| 419 | u32 lr_pe[4], tb_pe[4], tot_req_pixels[4]; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 420 | const u32 bytemask = 0xff; |
| 421 | const u32 shortmask = 0xffff; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 422 | u32 idx; |
| 423 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 424 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !pe_ext) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 425 | return; |
| 426 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 427 | c = &ctx->hw; |
| 428 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 429 | /* program SW pixel extension override for all pipes*/ |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 430 | for (color = 0; color < SDE_MAX_PLANES; color++) { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 431 | /* color 2 has the same set of registers as color 1 */ |
| 432 | if (color == 2) |
| 433 | continue; |
| 434 | |
| 435 | lr_pe[color] = ((pe_ext->right_ftch[color] & bytemask) << 24)| |
| 436 | ((pe_ext->right_rpt[color] & bytemask) << 16)| |
| 437 | ((pe_ext->left_ftch[color] & bytemask) << 8)| |
| 438 | (pe_ext->left_rpt[color] & bytemask); |
| 439 | |
| 440 | tb_pe[color] = ((pe_ext->btm_ftch[color] & bytemask) << 24)| |
| 441 | ((pe_ext->btm_rpt[color] & bytemask) << 16)| |
| 442 | ((pe_ext->top_ftch[color] & bytemask) << 8)| |
| 443 | (pe_ext->top_rpt[color] & bytemask); |
| 444 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 445 | tot_req_pixels[color] = (((pe_ext->roi_h[color] + |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 446 | pe_ext->num_ext_pxls_top[color] + |
| 447 | pe_ext->num_ext_pxls_btm[color]) & shortmask) << 16) | |
| 448 | ((pe_ext->roi_w[color] + |
| 449 | pe_ext->num_ext_pxls_left[color] + |
| 450 | pe_ext->num_ext_pxls_right[color]) & shortmask); |
| 451 | } |
| 452 | |
| 453 | /* color 0 */ |
| 454 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_LR + idx, lr_pe[0]); |
| 455 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_TB + idx, tb_pe[0]); |
| 456 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C0_REQ_PIXELS + idx, |
| 457 | tot_req_pixels[0]); |
| 458 | |
| 459 | /* color 1 and color 2 */ |
| 460 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_LR + idx, lr_pe[1]); |
| 461 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_TB + idx, tb_pe[1]); |
| 462 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C1C2_REQ_PIXELS + idx, |
| 463 | tot_req_pixels[1]); |
| 464 | |
| 465 | /* color 3 */ |
| 466 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_LR + idx, lr_pe[3]); |
| 467 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_TB + idx, lr_pe[3]); |
| 468 | SDE_REG_WRITE(c, SSPP_SW_PIX_EXT_C3_REQ_PIXELS + idx, |
| 469 | tot_req_pixels[3]); |
| 470 | } |
| 471 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 472 | static void _sde_hw_sspp_setup_scaler(struct sde_hw_pipe *ctx, |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 473 | struct sde_hw_pipe_cfg *sspp, |
| 474 | struct sde_hw_pixel_ext *pe, |
| 475 | void *scaler_cfg) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 476 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 477 | struct sde_hw_blk_reg_map *c; |
| 478 | int config_h = 0x0; |
| 479 | int config_v = 0x0; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 480 | u32 idx; |
| 481 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 482 | (void)sspp; |
| 483 | (void)scaler_cfg; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 484 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !pe) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 485 | return; |
| 486 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 487 | c = &ctx->hw; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 488 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 489 | /* enable scaler(s) if valid filter set */ |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 490 | if (pe->horz_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 491 | config_h |= pe->horz_filter[SDE_SSPP_COMP_0] << 8; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 492 | if (pe->horz_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 493 | config_h |= pe->horz_filter[SDE_SSPP_COMP_1_2] << 12; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 494 | if (pe->horz_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 495 | config_h |= pe->horz_filter[SDE_SSPP_COMP_3] << 16; |
| 496 | |
| 497 | if (config_h) |
| 498 | config_h |= BIT(0); |
| 499 | |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 500 | if (pe->vert_filter[SDE_SSPP_COMP_0] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 501 | config_v |= pe->vert_filter[SDE_SSPP_COMP_0] << 10; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 502 | if (pe->vert_filter[SDE_SSPP_COMP_1_2] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 503 | config_v |= pe->vert_filter[SDE_SSPP_COMP_1_2] << 14; |
Lloyd Atkinson | 9a67349 | 2016-07-05 11:41:57 -0400 | [diff] [blame] | 504 | if (pe->vert_filter[SDE_SSPP_COMP_3] < SDE_SCALE_FILTER_MAX) |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 505 | config_v |= pe->vert_filter[SDE_SSPP_COMP_3] << 18; |
| 506 | |
| 507 | if (config_v) |
| 508 | config_v |= BIT(1); |
| 509 | |
| 510 | SDE_REG_WRITE(c, SCALE_CONFIG + idx, config_h | config_v); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 511 | SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_X + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 512 | pe->init_phase_x[SDE_SSPP_COMP_0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 513 | SDE_REG_WRITE(c, COMP0_3_INIT_PHASE_Y + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 514 | pe->init_phase_y[SDE_SSPP_COMP_0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 515 | SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_X + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 516 | pe->phase_step_x[SDE_SSPP_COMP_0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 517 | SDE_REG_WRITE(c, COMP0_3_PHASE_STEP_Y + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 518 | pe->phase_step_y[SDE_SSPP_COMP_0]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 519 | |
| 520 | SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_X + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 521 | pe->init_phase_x[SDE_SSPP_COMP_1_2]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 522 | SDE_REG_WRITE(c, COMP1_2_INIT_PHASE_Y + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 523 | pe->init_phase_y[SDE_SSPP_COMP_1_2]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 524 | SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_X + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 525 | pe->phase_step_x[SDE_SSPP_COMP_1_2]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 526 | SDE_REG_WRITE(c, COMP1_2_PHASE_STEP_Y + idx, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 527 | pe->phase_step_y[SDE_SSPP_COMP_1_2]); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 528 | } |
| 529 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 530 | static void _sde_hw_sspp_setup_scaler3_lut(struct sde_hw_pipe *ctx, |
| 531 | struct sde_hw_scaler3_cfg *scaler3_cfg) |
| 532 | { |
| 533 | u32 idx; |
| 534 | int i, j, filter; |
| 535 | int config_lut = 0x0; |
| 536 | unsigned long lut_flags; |
| 537 | u32 lut_addr, lut_offset, lut_len; |
| 538 | u32 *lut[QSEED3_FILTERS] = {NULL, NULL, NULL, NULL, NULL}; |
| 539 | static const uint32_t offset[QSEED3_FILTERS][QSEED3_LUT_REGIONS][2] = { |
| 540 | {{18, 0x000}, {12, 0x120}, {12, 0x1E0}, {8, 0x2A0} }, |
| 541 | {{6, 0x320}, {3, 0x3E0}, {3, 0x440}, {3, 0x4A0} }, |
| 542 | {{6, 0x500}, {3, 0x5c0}, {3, 0x620}, {3, 0x680} }, |
| 543 | {{6, 0x380}, {3, 0x410}, {3, 0x470}, {3, 0x4d0} }, |
| 544 | {{6, 0x560}, {3, 0x5f0}, {3, 0x650}, {3, 0x6b0} }, |
| 545 | }; |
| 546 | |
| 547 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || |
| 548 | !scaler3_cfg) |
| 549 | return; |
| 550 | |
| 551 | lut_flags = (unsigned long) scaler3_cfg->lut_flag; |
| 552 | if (test_bit(QSEED3_COEF_LUT_DIR_BIT, &lut_flags) && |
| 553 | (scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) { |
| 554 | lut[0] = scaler3_cfg->dir_lut; |
| 555 | config_lut = 1; |
| 556 | } |
| 557 | if (test_bit(QSEED3_COEF_LUT_Y_CIR_BIT, &lut_flags) && |
| 558 | (scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && |
| 559 | (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { |
| 560 | lut[1] = scaler3_cfg->cir_lut + |
| 561 | scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE; |
| 562 | config_lut = 1; |
| 563 | } |
| 564 | if (test_bit(QSEED3_COEF_LUT_UV_CIR_BIT, &lut_flags) && |
| 565 | (scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) && |
| 566 | (scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) { |
| 567 | lut[2] = scaler3_cfg->cir_lut + |
| 568 | scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE; |
| 569 | config_lut = 1; |
| 570 | } |
| 571 | if (test_bit(QSEED3_COEF_LUT_Y_SEP_BIT, &lut_flags) && |
| 572 | (scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && |
| 573 | (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { |
| 574 | lut[3] = scaler3_cfg->sep_lut + |
| 575 | scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE; |
| 576 | config_lut = 1; |
| 577 | } |
| 578 | if (test_bit(QSEED3_COEF_LUT_UV_SEP_BIT, &lut_flags) && |
| 579 | (scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) && |
| 580 | (scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) { |
| 581 | lut[4] = scaler3_cfg->sep_lut + |
| 582 | scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE; |
| 583 | config_lut = 1; |
| 584 | } |
| 585 | |
| 586 | if (config_lut) { |
| 587 | for (filter = 0; filter < QSEED3_FILTERS; filter++) { |
| 588 | if (!lut[filter]) |
| 589 | continue; |
| 590 | lut_offset = 0; |
| 591 | for (i = 0; i < QSEED3_LUT_REGIONS; i++) { |
| 592 | lut_addr = QSEED3_COEF_LUT + idx |
| 593 | + offset[filter][i][1]; |
| 594 | lut_len = offset[filter][i][0] << 2; |
| 595 | for (j = 0; j < lut_len; j++) { |
| 596 | SDE_REG_WRITE(&ctx->hw, |
| 597 | lut_addr, |
| 598 | (lut[filter])[lut_offset++]); |
| 599 | lut_addr += 4; |
| 600 | } |
| 601 | } |
| 602 | } |
| 603 | } |
| 604 | |
| 605 | if (test_bit(QSEED3_COEF_LUT_SWAP_BIT, &lut_flags)) |
| 606 | SDE_REG_WRITE(&ctx->hw, QSEED3_COEF_LUT_CTRL + idx, BIT(0)); |
| 607 | |
| 608 | } |
| 609 | |
| 610 | static void _sde_hw_sspp_setup_scaler3_de(struct sde_hw_pipe *ctx, |
| 611 | struct sde_hw_scaler3_de_cfg *de_cfg) |
| 612 | { |
| 613 | u32 idx; |
| 614 | u32 sharp_lvl, sharp_ctl, shape_ctl, de_thr; |
| 615 | u32 adjust_a, adjust_b, adjust_c; |
| 616 | struct sde_hw_blk_reg_map *hw; |
| 617 | |
| 618 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !de_cfg) |
| 619 | return; |
| 620 | |
| 621 | if (!de_cfg->enable) |
| 622 | return; |
| 623 | |
| 624 | hw = &ctx->hw; |
| 625 | sharp_lvl = (de_cfg->sharpen_level1 & 0x1FF) | |
| 626 | ((de_cfg->sharpen_level2 & 0x1FF) << 16); |
| 627 | |
| 628 | sharp_ctl = ((de_cfg->limit & 0xF) << 9) | |
| 629 | ((de_cfg->prec_shift & 0x7) << 13) | |
| 630 | ((de_cfg->clip & 0x7) << 16); |
| 631 | |
| 632 | shape_ctl = (de_cfg->thr_quiet & 0xFF) | |
| 633 | ((de_cfg->thr_dieout & 0x3FF) << 16); |
| 634 | |
| 635 | de_thr = (de_cfg->thr_low & 0x3FF) | |
| 636 | ((de_cfg->thr_high & 0x3FF) << 16); |
| 637 | |
| 638 | adjust_a = (de_cfg->adjust_a[0] & 0x3FF) | |
| 639 | ((de_cfg->adjust_a[1] & 0x3FF) << 10) | |
| 640 | ((de_cfg->adjust_a[2] & 0x3FF) << 20); |
| 641 | |
| 642 | adjust_b = (de_cfg->adjust_b[0] & 0x3FF) | |
| 643 | ((de_cfg->adjust_b[1] & 0x3FF) << 10) | |
| 644 | ((de_cfg->adjust_b[2] & 0x3FF) << 20); |
| 645 | |
| 646 | adjust_c = (de_cfg->adjust_c[0] & 0x3FF) | |
| 647 | ((de_cfg->adjust_c[1] & 0x3FF) << 10) | |
| 648 | ((de_cfg->adjust_c[2] & 0x3FF) << 20); |
| 649 | |
| 650 | SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN + idx, sharp_lvl); |
| 651 | SDE_REG_WRITE(hw, QSEED3_DE_SHARPEN_CTL + idx, sharp_ctl); |
| 652 | SDE_REG_WRITE(hw, QSEED3_DE_SHAPE_CTL + idx, shape_ctl); |
| 653 | SDE_REG_WRITE(hw, QSEED3_DE_THRESHOLD + idx, de_thr); |
| 654 | SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_0 + idx, adjust_a); |
| 655 | SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_1 + idx, adjust_b); |
| 656 | SDE_REG_WRITE(hw, QSEED3_DE_ADJUST_DATA_2 + idx, adjust_c); |
| 657 | |
| 658 | } |
| 659 | |
| 660 | static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, |
| 661 | struct sde_hw_pipe_cfg *sspp, |
| 662 | struct sde_hw_pixel_ext *pe, |
| 663 | void *scaler_cfg) |
| 664 | { |
| 665 | u32 idx; |
| 666 | u32 op_mode = 0; |
| 667 | u32 phase_init, preload, src_y_rgb, src_uv, dst; |
| 668 | struct sde_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; |
| 669 | |
| 670 | (void)pe; |
| 671 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED3, &idx) || !sspp |
| 672 | || !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk) |
| 673 | return; |
| 674 | |
Dhaval Patel | a64725e | 2017-02-09 16:06:03 -0800 | [diff] [blame] | 675 | if (!scaler3_cfg->enable) |
| 676 | goto end; |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 677 | |
| 678 | op_mode |= BIT(0); |
| 679 | op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16; |
| 680 | |
| 681 | if (SDE_FORMAT_IS_YUV(sspp->layout.format)) { |
| 682 | op_mode |= BIT(12); |
| 683 | op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24; |
| 684 | } |
| 685 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 686 | op_mode |= (scaler3_cfg->blend_cfg & 1) << 31; |
| 687 | op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0; |
| 688 | |
| 689 | preload = |
| 690 | ((scaler3_cfg->preload_x[0] & 0x7F) << 0) | |
| 691 | ((scaler3_cfg->preload_y[0] & 0x7F) << 8) | |
| 692 | ((scaler3_cfg->preload_x[1] & 0x7F) << 16) | |
| 693 | ((scaler3_cfg->preload_y[1] & 0x7F) << 24); |
| 694 | |
| 695 | src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) | |
| 696 | ((scaler3_cfg->src_height[0] & 0x1FFFF) << 16); |
| 697 | |
| 698 | src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) | |
| 699 | ((scaler3_cfg->src_height[1] & 0x1FFFF) << 16); |
| 700 | |
| 701 | dst = (scaler3_cfg->dst_width & 0x1FFFF) | |
| 702 | ((scaler3_cfg->dst_height & 0x1FFFF) << 16); |
| 703 | |
| 704 | if (scaler3_cfg->de.enable) { |
| 705 | _sde_hw_sspp_setup_scaler3_de(ctx, &scaler3_cfg->de); |
| 706 | op_mode |= BIT(8); |
| 707 | } |
| 708 | |
| 709 | if (scaler3_cfg->lut_flag) |
| 710 | _sde_hw_sspp_setup_scaler3_lut(ctx, scaler3_cfg); |
| 711 | |
| 712 | if (ctx->cap->sblk->scaler_blk.version == 0x1002) { |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 713 | phase_init = |
| 714 | ((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) | |
| 715 | ((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) | |
| 716 | ((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) | |
| 717 | ((scaler3_cfg->init_phase_y[1] & 0x3F) << 24); |
| 718 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT + idx, phase_init); |
| 719 | } else { |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 720 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_H + idx, |
| 721 | scaler3_cfg->init_phase_x[0] & 0x1FFFFF); |
| 722 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_Y_V + idx, |
| 723 | scaler3_cfg->init_phase_y[0] & 0x1FFFFF); |
| 724 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_H + idx, |
| 725 | scaler3_cfg->init_phase_x[1] & 0x1FFFFF); |
| 726 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_INIT_UV_V + idx, |
| 727 | scaler3_cfg->init_phase_y[1] & 0x1FFFFF); |
| 728 | } |
| 729 | |
| 730 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_H + idx, |
| 731 | scaler3_cfg->phase_step_x[0] & 0xFFFFFF); |
| 732 | |
| 733 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_Y_V + idx, |
| 734 | scaler3_cfg->phase_step_y[0] & 0xFFFFFF); |
| 735 | |
| 736 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_H + idx, |
| 737 | scaler3_cfg->phase_step_x[1] & 0xFFFFFF); |
| 738 | |
| 739 | SDE_REG_WRITE(&ctx->hw, QSEED3_PHASE_STEP_UV_V + idx, |
| 740 | scaler3_cfg->phase_step_y[1] & 0xFFFFFF); |
| 741 | |
| 742 | SDE_REG_WRITE(&ctx->hw, QSEED3_PRELOAD + idx, preload); |
| 743 | |
| 744 | SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_Y_RGB_A + idx, src_y_rgb); |
| 745 | |
| 746 | SDE_REG_WRITE(&ctx->hw, QSEED3_SRC_SIZE_UV + idx, src_uv); |
| 747 | |
| 748 | SDE_REG_WRITE(&ctx->hw, QSEED3_DST_SIZE + idx, dst); |
| 749 | |
Dhaval Patel | a64725e | 2017-02-09 16:06:03 -0800 | [diff] [blame] | 750 | end: |
| 751 | if (!SDE_FORMAT_IS_DX(sspp->layout.format)) |
| 752 | op_mode |= BIT(14); |
| 753 | |
| 754 | if (sspp->layout.format->alpha_enable) { |
| 755 | op_mode |= BIT(10); |
| 756 | if (ctx->cap->sblk->scaler_blk.version == 0x1002) |
| 757 | op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30; |
| 758 | else |
| 759 | op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29; |
| 760 | } |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 761 | SDE_REG_WRITE(&ctx->hw, QSEED3_OP_MODE + idx, op_mode); |
| 762 | } |
| 763 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 764 | /** |
| 765 | * sde_hw_sspp_setup_rects() |
| 766 | */ |
| 767 | static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx, |
| 768 | struct sde_hw_pipe_cfg *cfg, |
Jeykumar Sankaran | 9fcfa48 | 2017-02-16 16:03:14 -0800 | [diff] [blame] | 769 | enum sde_sspp_multirect_index rect_index) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 770 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 771 | struct sde_hw_blk_reg_map *c; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 772 | u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 773 | u32 src_size_off, src_xy_off, out_size_off, out_xy_off; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 774 | u32 decimation = 0; |
| 775 | u32 idx; |
| 776 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 777 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !cfg) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 778 | return; |
| 779 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 780 | c = &ctx->hw; |
| 781 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 782 | if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0) { |
| 783 | src_size_off = SSPP_SRC_SIZE; |
| 784 | src_xy_off = SSPP_SRC_XY; |
| 785 | out_size_off = SSPP_OUT_SIZE; |
| 786 | out_xy_off = SSPP_OUT_XY; |
| 787 | } else { |
| 788 | src_size_off = SSPP_SRC_SIZE_REC1; |
| 789 | src_xy_off = SSPP_SRC_XY_REC1; |
| 790 | out_size_off = SSPP_OUT_SIZE_REC1; |
| 791 | out_xy_off = SSPP_OUT_XY_REC1; |
| 792 | } |
| 793 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 794 | |
| 795 | /* src and dest rect programming */ |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 796 | src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x); |
| 797 | src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w); |
| 798 | dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x); |
| 799 | dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 800 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 801 | if (rect_index == SDE_SSPP_RECT_SOLO) { |
| 802 | ystride0 = (cfg->layout.plane_pitch[0]) | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 803 | (cfg->layout.plane_pitch[1] << 16); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 804 | ystride1 = (cfg->layout.plane_pitch[2]) | |
Lloyd Atkinson | fa2489c | 2016-05-25 15:16:03 -0400 | [diff] [blame] | 805 | (cfg->layout.plane_pitch[3] << 16); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 806 | } else { |
| 807 | ystride0 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); |
| 808 | ystride1 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); |
| 809 | |
| 810 | if (rect_index == SDE_SSPP_RECT_0) { |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 811 | ystride0 = (ystride0 & 0xFFFF0000) | |
| 812 | (cfg->layout.plane_pitch[0] & 0x0000FFFF); |
| 813 | ystride1 = (ystride1 & 0xFFFF0000)| |
| 814 | (cfg->layout.plane_pitch[2] & 0x0000FFFF); |
| 815 | } else { |
| 816 | ystride0 = (ystride0 & 0x0000FFFF) | |
| 817 | ((cfg->layout.plane_pitch[0] << 16) & |
| 818 | 0xFFFF0000); |
| 819 | ystride1 = (ystride1 & 0x0000FFFF) | |
| 820 | ((cfg->layout.plane_pitch[2] << 16) & |
| 821 | 0xFFFF0000); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 822 | } |
| 823 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 824 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 825 | /* program scaler, phase registers, if pipes supporting scaling */ |
| 826 | if (ctx->cap->features & SDE_SSPP_SCALER) { |
| 827 | /* program decimation */ |
| 828 | decimation = ((1 << cfg->horz_decimation) - 1) << 8; |
| 829 | decimation |= ((1 << cfg->vert_decimation) - 1); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 830 | } |
| 831 | |
Clarence Ip | cb410d4 | 2016-06-26 22:52:33 -0400 | [diff] [blame] | 832 | /* rectangle register programming */ |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 833 | SDE_REG_WRITE(c, src_size_off + idx, src_size); |
| 834 | SDE_REG_WRITE(c, src_xy_off + idx, src_xy); |
| 835 | SDE_REG_WRITE(c, out_size_off + idx, dst_size); |
| 836 | SDE_REG_WRITE(c, out_xy_off + idx, dst_xy); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 837 | |
| 838 | SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); |
| 839 | SDE_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); |
| 840 | SDE_REG_WRITE(c, SSPP_DECIMATION_CONFIG + idx, decimation); |
| 841 | } |
| 842 | |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 843 | /** |
| 844 | * _sde_hw_sspp_setup_excl_rect() - set exclusion rect configs |
| 845 | * @ctx: Pointer to pipe context |
| 846 | * @excl_rect: Exclusion rect configs |
| 847 | */ |
| 848 | static void _sde_hw_sspp_setup_excl_rect(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 849 | struct sde_rect *excl_rect, |
| 850 | enum sde_sspp_multirect_index rect_index) |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 851 | { |
| 852 | struct sde_hw_blk_reg_map *c; |
| 853 | u32 size, xy; |
| 854 | u32 idx; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 855 | u32 reg_xy, reg_size; |
| 856 | u32 excl_ctrl, enable_bit; |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 857 | |
| 858 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !excl_rect) |
| 859 | return; |
| 860 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 861 | if (rect_index == SDE_SSPP_RECT_0 || rect_index == SDE_SSPP_RECT_SOLO) { |
| 862 | reg_xy = SSPP_EXCL_REC_XY; |
| 863 | reg_size = SSPP_EXCL_REC_SIZE; |
| 864 | enable_bit = BIT(0); |
| 865 | } else { |
| 866 | reg_xy = SSPP_EXCL_REC_XY_REC1; |
| 867 | reg_size = SSPP_EXCL_REC_SIZE_REC1; |
| 868 | enable_bit = BIT(1); |
| 869 | } |
| 870 | |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 871 | c = &ctx->hw; |
| 872 | |
| 873 | xy = (excl_rect->y << 16) | (excl_rect->x); |
| 874 | size = (excl_rect->h << 16) | (excl_rect->w); |
| 875 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 876 | excl_ctrl = SDE_REG_READ(c, SSPP_EXCL_REC_CTL + idx); |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 877 | if (!size) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 878 | SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx, |
| 879 | excl_ctrl & ~enable_bit); |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 880 | } else { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 881 | SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx, |
| 882 | excl_ctrl | enable_bit); |
| 883 | SDE_REG_WRITE(c, reg_size + idx, size); |
| 884 | SDE_REG_WRITE(c, reg_xy + idx, xy); |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 885 | } |
| 886 | } |
| 887 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 888 | static void sde_hw_sspp_setup_sourceaddress(struct sde_hw_pipe *ctx, |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 889 | struct sde_hw_pipe_cfg *cfg, |
| 890 | enum sde_sspp_multirect_index rect_mode) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 891 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 892 | int i; |
| 893 | u32 idx; |
| 894 | |
| 895 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 896 | return; |
| 897 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 898 | if (rect_mode == SDE_SSPP_RECT_SOLO) { |
| 899 | for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) |
| 900 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, |
| 901 | cfg->layout.plane_addr[i]); |
| 902 | } else if (rect_mode == SDE_SSPP_RECT_0) { |
| 903 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, |
| 904 | cfg->layout.plane_addr[0]); |
| 905 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, |
| 906 | cfg->layout.plane_addr[2]); |
| 907 | } else { |
| 908 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, |
| 909 | cfg->layout.plane_addr[0]); |
| 910 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, |
| 911 | cfg->layout.plane_addr[2]); |
| 912 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 913 | } |
| 914 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 915 | static void sde_hw_sspp_setup_csc(struct sde_hw_pipe *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 916 | struct sde_csc_cfg *data) |
| 917 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 918 | u32 idx; |
Alan Kwong | eab00a0c | 2017-03-10 13:22:58 -0800 | [diff] [blame] | 919 | bool csc10 = false; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 920 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 921 | if (_sspp_subblk_offset(ctx, SDE_SSPP_CSC, &idx) || !data) |
| 922 | return; |
| 923 | |
Alan Kwong | eab00a0c | 2017-03-10 13:22:58 -0800 | [diff] [blame] | 924 | if (test_bit(SDE_SSPP_CSC_10BIT, &ctx->cap->features)) { |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 925 | idx += CSC_10BIT_OFFSET; |
Alan Kwong | eab00a0c | 2017-03-10 13:22:58 -0800 | [diff] [blame] | 926 | csc10 = true; |
| 927 | } |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 928 | |
Alan Kwong | eab00a0c | 2017-03-10 13:22:58 -0800 | [diff] [blame] | 929 | sde_hw_csc_setup(&ctx->hw, idx, data, csc10); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | static void sde_hw_sspp_setup_sharpening(struct sde_hw_pipe *ctx, |
| 933 | struct sde_hw_sharp_cfg *cfg) |
| 934 | { |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 935 | struct sde_hw_blk_reg_map *c; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 936 | u32 idx; |
| 937 | |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 938 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SCALER_QSEED2, &idx) || !cfg || |
| 939 | !test_bit(SDE_SSPP_SCALER_QSEED2, &ctx->cap->features)) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 940 | return; |
| 941 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 942 | c = &ctx->hw; |
| 943 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 944 | SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx, cfg->strength); |
| 945 | SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x4, cfg->edge_thr); |
| 946 | SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0x8, cfg->smooth_thr); |
| 947 | SDE_REG_WRITE(c, VIG_0_QSEED2_SHARP + idx + 0xC, cfg->noise_thr); |
| 948 | } |
| 949 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 950 | static void sde_hw_sspp_setup_solidfill(struct sde_hw_pipe *ctx, u32 color, enum |
| 951 | sde_sspp_multirect_index rect_index) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 952 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 953 | u32 idx; |
| 954 | |
| 955 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 956 | return; |
| 957 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 958 | if (rect_index == SDE_SSPP_RECT_SOLO || rect_index == SDE_SSPP_RECT_0) |
| 959 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); |
| 960 | else |
| 961 | SDE_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, |
| 962 | color); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 963 | } |
| 964 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 965 | static void sde_hw_sspp_setup_danger_safe_lut(struct sde_hw_pipe *ctx, |
| 966 | struct sde_hw_pipe_qos_cfg *cfg) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 967 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 968 | u32 idx; |
| 969 | |
| 970 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 971 | return; |
| 972 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 973 | SDE_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT + idx, cfg->danger_lut); |
| 974 | SDE_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, cfg->safe_lut); |
| 975 | } |
| 976 | |
| 977 | static void sde_hw_sspp_setup_creq_lut(struct sde_hw_pipe *ctx, |
| 978 | struct sde_hw_pipe_qos_cfg *cfg) |
| 979 | { |
| 980 | u32 idx; |
| 981 | |
| 982 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 983 | return; |
| 984 | |
| 985 | SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT + idx, cfg->creq_lut); |
| 986 | } |
| 987 | |
| 988 | static void sde_hw_sspp_setup_qos_ctrl(struct sde_hw_pipe *ctx, |
| 989 | struct sde_hw_pipe_qos_cfg *cfg) |
| 990 | { |
| 991 | u32 idx; |
| 992 | u32 qos_ctrl = 0; |
| 993 | |
| 994 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 995 | return; |
| 996 | |
| 997 | if (cfg->vblank_en) { |
| 998 | qos_ctrl |= ((cfg->creq_vblank & |
| 999 | SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << |
| 1000 | SSPP_QOS_CTRL_CREQ_VBLANK_OFF); |
| 1001 | qos_ctrl |= ((cfg->danger_vblank & |
| 1002 | SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << |
| 1003 | SSPP_QOS_CTRL_DANGER_VBLANK_OFF); |
| 1004 | qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; |
| 1005 | } |
| 1006 | |
| 1007 | if (cfg->danger_safe_en) |
| 1008 | qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; |
| 1009 | |
| 1010 | SDE_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1011 | } |
| 1012 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1013 | static void sde_hw_sspp_setup_sys_cache(struct sde_hw_pipe *ctx, |
| 1014 | struct sde_hw_pipe_sc_cfg *cfg) |
| 1015 | { |
| 1016 | u32 idx, val; |
| 1017 | |
| 1018 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 1019 | return; |
| 1020 | |
| 1021 | if (!cfg) |
| 1022 | return; |
| 1023 | |
| 1024 | val = ((cfg->op_mode & 0x3) << 18) | |
| 1025 | ((cfg->rd_en & 0x1) << 15) | |
| 1026 | ((cfg->rd_scid & 0x1f) << 8) | |
| 1027 | ((cfg->rd_noallocate & 0x1) << 4) | |
| 1028 | ((cfg->rd_op_type & 0xf) << 0); |
| 1029 | |
| 1030 | SDE_REG_WRITE(&ctx->hw, SSPP_SYS_CACHE_MODE + idx, val); |
| 1031 | } |
| 1032 | |
| 1033 | static void sde_hw_sspp_get_sbuf_status(struct sde_hw_pipe *ctx, |
| 1034 | struct sde_hw_pipe_sbuf_status *status) |
| 1035 | { |
| 1036 | u32 idx, val; |
| 1037 | |
| 1038 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 1039 | return; |
| 1040 | |
| 1041 | if (!status) |
| 1042 | return; |
| 1043 | |
| 1044 | val = SDE_REG_READ(&ctx->hw, SSPP_SBUF_STATUS_PLANE0 + idx); |
| 1045 | status->empty[0] = val & SSPP_SBUF_STATUS_PLANE_EMPTY ? true : false; |
| 1046 | status->rd_ptr[0] = val & 0xffff; |
| 1047 | val = SDE_REG_READ(&ctx->hw, SSPP_SBUF_STATUS_PLANE1 + idx); |
| 1048 | status->empty[1] = val & SSPP_SBUF_STATUS_PLANE_EMPTY ? true : false; |
| 1049 | status->rd_ptr[1] = val & 0xffff; |
| 1050 | } |
| 1051 | |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 1052 | static void sde_hw_sspp_setup_ts_prefill(struct sde_hw_pipe *ctx, |
| 1053 | struct sde_hw_pipe_ts_cfg *cfg, |
| 1054 | enum sde_sspp_multirect_index index) |
| 1055 | { |
| 1056 | u32 idx; |
| 1057 | u32 ts_offset, ts_prefill_offset; |
| 1058 | u32 ts_count = 0, ts_bytes = 0; |
| 1059 | const struct sde_sspp_cfg *cap; |
| 1060 | |
| 1061 | if (!ctx || !cfg || !ctx->cap) |
| 1062 | return; |
| 1063 | |
| 1064 | if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx)) |
| 1065 | return; |
| 1066 | |
| 1067 | cap = ctx->cap; |
| 1068 | |
| 1069 | if (index == SDE_SSPP_RECT_0 && |
| 1070 | test_bit(SDE_SSPP_TS_PREFILL, &cap->features)) { |
| 1071 | ts_offset = SSPP_TRAFFIC_SHAPER; |
| 1072 | ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL; |
| 1073 | } else if (index == SDE_SSPP_RECT_1 && |
| 1074 | test_bit(SDE_SSPP_TS_PREFILL_REC1, &cap->features)) { |
| 1075 | ts_offset = SSPP_TRAFFIC_SHAPER_REC1; |
| 1076 | ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL; |
| 1077 | } else { |
| 1078 | return; |
| 1079 | } |
| 1080 | |
| 1081 | if (cfg->time) { |
| 1082 | ts_bytes = mult_frac(TS_CLK * 1000000ULL, cfg->size, |
| 1083 | cfg->time); |
| 1084 | if (ts_bytes > SSPP_TRAFFIC_SHAPER_BPC_MAX) |
| 1085 | ts_bytes = SSPP_TRAFFIC_SHAPER_BPC_MAX; |
| 1086 | } |
| 1087 | |
| 1088 | if (ts_bytes) { |
| 1089 | ts_count = DIV_ROUND_UP_ULL(cfg->size, ts_bytes); |
| 1090 | ts_bytes |= BIT(31) | BIT(27); |
| 1091 | } |
| 1092 | |
| 1093 | SDE_REG_WRITE(&ctx->hw, ts_offset, ts_bytes); |
| 1094 | SDE_REG_WRITE(&ctx->hw, ts_prefill_offset, ts_count); |
| 1095 | } |
| 1096 | |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1097 | static void _setup_layer_ops(struct sde_hw_pipe *c, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1098 | unsigned long features) |
| 1099 | { |
| 1100 | if (test_bit(SDE_SSPP_SRC, &features)) { |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1101 | c->ops.setup_format = sde_hw_sspp_setup_format; |
| 1102 | c->ops.setup_rects = sde_hw_sspp_setup_rects; |
| 1103 | c->ops.setup_sourceaddress = sde_hw_sspp_setup_sourceaddress; |
| 1104 | c->ops.setup_solidfill = sde_hw_sspp_setup_solidfill; |
Jeykumar Sankaran | 9fcfa48 | 2017-02-16 16:03:14 -0800 | [diff] [blame] | 1105 | c->ops.setup_pe = sde_hw_sspp_setup_pe_config; |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1106 | } |
Veera Sundaram Sankaran | 02dd6ac | 2016-12-22 15:08:29 -0800 | [diff] [blame] | 1107 | |
| 1108 | if (test_bit(SDE_SSPP_EXCL_RECT, &features)) |
| 1109 | c->ops.setup_excl_rect = _sde_hw_sspp_setup_excl_rect; |
| 1110 | |
Alan Kwong | 1a00e4d | 2016-07-18 09:42:30 -0400 | [diff] [blame] | 1111 | if (test_bit(SDE_SSPP_QOS, &features)) { |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1112 | c->ops.setup_danger_safe_lut = |
| 1113 | sde_hw_sspp_setup_danger_safe_lut; |
| 1114 | c->ops.setup_creq_lut = sde_hw_sspp_setup_creq_lut; |
| 1115 | c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1116 | } |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1117 | |
Alan Kwong | 2349d74 | 2017-04-20 08:27:30 -0700 | [diff] [blame^] | 1118 | if (test_bit(SDE_SSPP_TS_PREFILL, &features)) |
| 1119 | c->ops.setup_ts_prefill = sde_hw_sspp_setup_ts_prefill; |
| 1120 | |
abeykun | 6257614 | 2016-08-25 17:44:05 -0400 | [diff] [blame] | 1121 | if (test_bit(SDE_SSPP_CSC, &features) || |
| 1122 | test_bit(SDE_SSPP_CSC_10BIT, &features)) |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1123 | c->ops.setup_csc = sde_hw_sspp_setup_csc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1124 | |
Jeykumar Sankaran | 9fcfa48 | 2017-02-16 16:03:14 -0800 | [diff] [blame] | 1125 | if (test_bit(SDE_SSPP_SCALER_QSEED2, &features)) { |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1126 | c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening; |
Jeykumar Sankaran | 9fcfa48 | 2017-02-16 16:03:14 -0800 | [diff] [blame] | 1127 | c->ops.setup_scaler = _sde_hw_sspp_setup_scaler; |
| 1128 | } |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1129 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 1130 | if (sde_hw_sspp_multirect_enabled(c->cap)) |
| 1131 | c->ops.setup_multirect = sde_hw_sspp_setup_multirect; |
| 1132 | |
abeykun | 48f407a | 2016-08-25 12:06:44 -0400 | [diff] [blame] | 1133 | if (test_bit(SDE_SSPP_SCALER_QSEED3, &features)) |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1134 | c->ops.setup_scaler = _sde_hw_sspp_setup_scaler3; |
Benet Clark | eb1b446 | 2016-06-27 14:43:06 -0700 | [diff] [blame] | 1135 | |
| 1136 | if (test_bit(SDE_SSPP_HSIC, &features)) { |
| 1137 | /* TODO: add version based assignment here as inline or macro */ |
| 1138 | if (c->cap->sblk->hsic_blk.version == |
| 1139 | (SDE_COLOR_PROCESS_VER(0x1, 0x7))) { |
| 1140 | c->ops.setup_pa_hue = sde_setup_pipe_pa_hue_v1_7; |
| 1141 | c->ops.setup_pa_sat = sde_setup_pipe_pa_sat_v1_7; |
| 1142 | c->ops.setup_pa_val = sde_setup_pipe_pa_val_v1_7; |
| 1143 | c->ops.setup_pa_cont = sde_setup_pipe_pa_cont_v1_7; |
| 1144 | } |
| 1145 | } |
Benet Clark | d009b1d | 2016-06-27 14:45:59 -0700 | [diff] [blame] | 1146 | |
| 1147 | if (test_bit(SDE_SSPP_MEMCOLOR, &features)) { |
| 1148 | if (c->cap->sblk->memcolor_blk.version == |
| 1149 | (SDE_COLOR_PROCESS_VER(0x1, 0x7))) |
| 1150 | c->ops.setup_pa_memcolor = |
| 1151 | sde_setup_pipe_pa_memcol_v1_7; |
| 1152 | } |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1153 | |
| 1154 | if (test_bit(SDE_SSPP_SBUF, &features)) { |
| 1155 | c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache; |
| 1156 | c->ops.get_sbuf_status = sde_hw_sspp_get_sbuf_status; |
| 1157 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1158 | } |
| 1159 | |
| 1160 | static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1161 | void __iomem *addr, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1162 | struct sde_mdss_cfg *catalog, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1163 | struct sde_hw_blk_reg_map *b) |
| 1164 | { |
| 1165 | int i; |
| 1166 | |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1167 | if ((sspp < SSPP_MAX) && catalog && addr && b) { |
| 1168 | for (i = 0; i < catalog->sspp_count; i++) { |
| 1169 | if (sspp == catalog->sspp[i].id) { |
| 1170 | b->base_off = addr; |
| 1171 | b->blk_off = catalog->sspp[i].base; |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1172 | b->length = catalog->sspp[i].len; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1173 | b->hwversion = catalog->hwversion; |
Clarence Ip | 4ce5932 | 2016-06-26 22:27:51 -0400 | [diff] [blame] | 1174 | b->log_mask = SDE_DBG_MASK_SSPP; |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1175 | return &catalog->sspp[i]; |
| 1176 | } |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1177 | } |
| 1178 | } |
| 1179 | |
| 1180 | return ERR_PTR(-ENOMEM); |
| 1181 | } |
| 1182 | |
| 1183 | struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx, |
| 1184 | void __iomem *addr, |
Clarence Ip | e78efb7 | 2016-06-24 18:35:21 -0400 | [diff] [blame] | 1185 | struct sde_mdss_cfg *catalog) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1186 | { |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1187 | struct sde_hw_pipe *hw_pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1188 | struct sde_sspp_cfg *cfg; |
| 1189 | |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame] | 1190 | if (!addr || !catalog) |
| 1191 | return ERR_PTR(-EINVAL); |
| 1192 | |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1193 | hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); |
| 1194 | if (!hw_pipe) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1195 | return ERR_PTR(-ENOMEM); |
| 1196 | |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1197 | cfg = _sspp_offset(idx, addr, catalog, &hw_pipe->hw); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1198 | if (IS_ERR_OR_NULL(cfg)) { |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1199 | kfree(hw_pipe); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1200 | return ERR_PTR(-EINVAL); |
| 1201 | } |
| 1202 | |
| 1203 | /* Assign ops */ |
Clarence Ip | 32bcb00 | 2017-03-13 12:26:44 -0700 | [diff] [blame] | 1204 | hw_pipe->catalog = catalog; |
| 1205 | hw_pipe->mdp = &catalog->mdp[0]; |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1206 | hw_pipe->idx = idx; |
| 1207 | hw_pipe->cap = cfg; |
| 1208 | _setup_layer_ops(hw_pipe, hw_pipe->cap->features); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1209 | |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 1210 | sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, |
| 1211 | hw_pipe->hw.blk_off, |
| 1212 | hw_pipe->hw.blk_off + hw_pipe->hw.length, |
| 1213 | hw_pipe->hw.xin_id); |
| 1214 | |
| 1215 | if (cfg->sblk->scaler_blk.len) |
| 1216 | sde_dbg_reg_register_dump_range(SDE_DBG_NAME, |
| 1217 | cfg->sblk->scaler_blk.name, |
Lloyd Atkinson | ac4b6e0 | 2017-03-23 11:43:48 -0700 | [diff] [blame] | 1218 | hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base, |
| 1219 | hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base + |
| 1220 | cfg->sblk->scaler_blk.len, |
Lloyd Atkinson | 113aefd | 2016-10-23 13:15:18 -0400 | [diff] [blame] | 1221 | hw_pipe->hw.xin_id); |
| 1222 | |
Lloyd Atkinson | 7715873 | 2016-10-23 13:02:00 -0400 | [diff] [blame] | 1223 | return hw_pipe; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1224 | } |
| 1225 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1226 | void sde_hw_sspp_destroy(struct sde_hw_pipe *ctx) |
| 1227 | { |
| 1228 | kfree(ctx); |
| 1229 | } |
| 1230 | |