Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 1 | /* |
| 2 | * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Atmel, |
| 5 | * 2012 Hong Xu <hong.xu@atmel.com> |
| 6 | * |
| 7 | * Licensed under GPLv2 or later. |
| 8 | */ |
| 9 | |
| 10 | /include/ "skeleton.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "Atmel AT91SAM9N12 SoC"; |
| 14 | compatible = "atmel,at91sam9n12"; |
| 15 | interrupt-parent = <&aic>; |
| 16 | |
| 17 | aliases { |
| 18 | serial0 = &dbgu; |
| 19 | serial1 = &usart0; |
| 20 | serial2 = &usart1; |
| 21 | serial3 = &usart2; |
| 22 | serial4 = &usart3; |
| 23 | gpio0 = &pioA; |
| 24 | gpio1 = &pioB; |
| 25 | gpio2 = &pioC; |
| 26 | gpio3 = &pioD; |
| 27 | tcb0 = &tcb0; |
| 28 | tcb1 = &tcb1; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 29 | i2c0 = &i2c0; |
| 30 | i2c1 = &i2c1; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 31 | }; |
| 32 | cpus { |
| 33 | cpu@0 { |
| 34 | compatible = "arm,arm926ejs"; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | memory { |
| 39 | reg = <0x20000000 0x10000000>; |
| 40 | }; |
| 41 | |
| 42 | ahb { |
| 43 | compatible = "simple-bus"; |
| 44 | #address-cells = <1>; |
| 45 | #size-cells = <1>; |
| 46 | ranges; |
| 47 | |
| 48 | apb { |
| 49 | compatible = "simple-bus"; |
| 50 | #address-cells = <1>; |
| 51 | #size-cells = <1>; |
| 52 | ranges; |
| 53 | |
| 54 | aic: interrupt-controller@fffff000 { |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 55 | #interrupt-cells = <3>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 56 | compatible = "atmel,at91rm9200-aic"; |
| 57 | interrupt-controller; |
| 58 | reg = <0xfffff000 0x200>; |
| 59 | }; |
| 60 | |
| 61 | ramc0: ramc@ffffe800 { |
| 62 | compatible = "atmel,at91sam9g45-ddramc"; |
| 63 | reg = <0xffffe800 0x200>; |
| 64 | }; |
| 65 | |
| 66 | pmc: pmc@fffffc00 { |
| 67 | compatible = "atmel,at91rm9200-pmc"; |
| 68 | reg = <0xfffffc00 0x100>; |
| 69 | }; |
| 70 | |
| 71 | rstc@fffffe00 { |
| 72 | compatible = "atmel,at91sam9g45-rstc"; |
| 73 | reg = <0xfffffe00 0x10>; |
| 74 | }; |
| 75 | |
| 76 | pit: timer@fffffe30 { |
| 77 | compatible = "atmel,at91sam9260-pit"; |
| 78 | reg = <0xfffffe30 0xf>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 79 | interrupts = <1 4 7>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 80 | }; |
| 81 | |
| 82 | shdwc@fffffe10 { |
| 83 | compatible = "atmel,at91sam9x5-shdwc"; |
| 84 | reg = <0xfffffe10 0x10>; |
| 85 | }; |
| 86 | |
| 87 | tcb0: timer@f8008000 { |
| 88 | compatible = "atmel,at91sam9x5-tcb"; |
| 89 | reg = <0xf8008000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 90 | interrupts = <17 4 0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | tcb1: timer@f800c000 { |
| 94 | compatible = "atmel,at91sam9x5-tcb"; |
| 95 | reg = <0xf800c000 0x100>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 96 | interrupts = <17 4 0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | dma: dma-controller@ffffec00 { |
| 100 | compatible = "atmel,at91sam9g45-dma"; |
| 101 | reg = <0xffffec00 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 102 | interrupts = <20 4 0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 103 | }; |
| 104 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 105 | pinctrl@fffff400 { |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <1>; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 108 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 109 | ranges = <0xfffff400 0xfffff400 0x800>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 110 | |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 111 | atmel,mux-mask = < |
| 112 | /* A B C */ |
| 113 | 0xffffffff 0xffe07983 0x00000000 /* pioA */ |
| 114 | 0x00040000 0x00047e0f 0x00000000 /* pioB */ |
| 115 | 0xfdffffff 0x07c00000 0xb83fffff /* pioC */ |
| 116 | 0x003fffff 0x003f8000 0x00000000 /* pioD */ |
| 117 | >; |
| 118 | |
| 119 | /* shared pinctrl settings */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 120 | dbgu { |
| 121 | pinctrl_dbgu: dbgu-0 { |
| 122 | atmel,pins = |
| 123 | <0 9 0x1 0x0 /* PA9 periph A */ |
| 124 | 0 10 0x1 0x1>; /* PA10 periph with pullup */ |
| 125 | }; |
| 126 | }; |
| 127 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 128 | usart0 { |
| 129 | pinctrl_usart0: usart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 130 | atmel,pins = |
| 131 | <0 1 0x1 0x1 /* PA1 periph A with pullup */ |
| 132 | 0 0 0x1 0x0>; /* PA0 periph A */ |
| 133 | }; |
| 134 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 135 | pinctrl_usart0_rts: usart0_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 136 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 137 | <0 2 0x1 0x0>; /* PA2 periph A */ |
| 138 | }; |
| 139 | |
| 140 | pinctrl_usart0_cts: usart0_cts-0 { |
| 141 | atmel,pins = |
| 142 | <0 3 0x1 0x0>; /* PA3 periph A */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 143 | }; |
| 144 | }; |
| 145 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 146 | usart1 { |
| 147 | pinctrl_usart1: usart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 148 | atmel,pins = |
| 149 | <0 6 0x1 0x1 /* PA6 periph A with pullup */ |
| 150 | 0 5 0x1 0x0>; /* PA5 periph A */ |
| 151 | }; |
| 152 | }; |
| 153 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 154 | usart2 { |
| 155 | pinctrl_usart2: usart2-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 156 | atmel,pins = |
| 157 | <0 8 0x1 0x1 /* PA8 periph A with pullup */ |
| 158 | 0 7 0x1 0x0>; /* PA7 periph A */ |
| 159 | }; |
| 160 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 161 | pinctrl_usart2_rts: usart2_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 162 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 163 | <1 0 0x2 0x0>; /* PB0 periph B */ |
| 164 | }; |
| 165 | |
| 166 | pinctrl_usart2_cts: usart2_cts-0 { |
| 167 | atmel,pins = |
| 168 | <1 1 0x2 0x0>; /* PB1 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 169 | }; |
| 170 | }; |
| 171 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 172 | usart3 { |
| 173 | pinctrl_usart3: usart3-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 174 | atmel,pins = |
| 175 | <2 23 0x2 0x1 /* PC23 periph B with pullup */ |
| 176 | 2 22 0x2 0x0>; /* PC22 periph B */ |
| 177 | }; |
| 178 | |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 179 | pinctrl_usart3_rts: usart3_rts-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 180 | atmel,pins = |
Jean-Christophe PLAGNIOL-VILLARD | c58c0c5 | 2012-11-19 07:30:01 +0800 | [diff] [blame] | 181 | <2 24 0x2 0x0>; /* PC24 periph B */ |
| 182 | }; |
| 183 | |
| 184 | pinctrl_usart3_cts: usart3_cts-0 { |
| 185 | atmel,pins = |
| 186 | <2 25 0x2 0x0>; /* PC25 periph B */ |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 187 | }; |
| 188 | }; |
| 189 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 190 | uart0 { |
| 191 | pinctrl_uart0: uart0-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 192 | atmel,pins = |
| 193 | <2 9 0x3 0x1 /* PC9 periph C with pullup */ |
| 194 | 2 8 0x3 0x0>; /* PC8 periph C */ |
| 195 | }; |
| 196 | }; |
| 197 | |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 198 | uart1 { |
| 199 | pinctrl_uart1: uart1-0 { |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 200 | atmel,pins = |
| 201 | <2 16 0x3 0x1 /* PC17 periph C with pullup */ |
| 202 | 2 17 0x3 0x0>; /* PC16 periph C */ |
| 203 | }; |
| 204 | }; |
Jean-Christophe PLAGNIOL-VILLARD | 5314ec8 | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 205 | |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 206 | nand { |
| 207 | pinctrl_nand: nand-0 { |
| 208 | atmel,pins = |
| 209 | <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/ |
| 210 | 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */ |
| 211 | }; |
| 212 | }; |
| 213 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 214 | pioA: gpio@fffff400 { |
| 215 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 216 | reg = <0xfffff400 0x200>; |
| 217 | interrupts = <2 4 1>; |
| 218 | #gpio-cells = <2>; |
| 219 | gpio-controller; |
| 220 | interrupt-controller; |
| 221 | #interrupt-cells = <2>; |
| 222 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 223 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 224 | pioB: gpio@fffff600 { |
| 225 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 226 | reg = <0xfffff600 0x200>; |
| 227 | interrupts = <2 4 1>; |
| 228 | #gpio-cells = <2>; |
| 229 | gpio-controller; |
| 230 | interrupt-controller; |
| 231 | #interrupt-cells = <2>; |
| 232 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 233 | |
Jean-Christophe PLAGNIOL-VILLARD | e4541ff | 2012-07-04 17:20:46 +0800 | [diff] [blame] | 234 | pioC: gpio@fffff800 { |
| 235 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 236 | reg = <0xfffff800 0x200>; |
| 237 | interrupts = <3 4 1>; |
| 238 | #gpio-cells = <2>; |
| 239 | gpio-controller; |
| 240 | interrupt-controller; |
| 241 | #interrupt-cells = <2>; |
| 242 | }; |
| 243 | |
| 244 | pioD: gpio@fffffa00 { |
| 245 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
| 246 | reg = <0xfffffa00 0x200>; |
| 247 | interrupts = <3 4 1>; |
| 248 | #gpio-cells = <2>; |
| 249 | gpio-controller; |
| 250 | interrupt-controller; |
| 251 | #interrupt-cells = <2>; |
| 252 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 253 | }; |
| 254 | |
| 255 | dbgu: serial@fffff200 { |
| 256 | compatible = "atmel,at91sam9260-usart"; |
| 257 | reg = <0xfffff200 0x200>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 258 | interrupts = <1 4 7>; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 259 | pinctrl-names = "default"; |
| 260 | pinctrl-0 = <&pinctrl_dbgu>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 261 | status = "disabled"; |
| 262 | }; |
| 263 | |
| 264 | usart0: serial@f801c000 { |
| 265 | compatible = "atmel,at91sam9260-usart"; |
| 266 | reg = <0xf801c000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 267 | interrupts = <5 4 5>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 268 | atmel,use-dma-rx; |
| 269 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 270 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 271 | pinctrl-0 = <&pinctrl_usart0>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 272 | status = "disabled"; |
| 273 | }; |
| 274 | |
| 275 | usart1: serial@f8020000 { |
| 276 | compatible = "atmel,at91sam9260-usart"; |
| 277 | reg = <0xf8020000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 278 | interrupts = <6 4 5>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 279 | atmel,use-dma-rx; |
| 280 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 281 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 282 | pinctrl-0 = <&pinctrl_usart1>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 283 | status = "disabled"; |
| 284 | }; |
| 285 | |
| 286 | usart2: serial@f8024000 { |
| 287 | compatible = "atmel,at91sam9260-usart"; |
| 288 | reg = <0xf8024000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 289 | interrupts = <7 4 5>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 290 | atmel,use-dma-rx; |
| 291 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 292 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 293 | pinctrl-0 = <&pinctrl_usart2>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 294 | status = "disabled"; |
| 295 | }; |
| 296 | |
| 297 | usart3: serial@f8028000 { |
| 298 | compatible = "atmel,at91sam9260-usart"; |
| 299 | reg = <0xf8028000 0x4000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 300 | interrupts = <8 4 5>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 301 | atmel,use-dma-rx; |
| 302 | atmel,use-dma-tx; |
Jean-Christophe PLAGNIOL-VILLARD | ec6754a | 2012-07-05 16:56:09 +0800 | [diff] [blame] | 303 | pinctrl-names = "default"; |
Jean-Christophe PLAGNIOL-VILLARD | 9e3129e | 2012-11-19 06:40:01 +0800 | [diff] [blame] | 304 | pinctrl-0 = <&pinctrl_usart3>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 305 | status = "disabled"; |
| 306 | }; |
Ludovic Desroches | 05dcd36 | 2012-09-12 08:42:16 +0200 | [diff] [blame] | 307 | |
| 308 | i2c0: i2c@f8010000 { |
| 309 | compatible = "atmel,at91sam9x5-i2c"; |
| 310 | reg = <0xf8010000 0x100>; |
| 311 | interrupts = <9 4 6>; |
| 312 | #address-cells = <1>; |
| 313 | #size-cells = <0>; |
| 314 | status = "disabled"; |
| 315 | }; |
| 316 | |
| 317 | i2c1: i2c@f8014000 { |
| 318 | compatible = "atmel,at91sam9x5-i2c"; |
| 319 | reg = <0xf8014000 0x100>; |
| 320 | interrupts = <10 4 6>; |
| 321 | #address-cells = <1>; |
| 322 | #size-cells = <0>; |
| 323 | status = "disabled"; |
| 324 | }; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 325 | }; |
| 326 | |
| 327 | nand0: nand@40000000 { |
| 328 | compatible = "atmel,at91rm9200-nand"; |
| 329 | #address-cells = <1>; |
| 330 | #size-cells = <1>; |
| 331 | reg = < 0x40000000 0x10000000 |
| 332 | 0xffffe000 0x00000600 |
| 333 | 0xffffe600 0x00000200 |
| 334 | 0x00100000 0x00100000 |
| 335 | >; |
| 336 | atmel,nand-addr-offset = <21>; |
| 337 | atmel,nand-cmd-offset = <22>; |
Jean-Christophe PLAGNIOL-VILLARD | 7a38d45 | 2012-07-12 23:36:52 +0800 | [diff] [blame] | 338 | pinctrl-names = "default"; |
| 339 | pinctrl-0 = <&pinctrl_nand>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 340 | gpios = <&pioD 5 0 |
| 341 | &pioD 4 0 |
| 342 | 0 |
| 343 | >; |
| 344 | status = "disabled"; |
| 345 | }; |
| 346 | |
| 347 | usb0: ohci@00500000 { |
| 348 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 349 | reg = <0x00500000 0x00100000>; |
Ludovic Desroches | f8a073e | 2012-06-20 16:13:30 +0200 | [diff] [blame] | 350 | interrupts = <22 4 2>; |
Hong Xu | cce783c | 2012-04-17 14:26:29 +0800 | [diff] [blame] | 351 | status = "disabled"; |
| 352 | }; |
| 353 | }; |
| 354 | |
| 355 | i2c@0 { |
| 356 | compatible = "i2c-gpio"; |
| 357 | gpios = <&pioA 30 0 /* sda */ |
| 358 | &pioA 31 0 /* scl */ |
| 359 | >; |
| 360 | i2c-gpio,sda-open-drain; |
| 361 | i2c-gpio,scl-open-drain; |
| 362 | i2c-gpio,delay-us = <2>; /* ~100 kHz */ |
| 363 | #address-cells = <1>; |
| 364 | #size-cells = <0>; |
| 365 | status = "disabled"; |
| 366 | }; |
| 367 | }; |