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Jesse Barnes585fb112008-07-29 11:54:06 -07001/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
Jesse Barnes585fb112008-07-29 11:54:06 -070028/*
29 * The Bridge device's PCI config space has information about the
30 * fb aperture size and the amount of pre-reserved memory.
31 */
32#define INTEL_GMCH_CTRL 0x52
33#define INTEL_GMCH_ENABLED 0x4
34#define INTEL_GMCH_MEM_MASK 0x1
35#define INTEL_GMCH_MEM_64M 0x1
36#define INTEL_GMCH_MEM_128M 0
37
Eric Anholt241fa852009-01-02 18:05:51 -080038#define INTEL_GMCH_GMS_MASK (0xf << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070039#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
40#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
41#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
42#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
43#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
44#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
45
46#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
47#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
Eric Anholt241fa852009-01-02 18:05:51 -080048#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4)
49#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4)
50#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
51#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
52#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
53#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
Jesse Barnes585fb112008-07-29 11:54:06 -070054
55/* PCI config space */
56
57#define HPLLCC 0xc0 /* 855 only */
58#define GC_CLOCK_CONTROL_MASK (3 << 0)
59#define GC_CLOCK_133_200 (0 << 0)
60#define GC_CLOCK_100_200 (1 << 0)
61#define GC_CLOCK_100_133 (2 << 0)
62#define GC_CLOCK_166_250 (3 << 0)
63#define GCFGC 0xf0 /* 915+ only */
64#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
65#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
66#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
67#define GC_DISPLAY_CLOCK_MASK (7 << 4)
68#define LBB 0xf4
69
70/* VGA stuff */
71
72#define VGA_ST01_MDA 0x3ba
73#define VGA_ST01_CGA 0x3da
74
75#define VGA_MSR_WRITE 0x3c2
76#define VGA_MSR_READ 0x3cc
77#define VGA_MSR_MEM_EN (1<<1)
78#define VGA_MSR_CGA_MODE (1<<0)
79
80#define VGA_SR_INDEX 0x3c4
81#define VGA_SR_DATA 0x3c5
82
83#define VGA_AR_INDEX 0x3c0
84#define VGA_AR_VID_EN (1<<5)
85#define VGA_AR_DATA_WRITE 0x3c0
86#define VGA_AR_DATA_READ 0x3c1
87
88#define VGA_GR_INDEX 0x3ce
89#define VGA_GR_DATA 0x3cf
90/* GR05 */
91#define VGA_GR_MEM_READ_MODE_SHIFT 3
92#define VGA_GR_MEM_READ_MODE_PLANE 1
93/* GR06 */
94#define VGA_GR_MEM_MODE_MASK 0xc
95#define VGA_GR_MEM_MODE_SHIFT 2
96#define VGA_GR_MEM_A0000_AFFFF 0
97#define VGA_GR_MEM_A0000_BFFFF 1
98#define VGA_GR_MEM_B0000_B7FFF 2
99#define VGA_GR_MEM_B0000_BFFFF 3
100
101#define VGA_DACMASK 0x3c6
102#define VGA_DACRX 0x3c7
103#define VGA_DACWX 0x3c8
104#define VGA_DACDATA 0x3c9
105
106#define VGA_CR_INDEX_MDA 0x3b4
107#define VGA_CR_DATA_MDA 0x3b5
108#define VGA_CR_INDEX_CGA 0x3d4
109#define VGA_CR_DATA_CGA 0x3d5
110
111/*
112 * Memory interface instructions used by the kernel
113 */
114#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
115
116#define MI_NOOP MI_INSTR(0, 0)
117#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
118#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
119#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
120#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
121#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
122#define MI_FLUSH MI_INSTR(0x04, 0)
123#define MI_READ_FLUSH (1 << 0)
124#define MI_EXE_FLUSH (1 << 1)
125#define MI_NO_WRITE_FLUSH (1 << 2)
126#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
127#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
128#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
129#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
130#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
131#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
132#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
133#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
134#define MI_STORE_DWORD_INDEX_SHIFT 2
135#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
136#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
137#define MI_BATCH_NON_SECURE (1)
138#define MI_BATCH_NON_SECURE_I965 (1<<8)
139#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
140
141/*
142 * 3D instructions used by the kernel
143 */
144#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
145
146#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
147#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
148#define SC_UPDATE_SCISSOR (0x1<<1)
149#define SC_ENABLE_MASK (0x1<<0)
150#define SC_ENABLE (0x1<<0)
151#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
152#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
153#define SCI_YMIN_MASK (0xffff<<16)
154#define SCI_XMIN_MASK (0xffff<<0)
155#define SCI_YMAX_MASK (0xffff<<16)
156#define SCI_XMAX_MASK (0xffff<<0)
157#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
158#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
159#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
160#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
161#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
162#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
163#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
164#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
165#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
166#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
167#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
168#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
169#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
170#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
171#define BLT_DEPTH_8 (0<<24)
172#define BLT_DEPTH_16_565 (1<<24)
173#define BLT_DEPTH_16_1555 (2<<24)
174#define BLT_DEPTH_32 (3<<24)
175#define BLT_ROP_GXCOPY (0xcc<<16)
176#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
177#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
178#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
179#define ASYNC_FLIP (1<<22)
180#define DISPLAY_PLANE_A (0<<20)
181#define DISPLAY_PLANE_B (1<<20)
182
183/*
Jesse Barnesde151cf2008-11-12 10:03:55 -0800184 * Fence registers
185 */
186#define FENCE_REG_830_0 0x2000
187#define I830_FENCE_START_MASK 0x07f80000
188#define I830_FENCE_TILING_Y_SHIFT 12
189#define I830_FENCE_SIZE_BITS(size) ((get_order(size >> 19) - 1) << 8)
190#define I830_FENCE_PITCH_SHIFT 4
191#define I830_FENCE_REG_VALID (1<<0)
192
193#define I915_FENCE_START_MASK 0x0ff00000
194#define I915_FENCE_SIZE_BITS(size) ((get_order(size >> 20) - 1) << 8)
195
196#define FENCE_REG_965_0 0x03000
197#define I965_FENCE_PITCH_SHIFT 2
198#define I965_FENCE_TILING_Y_SHIFT 1
199#define I965_FENCE_REG_VALID (1<<0)
200
201/*
Jesse Barnes585fb112008-07-29 11:54:06 -0700202 * Instruction and interrupt control regs
203 */
Jesse Barnes585fb112008-07-29 11:54:06 -0700204#define PRB0_TAIL 0x02030
205#define PRB0_HEAD 0x02034
206#define PRB0_START 0x02038
207#define PRB0_CTL 0x0203c
208#define TAIL_ADDR 0x001FFFF8
209#define HEAD_WRAP_COUNT 0xFFE00000
210#define HEAD_WRAP_ONE 0x00200000
211#define HEAD_ADDR 0x001FFFFC
212#define RING_NR_PAGES 0x001FF000
213#define RING_REPORT_MASK 0x00000006
214#define RING_REPORT_64K 0x00000002
215#define RING_REPORT_128K 0x00000004
216#define RING_NO_REPORT 0x00000000
217#define RING_VALID_MASK 0x00000001
218#define RING_VALID 0x00000001
219#define RING_INVALID 0x00000000
220#define PRB1_TAIL 0x02040 /* 915+ only */
221#define PRB1_HEAD 0x02044 /* 915+ only */
222#define PRB1_START 0x02048 /* 915+ only */
223#define PRB1_CTL 0x0204c /* 915+ only */
224#define ACTHD_I965 0x02074
225#define HWS_PGA 0x02080
226#define HWS_ADDRESS_MASK 0xfffff000
227#define HWS_START_ADDRESS_SHIFT 4
228#define IPEIR 0x02088
229#define NOPID 0x02094
230#define HWSTAM 0x02098
231#define SCPD0 0x0209c /* 915+ only */
232#define IER 0x020a0
233#define IIR 0x020a4
234#define IMR 0x020a8
235#define ISR 0x020ac
236#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
237#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
238#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
239#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
240#define I915_HWB_OOM_INTERRUPT (1<<13)
241#define I915_SYNC_STATUS_INTERRUPT (1<<12)
242#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
243#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
244#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
245#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
246#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
247#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
248#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
249#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
250#define I915_DEBUG_INTERRUPT (1<<2)
251#define I915_USER_INTERRUPT (1<<1)
252#define I915_ASLE_INTERRUPT (1<<0)
253#define EIR 0x020b0
254#define EMR 0x020b4
255#define ESR 0x020b8
256#define INSTPM 0x020c0
257#define ACTHD 0x020c8
258#define FW_BLC 0x020d8
259#define FW_BLC_SELF 0x020e0 /* 915+ only */
260#define MI_ARB_STATE 0x020e4 /* 915+ only */
261#define CACHE_MODE_0 0x02120 /* 915+ only */
262#define CM0_MASK_SHIFT 16
263#define CM0_IZ_OPT_DISABLE (1<<6)
264#define CM0_ZR_OPT_DISABLE (1<<5)
265#define CM0_DEPTH_EVICT_DISABLE (1<<4)
266#define CM0_COLOR_EVICT_DISABLE (1<<3)
267#define CM0_DEPTH_WRITE_DISABLE (1<<1)
268#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
269#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
270
Jesse Barnesde151cf2008-11-12 10:03:55 -0800271
Jesse Barnes585fb112008-07-29 11:54:06 -0700272/*
273 * Framebuffer compression (915+ only)
274 */
275
276#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
277#define FBC_LL_BASE 0x03204 /* 4k page aligned */
278#define FBC_CONTROL 0x03208
279#define FBC_CTL_EN (1<<31)
280#define FBC_CTL_PERIODIC (1<<30)
281#define FBC_CTL_INTERVAL_SHIFT (16)
282#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
283#define FBC_CTL_STRIDE_SHIFT (5)
284#define FBC_CTL_FENCENO (1<<0)
285#define FBC_COMMAND 0x0320c
286#define FBC_CMD_COMPRESS (1<<0)
287#define FBC_STATUS 0x03210
288#define FBC_STAT_COMPRESSING (1<<31)
289#define FBC_STAT_COMPRESSED (1<<30)
290#define FBC_STAT_MODIFIED (1<<29)
291#define FBC_STAT_CURRENT_LINE (1<<0)
292#define FBC_CONTROL2 0x03214
293#define FBC_CTL_FENCE_DBL (0<<4)
294#define FBC_CTL_IDLE_IMM (0<<2)
295#define FBC_CTL_IDLE_FULL (1<<2)
296#define FBC_CTL_IDLE_LINE (2<<2)
297#define FBC_CTL_IDLE_DEBUG (3<<2)
298#define FBC_CTL_CPU_FENCE (1<<1)
299#define FBC_CTL_PLANEA (0<<0)
300#define FBC_CTL_PLANEB (1<<0)
301#define FBC_FENCE_OFF 0x0321b
302
303#define FBC_LL_SIZE (1536)
304
305/*
306 * GPIO regs
307 */
308#define GPIOA 0x5010
309#define GPIOB 0x5014
310#define GPIOC 0x5018
311#define GPIOD 0x501c
312#define GPIOE 0x5020
313#define GPIOF 0x5024
314#define GPIOG 0x5028
315#define GPIOH 0x502c
316# define GPIO_CLOCK_DIR_MASK (1 << 0)
317# define GPIO_CLOCK_DIR_IN (0 << 1)
318# define GPIO_CLOCK_DIR_OUT (1 << 1)
319# define GPIO_CLOCK_VAL_MASK (1 << 2)
320# define GPIO_CLOCK_VAL_OUT (1 << 3)
321# define GPIO_CLOCK_VAL_IN (1 << 4)
322# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
323# define GPIO_DATA_DIR_MASK (1 << 8)
324# define GPIO_DATA_DIR_IN (0 << 9)
325# define GPIO_DATA_DIR_OUT (1 << 9)
326# define GPIO_DATA_VAL_MASK (1 << 10)
327# define GPIO_DATA_VAL_OUT (1 << 11)
328# define GPIO_DATA_VAL_IN (1 << 12)
329# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
330
331/*
332 * Clock control & power management
333 */
334
335#define VGA0 0x6000
336#define VGA1 0x6004
337#define VGA_PD 0x6010
338#define VGA0_PD_P2_DIV_4 (1 << 7)
339#define VGA0_PD_P1_DIV_2 (1 << 5)
340#define VGA0_PD_P1_SHIFT 0
341#define VGA0_PD_P1_MASK (0x1f << 0)
342#define VGA1_PD_P2_DIV_4 (1 << 15)
343#define VGA1_PD_P1_DIV_2 (1 << 13)
344#define VGA1_PD_P1_SHIFT 8
345#define VGA1_PD_P1_MASK (0x1f << 8)
346#define DPLL_A 0x06014
347#define DPLL_B 0x06018
348#define DPLL_VCO_ENABLE (1 << 31)
349#define DPLL_DVO_HIGH_SPEED (1 << 30)
350#define DPLL_SYNCLOCK_ENABLE (1 << 29)
351#define DPLL_VGA_MODE_DIS (1 << 28)
352#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
353#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
354#define DPLL_MODE_MASK (3 << 26)
355#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
356#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
357#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
358#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
359#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
360#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
361
362#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
363#define I915_CRC_ERROR_ENABLE (1UL<<29)
364#define I915_CRC_DONE_ENABLE (1UL<<28)
365#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
366#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
367#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
368#define I915_DPST_EVENT_ENABLE (1UL<<23)
369#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
370#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
371#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
372#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
373#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
374#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
375#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
376#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
377#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
378#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
379#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
380#define I915_DPST_EVENT_STATUS (1UL<<7)
381#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
382#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
383#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
384#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
385#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
386#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
387
388#define SRX_INDEX 0x3c4
389#define SRX_DATA 0x3c5
390#define SR01 1
391#define SR01_SCREEN_OFF (1<<5)
392
393#define PPCR 0x61204
394#define PPCR_ON (1<<0)
395
396#define DVOB 0x61140
397#define DVOB_ON (1<<31)
398#define DVOC 0x61160
399#define DVOC_ON (1<<31)
400#define LVDS 0x61180
401#define LVDS_ON (1<<31)
402
403#define ADPA 0x61100
404#define ADPA_DPMS_MASK (~(3<<10))
405#define ADPA_DPMS_ON (0<<10)
406#define ADPA_DPMS_SUSPEND (1<<10)
407#define ADPA_DPMS_STANDBY (2<<10)
408#define ADPA_DPMS_OFF (3<<10)
409
410#define RING_TAIL 0x00
411#define TAIL_ADDR 0x001FFFF8
412#define RING_HEAD 0x04
413#define HEAD_WRAP_COUNT 0xFFE00000
414#define HEAD_WRAP_ONE 0x00200000
415#define HEAD_ADDR 0x001FFFFC
416#define RING_START 0x08
417#define START_ADDR 0xFFFFF000
418#define RING_LEN 0x0C
419#define RING_NR_PAGES 0x001FF000
420#define RING_REPORT_MASK 0x00000006
421#define RING_REPORT_64K 0x00000002
422#define RING_REPORT_128K 0x00000004
423#define RING_NO_REPORT 0x00000000
424#define RING_VALID_MASK 0x00000001
425#define RING_VALID 0x00000001
426#define RING_INVALID 0x00000000
427
428/* Scratch pad debug 0 reg:
429 */
430#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
431/*
432 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
433 * this field (only one bit may be set).
434 */
435#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
436#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
437/* i830, required in DVO non-gang */
438#define PLL_P2_DIVIDE_BY_4 (1 << 23)
439#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
440#define PLL_REF_INPUT_DREFCLK (0 << 13)
441#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
442#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
443#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
444#define PLL_REF_INPUT_MASK (3 << 13)
445#define PLL_LOAD_PULSE_PHASE_SHIFT 9
446/*
447 * Parallel to Serial Load Pulse phase selection.
448 * Selects the phase for the 10X DPLL clock for the PCIe
449 * digital display port. The range is 4 to 13; 10 or more
450 * is just a flip delay. The default is 6
451 */
452#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
453#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
454/*
455 * SDVO multiplier for 945G/GM. Not used on 965.
456 */
457#define SDVO_MULTIPLIER_MASK 0x000000ff
458#define SDVO_MULTIPLIER_SHIFT_HIRES 4
459#define SDVO_MULTIPLIER_SHIFT_VGA 0
460#define DPLL_A_MD 0x0601c /* 965+ only */
461/*
462 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
463 *
464 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
465 */
466#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
467#define DPLL_MD_UDI_DIVIDER_SHIFT 24
468/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
469#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
470#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
471/*
472 * SDVO/UDI pixel multiplier.
473 *
474 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
475 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
476 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
477 * dummy bytes in the datastream at an increased clock rate, with both sides of
478 * the link knowing how many bytes are fill.
479 *
480 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
481 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
482 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
483 * through an SDVO command.
484 *
485 * This register field has values of multiplication factor minus 1, with
486 * a maximum multiplier of 5 for SDVO.
487 */
488#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
489#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
490/*
491 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
492 * This best be set to the default value (3) or the CRT won't work. No,
493 * I don't entirely understand what this does...
494 */
495#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
496#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
497#define DPLL_B_MD 0x06020 /* 965+ only */
498#define FPA0 0x06040
499#define FPA1 0x06044
500#define FPB0 0x06048
501#define FPB1 0x0604c
502#define FP_N_DIV_MASK 0x003f0000
503#define FP_N_DIV_SHIFT 16
504#define FP_M1_DIV_MASK 0x00003f00
505#define FP_M1_DIV_SHIFT 8
506#define FP_M2_DIV_MASK 0x0000003f
507#define FP_M2_DIV_SHIFT 0
508#define DPLL_TEST 0x606c
509#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
510#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
511#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
512#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
513#define DPLLB_TEST_N_BYPASS (1 << 19)
514#define DPLLB_TEST_M_BYPASS (1 << 18)
515#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
516#define DPLLA_TEST_N_BYPASS (1 << 3)
517#define DPLLA_TEST_M_BYPASS (1 << 2)
518#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
519#define D_STATE 0x6104
520#define CG_2D_DIS 0x6200
521#define CG_3D_DIS 0x6204
522
523/*
524 * Palette regs
525 */
526
527#define PALETTE_A 0x0a000
528#define PALETTE_B 0x0a800
529
Eric Anholt673a3942008-07-30 12:06:12 -0700530/* MCH MMIO space */
531
532/*
533 * MCHBAR mirror.
534 *
535 * This mirrors the MCHBAR MMIO space whose location is determined by
536 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
537 * every way. It is not accessible from the CP register read instructions.
538 *
539 */
540#define MCHBAR_MIRROR_BASE 0x10000
541
542/** 915-945 and GM965 MCH register controlling DRAM channel access */
543#define DCC 0x10200
544#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
545#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
546#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
547#define DCC_ADDRESSING_MODE_MASK (3 << 0)
548#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
Eric Anholta7f014f2008-11-25 14:02:05 -0800549#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
Eric Anholt673a3942008-07-30 12:06:12 -0700550
551/** 965 MCH register controlling DRAM channel configuration */
552#define C0DRB3 0x10206
553#define C1DRB3 0x10606
554
Keith Packard881ee982008-11-02 23:08:44 -0800555/** GM965 GM45 render standby register */
556#define MCHBAR_RENDER_STANDBY 0x111B8
557
Eric Anholt7d573822009-01-02 13:33:00 -0800558#define PEG_BAND_GAP_DATA 0x14d68
559
Jesse Barnes585fb112008-07-29 11:54:06 -0700560/*
561 * Overlay regs
562 */
563
564#define OVADD 0x30000
565#define DOVSTA 0x30008
566#define OC_BUF (0x3<<20)
567#define OGAMC5 0x30010
568#define OGAMC4 0x30014
569#define OGAMC3 0x30018
570#define OGAMC2 0x3001c
571#define OGAMC1 0x30020
572#define OGAMC0 0x30024
573
574/*
575 * Display engine regs
576 */
577
578/* Pipe A timing regs */
579#define HTOTAL_A 0x60000
580#define HBLANK_A 0x60004
581#define HSYNC_A 0x60008
582#define VTOTAL_A 0x6000c
583#define VBLANK_A 0x60010
584#define VSYNC_A 0x60014
585#define PIPEASRC 0x6001c
586#define BCLRPAT_A 0x60020
587
588/* Pipe B timing regs */
589#define HTOTAL_B 0x61000
590#define HBLANK_B 0x61004
591#define HSYNC_B 0x61008
592#define VTOTAL_B 0x6100c
593#define VBLANK_B 0x61010
594#define VSYNC_B 0x61014
595#define PIPEBSRC 0x6101c
596#define BCLRPAT_B 0x61020
597
598/* VGA port control */
599#define ADPA 0x61100
600#define ADPA_DAC_ENABLE (1<<31)
601#define ADPA_DAC_DISABLE 0
602#define ADPA_PIPE_SELECT_MASK (1<<30)
603#define ADPA_PIPE_A_SELECT 0
604#define ADPA_PIPE_B_SELECT (1<<30)
605#define ADPA_USE_VGA_HVPOLARITY (1<<15)
606#define ADPA_SETS_HVPOLARITY 0
607#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
608#define ADPA_VSYNC_CNTL_ENABLE 0
609#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
610#define ADPA_HSYNC_CNTL_ENABLE 0
611#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
612#define ADPA_VSYNC_ACTIVE_LOW 0
613#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
614#define ADPA_HSYNC_ACTIVE_LOW 0
615#define ADPA_DPMS_MASK (~(3<<10))
616#define ADPA_DPMS_ON (0<<10)
617#define ADPA_DPMS_SUSPEND (1<<10)
618#define ADPA_DPMS_STANDBY (2<<10)
619#define ADPA_DPMS_OFF (3<<10)
620
621/* Hotplug control (945+ only) */
622#define PORT_HOTPLUG_EN 0x61110
Eric Anholt7d573822009-01-02 13:33:00 -0800623#define HDMIB_HOTPLUG_INT_EN (1 << 29)
624#define HDMIC_HOTPLUG_INT_EN (1 << 28)
625#define HDMID_HOTPLUG_INT_EN (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -0700626#define SDVOB_HOTPLUG_INT_EN (1 << 26)
627#define SDVOC_HOTPLUG_INT_EN (1 << 25)
628#define TV_HOTPLUG_INT_EN (1 << 18)
629#define CRT_HOTPLUG_INT_EN (1 << 9)
630#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
631
632#define PORT_HOTPLUG_STAT 0x61114
Eric Anholt7d573822009-01-02 13:33:00 -0800633#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
634#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
635#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
Jesse Barnes585fb112008-07-29 11:54:06 -0700636#define CRT_HOTPLUG_INT_STATUS (1 << 11)
637#define TV_HOTPLUG_INT_STATUS (1 << 10)
638#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
639#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
640#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
641#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
642#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
643#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
644
645/* SDVO port control */
646#define SDVOB 0x61140
647#define SDVOC 0x61160
648#define SDVO_ENABLE (1 << 31)
649#define SDVO_PIPE_B_SELECT (1 << 30)
650#define SDVO_STALL_SELECT (1 << 29)
651#define SDVO_INTERRUPT_ENABLE (1 << 26)
652/**
653 * 915G/GM SDVO pixel multiplier.
654 *
655 * Programmed value is multiplier - 1, up to 5x.
656 *
657 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
658 */
659#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
660#define SDVO_PORT_MULTIPLY_SHIFT 23
661#define SDVO_PHASE_SELECT_MASK (15 << 19)
662#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
663#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
664#define SDVOC_GANG_MODE (1 << 16)
Eric Anholt7d573822009-01-02 13:33:00 -0800665#define SDVO_ENCODING_SDVO (0x0 << 10)
666#define SDVO_ENCODING_HDMI (0x2 << 10)
667/** Requird for HDMI operation */
668#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
Jesse Barnes585fb112008-07-29 11:54:06 -0700669#define SDVO_BORDER_ENABLE (1 << 7)
Eric Anholt7d573822009-01-02 13:33:00 -0800670#define SDVO_AUDIO_ENABLE (1 << 6)
671/** New with 965, default is to be set */
672#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
673/** New with 965, default is to be set */
674#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
Jesse Barnes585fb112008-07-29 11:54:06 -0700675#define SDVOB_PCIE_CONCURRENCY (1 << 3)
676#define SDVO_DETECTED (1 << 2)
677/* Bits to be preserved when writing */
678#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
679#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
680
681/* DVO port control */
682#define DVOA 0x61120
683#define DVOB 0x61140
684#define DVOC 0x61160
685#define DVO_ENABLE (1 << 31)
686#define DVO_PIPE_B_SELECT (1 << 30)
687#define DVO_PIPE_STALL_UNUSED (0 << 28)
688#define DVO_PIPE_STALL (1 << 28)
689#define DVO_PIPE_STALL_TV (2 << 28)
690#define DVO_PIPE_STALL_MASK (3 << 28)
691#define DVO_USE_VGA_SYNC (1 << 15)
692#define DVO_DATA_ORDER_I740 (0 << 14)
693#define DVO_DATA_ORDER_FP (1 << 14)
694#define DVO_VSYNC_DISABLE (1 << 11)
695#define DVO_HSYNC_DISABLE (1 << 10)
696#define DVO_VSYNC_TRISTATE (1 << 9)
697#define DVO_HSYNC_TRISTATE (1 << 8)
698#define DVO_BORDER_ENABLE (1 << 7)
699#define DVO_DATA_ORDER_GBRG (1 << 6)
700#define DVO_DATA_ORDER_RGGB (0 << 6)
701#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
702#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
703#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
704#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
705#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
706#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
707#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
708#define DVO_PRESERVE_MASK (0x7<<24)
709#define DVOA_SRCDIM 0x61124
710#define DVOB_SRCDIM 0x61144
711#define DVOC_SRCDIM 0x61164
712#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
713#define DVO_SRCDIM_VERTICAL_SHIFT 0
714
715/* LVDS port control */
716#define LVDS 0x61180
717/*
718 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
719 * the DPLL semantics change when the LVDS is assigned to that pipe.
720 */
721#define LVDS_PORT_EN (1 << 31)
722/* Selects pipe B for LVDS data. Must be set on pre-965. */
723#define LVDS_PIPEB_SELECT (1 << 30)
724/*
725 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
726 * pixel.
727 */
728#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
729#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
730#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
731/*
732 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
733 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
734 * on.
735 */
736#define LVDS_A3_POWER_MASK (3 << 6)
737#define LVDS_A3_POWER_DOWN (0 << 6)
738#define LVDS_A3_POWER_UP (3 << 6)
739/*
740 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
741 * is set.
742 */
743#define LVDS_CLKB_POWER_MASK (3 << 4)
744#define LVDS_CLKB_POWER_DOWN (0 << 4)
745#define LVDS_CLKB_POWER_UP (3 << 4)
746/*
747 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
748 * setting for whether we are in dual-channel mode. The B3 pair will
749 * additionally only be powered up when LVDS_A3_POWER_UP is set.
750 */
751#define LVDS_B0B3_POWER_MASK (3 << 2)
752#define LVDS_B0B3_POWER_DOWN (0 << 2)
753#define LVDS_B0B3_POWER_UP (3 << 2)
754
755/* Panel power sequencing */
756#define PP_STATUS 0x61200
757#define PP_ON (1 << 31)
758/*
759 * Indicates that all dependencies of the panel are on:
760 *
761 * - PLL enabled
762 * - pipe enabled
763 * - LVDS/DVOB/DVOC on
764 */
765#define PP_READY (1 << 30)
766#define PP_SEQUENCE_NONE (0 << 28)
767#define PP_SEQUENCE_ON (1 << 28)
768#define PP_SEQUENCE_OFF (2 << 28)
769#define PP_SEQUENCE_MASK 0x30000000
770#define PP_CONTROL 0x61204
771#define POWER_TARGET_ON (1 << 0)
772#define PP_ON_DELAYS 0x61208
773#define PP_OFF_DELAYS 0x6120c
774#define PP_DIVISOR 0x61210
775
776/* Panel fitting */
777#define PFIT_CONTROL 0x61230
778#define PFIT_ENABLE (1 << 31)
779#define PFIT_PIPE_MASK (3 << 29)
780#define PFIT_PIPE_SHIFT 29
781#define VERT_INTERP_DISABLE (0 << 10)
782#define VERT_INTERP_BILINEAR (1 << 10)
783#define VERT_INTERP_MASK (3 << 10)
784#define VERT_AUTO_SCALE (1 << 9)
785#define HORIZ_INTERP_DISABLE (0 << 6)
786#define HORIZ_INTERP_BILINEAR (1 << 6)
787#define HORIZ_INTERP_MASK (3 << 6)
788#define HORIZ_AUTO_SCALE (1 << 5)
789#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
790#define PFIT_PGM_RATIOS 0x61234
791#define PFIT_VERT_SCALE_MASK 0xfff00000
792#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
793#define PFIT_AUTO_RATIOS 0x61238
794
795/* Backlight control */
796#define BLC_PWM_CTL 0x61254
797#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
798#define BLC_PWM_CTL2 0x61250 /* 965+ only */
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100799#define BLM_COMBINATION_MODE (1 << 30)
Jesse Barnes585fb112008-07-29 11:54:06 -0700800/*
801 * This is the most significant 15 bits of the number of backlight cycles in a
802 * complete cycle of the modulated backlight control.
803 *
804 * The actual value is this field multiplied by two.
805 */
806#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
807#define BLM_LEGACY_MODE (1 << 16)
808/*
809 * This is the number of cycles out of the backlight modulation cycle for which
810 * the backlight is on.
811 *
812 * This field must be no greater than the number of cycles in the complete
813 * backlight modulation cycle.
814 */
815#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
816#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
817
818/* TV port control */
819#define TV_CTL 0x68000
820/** Enables the TV encoder */
821# define TV_ENC_ENABLE (1 << 31)
822/** Sources the TV encoder input from pipe B instead of A. */
823# define TV_ENC_PIPEB_SELECT (1 << 30)
824/** Outputs composite video (DAC A only) */
825# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
826/** Outputs SVideo video (DAC B/C) */
827# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
828/** Outputs Component video (DAC A/B/C) */
829# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
830/** Outputs Composite and SVideo (DAC A/B/C) */
831# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
832# define TV_TRILEVEL_SYNC (1 << 21)
833/** Enables slow sync generation (945GM only) */
834# define TV_SLOW_SYNC (1 << 20)
835/** Selects 4x oversampling for 480i and 576p */
836# define TV_OVERSAMPLE_4X (0 << 18)
837/** Selects 2x oversampling for 720p and 1080i */
838# define TV_OVERSAMPLE_2X (1 << 18)
839/** Selects no oversampling for 1080p */
840# define TV_OVERSAMPLE_NONE (2 << 18)
841/** Selects 8x oversampling */
842# define TV_OVERSAMPLE_8X (3 << 18)
843/** Selects progressive mode rather than interlaced */
844# define TV_PROGRESSIVE (1 << 17)
845/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
846# define TV_PAL_BURST (1 << 16)
847/** Field for setting delay of Y compared to C */
848# define TV_YC_SKEW_MASK (7 << 12)
849/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
850# define TV_ENC_SDP_FIX (1 << 11)
851/**
852 * Enables a fix for the 915GM only.
853 *
854 * Not sure what it does.
855 */
856# define TV_ENC_C0_FIX (1 << 10)
857/** Bits that must be preserved by software */
858# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
859# define TV_FUSE_STATE_MASK (3 << 4)
860/** Read-only state that reports all features enabled */
861# define TV_FUSE_STATE_ENABLED (0 << 4)
862/** Read-only state that reports that Macrovision is disabled in hardware*/
863# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
864/** Read-only state that reports that TV-out is disabled in hardware. */
865# define TV_FUSE_STATE_DISABLED (2 << 4)
866/** Normal operation */
867# define TV_TEST_MODE_NORMAL (0 << 0)
868/** Encoder test pattern 1 - combo pattern */
869# define TV_TEST_MODE_PATTERN_1 (1 << 0)
870/** Encoder test pattern 2 - full screen vertical 75% color bars */
871# define TV_TEST_MODE_PATTERN_2 (2 << 0)
872/** Encoder test pattern 3 - full screen horizontal 75% color bars */
873# define TV_TEST_MODE_PATTERN_3 (3 << 0)
874/** Encoder test pattern 4 - random noise */
875# define TV_TEST_MODE_PATTERN_4 (4 << 0)
876/** Encoder test pattern 5 - linear color ramps */
877# define TV_TEST_MODE_PATTERN_5 (5 << 0)
878/**
879 * This test mode forces the DACs to 50% of full output.
880 *
881 * This is used for load detection in combination with TVDAC_SENSE_MASK
882 */
883# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
884# define TV_TEST_MODE_MASK (7 << 0)
885
886#define TV_DAC 0x68004
887/**
888 * Reports that DAC state change logic has reported change (RO).
889 *
890 * This gets cleared when TV_DAC_STATE_EN is cleared
891*/
892# define TVDAC_STATE_CHG (1 << 31)
893# define TVDAC_SENSE_MASK (7 << 28)
894/** Reports that DAC A voltage is above the detect threshold */
895# define TVDAC_A_SENSE (1 << 30)
896/** Reports that DAC B voltage is above the detect threshold */
897# define TVDAC_B_SENSE (1 << 29)
898/** Reports that DAC C voltage is above the detect threshold */
899# define TVDAC_C_SENSE (1 << 28)
900/**
901 * Enables DAC state detection logic, for load-based TV detection.
902 *
903 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
904 * to off, for load detection to work.
905 */
906# define TVDAC_STATE_CHG_EN (1 << 27)
907/** Sets the DAC A sense value to high */
908# define TVDAC_A_SENSE_CTL (1 << 26)
909/** Sets the DAC B sense value to high */
910# define TVDAC_B_SENSE_CTL (1 << 25)
911/** Sets the DAC C sense value to high */
912# define TVDAC_C_SENSE_CTL (1 << 24)
913/** Overrides the ENC_ENABLE and DAC voltage levels */
914# define DAC_CTL_OVERRIDE (1 << 7)
915/** Sets the slew rate. Must be preserved in software */
916# define ENC_TVDAC_SLEW_FAST (1 << 6)
917# define DAC_A_1_3_V (0 << 4)
918# define DAC_A_1_1_V (1 << 4)
919# define DAC_A_0_7_V (2 << 4)
920# define DAC_A_OFF (3 << 4)
921# define DAC_B_1_3_V (0 << 2)
922# define DAC_B_1_1_V (1 << 2)
923# define DAC_B_0_7_V (2 << 2)
924# define DAC_B_OFF (3 << 2)
925# define DAC_C_1_3_V (0 << 0)
926# define DAC_C_1_1_V (1 << 0)
927# define DAC_C_0_7_V (2 << 0)
928# define DAC_C_OFF (3 << 0)
929
930/**
931 * CSC coefficients are stored in a floating point format with 9 bits of
932 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
933 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
934 * -1 (0x3) being the only legal negative value.
935 */
936#define TV_CSC_Y 0x68010
937# define TV_RY_MASK 0x07ff0000
938# define TV_RY_SHIFT 16
939# define TV_GY_MASK 0x00000fff
940# define TV_GY_SHIFT 0
941
942#define TV_CSC_Y2 0x68014
943# define TV_BY_MASK 0x07ff0000
944# define TV_BY_SHIFT 16
945/**
946 * Y attenuation for component video.
947 *
948 * Stored in 1.9 fixed point.
949 */
950# define TV_AY_MASK 0x000003ff
951# define TV_AY_SHIFT 0
952
953#define TV_CSC_U 0x68018
954# define TV_RU_MASK 0x07ff0000
955# define TV_RU_SHIFT 16
956# define TV_GU_MASK 0x000007ff
957# define TV_GU_SHIFT 0
958
959#define TV_CSC_U2 0x6801c
960# define TV_BU_MASK 0x07ff0000
961# define TV_BU_SHIFT 16
962/**
963 * U attenuation for component video.
964 *
965 * Stored in 1.9 fixed point.
966 */
967# define TV_AU_MASK 0x000003ff
968# define TV_AU_SHIFT 0
969
970#define TV_CSC_V 0x68020
971# define TV_RV_MASK 0x0fff0000
972# define TV_RV_SHIFT 16
973# define TV_GV_MASK 0x000007ff
974# define TV_GV_SHIFT 0
975
976#define TV_CSC_V2 0x68024
977# define TV_BV_MASK 0x07ff0000
978# define TV_BV_SHIFT 16
979/**
980 * V attenuation for component video.
981 *
982 * Stored in 1.9 fixed point.
983 */
984# define TV_AV_MASK 0x000007ff
985# define TV_AV_SHIFT 0
986
987#define TV_CLR_KNOBS 0x68028
988/** 2s-complement brightness adjustment */
989# define TV_BRIGHTNESS_MASK 0xff000000
990# define TV_BRIGHTNESS_SHIFT 24
991/** Contrast adjustment, as a 2.6 unsigned floating point number */
992# define TV_CONTRAST_MASK 0x00ff0000
993# define TV_CONTRAST_SHIFT 16
994/** Saturation adjustment, as a 2.6 unsigned floating point number */
995# define TV_SATURATION_MASK 0x0000ff00
996# define TV_SATURATION_SHIFT 8
997/** Hue adjustment, as an integer phase angle in degrees */
998# define TV_HUE_MASK 0x000000ff
999# define TV_HUE_SHIFT 0
1000
1001#define TV_CLR_LEVEL 0x6802c
1002/** Controls the DAC level for black */
1003# define TV_BLACK_LEVEL_MASK 0x01ff0000
1004# define TV_BLACK_LEVEL_SHIFT 16
1005/** Controls the DAC level for blanking */
1006# define TV_BLANK_LEVEL_MASK 0x000001ff
1007# define TV_BLANK_LEVEL_SHIFT 0
1008
1009#define TV_H_CTL_1 0x68030
1010/** Number of pixels in the hsync. */
1011# define TV_HSYNC_END_MASK 0x1fff0000
1012# define TV_HSYNC_END_SHIFT 16
1013/** Total number of pixels minus one in the line (display and blanking). */
1014# define TV_HTOTAL_MASK 0x00001fff
1015# define TV_HTOTAL_SHIFT 0
1016
1017#define TV_H_CTL_2 0x68034
1018/** Enables the colorburst (needed for non-component color) */
1019# define TV_BURST_ENA (1 << 31)
1020/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1021# define TV_HBURST_START_SHIFT 16
1022# define TV_HBURST_START_MASK 0x1fff0000
1023/** Length of the colorburst */
1024# define TV_HBURST_LEN_SHIFT 0
1025# define TV_HBURST_LEN_MASK 0x0001fff
1026
1027#define TV_H_CTL_3 0x68038
1028/** End of hblank, measured in pixels minus one from start of hsync */
1029# define TV_HBLANK_END_SHIFT 16
1030# define TV_HBLANK_END_MASK 0x1fff0000
1031/** Start of hblank, measured in pixels minus one from start of hsync */
1032# define TV_HBLANK_START_SHIFT 0
1033# define TV_HBLANK_START_MASK 0x0001fff
1034
1035#define TV_V_CTL_1 0x6803c
1036/** XXX */
1037# define TV_NBR_END_SHIFT 16
1038# define TV_NBR_END_MASK 0x07ff0000
1039/** XXX */
1040# define TV_VI_END_F1_SHIFT 8
1041# define TV_VI_END_F1_MASK 0x00003f00
1042/** XXX */
1043# define TV_VI_END_F2_SHIFT 0
1044# define TV_VI_END_F2_MASK 0x0000003f
1045
1046#define TV_V_CTL_2 0x68040
1047/** Length of vsync, in half lines */
1048# define TV_VSYNC_LEN_MASK 0x07ff0000
1049# define TV_VSYNC_LEN_SHIFT 16
1050/** Offset of the start of vsync in field 1, measured in one less than the
1051 * number of half lines.
1052 */
1053# define TV_VSYNC_START_F1_MASK 0x00007f00
1054# define TV_VSYNC_START_F1_SHIFT 8
1055/**
1056 * Offset of the start of vsync in field 2, measured in one less than the
1057 * number of half lines.
1058 */
1059# define TV_VSYNC_START_F2_MASK 0x0000007f
1060# define TV_VSYNC_START_F2_SHIFT 0
1061
1062#define TV_V_CTL_3 0x68044
1063/** Enables generation of the equalization signal */
1064# define TV_EQUAL_ENA (1 << 31)
1065/** Length of vsync, in half lines */
1066# define TV_VEQ_LEN_MASK 0x007f0000
1067# define TV_VEQ_LEN_SHIFT 16
1068/** Offset of the start of equalization in field 1, measured in one less than
1069 * the number of half lines.
1070 */
1071# define TV_VEQ_START_F1_MASK 0x0007f00
1072# define TV_VEQ_START_F1_SHIFT 8
1073/**
1074 * Offset of the start of equalization in field 2, measured in one less than
1075 * the number of half lines.
1076 */
1077# define TV_VEQ_START_F2_MASK 0x000007f
1078# define TV_VEQ_START_F2_SHIFT 0
1079
1080#define TV_V_CTL_4 0x68048
1081/**
1082 * Offset to start of vertical colorburst, measured in one less than the
1083 * number of lines from vertical start.
1084 */
1085# define TV_VBURST_START_F1_MASK 0x003f0000
1086# define TV_VBURST_START_F1_SHIFT 16
1087/**
1088 * Offset to the end of vertical colorburst, measured in one less than the
1089 * number of lines from the start of NBR.
1090 */
1091# define TV_VBURST_END_F1_MASK 0x000000ff
1092# define TV_VBURST_END_F1_SHIFT 0
1093
1094#define TV_V_CTL_5 0x6804c
1095/**
1096 * Offset to start of vertical colorburst, measured in one less than the
1097 * number of lines from vertical start.
1098 */
1099# define TV_VBURST_START_F2_MASK 0x003f0000
1100# define TV_VBURST_START_F2_SHIFT 16
1101/**
1102 * Offset to the end of vertical colorburst, measured in one less than the
1103 * number of lines from the start of NBR.
1104 */
1105# define TV_VBURST_END_F2_MASK 0x000000ff
1106# define TV_VBURST_END_F2_SHIFT 0
1107
1108#define TV_V_CTL_6 0x68050
1109/**
1110 * Offset to start of vertical colorburst, measured in one less than the
1111 * number of lines from vertical start.
1112 */
1113# define TV_VBURST_START_F3_MASK 0x003f0000
1114# define TV_VBURST_START_F3_SHIFT 16
1115/**
1116 * Offset to the end of vertical colorburst, measured in one less than the
1117 * number of lines from the start of NBR.
1118 */
1119# define TV_VBURST_END_F3_MASK 0x000000ff
1120# define TV_VBURST_END_F3_SHIFT 0
1121
1122#define TV_V_CTL_7 0x68054
1123/**
1124 * Offset to start of vertical colorburst, measured in one less than the
1125 * number of lines from vertical start.
1126 */
1127# define TV_VBURST_START_F4_MASK 0x003f0000
1128# define TV_VBURST_START_F4_SHIFT 16
1129/**
1130 * Offset to the end of vertical colorburst, measured in one less than the
1131 * number of lines from the start of NBR.
1132 */
1133# define TV_VBURST_END_F4_MASK 0x000000ff
1134# define TV_VBURST_END_F4_SHIFT 0
1135
1136#define TV_SC_CTL_1 0x68060
1137/** Turns on the first subcarrier phase generation DDA */
1138# define TV_SC_DDA1_EN (1 << 31)
1139/** Turns on the first subcarrier phase generation DDA */
1140# define TV_SC_DDA2_EN (1 << 30)
1141/** Turns on the first subcarrier phase generation DDA */
1142# define TV_SC_DDA3_EN (1 << 29)
1143/** Sets the subcarrier DDA to reset frequency every other field */
1144# define TV_SC_RESET_EVERY_2 (0 << 24)
1145/** Sets the subcarrier DDA to reset frequency every fourth field */
1146# define TV_SC_RESET_EVERY_4 (1 << 24)
1147/** Sets the subcarrier DDA to reset frequency every eighth field */
1148# define TV_SC_RESET_EVERY_8 (2 << 24)
1149/** Sets the subcarrier DDA to never reset the frequency */
1150# define TV_SC_RESET_NEVER (3 << 24)
1151/** Sets the peak amplitude of the colorburst.*/
1152# define TV_BURST_LEVEL_MASK 0x00ff0000
1153# define TV_BURST_LEVEL_SHIFT 16
1154/** Sets the increment of the first subcarrier phase generation DDA */
1155# define TV_SCDDA1_INC_MASK 0x00000fff
1156# define TV_SCDDA1_INC_SHIFT 0
1157
1158#define TV_SC_CTL_2 0x68064
1159/** Sets the rollover for the second subcarrier phase generation DDA */
1160# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1161# define TV_SCDDA2_SIZE_SHIFT 16
1162/** Sets the increent of the second subcarrier phase generation DDA */
1163# define TV_SCDDA2_INC_MASK 0x00007fff
1164# define TV_SCDDA2_INC_SHIFT 0
1165
1166#define TV_SC_CTL_3 0x68068
1167/** Sets the rollover for the third subcarrier phase generation DDA */
1168# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1169# define TV_SCDDA3_SIZE_SHIFT 16
1170/** Sets the increent of the third subcarrier phase generation DDA */
1171# define TV_SCDDA3_INC_MASK 0x00007fff
1172# define TV_SCDDA3_INC_SHIFT 0
1173
1174#define TV_WIN_POS 0x68070
1175/** X coordinate of the display from the start of horizontal active */
1176# define TV_XPOS_MASK 0x1fff0000
1177# define TV_XPOS_SHIFT 16
1178/** Y coordinate of the display from the start of vertical active (NBR) */
1179# define TV_YPOS_MASK 0x00000fff
1180# define TV_YPOS_SHIFT 0
1181
1182#define TV_WIN_SIZE 0x68074
1183/** Horizontal size of the display window, measured in pixels*/
1184# define TV_XSIZE_MASK 0x1fff0000
1185# define TV_XSIZE_SHIFT 16
1186/**
1187 * Vertical size of the display window, measured in pixels.
1188 *
1189 * Must be even for interlaced modes.
1190 */
1191# define TV_YSIZE_MASK 0x00000fff
1192# define TV_YSIZE_SHIFT 0
1193
1194#define TV_FILTER_CTL_1 0x68080
1195/**
1196 * Enables automatic scaling calculation.
1197 *
1198 * If set, the rest of the registers are ignored, and the calculated values can
1199 * be read back from the register.
1200 */
1201# define TV_AUTO_SCALE (1 << 31)
1202/**
1203 * Disables the vertical filter.
1204 *
1205 * This is required on modes more than 1024 pixels wide */
1206# define TV_V_FILTER_BYPASS (1 << 29)
1207/** Enables adaptive vertical filtering */
1208# define TV_VADAPT (1 << 28)
1209# define TV_VADAPT_MODE_MASK (3 << 26)
1210/** Selects the least adaptive vertical filtering mode */
1211# define TV_VADAPT_MODE_LEAST (0 << 26)
1212/** Selects the moderately adaptive vertical filtering mode */
1213# define TV_VADAPT_MODE_MODERATE (1 << 26)
1214/** Selects the most adaptive vertical filtering mode */
1215# define TV_VADAPT_MODE_MOST (3 << 26)
1216/**
1217 * Sets the horizontal scaling factor.
1218 *
1219 * This should be the fractional part of the horizontal scaling factor divided
1220 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1221 *
1222 * (src width - 1) / ((oversample * dest width) - 1)
1223 */
1224# define TV_HSCALE_FRAC_MASK 0x00003fff
1225# define TV_HSCALE_FRAC_SHIFT 0
1226
1227#define TV_FILTER_CTL_2 0x68084
1228/**
1229 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1230 *
1231 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1232 */
1233# define TV_VSCALE_INT_MASK 0x00038000
1234# define TV_VSCALE_INT_SHIFT 15
1235/**
1236 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1237 *
1238 * \sa TV_VSCALE_INT_MASK
1239 */
1240# define TV_VSCALE_FRAC_MASK 0x00007fff
1241# define TV_VSCALE_FRAC_SHIFT 0
1242
1243#define TV_FILTER_CTL_3 0x68088
1244/**
1245 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1246 *
1247 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1248 *
1249 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1250 */
1251# define TV_VSCALE_IP_INT_MASK 0x00038000
1252# define TV_VSCALE_IP_INT_SHIFT 15
1253/**
1254 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1255 *
1256 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1257 *
1258 * \sa TV_VSCALE_IP_INT_MASK
1259 */
1260# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1261# define TV_VSCALE_IP_FRAC_SHIFT 0
1262
1263#define TV_CC_CONTROL 0x68090
1264# define TV_CC_ENABLE (1 << 31)
1265/**
1266 * Specifies which field to send the CC data in.
1267 *
1268 * CC data is usually sent in field 0.
1269 */
1270# define TV_CC_FID_MASK (1 << 27)
1271# define TV_CC_FID_SHIFT 27
1272/** Sets the horizontal position of the CC data. Usually 135. */
1273# define TV_CC_HOFF_MASK 0x03ff0000
1274# define TV_CC_HOFF_SHIFT 16
1275/** Sets the vertical position of the CC data. Usually 21 */
1276# define TV_CC_LINE_MASK 0x0000003f
1277# define TV_CC_LINE_SHIFT 0
1278
1279#define TV_CC_DATA 0x68094
1280# define TV_CC_RDY (1 << 31)
1281/** Second word of CC data to be transmitted. */
1282# define TV_CC_DATA_2_MASK 0x007f0000
1283# define TV_CC_DATA_2_SHIFT 16
1284/** First word of CC data to be transmitted. */
1285# define TV_CC_DATA_1_MASK 0x0000007f
1286# define TV_CC_DATA_1_SHIFT 0
1287
1288#define TV_H_LUMA_0 0x68100
1289#define TV_H_LUMA_59 0x681ec
1290#define TV_H_CHROMA_0 0x68200
1291#define TV_H_CHROMA_59 0x682ec
1292#define TV_V_LUMA_0 0x68300
1293#define TV_V_LUMA_42 0x683a8
1294#define TV_V_CHROMA_0 0x68400
1295#define TV_V_CHROMA_42 0x684a8
1296
1297/* Display & cursor control */
1298
1299/* Pipe A */
1300#define PIPEADSL 0x70000
1301#define PIPEACONF 0x70008
1302#define PIPEACONF_ENABLE (1<<31)
1303#define PIPEACONF_DISABLE 0
1304#define PIPEACONF_DOUBLE_WIDE (1<<30)
1305#define I965_PIPECONF_ACTIVE (1<<30)
1306#define PIPEACONF_SINGLE_WIDE 0
1307#define PIPEACONF_PIPE_UNLOCKED 0
1308#define PIPEACONF_PIPE_LOCKED (1<<25)
1309#define PIPEACONF_PALETTE 0
1310#define PIPEACONF_GAMMA (1<<24)
1311#define PIPECONF_FORCE_BORDER (1<<25)
1312#define PIPECONF_PROGRESSIVE (0 << 21)
1313#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1314#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1315#define PIPEASTAT 0x70024
1316#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1317#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1318#define PIPE_CRC_DONE_ENABLE (1UL<<28)
1319#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1320#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1321#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1322#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1323#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1324#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1325#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1326#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1327#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1328#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1329#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1330#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1331#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1332#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1333#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1334#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1335#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1336#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1337#define PIPE_DPST_EVENT_STATUS (1UL<<7)
1338#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1339#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1340#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1341#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1342#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1343#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1344#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1345
1346#define DSPARB 0x70030
1347#define DSPARB_CSTART_MASK (0x7f << 7)
1348#define DSPARB_CSTART_SHIFT 7
1349#define DSPARB_BSTART_MASK (0x7f)
1350#define DSPARB_BSTART_SHIFT 0
1351/*
1352 * The two pipe frame counter registers are not synchronized, so
1353 * reading a stable value is somewhat tricky. The following code
1354 * should work:
1355 *
1356 * do {
1357 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1358 * PIPE_FRAME_HIGH_SHIFT;
1359 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1360 * PIPE_FRAME_LOW_SHIFT);
1361 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1362 * PIPE_FRAME_HIGH_SHIFT);
1363 * } while (high1 != high2);
1364 * frame = (high1 << 8) | low1;
1365 */
1366#define PIPEAFRAMEHIGH 0x70040
1367#define PIPE_FRAME_HIGH_MASK 0x0000ffff
1368#define PIPE_FRAME_HIGH_SHIFT 0
1369#define PIPEAFRAMEPIXEL 0x70044
1370#define PIPE_FRAME_LOW_MASK 0xff000000
1371#define PIPE_FRAME_LOW_SHIFT 24
1372#define PIPE_PIXEL_MASK 0x00ffffff
1373#define PIPE_PIXEL_SHIFT 0
1374
1375/* Cursor A & B regs */
1376#define CURACNTR 0x70080
1377#define CURSOR_MODE_DISABLE 0x00
1378#define CURSOR_MODE_64_32B_AX 0x07
1379#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1380#define MCURSOR_GAMMA_ENABLE (1 << 26)
1381#define CURABASE 0x70084
1382#define CURAPOS 0x70088
1383#define CURSOR_POS_MASK 0x007FF
1384#define CURSOR_POS_SIGN 0x8000
1385#define CURSOR_X_SHIFT 0
1386#define CURSOR_Y_SHIFT 16
1387#define CURBCNTR 0x700c0
1388#define CURBBASE 0x700c4
1389#define CURBPOS 0x700c8
1390
1391/* Display A control */
1392#define DSPACNTR 0x70180
1393#define DISPLAY_PLANE_ENABLE (1<<31)
1394#define DISPLAY_PLANE_DISABLE 0
1395#define DISPPLANE_GAMMA_ENABLE (1<<30)
1396#define DISPPLANE_GAMMA_DISABLE 0
1397#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1398#define DISPPLANE_8BPP (0x2<<26)
1399#define DISPPLANE_15_16BPP (0x4<<26)
1400#define DISPPLANE_16BPP (0x5<<26)
1401#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1402#define DISPPLANE_32BPP (0x7<<26)
1403#define DISPPLANE_STEREO_ENABLE (1<<25)
1404#define DISPPLANE_STEREO_DISABLE 0
1405#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1406#define DISPPLANE_SEL_PIPE_A 0
1407#define DISPPLANE_SEL_PIPE_B (1<<24)
1408#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1409#define DISPPLANE_SRC_KEY_DISABLE 0
1410#define DISPPLANE_LINE_DOUBLE (1<<20)
1411#define DISPPLANE_NO_LINE_DOUBLE 0
1412#define DISPPLANE_STEREO_POLARITY_FIRST 0
1413#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1414#define DSPAADDR 0x70184
1415#define DSPASTRIDE 0x70188
1416#define DSPAPOS 0x7018C /* reserved */
1417#define DSPASIZE 0x70190
1418#define DSPASURF 0x7019C /* 965+ only */
1419#define DSPATILEOFF 0x701A4 /* 965+ only */
1420
1421/* VBIOS flags */
1422#define SWF00 0x71410
1423#define SWF01 0x71414
1424#define SWF02 0x71418
1425#define SWF03 0x7141c
1426#define SWF04 0x71420
1427#define SWF05 0x71424
1428#define SWF06 0x71428
1429#define SWF10 0x70410
1430#define SWF11 0x70414
1431#define SWF14 0x71420
1432#define SWF30 0x72414
1433#define SWF31 0x72418
1434#define SWF32 0x7241c
1435
1436/* Pipe B */
1437#define PIPEBDSL 0x71000
1438#define PIPEBCONF 0x71008
1439#define PIPEBSTAT 0x71024
1440#define PIPEBFRAMEHIGH 0x71040
1441#define PIPEBFRAMEPIXEL 0x71044
1442
1443/* Display B control */
1444#define DSPBCNTR 0x71180
1445#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1446#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1447#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1448#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1449#define DSPBADDR 0x71184
1450#define DSPBSTRIDE 0x71188
1451#define DSPBPOS 0x7118C
1452#define DSPBSIZE 0x71190
1453#define DSPBSURF 0x7119C
1454#define DSPBTILEOFF 0x711A4
1455
1456/* VBIOS regs */
1457#define VGACNTRL 0x71400
1458# define VGA_DISP_DISABLE (1 << 31)
1459# define VGA_2X_MODE (1 << 30)
1460# define VGA_PIPE_B_SELECT (1 << 29)
1461
1462#endif /* _I915_REG_H_ */