Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mm/mmu.c |
| 3 | * |
| 4 | * Copyright (C) 1995-2005 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 10 | #include <linux/module.h> |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/errno.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/bootmem.h> |
| 15 | #include <linux/mman.h> |
| 16 | #include <linux/nodemask.h> |
| 17 | |
| 18 | #include <asm/mach-types.h> |
| 19 | #include <asm/setup.h> |
| 20 | #include <asm/sizes.h> |
| 21 | #include <asm/tlb.h> |
| 22 | |
| 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach/map.h> |
| 25 | |
| 26 | #include "mm.h" |
| 27 | |
| 28 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); |
| 29 | |
Russell King | 6ae5a6e | 2006-09-30 10:50:05 +0100 | [diff] [blame] | 30 | extern void _stext, _etext, __data_start, _end; |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 31 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
| 32 | |
| 33 | /* |
| 34 | * empty_zero_page is a special page that is used for |
| 35 | * zero-initialized data and COW. |
| 36 | */ |
| 37 | struct page *empty_zero_page; |
| 38 | |
| 39 | /* |
| 40 | * The pmd table for the upper-most set of pages. |
| 41 | */ |
| 42 | pmd_t *top_pmd; |
| 43 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 44 | #define CPOLICY_UNCACHED 0 |
| 45 | #define CPOLICY_BUFFERED 1 |
| 46 | #define CPOLICY_WRITETHROUGH 2 |
| 47 | #define CPOLICY_WRITEBACK 3 |
| 48 | #define CPOLICY_WRITEALLOC 4 |
| 49 | |
| 50 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; |
| 51 | static unsigned int ecc_mask __initdata = 0; |
| 52 | pgprot_t pgprot_kernel; |
| 53 | |
| 54 | EXPORT_SYMBOL(pgprot_kernel); |
| 55 | |
| 56 | struct cachepolicy { |
| 57 | const char policy[16]; |
| 58 | unsigned int cr_mask; |
| 59 | unsigned int pmd; |
| 60 | unsigned int pte; |
| 61 | }; |
| 62 | |
| 63 | static struct cachepolicy cache_policies[] __initdata = { |
| 64 | { |
| 65 | .policy = "uncached", |
| 66 | .cr_mask = CR_W|CR_C, |
| 67 | .pmd = PMD_SECT_UNCACHED, |
| 68 | .pte = 0, |
| 69 | }, { |
| 70 | .policy = "buffered", |
| 71 | .cr_mask = CR_C, |
| 72 | .pmd = PMD_SECT_BUFFERED, |
| 73 | .pte = PTE_BUFFERABLE, |
| 74 | }, { |
| 75 | .policy = "writethrough", |
| 76 | .cr_mask = 0, |
| 77 | .pmd = PMD_SECT_WT, |
| 78 | .pte = PTE_CACHEABLE, |
| 79 | }, { |
| 80 | .policy = "writeback", |
| 81 | .cr_mask = 0, |
| 82 | .pmd = PMD_SECT_WB, |
| 83 | .pte = PTE_BUFFERABLE|PTE_CACHEABLE, |
| 84 | }, { |
| 85 | .policy = "writealloc", |
| 86 | .cr_mask = 0, |
| 87 | .pmd = PMD_SECT_WBWA, |
| 88 | .pte = PTE_BUFFERABLE|PTE_CACHEABLE, |
| 89 | } |
| 90 | }; |
| 91 | |
| 92 | /* |
| 93 | * These are useful for identifing cache coherency |
| 94 | * problems by allowing the cache or the cache and |
| 95 | * writebuffer to be turned off. (Note: the write |
| 96 | * buffer should not be on and the cache off). |
| 97 | */ |
| 98 | static void __init early_cachepolicy(char **p) |
| 99 | { |
| 100 | int i; |
| 101 | |
| 102 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
| 103 | int len = strlen(cache_policies[i].policy); |
| 104 | |
| 105 | if (memcmp(*p, cache_policies[i].policy, len) == 0) { |
| 106 | cachepolicy = i; |
| 107 | cr_alignment &= ~cache_policies[i].cr_mask; |
| 108 | cr_no_alignment &= ~cache_policies[i].cr_mask; |
| 109 | *p += len; |
| 110 | break; |
| 111 | } |
| 112 | } |
| 113 | if (i == ARRAY_SIZE(cache_policies)) |
| 114 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); |
| 115 | flush_cache_all(); |
| 116 | set_cr(cr_alignment); |
| 117 | } |
| 118 | __early_param("cachepolicy=", early_cachepolicy); |
| 119 | |
| 120 | static void __init early_nocache(char **__unused) |
| 121 | { |
| 122 | char *p = "buffered"; |
| 123 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); |
| 124 | early_cachepolicy(&p); |
| 125 | } |
| 126 | __early_param("nocache", early_nocache); |
| 127 | |
| 128 | static void __init early_nowrite(char **__unused) |
| 129 | { |
| 130 | char *p = "uncached"; |
| 131 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); |
| 132 | early_cachepolicy(&p); |
| 133 | } |
| 134 | __early_param("nowb", early_nowrite); |
| 135 | |
| 136 | static void __init early_ecc(char **p) |
| 137 | { |
| 138 | if (memcmp(*p, "on", 2) == 0) { |
| 139 | ecc_mask = PMD_PROTECTION; |
| 140 | *p += 2; |
| 141 | } else if (memcmp(*p, "off", 3) == 0) { |
| 142 | ecc_mask = 0; |
| 143 | *p += 3; |
| 144 | } |
| 145 | } |
| 146 | __early_param("ecc=", early_ecc); |
| 147 | |
| 148 | static int __init noalign_setup(char *__unused) |
| 149 | { |
| 150 | cr_alignment &= ~CR_A; |
| 151 | cr_no_alignment &= ~CR_A; |
| 152 | set_cr(cr_alignment); |
| 153 | return 1; |
| 154 | } |
| 155 | __setup("noalign", noalign_setup); |
| 156 | |
Russell King | 255d1f8 | 2006-12-18 00:12:47 +0000 | [diff] [blame^] | 157 | #ifndef CONFIG_SMP |
| 158 | void adjust_cr(unsigned long mask, unsigned long set) |
| 159 | { |
| 160 | unsigned long flags; |
| 161 | |
| 162 | mask &= ~CR_A; |
| 163 | |
| 164 | set &= mask; |
| 165 | |
| 166 | local_irq_save(flags); |
| 167 | |
| 168 | cr_no_alignment = (cr_no_alignment & ~mask) | set; |
| 169 | cr_alignment = (cr_alignment & ~mask) | set; |
| 170 | |
| 171 | set_cr((get_cr() & ~mask) | set); |
| 172 | |
| 173 | local_irq_restore(flags); |
| 174 | } |
| 175 | #endif |
| 176 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 177 | struct mem_types { |
| 178 | unsigned int prot_pte; |
| 179 | unsigned int prot_l1; |
| 180 | unsigned int prot_sect; |
| 181 | unsigned int domain; |
| 182 | }; |
| 183 | |
| 184 | static struct mem_types mem_types[] __initdata = { |
| 185 | [MT_DEVICE] = { |
| 186 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 187 | L_PTE_WRITE, |
| 188 | .prot_l1 = PMD_TYPE_TABLE, |
| 189 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED | |
| 190 | PMD_SECT_AP_WRITE, |
| 191 | .domain = DOMAIN_IO, |
| 192 | }, |
| 193 | [MT_CACHECLEAN] = { |
| 194 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4, |
| 195 | .domain = DOMAIN_KERNEL, |
| 196 | }, |
| 197 | [MT_MINICLEAN] = { |
| 198 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE, |
| 199 | .domain = DOMAIN_KERNEL, |
| 200 | }, |
| 201 | [MT_LOW_VECTORS] = { |
| 202 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 203 | L_PTE_EXEC, |
| 204 | .prot_l1 = PMD_TYPE_TABLE, |
| 205 | .domain = DOMAIN_USER, |
| 206 | }, |
| 207 | [MT_HIGH_VECTORS] = { |
| 208 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 209 | L_PTE_USER | L_PTE_EXEC, |
| 210 | .prot_l1 = PMD_TYPE_TABLE, |
| 211 | .domain = DOMAIN_USER, |
| 212 | }, |
| 213 | [MT_MEMORY] = { |
| 214 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE, |
| 215 | .domain = DOMAIN_KERNEL, |
| 216 | }, |
| 217 | [MT_ROM] = { |
| 218 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4, |
| 219 | .domain = DOMAIN_KERNEL, |
| 220 | }, |
| 221 | [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */ |
| 222 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
| 223 | L_PTE_WRITE, |
| 224 | .prot_l1 = PMD_TYPE_TABLE, |
| 225 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED | |
| 226 | PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | |
| 227 | PMD_SECT_TEX(1), |
| 228 | .domain = DOMAIN_IO, |
| 229 | }, |
| 230 | [MT_NONSHARED_DEVICE] = { |
| 231 | .prot_l1 = PMD_TYPE_TABLE, |
| 232 | .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV | |
| 233 | PMD_SECT_AP_WRITE, |
| 234 | .domain = DOMAIN_IO, |
| 235 | } |
| 236 | }; |
| 237 | |
| 238 | /* |
| 239 | * Adjust the PMD section entries according to the CPU in use. |
| 240 | */ |
| 241 | static void __init build_mem_type_table(void) |
| 242 | { |
| 243 | struct cachepolicy *cp; |
| 244 | unsigned int cr = get_cr(); |
| 245 | unsigned int user_pgprot, kern_pgprot; |
| 246 | int cpu_arch = cpu_architecture(); |
| 247 | int i; |
| 248 | |
| 249 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
| 250 | if (cachepolicy > CPOLICY_BUFFERED) |
| 251 | cachepolicy = CPOLICY_BUFFERED; |
| 252 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
| 253 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
| 254 | cachepolicy = CPOLICY_WRITETHROUGH; |
| 255 | #endif |
| 256 | if (cpu_arch < CPU_ARCH_ARMv5) { |
| 257 | if (cachepolicy >= CPOLICY_WRITEALLOC) |
| 258 | cachepolicy = CPOLICY_WRITEBACK; |
| 259 | ecc_mask = 0; |
| 260 | } |
| 261 | |
| 262 | /* |
| 263 | * Xscale must not have PMD bit 4 set for section mappings. |
| 264 | */ |
| 265 | if (cpu_is_xscale()) |
| 266 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 267 | mem_types[i].prot_sect &= ~PMD_BIT4; |
| 268 | |
| 269 | /* |
| 270 | * ARMv5 and lower, excluding Xscale, bit 4 must be set for |
| 271 | * page tables. |
| 272 | */ |
| 273 | if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale()) |
| 274 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
| 275 | if (mem_types[i].prot_l1) |
| 276 | mem_types[i].prot_l1 |= PMD_BIT4; |
| 277 | |
| 278 | cp = &cache_policies[cachepolicy]; |
| 279 | kern_pgprot = user_pgprot = cp->pte; |
| 280 | |
| 281 | /* |
| 282 | * Enable CPU-specific coherency if supported. |
| 283 | * (Only available on XSC3 at the moment.) |
| 284 | */ |
| 285 | if (arch_is_coherent()) { |
| 286 | if (cpu_is_xsc3()) { |
| 287 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
Lennert Buytenhek | 0e5fdca | 2006-12-02 00:03:47 +0100 | [diff] [blame] | 288 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 289 | } |
| 290 | } |
| 291 | |
| 292 | /* |
| 293 | * ARMv6 and above have extended page tables. |
| 294 | */ |
| 295 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { |
| 296 | /* |
| 297 | * bit 4 becomes XN which we must clear for the |
| 298 | * kernel memory mapping. |
| 299 | */ |
| 300 | mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN; |
| 301 | mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN; |
| 302 | |
| 303 | /* |
| 304 | * Mark cache clean areas and XIP ROM read only |
| 305 | * from SVC mode and no access from userspace. |
| 306 | */ |
| 307 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 308 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 309 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
| 310 | |
| 311 | /* |
| 312 | * Mark the device area as "shared device" |
| 313 | */ |
| 314 | mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE; |
| 315 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; |
| 316 | |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 317 | #ifdef CONFIG_SMP |
| 318 | /* |
| 319 | * Mark memory with the "shared" attribute for SMP systems |
| 320 | */ |
| 321 | user_pgprot |= L_PTE_SHARED; |
| 322 | kern_pgprot |= L_PTE_SHARED; |
| 323 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
| 324 | #endif |
| 325 | } |
| 326 | |
| 327 | for (i = 0; i < 16; i++) { |
| 328 | unsigned long v = pgprot_val(protection_map[i]); |
| 329 | v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot; |
| 330 | protection_map[i] = __pgprot(v); |
| 331 | } |
| 332 | |
| 333 | mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot; |
| 334 | mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot; |
| 335 | |
| 336 | if (cpu_arch >= CPU_ARCH_ARMv5) { |
| 337 | #ifndef CONFIG_SMP |
| 338 | /* |
| 339 | * Only use write-through for non-SMP systems |
| 340 | */ |
| 341 | mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; |
| 342 | mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE; |
| 343 | #endif |
| 344 | } else { |
| 345 | mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); |
| 346 | } |
| 347 | |
| 348 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
| 349 | L_PTE_DIRTY | L_PTE_WRITE | |
| 350 | L_PTE_EXEC | kern_pgprot); |
| 351 | |
| 352 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; |
| 353 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; |
| 354 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; |
| 355 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
| 356 | |
| 357 | switch (cp->pmd) { |
| 358 | case PMD_SECT_WT: |
| 359 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; |
| 360 | break; |
| 361 | case PMD_SECT_WB: |
| 362 | case PMD_SECT_WBWA: |
| 363 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; |
| 364 | break; |
| 365 | } |
| 366 | printk("Memory policy: ECC %sabled, Data cache %s\n", |
| 367 | ecc_mask ? "en" : "dis", cp->policy); |
| 368 | } |
| 369 | |
| 370 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
| 371 | |
| 372 | /* |
| 373 | * Create a SECTION PGD between VIRT and PHYS in domain |
| 374 | * DOMAIN with protection PROT. This operates on half- |
| 375 | * pgdir entry increments. |
| 376 | */ |
| 377 | static inline void |
| 378 | alloc_init_section(unsigned long virt, unsigned long phys, int prot) |
| 379 | { |
| 380 | pmd_t *pmdp = pmd_off_k(virt); |
| 381 | |
| 382 | if (virt & (1 << 20)) |
| 383 | pmdp++; |
| 384 | |
| 385 | *pmdp = __pmd(phys | prot); |
| 386 | flush_pmd_entry(pmdp); |
| 387 | } |
| 388 | |
| 389 | /* |
| 390 | * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT |
| 391 | */ |
| 392 | static inline void |
| 393 | alloc_init_supersection(unsigned long virt, unsigned long phys, int prot) |
| 394 | { |
| 395 | int i; |
| 396 | |
| 397 | for (i = 0; i < 16; i += 1) { |
| 398 | alloc_init_section(virt, phys, prot | PMD_SECT_SUPER); |
| 399 | |
| 400 | virt += (PGDIR_SIZE / 2); |
| 401 | } |
| 402 | } |
| 403 | |
| 404 | /* |
| 405 | * Add a PAGE mapping between VIRT and PHYS in domain |
| 406 | * DOMAIN with protection PROT. Note that due to the |
| 407 | * way we map the PTEs, we must allocate two PTE_SIZE'd |
| 408 | * blocks - one for the Linux pte table, and one for |
| 409 | * the hardware pte table. |
| 410 | */ |
| 411 | static inline void |
| 412 | alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot) |
| 413 | { |
| 414 | pmd_t *pmdp = pmd_off_k(virt); |
| 415 | pte_t *ptep; |
| 416 | |
| 417 | if (pmd_none(*pmdp)) { |
| 418 | ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * |
| 419 | sizeof(pte_t)); |
| 420 | |
| 421 | __pmd_populate(pmdp, __pa(ptep) | prot_l1); |
| 422 | } |
| 423 | ptep = pte_offset_kernel(pmdp, virt); |
| 424 | |
Russell King | ad1ae2f | 2006-12-13 14:34:43 +0000 | [diff] [blame] | 425 | set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0); |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | /* |
| 429 | * Create the page directory entries and any necessary |
| 430 | * page tables for the mapping specified by `md'. We |
| 431 | * are able to cope here with varying sizes and address |
| 432 | * offsets, and we take full advantage of sections and |
| 433 | * supersections. |
| 434 | */ |
| 435 | void __init create_mapping(struct map_desc *md) |
| 436 | { |
| 437 | unsigned long virt, length; |
| 438 | int prot_sect, prot_l1, domain; |
| 439 | pgprot_t prot_pte; |
| 440 | unsigned long off = (u32)__pfn_to_phys(md->pfn); |
| 441 | |
| 442 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { |
| 443 | printk(KERN_WARNING "BUG: not creating mapping for " |
| 444 | "0x%08llx at 0x%08lx in user region\n", |
| 445 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 446 | return; |
| 447 | } |
| 448 | |
| 449 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && |
| 450 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { |
| 451 | printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " |
| 452 | "overlaps vmalloc space\n", |
| 453 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 454 | } |
| 455 | |
| 456 | domain = mem_types[md->type].domain; |
| 457 | prot_pte = __pgprot(mem_types[md->type].prot_pte); |
| 458 | prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain); |
| 459 | prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain); |
| 460 | |
| 461 | /* |
| 462 | * Catch 36-bit addresses |
| 463 | */ |
| 464 | if(md->pfn >= 0x100000) { |
| 465 | if(domain) { |
| 466 | printk(KERN_ERR "MM: invalid domain in supersection " |
| 467 | "mapping for 0x%08llx at 0x%08lx\n", |
| 468 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 469 | return; |
| 470 | } |
| 471 | if((md->virtual | md->length | __pfn_to_phys(md->pfn)) |
| 472 | & ~SUPERSECTION_MASK) { |
| 473 | printk(KERN_ERR "MM: cannot create mapping for " |
| 474 | "0x%08llx at 0x%08lx invalid alignment\n", |
| 475 | __pfn_to_phys((u64)md->pfn), md->virtual); |
| 476 | return; |
| 477 | } |
| 478 | |
| 479 | /* |
| 480 | * Shift bits [35:32] of address into bits [23:20] of PMD |
| 481 | * (See ARMv6 spec). |
| 482 | */ |
| 483 | off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); |
| 484 | } |
| 485 | |
| 486 | virt = md->virtual; |
| 487 | off -= virt; |
| 488 | length = md->length; |
| 489 | |
| 490 | if (mem_types[md->type].prot_l1 == 0 && |
| 491 | (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) { |
| 492 | printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " |
| 493 | "be mapped using pages, ignoring.\n", |
| 494 | __pfn_to_phys(md->pfn), md->virtual); |
| 495 | return; |
| 496 | } |
| 497 | |
| 498 | while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) { |
| 499 | alloc_init_page(virt, virt + off, prot_l1, prot_pte); |
| 500 | |
| 501 | virt += PAGE_SIZE; |
| 502 | length -= PAGE_SIZE; |
| 503 | } |
| 504 | |
| 505 | /* N.B. ARMv6 supersections are only defined to work with domain 0. |
| 506 | * Since domain assignments can in fact be arbitrary, the |
| 507 | * 'domain == 0' check below is required to insure that ARMv6 |
| 508 | * supersections are only allocated for domain 0 regardless |
| 509 | * of the actual domain assignments in use. |
| 510 | */ |
| 511 | if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3()) |
| 512 | && domain == 0) { |
| 513 | /* |
| 514 | * Align to supersection boundary if !high pages. |
| 515 | * High pages have already been checked for proper |
| 516 | * alignment above and they will fail the SUPSERSECTION_MASK |
| 517 | * check because of the way the address is encoded into |
| 518 | * offset. |
| 519 | */ |
| 520 | if (md->pfn <= 0x100000) { |
| 521 | while ((virt & ~SUPERSECTION_MASK || |
| 522 | (virt + off) & ~SUPERSECTION_MASK) && |
| 523 | length >= (PGDIR_SIZE / 2)) { |
| 524 | alloc_init_section(virt, virt + off, prot_sect); |
| 525 | |
| 526 | virt += (PGDIR_SIZE / 2); |
| 527 | length -= (PGDIR_SIZE / 2); |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | while (length >= SUPERSECTION_SIZE) { |
| 532 | alloc_init_supersection(virt, virt + off, prot_sect); |
| 533 | |
| 534 | virt += SUPERSECTION_SIZE; |
| 535 | length -= SUPERSECTION_SIZE; |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | /* |
| 540 | * A section mapping covers half a "pgdir" entry. |
| 541 | */ |
| 542 | while (length >= (PGDIR_SIZE / 2)) { |
| 543 | alloc_init_section(virt, virt + off, prot_sect); |
| 544 | |
| 545 | virt += (PGDIR_SIZE / 2); |
| 546 | length -= (PGDIR_SIZE / 2); |
| 547 | } |
| 548 | |
| 549 | while (length >= PAGE_SIZE) { |
| 550 | alloc_init_page(virt, virt + off, prot_l1, prot_pte); |
| 551 | |
| 552 | virt += PAGE_SIZE; |
| 553 | length -= PAGE_SIZE; |
| 554 | } |
| 555 | } |
| 556 | |
| 557 | /* |
| 558 | * Create the architecture specific mappings |
| 559 | */ |
| 560 | void __init iotable_init(struct map_desc *io_desc, int nr) |
| 561 | { |
| 562 | int i; |
| 563 | |
| 564 | for (i = 0; i < nr; i++) |
| 565 | create_mapping(io_desc + i); |
| 566 | } |
| 567 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 568 | static inline void prepare_page_table(struct meminfo *mi) |
| 569 | { |
| 570 | unsigned long addr; |
| 571 | |
| 572 | /* |
| 573 | * Clear out all the mappings below the kernel image. |
| 574 | */ |
| 575 | for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) |
| 576 | pmd_clear(pmd_off_k(addr)); |
| 577 | |
| 578 | #ifdef CONFIG_XIP_KERNEL |
| 579 | /* The XIP kernel is mapped in the module area -- skip over it */ |
| 580 | addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; |
| 581 | #endif |
| 582 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) |
| 583 | pmd_clear(pmd_off_k(addr)); |
| 584 | |
| 585 | /* |
| 586 | * Clear out all the kernel space mappings, except for the first |
| 587 | * memory bank, up to the end of the vmalloc region. |
| 588 | */ |
| 589 | for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); |
| 590 | addr < VMALLOC_END; addr += PGDIR_SIZE) |
| 591 | pmd_clear(pmd_off_k(addr)); |
| 592 | } |
| 593 | |
| 594 | /* |
| 595 | * Reserve the various regions of node 0 |
| 596 | */ |
| 597 | void __init reserve_node_zero(pg_data_t *pgdat) |
| 598 | { |
| 599 | unsigned long res_size = 0; |
| 600 | |
| 601 | /* |
| 602 | * Register the kernel text and data with bootmem. |
| 603 | * Note that this can only be in node 0. |
| 604 | */ |
| 605 | #ifdef CONFIG_XIP_KERNEL |
| 606 | reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start); |
| 607 | #else |
| 608 | reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext); |
| 609 | #endif |
| 610 | |
| 611 | /* |
| 612 | * Reserve the page tables. These are already in use, |
| 613 | * and can only be in node 0. |
| 614 | */ |
| 615 | reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), |
| 616 | PTRS_PER_PGD * sizeof(pgd_t)); |
| 617 | |
| 618 | /* |
| 619 | * Hmm... This should go elsewhere, but we really really need to |
| 620 | * stop things allocating the low memory; ideally we need a better |
| 621 | * implementation of GFP_DMA which does not assume that DMA-able |
| 622 | * memory starts at zero. |
| 623 | */ |
| 624 | if (machine_is_integrator() || machine_is_cintegrator()) |
| 625 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; |
| 626 | |
| 627 | /* |
| 628 | * These should likewise go elsewhere. They pre-reserve the |
| 629 | * screen memory region at the start of main system memory. |
| 630 | */ |
| 631 | if (machine_is_edb7211()) |
| 632 | res_size = 0x00020000; |
| 633 | if (machine_is_p720t()) |
| 634 | res_size = 0x00014000; |
| 635 | |
Ben Dooks | bbf6f28 | 2006-12-07 20:47:58 +0100 | [diff] [blame] | 636 | /* H1940 and RX3715 need to reserve this for suspend */ |
| 637 | |
| 638 | if (machine_is_h1940() || machine_is_rx3715()) { |
Ben Dooks | 9073341 | 2006-12-06 01:50:24 +0100 | [diff] [blame] | 639 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000); |
| 640 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000); |
| 641 | } |
| 642 | |
Russell King | d111e8f | 2006-09-27 15:27:33 +0100 | [diff] [blame] | 643 | #ifdef CONFIG_SA1111 |
| 644 | /* |
| 645 | * Because of the SA1111 DMA bug, we want to preserve our |
| 646 | * precious DMA-able memory... |
| 647 | */ |
| 648 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; |
| 649 | #endif |
| 650 | if (res_size) |
| 651 | reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size); |
| 652 | } |
| 653 | |
| 654 | /* |
| 655 | * Set up device the mappings. Since we clear out the page tables for all |
| 656 | * mappings above VMALLOC_END, we will remove any debug device mappings. |
| 657 | * This means you have to be careful how you debug this function, or any |
| 658 | * called function. This means you can't use any function or debugging |
| 659 | * method which may touch any device, otherwise the kernel _will_ crash. |
| 660 | */ |
| 661 | static void __init devicemaps_init(struct machine_desc *mdesc) |
| 662 | { |
| 663 | struct map_desc map; |
| 664 | unsigned long addr; |
| 665 | void *vectors; |
| 666 | |
| 667 | /* |
| 668 | * Allocate the vector page early. |
| 669 | */ |
| 670 | vectors = alloc_bootmem_low_pages(PAGE_SIZE); |
| 671 | BUG_ON(!vectors); |
| 672 | |
| 673 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) |
| 674 | pmd_clear(pmd_off_k(addr)); |
| 675 | |
| 676 | /* |
| 677 | * Map the kernel if it is XIP. |
| 678 | * It is always first in the modulearea. |
| 679 | */ |
| 680 | #ifdef CONFIG_XIP_KERNEL |
| 681 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); |
| 682 | map.virtual = MODULE_START; |
| 683 | map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
| 684 | map.type = MT_ROM; |
| 685 | create_mapping(&map); |
| 686 | #endif |
| 687 | |
| 688 | /* |
| 689 | * Map the cache flushing regions. |
| 690 | */ |
| 691 | #ifdef FLUSH_BASE |
| 692 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); |
| 693 | map.virtual = FLUSH_BASE; |
| 694 | map.length = SZ_1M; |
| 695 | map.type = MT_CACHECLEAN; |
| 696 | create_mapping(&map); |
| 697 | #endif |
| 698 | #ifdef FLUSH_BASE_MINICACHE |
| 699 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); |
| 700 | map.virtual = FLUSH_BASE_MINICACHE; |
| 701 | map.length = SZ_1M; |
| 702 | map.type = MT_MINICLEAN; |
| 703 | create_mapping(&map); |
| 704 | #endif |
| 705 | |
| 706 | /* |
| 707 | * Create a mapping for the machine vectors at the high-vectors |
| 708 | * location (0xffff0000). If we aren't using high-vectors, also |
| 709 | * create a mapping at the low-vectors virtual address. |
| 710 | */ |
| 711 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
| 712 | map.virtual = 0xffff0000; |
| 713 | map.length = PAGE_SIZE; |
| 714 | map.type = MT_HIGH_VECTORS; |
| 715 | create_mapping(&map); |
| 716 | |
| 717 | if (!vectors_high()) { |
| 718 | map.virtual = 0; |
| 719 | map.type = MT_LOW_VECTORS; |
| 720 | create_mapping(&map); |
| 721 | } |
| 722 | |
| 723 | /* |
| 724 | * Ask the machine support to map in the statically mapped devices. |
| 725 | */ |
| 726 | if (mdesc->map_io) |
| 727 | mdesc->map_io(); |
| 728 | |
| 729 | /* |
| 730 | * Finally flush the caches and tlb to ensure that we're in a |
| 731 | * consistent state wrt the writebuffer. This also ensures that |
| 732 | * any write-allocated cache lines in the vector page are written |
| 733 | * back. After this point, we can start to touch devices again. |
| 734 | */ |
| 735 | local_flush_tlb_all(); |
| 736 | flush_cache_all(); |
| 737 | } |
| 738 | |
| 739 | /* |
| 740 | * paging_init() sets up the page tables, initialises the zone memory |
| 741 | * maps, and sets up the zero page, bad page and bad page tables. |
| 742 | */ |
| 743 | void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) |
| 744 | { |
| 745 | void *zero_page; |
| 746 | |
| 747 | build_mem_type_table(); |
| 748 | prepare_page_table(mi); |
| 749 | bootmem_init(mi); |
| 750 | devicemaps_init(mdesc); |
| 751 | |
| 752 | top_pmd = pmd_off_k(0xffff0000); |
| 753 | |
| 754 | /* |
| 755 | * allocate the zero page. Note that we count on this going ok. |
| 756 | */ |
| 757 | zero_page = alloc_bootmem_low_pages(PAGE_SIZE); |
| 758 | memzero(zero_page, PAGE_SIZE); |
| 759 | empty_zero_page = virt_to_page(zero_page); |
| 760 | flush_dcache_page(empty_zero_page); |
| 761 | } |
Russell King | ae8f154 | 2006-09-27 15:38:34 +0100 | [diff] [blame] | 762 | |
| 763 | /* |
| 764 | * In order to soft-boot, we need to insert a 1:1 mapping in place of |
| 765 | * the user-mode pages. This will then ensure that we have predictable |
| 766 | * results when turning the mmu off |
| 767 | */ |
| 768 | void setup_mm_for_reboot(char mode) |
| 769 | { |
| 770 | unsigned long base_pmdval; |
| 771 | pgd_t *pgd; |
| 772 | int i; |
| 773 | |
| 774 | if (current->mm && current->mm->pgd) |
| 775 | pgd = current->mm->pgd; |
| 776 | else |
| 777 | pgd = init_mm.pgd; |
| 778 | |
| 779 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; |
| 780 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) |
| 781 | base_pmdval |= PMD_BIT4; |
| 782 | |
| 783 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { |
| 784 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; |
| 785 | pmd_t *pmd; |
| 786 | |
| 787 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); |
| 788 | pmd[0] = __pmd(pmdval); |
| 789 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); |
| 790 | flush_pmd_entry(pmd); |
| 791 | } |
| 792 | } |