blob: 4329d39f902cd4eed4181e119c6f0325fc3f0de0 [file] [log] [blame]
Tim Small5a2c6752007-07-19 01:49:42 -07001/*
2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License.
7 *
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10 * others.
11 *
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13 *
14 * Written with reference to 82443BX Host Bridge Datasheet:
Justin P. Mattock631dd1a2010-10-18 11:03:14 +020015 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
Tim Small5a2c6752007-07-19 01:49:42 -070016 * references to this document given in [].
17 *
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26
27#include <linux/pci.h>
28#include <linux/pci_ids.h>
29
Tim Small5a2c6752007-07-19 01:49:42 -070030
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -070031#include <linux/edac.h>
Douglas Thompson20bcb7a2007-07-19 01:49:47 -070032#include "edac_core.h"
Tim Small5a2c6752007-07-19 01:49:42 -070033
34#define I82443_REVISION "0.1"
35
36#define EDAC_MOD_STR "i82443bxgx_edac"
37
Tim Small5a2c6752007-07-19 01:49:42 -070038/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
40 * rows" "The 82443BX supports multiple-bit error detection and
41 * single-bit error correction when ECC mode is enabled and
42 * single/multi-bit error detection when correction is disabled.
43 * During writes to the DRAM, the 82443BX generates ECC for the data
44 * on a QWord basis. Partial QWord writes require a read-modify-write
45 * cycle when ECC is enabled."
46*/
47
48/* "Additionally, the 82443BX ensures that the data is corrected in
49 * main memory so that accumulation of errors is prevented. Another
50 * error within the same QWord would result in a double-bit error
51 * which is unrecoverable. This is known as hardware scrubbing since
52 * it requires no software intervention to correct the data in memory."
53 */
54
55/* [Also see page 100 (section 4.3), "DRAM Interface"]
56 * [Also see page 112 (section 4.6.1.4), ECC]
57 */
58
59#define I82443BXGX_NR_CSROWS 8
60#define I82443BXGX_NR_CHANS 1
61#define I82443BXGX_NR_DIMMS 4
62
Tim Small5a2c6752007-07-19 01:49:42 -070063/* 82443 PCI Device 0 */
Douglas Thompson11116602007-07-19 01:50:07 -070064#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
65 * config space offset */
66#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
67 * row is non-ECC */
68#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
Tim Small5a2c6752007-07-19 01:49:42 -070069
Douglas Thompson11116602007-07-19 01:50:07 -070070#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
71#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
72#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
73#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
74#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
Tim Small5a2c6752007-07-19 01:49:42 -070075
76#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
77
Tim Small5a2c6752007-07-19 01:49:42 -070078/* 82443 PCI Device 0 */
Douglas Thompson11116602007-07-19 01:50:07 -070079#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
80 * config space offset, Error Address
81 * Pointer Register */
82#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
83#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
84#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
Tim Small5a2c6752007-07-19 01:49:42 -070085
Douglas Thompson11116602007-07-19 01:50:07 -070086#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
Tim Small5a2c6752007-07-19 01:49:42 -070087 * config space offset. */
Douglas Thompson11116602007-07-19 01:50:07 -070088#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
89#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
Tim Small5a2c6752007-07-19 01:49:42 -070090
Douglas Thompson11116602007-07-19 01:50:07 -070091#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
Tim Small5a2c6752007-07-19 01:49:42 -070092 * config space offset. */
Douglas Thompson11116602007-07-19 01:50:07 -070093#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
94#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
95#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
96#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
Tim Small5a2c6752007-07-19 01:49:42 -070097
Douglas Thompson11116602007-07-19 01:50:07 -070098#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
99 * config space offset. */
100#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
101#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
Tim Small5a2c6752007-07-19 01:49:42 -0700102#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
Douglas Thompson11116602007-07-19 01:50:07 -0700103#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
Tim Small5a2c6752007-07-19 01:49:42 -0700104
Douglas Thompson11116602007-07-19 01:50:07 -0700105#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
106 * config space offset. */
Tim Small5a2c6752007-07-19 01:49:42 -0700107
108/* FIXME - don't poll when ECC disabled? */
109
Tim Small5a2c6752007-07-19 01:49:42 -0700110struct i82443bxgx_edacmc_error_info {
111 u32 eap;
112};
113
Dave Jiang456a2f92007-07-19 01:50:10 -0700114static struct edac_pci_ctl_info *i82443bxgx_pci;
115
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700116static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
117 * already registered driver
118 */
119
120static int i82443bxgx_registered = 1;
121
Douglas Thompson11116602007-07-19 01:50:07 -0700122static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700123 struct i82443bxgx_edacmc_error_info
124 *info)
Tim Small5a2c6752007-07-19 01:49:42 -0700125{
126 struct pci_dev *pdev;
127 pdev = to_pci_dev(mci->dev);
128 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
129 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
130 /* Clear error to allow next error to be reported [p.61] */
131 pci_write_bits32(pdev, I82443BXGX_EAP,
132 I82443BXGX_EAP_OFFSET_SBE,
133 I82443BXGX_EAP_OFFSET_SBE);
134
135 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
136 /* Clear error to allow next error to be reported [p.61] */
137 pci_write_bits32(pdev, I82443BXGX_EAP,
138 I82443BXGX_EAP_OFFSET_MBE,
139 I82443BXGX_EAP_OFFSET_MBE);
140}
141
Douglas Thompson11116602007-07-19 01:50:07 -0700142static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
143 struct
144 i82443bxgx_edacmc_error_info
145 *info, int handle_errors)
Tim Small5a2c6752007-07-19 01:49:42 -0700146{
147 int error_found = 0;
148 u32 eapaddr, page, pageoffset;
149
150 /* bits 30:12 hold the 4kb block in which the error occurred
151 * [p.61] */
152 eapaddr = (info->eap & 0xfffff000);
153 page = eapaddr >> PAGE_SHIFT;
154 pageoffset = eapaddr - (page << PAGE_SHIFT);
155
Douglas Thompson11116602007-07-19 01:50:07 -0700156 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
Tim Small5a2c6752007-07-19 01:49:42 -0700157 error_found = 1;
158 if (handle_errors)
Douglas Thompson11116602007-07-19 01:50:07 -0700159 edac_mc_handle_ce(mci, page, pageoffset,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700160 /* 440BX/GX don't make syndrome information
161 * available */
162 0, edac_mc_find_csrow_by_page(mci, page), 0,
163 mci->ctl_name);
Tim Small5a2c6752007-07-19 01:49:42 -0700164 }
165
Douglas Thompson11116602007-07-19 01:50:07 -0700166 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
Tim Small5a2c6752007-07-19 01:49:42 -0700167 error_found = 1;
168 if (handle_errors)
Douglas Thompson11116602007-07-19 01:50:07 -0700169 edac_mc_handle_ue(mci, page, pageoffset,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700170 edac_mc_find_csrow_by_page(mci, page),
171 mci->ctl_name);
Tim Small5a2c6752007-07-19 01:49:42 -0700172 }
173
174 return error_found;
175}
176
Tim Small5a2c6752007-07-19 01:49:42 -0700177static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
178{
179 struct i82443bxgx_edacmc_error_info info;
180
Joe Perches63ae96b2010-05-26 14:44:14 -0700181 debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700182 i82443bxgx_edacmc_get_error_info(mci, &info);
183 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
184}
185
Tim Small5a2c6752007-07-19 01:49:42 -0700186static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700187 struct pci_dev *pdev,
188 enum edac_type edac_mode,
189 enum mem_type mtype)
Tim Small5a2c6752007-07-19 01:49:42 -0700190{
191 struct csrow_info *csrow;
192 int index;
193 u8 drbar, dramc;
194 u32 row_base, row_high_limit, row_high_limit_last;
195
196 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
197 row_high_limit_last = 0;
198 for (index = 0; index < mci->nr_csrows; index++) {
199 csrow = &mci->csrows[index];
200 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
Joe Perches63ae96b2010-05-26 14:44:14 -0700201 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
202 mci->mc_idx, __FILE__, __func__, index, drbar);
Tim Small5a2c6752007-07-19 01:49:42 -0700203 row_high_limit = ((u32) drbar << 23);
204 /* find the DRAM Chip Select Base address and mask */
Joe Perches63ae96b2010-05-26 14:44:14 -0700205 debugf1("MC%d: %s: %s() Row=%d, "
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300206 "Boundary Address=%#0x, Last = %#0x\n",
Joe Perches63ae96b2010-05-26 14:44:14 -0700207 mci->mc_idx, __FILE__, __func__, index, row_high_limit,
Tim Small5a2c6752007-07-19 01:49:42 -0700208 row_high_limit_last);
209
210 /* 440GX goes to 2GB, represented with a DRB of 0. */
211 if (row_high_limit_last && !row_high_limit)
212 row_high_limit = 1UL << 31;
213
214 /* This row is empty [p.49] */
215 if (row_high_limit == row_high_limit_last)
216 continue;
217 row_base = row_high_limit_last;
218 csrow->first_page = row_base >> PAGE_SHIFT;
219 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
220 csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
221 /* EAP reports in 4kilobyte granularity [61] */
222 csrow->grain = 1 << 12;
223 csrow->mtype = mtype;
224 /* I don't think 440BX can tell you device type? FIXME? */
225 csrow->dtype = DEV_UNKNOWN;
226 /* Mode is global to all rows on 440BX */
227 csrow->edac_mode = edac_mode;
228 row_high_limit_last = row_high_limit;
229 }
230}
231
Douglas Thompson11116602007-07-19 01:50:07 -0700232static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
Tim Small5a2c6752007-07-19 01:49:42 -0700233{
234 struct mem_ctl_info *mci;
235 u8 dramc;
236 u32 nbxcfg, ecc_mode;
237 enum mem_type mtype;
238 enum edac_type edac_mode;
239
Joe Perches63ae96b2010-05-26 14:44:14 -0700240 debugf0("MC: %s: %s()\n", __FILE__, __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700241
242 /* Something is really hosed if PCI config space reads from
Douglas Thompson052dfb42007-07-19 01:50:13 -0700243 * the MC aren't working.
244 */
Tim Small5a2c6752007-07-19 01:49:42 -0700245 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
246 return -EIO;
247
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700248 mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
Tim Small5a2c6752007-07-19 01:49:42 -0700249
250 if (mci == NULL)
251 return -ENOMEM;
252
Joe Perches63ae96b2010-05-26 14:44:14 -0700253 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
Tim Small5a2c6752007-07-19 01:49:42 -0700254 mci->dev = &pdev->dev;
255 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
256 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
257 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
258 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
Douglas Thompson11116602007-07-19 01:50:07 -0700259 case I82443BXGX_DRAMC_DRAM_IS_EDO:
Tim Small5a2c6752007-07-19 01:49:42 -0700260 mtype = MEM_EDO;
261 break;
262 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
263 mtype = MEM_SDR;
264 break;
265 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
266 mtype = MEM_RDR;
267 break;
268 default:
Douglas Thompson052dfb42007-07-19 01:50:13 -0700269 debugf0("Unknown/reserved DRAM type value "
270 "in DRAMC register!\n");
Tim Small5a2c6752007-07-19 01:49:42 -0700271 mtype = -MEM_UNKNOWN;
272 }
273
274 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
275 mci->edac_cap = mci->edac_ctl_cap;
276 else
277 mci->edac_cap = EDAC_FLAG_NONE;
278
279 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
280 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
281 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
Douglas Thompson052dfb42007-07-19 01:50:13 -0700282 (BIT(0) | BIT(1)));
Tim Small5a2c6752007-07-19 01:49:42 -0700283
284 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
Douglas Thompson052dfb42007-07-19 01:50:13 -0700285 ? SCRUB_HW_SRC : SCRUB_NONE;
Tim Small5a2c6752007-07-19 01:49:42 -0700286
Douglas Thompson11116602007-07-19 01:50:07 -0700287 switch (ecc_mode) {
Tim Small5a2c6752007-07-19 01:49:42 -0700288 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
289 edac_mode = EDAC_NONE;
290 break;
291 case I82443BXGX_NBXCFG_INTEGRITY_EC:
292 edac_mode = EDAC_EC;
293 break;
294 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
295 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
296 edac_mode = EDAC_SECDED;
297 break;
298 default:
Douglas Thompson052dfb42007-07-19 01:50:13 -0700299 debugf0("%s(): Unknown/reserved ECC state "
300 "in NBXCFG register!\n", __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700301 edac_mode = EDAC_UNKNOWN;
302 break;
303 }
304
305 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
306
307 /* Many BIOSes don't clear error flags on boot, so do this
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300308 * here, or we get "phantom" errors occurring at module-load
Tim Small5a2c6752007-07-19 01:49:42 -0700309 * time. */
310 pci_write_bits32(pdev, I82443BXGX_EAP,
Douglas Thompson052dfb42007-07-19 01:50:13 -0700311 (I82443BXGX_EAP_OFFSET_SBE |
312 I82443BXGX_EAP_OFFSET_MBE),
313 (I82443BXGX_EAP_OFFSET_SBE |
314 I82443BXGX_EAP_OFFSET_MBE));
Tim Small5a2c6752007-07-19 01:49:42 -0700315
316 mci->mod_name = EDAC_MOD_STR;
317 mci->mod_ver = I82443_REVISION;
318 mci->ctl_name = "I82443BXGX";
Dave Jiangc4192702007-07-19 01:49:47 -0700319 mci->dev_name = pci_name(pdev);
Tim Small5a2c6752007-07-19 01:49:42 -0700320 mci->edac_check = i82443bxgx_edacmc_check;
321 mci->ctl_page_to_phys = NULL;
322
Doug Thompsonb8f6f972007-07-19 01:50:26 -0700323 if (edac_mc_add_mc(mci)) {
Tim Small5a2c6752007-07-19 01:49:42 -0700324 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
325 goto fail;
326 }
327
Dave Jiang456a2f92007-07-19 01:50:10 -0700328 /* allocating generic PCI control info */
329 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
330 if (!i82443bxgx_pci) {
331 printk(KERN_WARNING
332 "%s(): Unable to create PCI control\n",
333 __func__);
334 printk(KERN_WARNING
335 "%s(): PCI error report via EDAC not setup\n",
336 __func__);
337 }
338
Joe Perches63ae96b2010-05-26 14:44:14 -0700339 debugf3("MC: %s: %s(): success\n", __FILE__, __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700340 return 0;
341
Douglas Thompson052dfb42007-07-19 01:50:13 -0700342fail:
Tim Small5a2c6752007-07-19 01:49:42 -0700343 edac_mc_free(mci);
344 return -ENODEV;
345}
Douglas Thompson11116602007-07-19 01:50:07 -0700346
Tim Small5a2c6752007-07-19 01:49:42 -0700347EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
348
349/* returns count (>= 0), or negative on error */
350static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
Douglas Thompson11116602007-07-19 01:50:07 -0700351 const struct pci_device_id *ent)
Tim Small5a2c6752007-07-19 01:49:42 -0700352{
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700353 int rc;
354
Joe Perches63ae96b2010-05-26 14:44:14 -0700355 debugf0("MC: %s: %s()\n", __FILE__, __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700356
Roman Fietzeee6583f2010-05-18 14:45:47 +0200357 /* don't need to call pci_enable_device() */
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700358 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
359
360 if (mci_pdev == NULL)
361 mci_pdev = pci_dev_get(pdev);
362
363 return rc;
Tim Small5a2c6752007-07-19 01:49:42 -0700364}
365
Tim Small5a2c6752007-07-19 01:49:42 -0700366static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
367{
368 struct mem_ctl_info *mci;
369
Joe Perches63ae96b2010-05-26 14:44:14 -0700370 debugf0("%s: %s()\n", __FILE__, __func__);
Tim Small5a2c6752007-07-19 01:49:42 -0700371
Dave Jiang456a2f92007-07-19 01:50:10 -0700372 if (i82443bxgx_pci)
373 edac_pci_release_generic_ctl(i82443bxgx_pci);
374
Douglas Thompson11116602007-07-19 01:50:07 -0700375 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
Tim Small5a2c6752007-07-19 01:49:42 -0700376 return;
377
378 edac_mc_free(mci);
379}
Tim Small5a2c6752007-07-19 01:49:42 -0700380
Douglas Thompson11116602007-07-19 01:50:07 -0700381EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
Tim Small5a2c6752007-07-19 01:49:42 -0700382
383static const struct pci_device_id i82443bxgx_pci_tbl[] __devinitdata = {
384 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
385 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
386 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
387 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
388 {0,} /* 0 terminated list. */
389};
390
391MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
392
Tim Small5a2c6752007-07-19 01:49:42 -0700393static struct pci_driver i82443bxgx_edacmc_driver = {
394 .name = EDAC_MOD_STR,
395 .probe = i82443bxgx_edacmc_init_one,
396 .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
397 .id_table = i82443bxgx_pci_tbl,
398};
399
Tim Small5a2c6752007-07-19 01:49:42 -0700400static int __init i82443bxgx_edacmc_init(void)
401{
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700402 int pci_rc;
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700403 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
404 opstate_init();
405
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700406 pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
407 if (pci_rc < 0)
408 goto fail0;
409
410 if (mci_pdev == NULL) {
411 const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
412 int i = 0;
413 i82443bxgx_registered = 0;
414
415 while (mci_pdev == NULL && id->vendor != 0) {
416 mci_pdev = pci_get_device(id->vendor,
417 id->device, NULL);
418 i++;
419 id = &i82443bxgx_pci_tbl[i];
420 }
421 if (!mci_pdev) {
422 debugf0("i82443bxgx pci_get_device fail\n");
423 pci_rc = -ENODEV;
424 goto fail1;
425 }
426
427 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
428
429 if (pci_rc < 0) {
430 debugf0("i82443bxgx init fail\n");
431 pci_rc = -ENODEV;
432 goto fail1;
433 }
434 }
435
436 return 0;
437
438fail1:
439 pci_unregister_driver(&i82443bxgx_edacmc_driver);
440
441fail0:
442 if (mci_pdev != NULL)
443 pci_dev_put(mci_pdev);
444
445 return pci_rc;
Tim Small5a2c6752007-07-19 01:49:42 -0700446}
447
Tim Small5a2c6752007-07-19 01:49:42 -0700448static void __exit i82443bxgx_edacmc_exit(void)
449{
450 pci_unregister_driver(&i82443bxgx_edacmc_driver);
Vladislav Bogdanov53a2fe52008-10-15 22:04:26 -0700451
452 if (!i82443bxgx_registered)
453 i82443bxgx_edacmc_remove_one(mci_pdev);
454
455 if (mci_pdev)
456 pci_dev_put(mci_pdev);
Tim Small5a2c6752007-07-19 01:49:42 -0700457}
458
Tim Small5a2c6752007-07-19 01:49:42 -0700459module_init(i82443bxgx_edacmc_init);
460module_exit(i82443bxgx_edacmc_exit);
461
Tim Small5a2c6752007-07-19 01:49:42 -0700462MODULE_LICENSE("GPL");
463MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
464MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
Hitoshi Mitakec3c52bc2008-04-29 01:03:18 -0700465
466module_param(edac_op_state, int, 0444);
467MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");