blob: 92b52ebd0eb635c67d94a8ad21539f25762430d9 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040023#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070024#include <linux/kallsyms.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090025#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Doug Thompsonbd8481e2006-05-08 17:06:09 -070027/* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
30 */
31static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
32{
33 dev->broken_parity_status = 1; /* This device gives false positives */
34}
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
36DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
37
Linus Torvalds1da177e2005-04-16 15:20:36 -070038/* Deal with broken BIOS'es that neglect to enable passive release,
39 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -080040static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070041{
42 struct pci_dev *d = NULL;
43 unsigned char dlc;
44
45 /* We have to make sure a particular bit is set in the PIIX3
46 ISA bridge, so we have to go out and find it. */
47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
48 pci_read_config_byte(d, 0x82, &dlc);
49 if (!(dlc & 1<<1)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070050 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 dlc |= 1<<1;
52 pci_write_config_byte(d, 0x82, dlc);
53 }
54 }
55}
Andrew Morton652c5382007-11-21 15:07:13 -080056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
59/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
60 but VIA don't answer queries. If you happen to have good contacts at VIA
61 ask them for me please -- Alan
62
63 This appears to be BIOS not version dependent. So presumably there is a
64 chipset level fix */
Adrian Bunkc30ca1d2006-12-19 05:13:15 +010065int isa_dma_bridge_buggy;
66EXPORT_SYMBOL(isa_dma_bridge_buggy);
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
69{
70 if (!isa_dma_bridge_buggy) {
71 isa_dma_bridge_buggy=1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070072 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 }
74}
75 /*
76 * Its not totally clear which chipsets are the problematic ones
77 * We know 82C586 and 82C596 variants are affected.
78 */
Andrew Morton652c5382007-11-21 15:07:13 -080079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
85DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070086
87int pci_pci_problems;
Adrian Bunkc30ca1d2006-12-19 05:13:15 +010088EXPORT_SYMBOL(pci_pci_problems);
Linus Torvalds1da177e2005-04-16 15:20:36 -070089
90/*
91 * Chipsets where PCI->PCI transfers vanish or hang
92 */
93static void __devinit quirk_nopcipci(struct pci_dev *dev)
94{
95 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070096 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 pci_pci_problems |= PCIPCI_FAIL;
98 }
99}
Andrew Morton652c5382007-11-21 15:07:13 -0800100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700102
103static void __devinit quirk_nopciamd(struct pci_dev *dev)
104{
105 u8 rev;
106 pci_read_config_byte(dev, 0x08, &rev);
107 if (rev == 0x13) {
108 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700110 pci_pci_problems |= PCIAGP_FAIL;
111 }
112}
Andrew Morton652c5382007-11-21 15:07:13 -0800113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115/*
116 * Triton requires workarounds to be used by the drivers
117 */
118static void __devinit quirk_triton(struct pci_dev *dev)
119{
120 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 pci_pci_problems |= PCIPCI_TRITON;
123 }
124}
Andrew Morton652c5382007-11-21 15:07:13 -0800125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
130/*
131 * VIA Apollo KT133 needs PCI latency patch
132 * Made according to a windows driver based patch by George E. Breese
133 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
134 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
135 * the info on which Mr Breese based his work.
136 *
137 * Updated based on further information from the site and also on
138 * information provided by VIA
139 */
Alan Cox1597cac2006-12-04 15:14:45 -0800140static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141{
142 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700151 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 goto exit;
153 } else {
154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
155 if (p==NULL) /* No problem parts */
156 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700158 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 goto exit;
160 }
161
162 /*
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
168 *
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
173 */
174
175 pci_read_config_byte(dev, 0x76, &busarb);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
178 busarb &= ~(1<<5);
179 busarb |= (1<<4);
180 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182exit:
183 pci_dev_put(p);
184}
Andrew Morton652c5382007-11-21 15:07:13 -0800185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800188/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800189DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192
193/*
194 * VIA Apollo VP3 needs ETBF on BT848/878
195 */
196static void __devinit quirk_viaetbf(struct pci_dev *dev)
197{
198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 pci_pci_problems |= PCIPCI_VIAETBF;
201 }
202}
Andrew Morton652c5382007-11-21 15:07:13 -0800203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
205static void __devinit quirk_vsfx(struct pci_dev *dev)
206{
207 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 pci_pci_problems |= PCIPCI_VSFX;
210 }
211}
Andrew Morton652c5382007-11-21 15:07:13 -0800212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
214/*
215 * Ali Magik requires workarounds to be used by the drivers
216 * that DMA to AGP space. Latency must be set to 0xA and triton
217 * workaround applied too
218 * [Info kindly provided by ALi]
219 */
220static void __init quirk_alimagik(struct pci_dev *dev)
221{
222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
225 }
226}
Andrew Morton652c5382007-11-21 15:07:13 -0800227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229
230/*
231 * Natoma has some interesting boundary conditions with Zoran stuff
232 * at least
233 */
234static void __devinit quirk_natoma(struct pci_dev *dev)
235{
236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 pci_pci_problems |= PCIPCI_NATOMA;
239 }
240}
Andrew Morton652c5382007-11-21 15:07:13 -0800241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247
248/*
249 * This chip can cause PCI parity errors if config register 0xA0 is read
250 * while DMAs are occurring.
251 */
252static void __devinit quirk_citrine(struct pci_dev *dev)
253{
254 dev->cfg_size = 0xA0;
255}
Andrew Morton652c5382007-11-21 15:07:13 -0800256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257
258/*
259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
260 * If it's needed, re-allocate the region.
261 */
262static void __devinit quirk_s3_64M(struct pci_dev *dev)
263{
264 struct resource *r = &dev->resource[0];
265
266 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
267 r->start = 0;
268 r->end = 0x3ffffff;
269 }
270}
Andrew Morton652c5382007-11-21 15:07:13 -0800271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273
Linus Torvalds6693e742005-10-25 20:40:09 -0700274static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
275 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276{
277 region &= ~(size-1);
278 if (region) {
David S. Miller085ae412005-08-08 13:19:08 -0700279 struct pci_bus_region bus_region;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 struct resource *res = dev->resource + nr;
281
282 res->name = pci_name(dev);
283 res->start = region;
284 res->end = region + size - 1;
285 res->flags = IORESOURCE_IO;
David S. Miller085ae412005-08-08 13:19:08 -0700286
287 /* Convert from PCI bus to resource space. */
288 bus_region.start = res->start;
289 bus_region.end = res->end;
290 pcibios_bus_to_resource(dev, res, &bus_region);
291
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 pci_claim_resource(dev, nr);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 }
295}
296
297/*
298 * ATI Northbridge setups MCE the processor if you even
299 * read somewhere between 0x3b0->0x3bb or read 0x3d3
300 */
301static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
302{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
305 request_region(0x3b0, 0x0C, "RadeonIGP");
306 request_region(0x3d3, 0x01, "RadeonIGP");
307}
Andrew Morton652c5382007-11-21 15:07:13 -0800308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309
310/*
311 * Let's make the southbridge information explicit instead
312 * of having to worry about people probing the ACPI areas,
313 * for example.. (Yes, it happens, and if you read the wrong
314 * ACPI register it will put the machine to sleep with no
315 * way of waking it up again. Bummer).
316 *
317 * ALI M7101: Two IO regions pointed to by words at
318 * 0xE0 (64 bytes of ACPI registers)
319 * 0xE2 (32 bytes of SMB registers)
320 */
321static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
322{
323 u16 region;
324
325 pci_read_config_word(dev, 0xE0, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700326 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 pci_read_config_word(dev, 0xE2, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329}
Andrew Morton652c5382007-11-21 15:07:13 -0800330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
Linus Torvalds6693e742005-10-25 20:40:09 -0700332static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
333{
334 u32 devres;
335 u32 mask, size, base;
336
337 pci_read_config_dword(dev, port, &devres);
338 if ((devres & enable) != enable)
339 return;
340 mask = (devres >> 16) & 15;
341 base = devres & 0xffff;
342 size = 16;
343 for (;;) {
344 unsigned bit = size >> 1;
345 if ((bit & mask) == bit)
346 break;
347 size = bit;
348 }
349 /*
350 * For now we only print it out. Eventually we'll want to
351 * reserve it (at least if it's in the 0x1000+ range), but
352 * let's get enough confirmation reports first.
353 */
354 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700356}
357
358static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
359{
360 u32 devres;
361 u32 mask, size, base;
362
363 pci_read_config_dword(dev, port, &devres);
364 if ((devres & enable) != enable)
365 return;
366 base = devres & 0xffff0000;
367 mask = (devres & 0x3f) << 16;
368 size = 128 << 16;
369 for (;;) {
370 unsigned bit = size >> 1;
371 if ((bit & mask) == bit)
372 break;
373 size = bit;
374 }
375 /*
376 * For now we only print it out. Eventually we'll want to
377 * reserve it, but let's get enough confirmation reports first.
378 */
379 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700381}
382
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383/*
384 * PIIX4 ACPI: Two IO regions pointed to by longwords at
385 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800386 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700387 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 */
389static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
390{
Linus Torvalds6693e742005-10-25 20:40:09 -0700391 u32 region, res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
393 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700394 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 pci_read_config_dword(dev, 0x90, &region);
Linus Torvalds08db2a72005-10-30 14:40:07 -0800396 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700397
398 /* Device resource A has enables for some of the other ones */
399 pci_read_config_dword(dev, 0x5c, &res_a);
400
401 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
402 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
403
404 /* Device resource D is just bitfields for static resources */
405
406 /* Device 12 enabled? */
407 if (res_a & (1 << 29)) {
408 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
409 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
410 }
411 /* Device 13 enabled? */
412 if (res_a & (1 << 30)) {
413 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
414 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
415 }
416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418}
Andrew Morton652c5382007-11-21 15:07:13 -0800419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422/*
423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
424 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
425 * 0x58 (64 bytes of GPIO I/O space)
426 */
427static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
428{
429 u32 region;
430
431 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700432 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700433
434 pci_read_config_dword(dev, 0x58, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436}
Andrew Morton652c5382007-11-21 15:07:13 -0800437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000448static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
449{
450 u32 region;
451
452 pci_read_config_dword(dev, 0x40, &region);
453 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
454
455 pci_read_config_dword(dev, 0x48, &region);
456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
457}
Andrew Morton652c5382007-11-21 15:07:13 -0800458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000472
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473/*
474 * VIA ACPI: One IO region pointed to by longword at
475 * 0x48 or 0x20 (256 bytes of ACPI registers)
476 */
477static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
478{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 u32 region;
480
Auke Kok651472f2007-08-27 16:18:10 -0700481 if (dev->revision & 0x10) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 pci_read_config_dword(dev, 0x48, &region);
483 region &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485 }
486}
Andrew Morton652c5382007-11-21 15:07:13 -0800487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488
489/*
490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
491 * 0x48 (256 bytes of ACPI registers)
492 * 0x70 (128 bytes of hardware monitoring register)
493 * 0x90 (16 bytes of SMB registers)
494 */
495static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
496{
497 u16 hm;
498 u32 smb;
499
500 quirk_vt82c586_acpi(dev);
501
502 pci_read_config_word(dev, 0x70, &hm);
503 hm &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300504 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505
506 pci_read_config_dword(dev, 0x90, &smb);
507 smb &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509}
Andrew Morton652c5382007-11-21 15:07:13 -0800510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400512/*
513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
514 * 0x88 (128 bytes of power management registers)
515 * 0xd0 (16 bytes of SMB registers)
516 */
517static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
518{
519 u16 pm, smb;
520
521 pci_read_config_word(dev, 0x88, &pm);
522 pm &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700523 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400524
525 pci_read_config_word(dev, 0xd0, &smb);
526 smb &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700527 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400528}
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
530
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531
532#ifdef CONFIG_X86_IO_APIC
533
534#include <asm/io_apic.h>
535
536/*
537 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
538 * devices to the external APIC.
539 *
540 * TODO: When we have device-specific interrupt routers,
541 * this code will go away from quirks.
542 */
Alan Cox1597cac2006-12-04 15:14:45 -0800543static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544{
545 u8 tmp;
546
547 if (nr_ioapics < 1)
548 tmp = 0; /* nothing routed to external APIC */
549 else
550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
551
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 tmp == 0 ? "Disa" : "Ena");
554
555 /* Offset 0x58: External APIC IRQ output control */
556 pci_write_config_byte (dev, 0x58, tmp);
557}
Andrew Morton652c5382007-11-21 15:07:13 -0800558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560
561/*
Karsten Wiesea1740912005-09-03 15:56:33 -0700562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
563 * This leads to doubled level interrupt rates.
564 * Set this bit to get rid of cycle wastage.
565 * Otherwise uncritical.
566 */
Alan Cox1597cac2006-12-04 15:14:45 -0800567static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700568{
569 u8 misc_control2;
570#define BYPASS_APIC_DEASSERT 8
571
572 pci_read_config_byte(dev, 0x5B, &misc_control2);
573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
576 }
577}
578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200579DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700580
581/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582 * The AMD io apic can hang the box when an apic irq is masked.
583 * We check all revs >= B0 (yet not in the pre production!) as the bug
584 * is currently marked NoFix
585 *
586 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700587 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 * of course. However the advice is demonstrably good even if so..
589 */
590static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
591{
Auke Kok44c10132007-06-08 15:46:36 -0700592 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595 }
596}
Andrew Morton652c5382007-11-21 15:07:13 -0800597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598
599static void __init quirk_ioapic_rmw(struct pci_dev *dev)
600{
601 if (dev->devfn == 0 && dev->bus->number == 0)
602 sis_apic_bug = 1;
603}
Andrew Morton652c5382007-11-21 15:07:13 -0800604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606#define AMD8131_revA0 0x01
607#define AMD8131_revB0 0x11
608#define AMD8131_MISC 0x40
609#define AMD8131_NIOAMODE_BIT 0
Alan Cox1597cac2006-12-04 15:14:45 -0800610static void quirk_amd_8131_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611{
Auke Kok44c10132007-06-08 15:46:36 -0700612 unsigned char tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700613
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 if (nr_ioapics == 0)
615 return;
616
Auke Kok44c10132007-06-08 15:46:36 -0700617 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700618 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
620 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
621 pci_write_config_byte( dev, AMD8131_MISC, tmp);
622 }
623}
John W. Linville5da594b2006-03-20 14:33:56 -0500624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200625DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626#endif /* CONFIG_X86_IO_APIC */
627
Peter Orubad556ad42007-05-15 13:59:13 +0200628/*
629 * Some settings of MMRBC can lead to data corruption so block changes.
630 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
631 */
632static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
633{
Auke Kokaa288d42007-08-27 16:17:47 -0700634 if (dev->subordinate && dev->revision <= 0x12) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700635 dev_info(&dev->dev, "AMD8131 rev %x detected; "
636 "disabling PCI-X MMRBC\n", dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200637 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
638 }
639}
640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641
642/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700643 * FIXME: it is questionable that quirk_via_acpi
644 * is needed. It shows up as an ISA bridge, and does not
645 * support the PCI_INTERRUPT_LINE register at all. Therefore
646 * it seems like setting the pci_dev's 'irq' to the
647 * value of the ACPI SCI interrupt is only done for convenience.
648 * -jgarzik
649 */
650static void __devinit quirk_via_acpi(struct pci_dev *d)
651{
652 /*
653 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
654 */
655 u8 irq;
656 pci_read_config_byte(d, 0x42, &irq);
657 irq &= 0xf;
658 if (irq && (irq != 2))
659 d->irq = irq;
660}
Andrew Morton652c5382007-11-21 15:07:13 -0800661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663
Daniel Drake09d60292006-09-25 16:52:19 -0700664
665/*
Alan Cox1597cac2006-12-04 15:14:45 -0800666 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700667 */
Alan Cox1597cac2006-12-04 15:14:45 -0800668
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800669static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
670
671static void quirk_via_bridge(struct pci_dev *dev)
672{
673 /* See what bridge we have and find the device ranges */
674 switch (dev->device) {
675 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800676 /* The VT82C686 is special, it attaches to PCI and can have
677 any device number. All its subdevices are functions of
678 that single device. */
679 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
680 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800681 break;
682 case PCI_DEVICE_ID_VIA_8237:
683 case PCI_DEVICE_ID_VIA_8237A:
684 via_vlink_dev_lo = 15;
685 break;
686 case PCI_DEVICE_ID_VIA_8235:
687 via_vlink_dev_lo = 16;
688 break;
689 case PCI_DEVICE_ID_VIA_8231:
690 case PCI_DEVICE_ID_VIA_8233_0:
691 case PCI_DEVICE_ID_VIA_8233A:
692 case PCI_DEVICE_ID_VIA_8233C_0:
693 via_vlink_dev_lo = 17;
694 break;
695 }
696}
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700705
Alan Cox1597cac2006-12-04 15:14:45 -0800706/**
707 * quirk_via_vlink - VIA VLink IRQ number update
708 * @dev: PCI device
709 *
710 * If the device we are dealing with is on a PIC IRQ we need to
711 * ensure that the IRQ line register which usually is not relevant
712 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800713 * to the right place.
714 * We only do this on systems where a VIA south bridge was detected,
715 * and only for VIA devices on the motherboard (see quirk_via_bridge
716 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800717 */
718
719static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400720{
721 u8 irq, new_irq;
722
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800723 /* Check if we have VLink at all */
724 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700725 return;
726
727 new_irq = dev->irq;
728
729 /* Don't quirk interrupts outside the legacy IRQ range */
730 if (!new_irq || new_irq > 15)
731 return;
732
Alan Cox1597cac2006-12-04 15:14:45 -0800733 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800734 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
735 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800736 return;
737
738 /* This is an internal VLink device on a PIC interrupt. The BIOS
739 ought to have set this but may not have, so we redo it */
740
Len Brown25be5e62005-05-27 04:21:50 -0400741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
742 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700743 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
744 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400745 udelay(15); /* unknown if delay really needed */
746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
747 }
748}
Alan Cox1597cac2006-12-04 15:14:45 -0800749DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400750
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 * VIA VT82C598 has its device ID settable and many BIOSes
753 * set it to the ID of VT82C597 for backward compatibility.
754 * We need to switch it off to be able to recognize the real
755 * type of the chip.
756 */
757static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
758{
759 pci_write_config_byte(dev, 0xfc, 0);
760 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
761}
Andrew Morton652c5382007-11-21 15:07:13 -0800762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700763
764/*
765 * CardBus controllers have a legacy base address that enables them
766 * to respond as i82365 pcmcia controllers. We don't want them to
767 * do this even if the Linux CardBus driver is not loaded, because
768 * the Linux i82365 driver does not (and should not) handle CardBus.
769 */
Alan Cox1597cac2006-12-04 15:14:45 -0800770static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771{
772 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
773 return;
774 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
775}
776DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200777DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778
779/*
780 * Following the PCI ordering rules is optional on the AMD762. I'm not
781 * sure what the designers were smoking but let's not inhale...
782 *
783 * To be fair to AMD, it follows the spec by default, its BIOS people
784 * who turn it off!
785 */
Alan Cox1597cac2006-12-04 15:14:45 -0800786static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700787{
788 u32 pcic;
789 pci_read_config_dword(dev, 0x4C, &pcic);
790 if ((pcic&6)!=6) {
791 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700792 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793 pci_write_config_dword(dev, 0x4C, pcic);
794 pci_read_config_dword(dev, 0x84, &pcic);
795 pcic |= (1<<23); /* Required in this mode */
796 pci_write_config_dword(dev, 0x84, pcic);
797 }
798}
Andrew Morton652c5382007-11-21 15:07:13 -0800799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200800DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801
802/*
803 * DreamWorks provided workaround for Dunord I-3000 problem
804 *
805 * This card decodes and responds to addresses not apparently
806 * assigned to it. We force a larger allocation to ensure that
807 * nothing gets put too close to it.
808 */
809static void __devinit quirk_dunord ( struct pci_dev * dev )
810{
811 struct resource *r = &dev->resource [1];
812 r->start = 0;
813 r->end = 0xffffff;
814}
Andrew Morton652c5382007-11-21 15:07:13 -0800815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700816
817/*
818 * i82380FB mobile docking controller: its PCI-to-PCI bridge
819 * is subtractive decoding (transparent), and does indicate this
820 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
821 * instead of 0x01.
822 */
823static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
824{
825 dev->transparent = 1;
826}
Andrew Morton652c5382007-11-21 15:07:13 -0800827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
830/*
831 * Common misconfiguration of the MediaGX/Geode PCI master that will
832 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
833 * datasheets found at http://www.national.com/ds/GX for info on what
834 * these bits do. <christer@weinigel.se>
835 */
Alan Cox1597cac2006-12-04 15:14:45 -0800836static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837{
838 u8 reg;
839 pci_read_config_byte(dev, 0x41, &reg);
840 if (reg & 2) {
841 reg &= ~2;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700842 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 pci_write_config_byte(dev, 0x41, reg);
844 }
845}
Andrew Morton652c5382007-11-21 15:07:13 -0800846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
847DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700848
849/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 * Ensure C0 rev restreaming is off. This is normally done by
851 * the BIOS but in the odd case it is not the results are corruption
852 * hence the presence of a Linux check
853 */
Alan Cox1597cac2006-12-04 15:14:45 -0800854static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855{
856 u16 config;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857
Auke Kok44c10132007-06-08 15:46:36 -0700858 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859 return;
860 pci_read_config_word(pdev, 0x40, &config);
861 if (config & (1<<6)) {
862 config &= ~(1<<6);
863 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700864 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 }
866}
Andrew Morton652c5382007-11-21 15:07:13 -0800867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200868DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
Crane Cai05a7d222008-02-02 13:56:56 +0800870static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -0800871{
Crane Cai05a7d222008-02-02 13:56:56 +0800872 /* set sb600/sb700/sb800 sata to ahci mode */
873 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -0800874
Crane Cai05a7d222008-02-02 13:56:56 +0800875 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
876 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -0800877 pci_read_config_byte(pdev, 0x40, &tmp);
878 pci_write_config_byte(pdev, 0x40, tmp|1);
879 pci_write_config_byte(pdev, 0x9, 1);
880 pci_write_config_byte(pdev, 0xa, 6);
881 pci_write_config_byte(pdev, 0x40, tmp);
882
Conke Huc9f89472007-01-09 05:32:51 -0500883 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +0800884 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -0800885 }
886}
Crane Cai05a7d222008-02-02 13:56:56 +0800887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200888DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +0800889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200890DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -0800891
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892/*
893 * Serverworks CSB5 IDE does not fully support native mode
894 */
895static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
896{
897 u8 prog;
898 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
899 if (prog & 5) {
900 prog &= ~5;
901 pdev->class &= ~5;
902 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +0100903 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904 }
905}
Andrew Morton652c5382007-11-21 15:07:13 -0800906DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907
908/*
909 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
910 */
911static void __init quirk_ide_samemode(struct pci_dev *pdev)
912{
913 u8 prog;
914
915 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
916
917 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700918 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919 prog &= ~5;
920 pdev->class &= ~5;
921 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922 }
923}
Alan Cox368c73d2006-10-04 00:41:26 +0100924DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925
926/* This was originally an Alpha specific thing, but it really fits here.
927 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
928 */
929static void __init quirk_eisa_bridge(struct pci_dev *dev)
930{
931 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
932}
Andrew Morton652c5382007-11-21 15:07:13 -0800933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934
Johannes Goecke7daa0c42006-04-20 02:43:17 -0700935
936/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
938 * is not activated. The myth is that Asus said that they do not want the
939 * users to be irritated by just another PCI Device in the Win98 device
940 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
941 * package 2.7.0 for details)
942 *
943 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
944 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +0200945 * becomes necessary to do this tweak in two steps -- the chosen trigger
946 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +0100947 *
948 * Note that we used to unhide the SMBus that way on Toshiba laptops
949 * (Satellite A40 and Tecra M2) but then found that the thermal management
950 * was done by SMM code, which could cause unsynchronized concurrent
951 * accesses to the SMBus registers, with potentially bad effects. Thus you
952 * should be very careful when adding new entries: if SMM is accessing the
953 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -0700954 *
955 * Likewise, many recent laptops use ACPI for thermal management. If the
956 * ACPI DSDT code accesses the SMBus, then Linux should not access it
957 * natively, and keeping the SMBus hidden is the right thing to do. If you
958 * are about to add an entry in the table below, please first disassemble
959 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700960 */
Vivek Goyal9d24a812007-01-11 01:52:44 +0100961static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700962
963static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
964{
965 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
966 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
967 switch(dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +0200968 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700969 case 0x8070: /* P4B */
970 case 0x8088: /* P4B533 */
971 case 0x1626: /* L3C notebook */
972 asus_hides_smbus = 1;
973 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +0100974 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700975 switch(dev->subsystem_device) {
976 case 0x80b1: /* P4GE-V */
977 case 0x80b2: /* P4PE */
978 case 0x8093: /* P4B533-V */
979 asus_hides_smbus = 1;
980 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +0100981 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700982 switch(dev->subsystem_device) {
983 case 0x8030: /* P4T533 */
984 asus_hides_smbus = 1;
985 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +0100986 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987 switch (dev->subsystem_device) {
988 case 0x8070: /* P4G8X Deluxe */
989 asus_hides_smbus = 1;
990 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +0100991 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +0200992 switch (dev->subsystem_device) {
993 case 0x80c9: /* PU-DLS */
994 asus_hides_smbus = 1;
995 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +0100996 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 switch (dev->subsystem_device) {
998 case 0x1751: /* M2N notebook */
999 case 0x1821: /* M5N notebook */
1000 asus_hides_smbus = 1;
1001 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001002 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001003 switch (dev->subsystem_device) {
1004 case 0x184b: /* W1N notebook */
1005 case 0x186a: /* M6Ne notebook */
1006 asus_hides_smbus = 1;
1007 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001008 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001009 switch (dev->subsystem_device) {
1010 case 0x80f2: /* P4P800-X */
1011 asus_hides_smbus = 1;
1012 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001013 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001014 switch (dev->subsystem_device) {
1015 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001016 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001017 asus_hides_smbus = 1;
1018 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1020 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1021 switch(dev->subsystem_device) {
1022 case 0x088C: /* HP Compaq nc8000 */
1023 case 0x0890: /* HP Compaq nc6000 */
1024 asus_hides_smbus = 1;
1025 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001026 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 switch (dev->subsystem_device) {
1028 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001029 case 0x12bd: /* HP D530 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 asus_hides_smbus = 1;
1031 }
Jean Delvare677cc642007-11-21 18:29:06 +01001032 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1033 switch (dev->subsystem_device) {
1034 case 0x12bf: /* HP xw4100 */
1035 asus_hides_smbus = 1;
1036 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1038 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1039 switch(dev->subsystem_device) {
1040 case 0xC00C: /* Samsung P35 notebook */
1041 asus_hides_smbus = 1;
1042 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001043 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1045 switch(dev->subsystem_device) {
1046 case 0x0058: /* Compaq Evo N620c */
1047 asus_hides_smbus = 1;
1048 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001049 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1050 switch(dev->subsystem_device) {
1051 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1052 /* Motherboard doesn't have Host bridge
1053 * subvendor/subdevice IDs, therefore checking
1054 * its on-board VGA controller */
1055 asus_hides_smbus = 1;
1056 }
Jean Delvare10260d92008-06-04 13:53:31 +02001057 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1058 switch(dev->subsystem_device) {
1059 case 0x00b8: /* Compaq Evo D510 CMT */
1060 case 0x00b9: /* Compaq Evo D510 SFF */
1061 asus_hides_smbus = 1;
1062 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001063 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1064 switch (dev->subsystem_device) {
1065 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1066 /* Motherboard doesn't have host bridge
1067 * subvendor/subdevice IDs, therefore checking
1068 * its on-board VGA controller */
1069 asus_hides_smbus = 1;
1070 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001071 }
1072}
Andrew Morton652c5382007-11-21 15:07:13 -08001073DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1075DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1079DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1080DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083
Andrew Morton652c5382007-11-21 15:07:13 -08001084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
Jean Delvare10260d92008-06-04 13:53:31 +02001085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001087
Alan Cox1597cac2006-12-04 15:14:45 -08001088static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089{
1090 u16 val;
1091
1092 if (likely(!asus_hides_smbus))
1093 return;
1094
1095 pci_read_config_word(dev, 0xF2, &val);
1096 if (val & 0x8) {
1097 pci_write_config_word(dev, 0xF2, val & (~0x8));
1098 pci_read_config_word(dev, 0xF2, &val);
1099 if (val & 0x8)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001100 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001102 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 }
1104}
Andrew Morton652c5382007-11-21 15:07:13 -08001105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1107DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1108DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001112DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1113DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1115DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1116DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1117DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1118DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001119
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001120/* It appears we just have one such device. If not, we have a warning */
1121static void __iomem *asus_rcba_base;
1122static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001123{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001124 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001125
1126 if (likely(!asus_hides_smbus))
1127 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001128 WARN_ON(asus_rcba_base);
1129
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001130 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001131 /* use bits 31:14, 16 kB aligned */
1132 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1133 if (asus_rcba_base == NULL)
1134 return;
1135}
1136
1137static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1138{
1139 u32 val;
1140
1141 if (likely(!asus_hides_smbus || !asus_rcba_base))
1142 return;
1143 /* read the Function Disable register, dword mode only */
1144 val = readl(asus_rcba_base + 0x3418);
1145 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1146}
1147
1148static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1149{
1150 if (likely(!asus_hides_smbus || !asus_rcba_base))
1151 return;
1152 iounmap(asus_rcba_base);
1153 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001154 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001155}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001156
1157static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1158{
1159 asus_hides_smbus_lpc_ich6_suspend(dev);
1160 asus_hides_smbus_lpc_ich6_resume_early(dev);
1161 asus_hides_smbus_lpc_ich6_resume(dev);
1162}
Andrew Morton652c5382007-11-21 15:07:13 -08001163DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001164DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1165DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1166DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001167
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168/*
1169 * SiS 96x south bridge: BIOS typically hides SMBus device...
1170 */
Alan Cox1597cac2006-12-04 15:14:45 -08001171static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001172{
1173 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001174 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001175 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001176 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001177 pci_write_config_byte(dev, 0x77, val & ~0x10);
1178 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179}
Andrew Morton652c5382007-11-21 15:07:13 -08001180DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1181DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1183DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001184DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1185DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1186DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1187DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189/*
1190 * ... This is further complicated by the fact that some SiS96x south
1191 * bridges pretend to be 85C503/5513 instead. In that case see if we
1192 * spotted a compatible north bridge to make sure.
1193 * (pci_find_device doesn't work yet)
1194 *
1195 * We can also enable the sis96x bit in the discovery register..
1196 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001197#define SIS_DETECT_REGISTER 0x40
1198
Alan Cox1597cac2006-12-04 15:14:45 -08001199static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200{
1201 u8 reg;
1202 u16 devid;
1203
1204 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1205 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1206 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1207 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1208 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1209 return;
1210 }
1211
Linus Torvalds1da177e2005-04-16 15:20:36 -07001212 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001213 * Ok, it now shows up as a 96x.. run the 96x quirk by
1214 * hand in case it has already been processed.
1215 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216 */
1217 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001218 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219}
Andrew Morton652c5382007-11-21 15:07:13 -08001220DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001221DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001224/*
1225 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1226 * and MC97 modem controller are disabled when a second PCI soundcard is
1227 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1228 * -- bjd
1229 */
Alan Cox1597cac2006-12-04 15:14:45 -08001230static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001231{
1232 u8 val;
1233 int asus_hides_ac97 = 0;
1234
1235 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1236 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1237 asus_hides_ac97 = 1;
1238 }
1239
1240 if (!asus_hides_ac97)
1241 return;
1242
1243 pci_read_config_byte(dev, 0x50, &val);
1244 if (val & 0xc0) {
1245 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1246 pci_read_config_byte(dev, 0x50, &val);
1247 if (val & 0xc0)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001248 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001249 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001250 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001251 }
1252}
Andrew Morton652c5382007-11-21 15:07:13 -08001253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001254DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001255
Tejun Heo77967052006-08-19 03:54:39 +09001256#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001257
1258/*
1259 * If we are using libata we can drive this chip properly but must
1260 * do this early on to make the additional device appear during
1261 * the PCI scanning.
1262 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001263static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001264{
Tejun Heoe34bb372007-02-26 20:24:03 +09001265 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001266 u8 hdr;
1267
1268 /* Only poke fn 0 */
1269 if (PCI_FUNC(pdev->devfn))
1270 return;
1271
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001272 pci_read_config_dword(pdev, 0x40, &conf1);
1273 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001274
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001275 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1276 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001277
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001278 switch (pdev->device) {
1279 case PCI_DEVICE_ID_JMICRON_JMB360:
1280 /* The controller should be in single function ahci mode */
1281 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1282 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001283
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001284 case PCI_DEVICE_ID_JMICRON_JMB365:
1285 case PCI_DEVICE_ID_JMICRON_JMB366:
1286 /* Redirect IDE second PATA port to the right spot */
1287 conf5 |= (1 << 24);
1288 /* Fall through */
1289 case PCI_DEVICE_ID_JMICRON_JMB361:
1290 case PCI_DEVICE_ID_JMICRON_JMB363:
1291 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1292 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001293 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001294 break;
1295
1296 case PCI_DEVICE_ID_JMICRON_JMB368:
1297 /* The controller should be in single function IDE mode */
1298 conf1 |= 0x00C00000; /* Set 22, 23 */
1299 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001300 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001301
1302 pci_write_config_dword(pdev, 0x40, conf1);
1303 pci_write_config_dword(pdev, 0x80, conf5);
1304
1305 /* Update pdev accordingly */
1306 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1307 pdev->hdr_type = hdr & 0x7f;
1308 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001309
1310 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1311 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001312}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001313DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1314DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1315DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1316DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1317DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1318DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001319DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1320DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1321DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1322DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1323DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1324DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001325
1326#endif
1327
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328#ifdef CONFIG_X86_IO_APIC
1329static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1330{
1331 int i;
1332
1333 if ((pdev->class >> 8) != 0xff00)
1334 return;
1335
1336 /* the first BAR is the location of the IO APIC...we must
1337 * not touch this (and it's already covered by the fixmap), so
1338 * forcibly insert it into the resource tree */
1339 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1340 insert_resource(&iomem_resource, &pdev->resource[0]);
1341
1342 /* The next five BARs all seem to be rubbish, so just clean
1343 * them out */
1344 for (i=1; i < 6; i++) {
1345 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1346 }
1347
1348}
Andrew Morton652c5382007-11-21 15:07:13 -08001349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350#endif
1351
Linus Torvalds1da177e2005-04-16 15:20:36 -07001352int pcie_mch_quirk;
Adrian Bunkc30ca1d2006-12-19 05:13:15 +01001353EXPORT_SYMBOL(pcie_mch_quirk);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354
1355static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1356{
1357 pcie_mch_quirk = 1;
1358}
Andrew Morton652c5382007-11-21 15:07:13 -08001359DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1360DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1361DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362
Kristen Accardi4602b882005-08-16 15:15:58 -07001363
1364/*
1365 * It's possible for the MSI to get corrupted if shpc and acpi
1366 * are used together on certain PXH-based systems.
1367 */
1368static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1369{
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001370 pci_msi_off(dev);
Kristen Accardi4602b882005-08-16 15:15:58 -07001371 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001372 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001373}
1374DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1375DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1376DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1377DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1378DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1379
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001380/*
1381 * Some Intel PCI Express chipsets have trouble with downstream
1382 * device power management.
1383 */
1384static void quirk_intel_pcie_pm(struct pci_dev * dev)
1385{
1386 pci_pm_d3_delay = 120;
1387 dev->no_d1d2 = 1;
1388}
1389
1390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1402DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1403DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1404DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1405DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1406DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1407DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1408DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1409DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001411
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001412/*
1413 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1414 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1415 * Re-allocate the region if needed...
1416 */
1417static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1418{
1419 struct resource *r = &dev->resource[0];
1420
1421 if (r->start & 0x8) {
1422 r->start = 0;
1423 r->end = 0xf;
1424 }
1425}
1426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1427 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1428 quirk_tc86c001_ide);
1429
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430static void __devinit quirk_netmos(struct pci_dev *dev)
1431{
1432 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1433 unsigned int num_serial = dev->subsystem_device & 0xf;
1434
1435 /*
1436 * These Netmos parts are multiport serial devices with optional
1437 * parallel ports. Even when parallel ports are present, they
1438 * are identified as class SERIAL, which means the serial driver
1439 * will claim them. To prevent this, mark them as class OTHER.
1440 * These combo devices should be claimed by parport_serial.
1441 *
1442 * The subdevice ID is of the form 0x00PS, where <P> is the number
1443 * of parallel ports and <S> is the number of serial ports.
1444 */
1445 switch (dev->device) {
1446 case PCI_DEVICE_ID_NETMOS_9735:
1447 case PCI_DEVICE_ID_NETMOS_9745:
1448 case PCI_DEVICE_ID_NETMOS_9835:
1449 case PCI_DEVICE_ID_NETMOS_9845:
1450 case PCI_DEVICE_ID_NETMOS_9855:
1451 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1452 num_parallel) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001453 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454 "%u serial); changing class SERIAL to OTHER "
1455 "(use parport_serial)\n",
1456 dev->device, num_parallel, num_serial);
1457 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1458 (dev->class & 0xff);
1459 }
1460 }
1461}
1462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1463
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001464static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1465{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001466 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001467 u8 __iomem *csr;
1468 u8 cmd_hi;
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001469 int pm;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001470
1471 switch (dev->device) {
1472 /* PCI IDs taken from drivers/net/e100.c */
1473 case 0x1029:
1474 case 0x1030 ... 0x1034:
1475 case 0x1038 ... 0x103E:
1476 case 0x1050 ... 0x1057:
1477 case 0x1059:
1478 case 0x1064 ... 0x106B:
1479 case 0x1091 ... 0x1095:
1480 case 0x1209:
1481 case 0x1229:
1482 case 0x2449:
1483 case 0x2459:
1484 case 0x245D:
1485 case 0x27DC:
1486 break;
1487 default:
1488 return;
1489 }
1490
1491 /*
1492 * Some firmware hands off the e100 with interrupts enabled,
1493 * which can cause a flood of interrupts if packets are
1494 * received before the driver attaches to the device. So
1495 * disable all e100 interrupts here. The driver will
1496 * re-enable them when it's ready.
1497 */
1498 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001499
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001500 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001501 return;
1502
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001503 /*
1504 * Check that the device is in the D0 power state. If it's not,
1505 * there is no point to look any further.
1506 */
1507 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1508 if (pm) {
1509 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1510 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1511 return;
1512 }
1513
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001514 /* Convert from PCI bus to resource space. */
1515 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001516 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001517 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001518 return;
1519 }
1520
1521 cmd_hi = readb(csr + 3);
1522 if (cmd_hi == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001523 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1524 "disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001525 writeb(1, csr + 3);
1526 }
1527
1528 iounmap(csr);
1529}
Marian Balakowicz4e68fc92007-07-03 11:03:18 +02001530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001531
1532static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1533{
1534 /* rev 1 ncr53c810 chips don't set the class at all which means
1535 * they don't get their resources remapped. Fix that here.
1536 */
1537
1538 if (dev->class == PCI_CLASS_NOT_DEFINED) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001539 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001540 dev->class = PCI_CLASS_STORAGE_SCSI;
1541 }
1542}
1543DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1544
Linus Torvalds1da177e2005-04-16 15:20:36 -07001545static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1546{
1547 while (f < end) {
1548 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1549 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -07001550#ifdef DEBUG
Bjorn Helgaas0255f542008-03-04 15:22:07 -08001551 dev_dbg(&dev->dev, "calling ");
Linus Torvaldsa442ac52008-05-15 17:50:37 -07001552 print_fn_descriptor_symbol("%s\n", f->hook);
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -07001553#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001554 f->hook(dev);
1555 }
1556 f++;
1557 }
1558}
1559
1560extern struct pci_fixup __start_pci_fixups_early[];
1561extern struct pci_fixup __end_pci_fixups_early[];
1562extern struct pci_fixup __start_pci_fixups_header[];
1563extern struct pci_fixup __end_pci_fixups_header[];
1564extern struct pci_fixup __start_pci_fixups_final[];
1565extern struct pci_fixup __end_pci_fixups_final[];
1566extern struct pci_fixup __start_pci_fixups_enable[];
1567extern struct pci_fixup __end_pci_fixups_enable[];
Alan Cox1597cac2006-12-04 15:14:45 -08001568extern struct pci_fixup __start_pci_fixups_resume[];
1569extern struct pci_fixup __end_pci_fixups_resume[];
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001570extern struct pci_fixup __start_pci_fixups_resume_early[];
1571extern struct pci_fixup __end_pci_fixups_resume_early[];
1572extern struct pci_fixup __start_pci_fixups_suspend[];
1573extern struct pci_fixup __end_pci_fixups_suspend[];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001574
1575
1576void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1577{
1578 struct pci_fixup *start, *end;
1579
1580 switch(pass) {
1581 case pci_fixup_early:
1582 start = __start_pci_fixups_early;
1583 end = __end_pci_fixups_early;
1584 break;
1585
1586 case pci_fixup_header:
1587 start = __start_pci_fixups_header;
1588 end = __end_pci_fixups_header;
1589 break;
1590
1591 case pci_fixup_final:
1592 start = __start_pci_fixups_final;
1593 end = __end_pci_fixups_final;
1594 break;
1595
1596 case pci_fixup_enable:
1597 start = __start_pci_fixups_enable;
1598 end = __end_pci_fixups_enable;
1599 break;
1600
Alan Cox1597cac2006-12-04 15:14:45 -08001601 case pci_fixup_resume:
1602 start = __start_pci_fixups_resume;
1603 end = __end_pci_fixups_resume;
1604 break;
1605
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001606 case pci_fixup_resume_early:
1607 start = __start_pci_fixups_resume_early;
1608 end = __end_pci_fixups_resume_early;
1609 break;
1610
1611 case pci_fixup_suspend:
1612 start = __start_pci_fixups_suspend;
1613 end = __end_pci_fixups_suspend;
1614 break;
1615
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616 default:
1617 /* stupid compiler warning, you would think with an enum... */
1618 return;
1619 }
1620 pci_do_fixups(dev, start, end);
1621}
Adrian Bunkc30ca1d2006-12-19 05:13:15 +01001622EXPORT_SYMBOL(pci_fixup_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001623
Daniel Yeisley9d265122005-12-05 07:06:43 -05001624/* Enable 1k I/O space granularity on the Intel P64H2 */
1625static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1626{
1627 u16 en1k;
1628 u8 io_base_lo, io_limit_lo;
1629 unsigned long base, limit;
1630 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1631
1632 pci_read_config_word(dev, 0x40, &en1k);
1633
1634 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001635 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Daniel Yeisley9d265122005-12-05 07:06:43 -05001636
1637 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1638 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1639 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1640 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1641
1642 if (base <= limit) {
1643 res->start = base;
1644 res->end = limit + 0x3ff;
1645 }
1646 }
1647}
1648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1649
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001650/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1651 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1652 * in drivers/pci/setup-bus.c
1653 */
1654static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1655{
1656 u16 en1k, iobl_adr, iobl_adr_1k;
1657 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1658
1659 pci_read_config_word(dev, 0x40, &en1k);
1660
1661 if (en1k & 0x200) {
1662 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1663
1664 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1665
1666 if (iobl_adr != iobl_adr_1k) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001667 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
Daniel Yeisley15a260d2006-12-21 14:34:57 -05001668 iobl_adr,iobl_adr_1k);
1669 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1670 }
1671 }
1672}
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1674
Brice Goglincf34a8e2006-06-13 14:35:42 -04001675/* Under some circumstances, AER is not linked with extended capabilities.
1676 * Force it to be linked by setting the corresponding control bit in the
1677 * config space.
1678 */
Alan Cox1597cac2006-12-04 15:14:45 -08001679static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04001680{
1681 uint8_t b;
1682 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1683 if (!(b & 0x20)) {
1684 pci_write_config_byte(dev, 0xf41, b | 0x20);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001685 dev_info(&dev->dev,
1686 "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04001687 }
1688 }
1689}
1690DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1691 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001692DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08001693 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04001694
Tim Yamin53a9bf42007-11-01 23:14:54 +00001695static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1696{
1697 /*
1698 * Disable PCI Bus Parking and PCI Master read caching on CX700
1699 * which causes unspecified timing errors with a VT6212L on the PCI
1700 * bus leading to USB2.0 packet loss. The defaults are that these
1701 * features are turned off but some BIOSes turn them on.
1702 */
1703
1704 uint8_t b;
1705 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1706 if (b & 0x40) {
1707 /* Turn off PCI Bus Parking */
1708 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1709
Tim Yaminbc043272008-03-30 20:58:59 +01001710 dev_info(&dev->dev,
1711 "Disabling VIA CX700 PCI parking\n");
1712 }
1713 }
1714
1715 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1716 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00001717 /* Turn off PCI Master read caching */
1718 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01001719
1720 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001721 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01001722
1723 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00001724 pci_write_config_byte(dev, 0x77, 0x0);
1725
Bjorn Helgaasd6505a52008-02-29 16:12:18 -07001726 dev_info(&dev->dev,
Tim Yaminbc043272008-03-30 20:58:59 +01001727 "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00001728 }
1729 }
1730}
1731DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1732
Brice Goglin3f79e102006-08-31 01:54:56 -04001733#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07001734/* Some chipsets do not support MSI. We cannot easily rely on setting
1735 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1736 * some other busses controlled by the chipset even if Linux is not
1737 * aware of it. Instead of setting the flag on all busses in the
1738 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04001739 */
Tejun Heoebdf7d32007-05-31 00:40:48 -07001740static void __init quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04001741{
Michael Ellerman88187df2007-01-25 19:34:07 +11001742 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001743 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04001744}
Tejun Heoebdf7d32007-05-31 00:40:48 -07001745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1746DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05001748DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04001749
1750/* Disable MSI on chipsets that are known to not support it */
1751static void __devinit quirk_disable_msi(struct pci_dev *dev)
1752{
1753 if (dev->subordinate) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001754 dev_warn(&dev->dev, "MSI quirk detected; "
1755 "subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04001756 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1757 }
1758}
1759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04001760
1761/* Go through the list of Hypertransport capabilities and
1762 * return 1 if a HT MSI capability is found and enabled */
1763static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1764{
Michael Ellerman7a380502006-11-22 18:26:21 +11001765 int pos, ttl = 48;
1766
1767 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1768 while (pos && ttl--) {
1769 u8 flags;
1770
1771 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1772 &flags) == 0)
1773 {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001774 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11001775 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001776 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11001777 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04001778 }
Michael Ellerman7a380502006-11-22 18:26:21 +11001779
1780 pos = pci_find_next_ht_capability(dev, pos,
1781 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04001782 }
1783 return 0;
1784}
1785
1786/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1787static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1788{
1789 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001790 dev_warn(&dev->dev, "MSI quirk detected; "
1791 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04001792 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1793 }
1794}
1795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1796 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08001797
1798
Brice Goglin6397c752006-08-31 01:55:32 -04001799/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1800 * MSI are supported if the MSI capability set in any of these mappings.
1801 */
1802static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1803{
1804 struct pci_dev *pdev;
1805
1806 if (!dev->subordinate)
1807 return;
1808
1809 /* check HT MSI cap on this chipset and the root one.
1810 * a single one having MSI is enough to be sure that MSI are supported.
1811 */
Alan Cox11f242f2006-10-10 14:39:00 -07001812 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08001813 if (!pdev)
1814 return;
David Rientjes0c875c22006-12-03 11:55:34 -08001815 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001816 dev_warn(&dev->dev, "MSI quirk detected; "
1817 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04001818 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1819 }
Alan Cox11f242f2006-10-10 14:39:00 -07001820 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04001821}
1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1823 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07001824
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07001825/* Force enable MSI mapping capability on HT bridges */
1826static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08001827{
1828 int pos, ttl = 48;
1829
1830 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1831 while (pos && ttl--) {
1832 u8 flags;
1833
1834 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1835 &flags) == 0) {
1836 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1837
1838 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1839 flags | HT_MSI_FLAGS_ENABLE);
1840 }
1841 pos = pci_find_next_ht_capability(dev, pos,
1842 HT_CAPTYPE_MSI_MAPPING);
1843 }
1844}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07001845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1846 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1847 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08001848
1849static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1850{
1851 struct pci_dev *host_bridge;
1852 int pos, ttl = 48;
1853
1854 /*
1855 * HT MSI mapping should be disabled on devices that are below
1856 * a non-Hypertransport host bridge. Locate the host bridge...
1857 */
1858 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1859 if (host_bridge == NULL) {
1860 dev_warn(&dev->dev,
1861 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1862 return;
1863 }
1864
1865 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1866 if (pos != 0) {
1867 /* Host bridge is to HT */
1868 ht_enable_msi_mapping(dev);
1869 return;
1870 }
1871
1872 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1873 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1874 while (pos && ttl--) {
1875 u8 flags;
1876
1877 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1878 &flags) == 0) {
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07001879 dev_info(&dev->dev, "Disabling HT MSI mapping");
Peer Chen9dc625e2008-02-04 23:50:13 -08001880 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1881 flags & ~HT_MSI_FLAGS_ENABLE);
1882 }
1883 pos = pci_find_next_ht_capability(dev, pos,
1884 HT_CAPTYPE_MSI_MAPPING);
1885 }
1886}
1887DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
Björn Krombholz439a7732008-05-12 00:24:27 +02001888DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
Peer Chen9dc625e2008-02-04 23:50:13 -08001889
David Millerba698ad2007-10-25 01:16:30 -07001890static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1891{
1892 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1893}
Shane Huang4600c9d2008-01-25 15:46:24 +09001894static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1895{
1896 struct pci_dev *p;
1897
1898 /* SB700 MSI issue will be fixed at HW level from revision A21,
1899 * we need check PCI REVISION ID of SMBus controller to get SB700
1900 * revision.
1901 */
1902 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1903 NULL);
1904 if (!p)
1905 return;
1906
1907 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1908 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1909 pci_dev_put(p);
1910}
David Millerba698ad2007-10-25 01:16:30 -07001911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1912 PCI_DEVICE_ID_TIGON3_5780,
1913 quirk_msi_intx_disable_bug);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1915 PCI_DEVICE_ID_TIGON3_5780S,
1916 quirk_msi_intx_disable_bug);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1918 PCI_DEVICE_ID_TIGON3_5714,
1919 quirk_msi_intx_disable_bug);
1920DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1921 PCI_DEVICE_ID_TIGON3_5714S,
1922 quirk_msi_intx_disable_bug);
1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1924 PCI_DEVICE_ID_TIGON3_5715,
1925 quirk_msi_intx_disable_bug);
1926DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1927 PCI_DEVICE_ID_TIGON3_5715S,
1928 quirk_msi_intx_disable_bug);
1929
David Millerbc38b412007-10-25 01:16:52 -07001930DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09001931 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07001932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09001933 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07001934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09001935 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07001936DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09001937 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07001938DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09001939 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07001940
1941DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1942 quirk_msi_intx_disable_bug);
1943DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1944 quirk_msi_intx_disable_bug);
1945DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1946 quirk_msi_intx_disable_bug);
1947
Brice Goglin3f79e102006-08-31 01:54:56 -04001948#endif /* CONFIG_PCI_MSI */