Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 19 | #include <linux/of_address.h> |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 20 | #include <linux/kthread.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 21 | #include "msm_drv.h" |
Rob Clark | edcd60c | 2016-03-16 12:56:12 -0400 | [diff] [blame] | 22 | #include "msm_debugfs.h" |
Rob Clark | fde5de6 | 2016-03-15 15:35:08 -0400 | [diff] [blame] | 23 | #include "msm_fence.h" |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 24 | #include "msm_gpu.h" |
Rob Clark | dd2da6e | 2013-11-30 16:12:10 -0500 | [diff] [blame] | 25 | #include "msm_kms.h" |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 26 | #include "sde_wb.h" |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 27 | |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 28 | /* |
| 29 | * MSM driver version: |
| 30 | * - 1.0.0 - initial interface |
| 31 | * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers |
Rob Clark | 7a3bcc0 | 2016-09-16 18:37:44 -0400 | [diff] [blame] | 32 | * - 1.2.0 - adds explicit fence support for submit ioctl |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 33 | */ |
| 34 | #define MSM_VERSION_MAJOR 1 |
Rob Clark | 7a3bcc0 | 2016-09-16 18:37:44 -0400 | [diff] [blame] | 35 | #define MSM_VERSION_MINOR 2 |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 36 | #define MSM_VERSION_PATCHLEVEL 0 |
| 37 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 38 | #define TEARDOWN_DEADLOCK_RETRY_MAX 5 |
| 39 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 40 | static void msm_fb_output_poll_changed(struct drm_device *dev) |
| 41 | { |
| 42 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 43 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 44 | if (priv->fbdev) |
| 45 | drm_fb_helper_hotplug_event(priv->fbdev); |
| 46 | } |
| 47 | |
| 48 | static const struct drm_mode_config_funcs mode_config_funcs = { |
| 49 | .fb_create = msm_framebuffer_create, |
| 50 | .output_poll_changed = msm_fb_output_poll_changed, |
Dhaval Patel | 7a7d85d | 2016-08-26 16:35:34 -0700 | [diff] [blame] | 51 | .atomic_check = drm_atomic_helper_check, |
Rob Clark | cf3a7e4 | 2014-11-08 13:21:06 -0500 | [diff] [blame] | 52 | .atomic_commit = msm_atomic_commit, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 53 | }; |
| 54 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 55 | int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 56 | { |
| 57 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 58 | int idx = priv->num_mmus++; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 59 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 60 | if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus))) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 61 | return -EINVAL; |
| 62 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 63 | priv->mmus[idx] = mmu; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 64 | |
| 65 | return idx; |
| 66 | } |
| 67 | |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 68 | void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu) |
| 69 | { |
| 70 | struct msm_drm_private *priv = dev->dev_private; |
| 71 | int idx; |
| 72 | |
| 73 | if (priv->num_mmus <= 0) { |
| 74 | dev_err(dev->dev, "invalid num mmus %d\n", priv->num_mmus); |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | idx = priv->num_mmus - 1; |
| 79 | |
| 80 | /* only support reverse-order deallocation */ |
| 81 | if (priv->mmus[idx] != mmu) { |
| 82 | dev_err(dev->dev, "unexpected mmu at idx %d\n", idx); |
| 83 | return; |
| 84 | } |
| 85 | |
| 86 | --priv->num_mmus; |
| 87 | priv->mmus[idx] = 0; |
| 88 | } |
| 89 | |
| 90 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 91 | #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING |
| 92 | static bool reglog = false; |
| 93 | MODULE_PARM_DESC(reglog, "Enable register read/write logging"); |
| 94 | module_param(reglog, bool, 0600); |
| 95 | #else |
| 96 | #define reglog 0 |
| 97 | #endif |
| 98 | |
Archit Taneja | a9ee34b | 2015-07-13 12:12:07 +0530 | [diff] [blame] | 99 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Rob Clark | e90dfec | 2015-01-30 17:05:41 -0500 | [diff] [blame] | 100 | static bool fbdev = true; |
| 101 | MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); |
| 102 | module_param(fbdev, bool, 0600); |
| 103 | #endif |
| 104 | |
Rob Clark | 3a10ba8 | 2014-09-08 14:24:57 -0400 | [diff] [blame] | 105 | static char *vram = "16m"; |
Rob Clark | 4313c74 | 2016-02-03 14:02:04 -0500 | [diff] [blame] | 106 | MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 107 | module_param(vram, charp, 0); |
| 108 | |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 109 | /* |
| 110 | * Util/helpers: |
| 111 | */ |
| 112 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 113 | void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, |
| 114 | const char *dbgname) |
| 115 | { |
| 116 | struct resource *res; |
| 117 | unsigned long size; |
| 118 | void __iomem *ptr; |
| 119 | |
| 120 | if (name) |
| 121 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); |
| 122 | else |
| 123 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 124 | |
| 125 | if (!res) { |
| 126 | dev_err(&pdev->dev, "failed to get memory resource: %s\n", name); |
| 127 | return ERR_PTR(-EINVAL); |
| 128 | } |
| 129 | |
| 130 | size = resource_size(res); |
| 131 | |
| 132 | ptr = devm_ioremap_nocache(&pdev->dev, res->start, size); |
| 133 | if (!ptr) { |
| 134 | dev_err(&pdev->dev, "failed to ioremap: %s\n", name); |
| 135 | return ERR_PTR(-ENOMEM); |
| 136 | } |
| 137 | |
| 138 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 139 | printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 140 | |
| 141 | return ptr; |
| 142 | } |
| 143 | |
Lloyd Atkinson | 1a0c917 | 2016-10-04 10:01:24 -0400 | [diff] [blame] | 144 | void msm_iounmap(struct platform_device *pdev, void __iomem *addr) |
| 145 | { |
| 146 | devm_iounmap(&pdev->dev, addr); |
| 147 | } |
| 148 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 149 | void msm_writel(u32 data, void __iomem *addr) |
| 150 | { |
| 151 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 152 | printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 153 | writel(data, addr); |
| 154 | } |
| 155 | |
| 156 | u32 msm_readl(const void __iomem *addr) |
| 157 | { |
| 158 | u32 val = readl(addr); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 159 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 160 | if (reglog) |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 161 | printk(KERN_ERR "IO:R %p %08x\n", addr, val); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 162 | return val; |
| 163 | } |
| 164 | |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 165 | struct vblank_event { |
| 166 | struct list_head node; |
| 167 | int crtc_id; |
| 168 | bool enable; |
| 169 | }; |
| 170 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 171 | static void vblank_ctrl_worker(struct kthread_work *work) |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 172 | { |
| 173 | struct msm_vblank_ctrl *vbl_ctrl = container_of(work, |
| 174 | struct msm_vblank_ctrl, work); |
| 175 | struct msm_drm_private *priv = container_of(vbl_ctrl, |
| 176 | struct msm_drm_private, vblank_ctrl); |
| 177 | struct msm_kms *kms = priv->kms; |
| 178 | struct vblank_event *vbl_ev, *tmp; |
| 179 | unsigned long flags; |
| 180 | |
| 181 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 182 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { |
| 183 | list_del(&vbl_ev->node); |
| 184 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 185 | |
| 186 | if (vbl_ev->enable) |
| 187 | kms->funcs->enable_vblank(kms, |
| 188 | priv->crtcs[vbl_ev->crtc_id]); |
| 189 | else |
| 190 | kms->funcs->disable_vblank(kms, |
| 191 | priv->crtcs[vbl_ev->crtc_id]); |
| 192 | |
| 193 | kfree(vbl_ev); |
| 194 | |
| 195 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 196 | } |
| 197 | |
| 198 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 199 | } |
| 200 | |
| 201 | static int vblank_ctrl_queue_work(struct msm_drm_private *priv, |
| 202 | int crtc_id, bool enable) |
| 203 | { |
| 204 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
| 205 | struct vblank_event *vbl_ev; |
| 206 | unsigned long flags; |
| 207 | |
| 208 | vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC); |
| 209 | if (!vbl_ev) |
| 210 | return -ENOMEM; |
| 211 | |
| 212 | vbl_ev->crtc_id = crtc_id; |
| 213 | vbl_ev->enable = enable; |
| 214 | |
| 215 | spin_lock_irqsave(&vbl_ctrl->lock, flags); |
| 216 | list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list); |
| 217 | spin_unlock_irqrestore(&vbl_ctrl->lock, flags); |
| 218 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 219 | kthread_queue_work(&priv->disp_thread[crtc_id].worker, &vbl_ctrl->work); |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 220 | |
| 221 | return 0; |
| 222 | } |
| 223 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 224 | static int msm_drm_uninit(struct device *dev) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 225 | { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 226 | struct platform_device *pdev = to_platform_device(dev); |
| 227 | struct drm_device *ddev = platform_get_drvdata(pdev); |
| 228 | struct msm_drm_private *priv = ddev->dev_private; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 229 | struct msm_kms *kms = priv->kms; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 230 | struct msm_gpu *gpu = priv->gpu; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 231 | struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl; |
| 232 | struct vblank_event *vbl_ev, *tmp; |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 233 | int i; |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 234 | |
| 235 | /* We must cancel and cleanup any pending vblank enable/disable |
| 236 | * work before drm_irq_uninstall() to avoid work re-enabling an |
| 237 | * irq after uninstall has disabled it. |
| 238 | */ |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 239 | kthread_flush_work(&vbl_ctrl->work); |
Hai Li | 78b1d47 | 2015-07-27 13:49:45 -0400 | [diff] [blame] | 240 | list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) { |
| 241 | list_del(&vbl_ev->node); |
| 242 | kfree(vbl_ev); |
| 243 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 244 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 245 | /* clean up display commit worker threads */ |
| 246 | for (i = 0; i < priv->num_crtcs; i++) { |
| 247 | if (priv->disp_thread[i].thread) { |
| 248 | kthread_flush_worker(&priv->disp_thread[i].worker); |
| 249 | kthread_stop(priv->disp_thread[i].thread); |
| 250 | priv->disp_thread[i].thread = NULL; |
| 251 | } |
| 252 | } |
| 253 | |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 254 | msm_gem_shrinker_cleanup(ddev); |
| 255 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 256 | drm_kms_helper_poll_fini(ddev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 257 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 258 | drm_mode_config_cleanup(ddev); |
| 259 | drm_vblank_cleanup(ddev); |
| 260 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 261 | drm_dev_unregister(ddev); |
Archit Taneja | 8208ed9 | 2016-05-02 11:05:53 +0530 | [diff] [blame] | 262 | |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 263 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 264 | if (fbdev && priv->fbdev) |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 265 | msm_fbdev_free(ddev); |
Archit Taneja | 1aaa57f | 2016-02-25 11:19:45 +0530 | [diff] [blame] | 266 | #endif |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 267 | drm_mode_config_cleanup(ddev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 268 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 269 | pm_runtime_get_sync(dev); |
| 270 | drm_irq_uninstall(ddev); |
| 271 | pm_runtime_put_sync(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 272 | |
| 273 | flush_workqueue(priv->wq); |
| 274 | destroy_workqueue(priv->wq); |
| 275 | |
Archit Taneja | 1697608 | 2016-11-03 17:36:18 +0530 | [diff] [blame] | 276 | if (kms && kms->funcs) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 277 | kms->funcs->destroy(kms); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 278 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 279 | if (gpu) { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 280 | mutex_lock(&ddev->struct_mutex); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 281 | gpu->funcs->pm_suspend(gpu); |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 282 | mutex_unlock(&ddev->struct_mutex); |
Rob Clark | 774449e | 2015-05-15 09:19:36 -0400 | [diff] [blame] | 283 | gpu->funcs->destroy(gpu); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 284 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 285 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 286 | if (priv->vram.paddr) { |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 287 | unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 288 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 289 | drm_mm_takedown(&priv->vram.mm); |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 290 | dma_free_attrs(dev, priv->vram.size, NULL, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 291 | priv->vram.paddr, attrs); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 292 | } |
| 293 | |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 294 | sde_evtlog_destroy(); |
| 295 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 296 | sde_power_client_destroy(&priv->phandle, priv->pclient); |
| 297 | sde_power_resource_deinit(pdev, &priv->phandle); |
| 298 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 299 | component_unbind_all(dev, ddev); |
| 300 | |
| 301 | sde_power_client_destroy(&priv->phandle, priv->pclient); |
| 302 | |
| 303 | sde_power_resource_deinit(pdev, &priv->phandle); |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 304 | |
Archit Taneja | 0a6030d | 2016-05-08 21:36:28 +0530 | [diff] [blame] | 305 | msm_mdss_destroy(ddev); |
| 306 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 307 | ddev->dev_private = NULL; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 308 | kfree(priv); |
| 309 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 310 | drm_dev_unref(ddev); |
| 311 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 312 | return 0; |
| 313 | } |
| 314 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 315 | #define KMS_MDP4 4 |
| 316 | #define KMS_MDP5 5 |
| 317 | #define KMS_SDE 3 |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 318 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 319 | static int get_mdp_ver(struct platform_device *pdev) |
| 320 | { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 321 | #ifdef CONFIG_OF |
| 322 | static const struct of_device_id match_types[] = { { |
| 323 | .compatible = "qcom,mdss_mdp", |
| 324 | .data = (void *)KMS_MDP5, |
| 325 | }, |
| 326 | { |
| 327 | .compatible = "qcom,sde-kms", |
| 328 | .data = (void *)KMS_SDE, |
| 329 | /* end node */ |
| 330 | } }; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 331 | struct device *dev = &pdev->dev; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 332 | const struct of_device_id *match; |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 333 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 334 | match = of_match_node(match_types, dev->of_node); |
| 335 | if (match) |
| 336 | return (int)(unsigned long)match->data; |
| 337 | #endif |
| 338 | return KMS_MDP4; |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 339 | } |
| 340 | |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 341 | static int msm_init_vram(struct drm_device *dev) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 342 | { |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 343 | struct msm_drm_private *priv = dev->dev_private; |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 344 | struct device_node *node; |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 345 | unsigned long size = 0; |
| 346 | int ret = 0; |
| 347 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 348 | /* In the device-tree world, we could have a 'memory-region' |
| 349 | * phandle, which gives us a link to our "vram". Allocating |
| 350 | * is all nicely abstracted behind the dma api, but we need |
| 351 | * to know the entire size to allocate it all in one go. There |
| 352 | * are two cases: |
| 353 | * 1) device with no IOMMU, in which case we need exclusive |
| 354 | * access to a VRAM carveout big enough for all gpu |
| 355 | * buffers |
| 356 | * 2) device with IOMMU, but where the bootloader puts up |
| 357 | * a splash screen. In this case, the VRAM carveout |
| 358 | * need only be large enough for fbdev fb. But we need |
| 359 | * exclusive access to the buffer to avoid the kernel |
| 360 | * using those pages for other purposes (which appears |
| 361 | * as corruption on screen before we have a chance to |
| 362 | * load and do initial modeset) |
| 363 | */ |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 364 | |
| 365 | node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); |
| 366 | if (node) { |
| 367 | struct resource r; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 368 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 369 | ret = of_address_to_resource(node, 0, &r); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 370 | |
Peter Chen | 2ca41c17 | 2016-07-04 16:49:50 +0800 | [diff] [blame] | 371 | of_node_put(node); |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 372 | if (ret) |
| 373 | return ret; |
| 374 | size = r.end - r.start; |
Thierry Reding | fc99f97 | 2015-04-09 16:39:51 +0200 | [diff] [blame] | 375 | DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 376 | |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 377 | /* if we have no IOMMU, then we need to use carveout allocator. |
| 378 | * Grab the entire CMA chunk carved out in early startup in |
| 379 | * mach-msm: |
| 380 | */ |
| 381 | } else if (!iommu_present(&platform_bus_type)) { |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 382 | DRM_INFO("using %s VRAM carveout\n", vram); |
| 383 | size = memparse(vram, NULL); |
| 384 | } |
| 385 | |
| 386 | if (size) { |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 387 | unsigned long attrs = 0; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 388 | void *p; |
| 389 | |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 390 | priv->vram.size = size; |
| 391 | |
| 392 | drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); |
| 393 | |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 394 | attrs |= DMA_ATTR_NO_KERNEL_MAPPING; |
| 395 | attrs |= DMA_ATTR_WRITE_COMBINE; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 396 | |
| 397 | /* note that for no-kernel-mapping, the vaddr returned |
| 398 | * is bogus, but non-null if allocation succeeded: |
| 399 | */ |
| 400 | p = dma_alloc_attrs(dev->dev, size, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 401 | &priv->vram.paddr, GFP_KERNEL, attrs); |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 402 | if (!p) { |
| 403 | dev_err(dev->dev, "failed to allocate VRAM\n"); |
| 404 | priv->vram.paddr = 0; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 405 | return -ENOMEM; |
Rob Clark | 871d812 | 2013-11-16 12:56:06 -0500 | [diff] [blame] | 406 | } |
| 407 | |
| 408 | dev_info(dev->dev, "VRAM: %08x->%08x\n", |
| 409 | (uint32_t)priv->vram.paddr, |
| 410 | (uint32_t)(priv->vram.paddr + size)); |
| 411 | } |
| 412 | |
Rob Clark | 072f1f9 | 2015-03-03 15:04:25 -0500 | [diff] [blame] | 413 | return ret; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 414 | } |
| 415 | |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 416 | #ifdef CONFIG_OF |
| 417 | static int msm_component_bind_all(struct device *dev, |
| 418 | struct drm_device *drm_dev) |
| 419 | { |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 420 | int ret; |
| 421 | |
| 422 | ret = component_bind_all(dev, drm_dev); |
| 423 | if (ret) |
| 424 | DRM_ERROR("component_bind_all failed: %d\n", ret); |
| 425 | |
| 426 | return ret; |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 427 | } |
| 428 | #else |
| 429 | static int msm_component_bind_all(struct device *dev, |
| 430 | struct drm_device *drm_dev) |
| 431 | { |
| 432 | return 0; |
| 433 | } |
| 434 | #endif |
| 435 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 436 | static int msm_drm_init(struct device *dev, struct drm_driver *drv) |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 437 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 438 | struct platform_device *pdev = to_platform_device(dev); |
| 439 | struct drm_device *ddev; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 440 | struct msm_drm_private *priv; |
| 441 | struct msm_kms *kms; |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 442 | int ret, i; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 443 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 444 | ddev = drm_dev_alloc(drv, dev); |
| 445 | if (!ddev) { |
| 446 | dev_err(dev, "failed to allocate drm_device\n"); |
| 447 | return -ENOMEM; |
| 448 | } |
| 449 | |
| 450 | drm_mode_config_init(ddev); |
| 451 | platform_set_drvdata(pdev, ddev); |
| 452 | ddev->platformdev = pdev; |
| 453 | |
| 454 | ret = drm_dev_register(ddev, 0); |
| 455 | if (ret) |
| 456 | goto fail; |
| 457 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 458 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 459 | if (!priv) { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 460 | ret = -ENOMEM; |
| 461 | goto priv_alloc_fail; |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 462 | } |
| 463 | |
| 464 | ddev->dev_private = priv; |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 465 | priv->dev = ddev; |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 466 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 467 | ret = msm_mdss_init(ddev); |
| 468 | if (ret) |
| 469 | goto mdss_init_fail; |
| 470 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 471 | priv->wq = alloc_ordered_workqueue("msm_drm", 0); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 472 | init_waitqueue_head(&priv->pending_crtcs_event); |
| 473 | |
| 474 | INIT_LIST_HEAD(&priv->client_event_list); |
| 475 | INIT_LIST_HEAD(&priv->inactive_list); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 476 | INIT_LIST_HEAD(&priv->vblank_ctrl.event_list); |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 477 | kthread_init_work(&priv->vblank_ctrl.work, vblank_ctrl_worker); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 478 | spin_lock_init(&priv->vblank_ctrl.lock); |
| 479 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 480 | ret = sde_power_resource_init(pdev, &priv->phandle); |
| 481 | if (ret) { |
| 482 | pr_err("sde power resource init failed\n"); |
| 483 | goto fail; |
| 484 | } |
Rob Clark | 5bf9c0b | 2015-03-03 15:04:24 -0500 | [diff] [blame] | 485 | |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 486 | priv->pclient = sde_power_client_create(&priv->phandle, "sde"); |
| 487 | if (IS_ERR_OR_NULL(priv->pclient)) { |
| 488 | pr_err("sde power client create failed\n"); |
| 489 | ret = -EINVAL; |
| 490 | goto fail; |
| 491 | } |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 492 | |
| 493 | /* Bind all our sub-components: */ |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 494 | ret = msm_component_bind_all(dev, ddev); |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 495 | if (ret) |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 496 | return ret; |
| 497 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 498 | ret = msm_init_vram(ddev); |
Rob Clark | 13f1556 | 2015-05-07 15:20:13 -0400 | [diff] [blame] | 499 | if (ret) |
| 500 | goto fail; |
| 501 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 502 | ret = sde_evtlog_init(ddev->primary->debugfs_root); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 503 | if (ret) { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 504 | dev_err(dev, "failed to init evtlog: %d\n", ret); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 505 | goto fail; |
| 506 | } |
Rob Clark | 6820939 | 2016-05-17 16:19:32 -0400 | [diff] [blame] | 507 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 508 | switch (get_mdp_ver(pdev)) { |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 509 | case KMS_MDP4: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 510 | kms = mdp4_kms_init(ddev); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 511 | break; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 512 | case KMS_MDP5: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 513 | kms = mdp5_kms_init(ddev); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 514 | break; |
| 515 | case KMS_SDE: |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 516 | kms = sde_kms_init(ddev); |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 517 | break; |
| 518 | default: |
| 519 | kms = ERR_PTR(-ENODEV); |
| 520 | break; |
| 521 | } |
| 522 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 523 | if (IS_ERR(kms)) { |
| 524 | /* |
| 525 | * NOTE: once we have GPU support, having no kms should not |
| 526 | * be considered fatal.. ideally we would still support gpu |
| 527 | * and (for example) use dmabuf/prime to share buffers with |
| 528 | * imx drm driver on iMX5 |
| 529 | */ |
Lloyd Atkinson | 1e2497e | 2016-09-26 17:55:48 -0400 | [diff] [blame] | 530 | priv->kms = NULL; |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 531 | dev_err(dev, "failed to load kms\n"); |
Thomas Meyer | e4826a9 | 2013-09-16 23:19:54 +0200 | [diff] [blame] | 532 | ret = PTR_ERR(kms); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 533 | goto fail; |
| 534 | } |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 535 | priv->kms = kms; |
| 536 | pm_runtime_enable(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 537 | |
Alan Kwong | 2994628 | 2017-02-01 21:55:56 -0800 | [diff] [blame^] | 538 | if (kms) { |
| 539 | ret = kms->funcs->hw_init(kms); |
| 540 | if (ret) { |
| 541 | dev_err(dev, "kms hw init failed: %d\n", ret); |
| 542 | goto fail; |
| 543 | } |
| 544 | } |
| 545 | ddev->mode_config.funcs = &mode_config_funcs; |
| 546 | |
Sandeep Panda | f48c46a | 2016-10-24 09:48:50 +0530 | [diff] [blame] | 547 | for (i = 0; i < priv->num_crtcs; i++) { |
| 548 | priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id; |
| 549 | kthread_init_worker(&priv->disp_thread[i].worker); |
| 550 | priv->disp_thread[i].dev = ddev; |
| 551 | priv->disp_thread[i].thread = |
| 552 | kthread_run(kthread_worker_fn, |
| 553 | &priv->disp_thread[i].worker, |
| 554 | "crtc_commit:%d", |
| 555 | priv->disp_thread[i].crtc_id); |
| 556 | |
| 557 | if (IS_ERR(priv->disp_thread[i].thread)) { |
| 558 | dev_err(dev, "failed to create kthread\n"); |
| 559 | priv->disp_thread[i].thread = NULL; |
| 560 | /* clean up previously created threads if any */ |
| 561 | for (i -= 1; i >= 0; i--) { |
| 562 | kthread_stop(priv->disp_thread[i].thread); |
| 563 | priv->disp_thread[i].thread = NULL; |
| 564 | } |
| 565 | goto fail; |
| 566 | } |
| 567 | } |
| 568 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 569 | ret = drm_vblank_init(ddev, priv->num_crtcs); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 570 | if (ret < 0) { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 571 | dev_err(dev, "failed to initialize vblank\n"); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 572 | goto fail; |
| 573 | } |
| 574 | |
Archit Taneja | a2b3a55 | 2016-05-18 15:06:03 +0530 | [diff] [blame] | 575 | if (kms) { |
| 576 | pm_runtime_get_sync(dev); |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 577 | ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); |
Archit Taneja | a2b3a55 | 2016-05-18 15:06:03 +0530 | [diff] [blame] | 578 | pm_runtime_put_sync(dev); |
| 579 | if (ret < 0) { |
| 580 | dev_err(dev, "failed to install IRQ handler\n"); |
| 581 | goto fail; |
| 582 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 583 | } |
| 584 | |
Rob Clark | a7d3c95 | 2014-05-30 14:47:38 -0400 | [diff] [blame] | 585 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 586 | drm_mode_config_reset(ddev); |
| 587 | |
| 588 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
| 589 | if (fbdev) |
| 590 | priv->fbdev = msm_fbdev_init(ddev); |
| 591 | #endif |
| 592 | |
| 593 | ret = msm_debugfs_late_init(ddev); |
| 594 | if (ret) |
| 595 | goto fail; |
| 596 | |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 597 | /* perform subdriver post initialization */ |
| 598 | if (kms && kms->funcs && kms->funcs->postinit) { |
| 599 | ret = kms->funcs->postinit(kms); |
| 600 | if (ret) { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 601 | pr_err("kms post init failed: %d\n", ret); |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 602 | goto fail; |
| 603 | } |
| 604 | } |
| 605 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 606 | drm_kms_helper_poll_init(ddev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 607 | |
| 608 | return 0; |
| 609 | |
| 610 | fail: |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 611 | msm_drm_uninit(dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 612 | return ret; |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 613 | mdss_init_fail: |
| 614 | kfree(priv); |
| 615 | priv_alloc_fail: |
| 616 | drm_dev_unref(ddev); |
| 617 | return ret; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 618 | } |
| 619 | |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 620 | /* |
| 621 | * DRM operations: |
| 622 | */ |
| 623 | |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 624 | #ifdef CONFIG_QCOM_KGSL |
| 625 | static void load_gpu(struct drm_device *dev) |
| 626 | { |
| 627 | } |
| 628 | #else |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 629 | static void load_gpu(struct drm_device *dev) |
| 630 | { |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 631 | static DEFINE_MUTEX(init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 632 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 633 | |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 634 | mutex_lock(&init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 635 | |
Rob Clark | e2550b7 | 2014-09-05 13:30:27 -0400 | [diff] [blame] | 636 | if (!priv->gpu) |
| 637 | priv->gpu = adreno_load_gpu(dev); |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 638 | |
Rob Clark | a1ad352 | 2014-07-11 11:59:22 -0400 | [diff] [blame] | 639 | mutex_unlock(&init_lock); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 640 | } |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 641 | #endif |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 642 | |
| 643 | static int msm_open(struct drm_device *dev, struct drm_file *file) |
| 644 | { |
| 645 | struct msm_file_private *ctx; |
| 646 | |
| 647 | /* For now, load gpu on open.. to avoid the requirement of having |
| 648 | * firmware in the initrd. |
| 649 | */ |
| 650 | load_gpu(dev); |
| 651 | |
| 652 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
| 653 | if (!ctx) |
| 654 | return -ENOMEM; |
| 655 | |
| 656 | file->driver_priv = ctx; |
| 657 | |
Clarence Ip | 0e19a5d | 2016-08-10 16:36:50 -0400 | [diff] [blame] | 658 | if (dev && dev->dev_private) { |
| 659 | struct msm_drm_private *priv = dev->dev_private; |
| 660 | struct msm_kms *kms; |
| 661 | |
| 662 | kms = priv->kms; |
| 663 | if (kms && kms->funcs && kms->funcs->postopen) |
| 664 | kms->funcs->postopen(kms, file); |
| 665 | } |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 666 | return 0; |
| 667 | } |
| 668 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 669 | static void msm_preclose(struct drm_device *dev, struct drm_file *file) |
| 670 | { |
| 671 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 672 | struct msm_kms *kms = priv->kms; |
| 673 | |
| 674 | if (kms && kms->funcs && kms->funcs->preclose) |
| 675 | kms->funcs->preclose(kms, file); |
| 676 | } |
| 677 | |
| 678 | static void msm_postclose(struct drm_device *dev, struct drm_file *file) |
| 679 | { |
| 680 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 681 | struct msm_file_private *ctx = file->driver_priv; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 682 | struct msm_kms *kms = priv->kms; |
| 683 | |
| 684 | if (kms && kms->funcs && kms->funcs->postclose) |
| 685 | kms->funcs->postclose(kms, file); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 686 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 687 | mutex_lock(&dev->struct_mutex); |
| 688 | if (ctx == priv->lastctx) |
| 689 | priv->lastctx = NULL; |
| 690 | mutex_unlock(&dev->struct_mutex); |
| 691 | |
| 692 | kfree(ctx); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 693 | } |
| 694 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 695 | static int msm_disable_all_modes_commit( |
| 696 | struct drm_device *dev, |
| 697 | struct drm_atomic_state *state) |
| 698 | { |
| 699 | struct drm_plane *plane; |
| 700 | struct drm_crtc *crtc; |
| 701 | unsigned int plane_mask; |
| 702 | int ret; |
| 703 | |
| 704 | plane_mask = 0; |
| 705 | drm_for_each_plane(plane, dev) { |
| 706 | struct drm_plane_state *plane_state; |
| 707 | |
| 708 | plane_state = drm_atomic_get_plane_state(state, plane); |
| 709 | if (IS_ERR(plane_state)) { |
| 710 | ret = PTR_ERR(plane_state); |
| 711 | goto fail; |
| 712 | } |
| 713 | |
| 714 | plane_state->rotation = BIT(DRM_ROTATE_0); |
| 715 | |
| 716 | plane->old_fb = plane->fb; |
| 717 | plane_mask |= 1 << drm_plane_index(plane); |
| 718 | |
| 719 | /* disable non-primary: */ |
| 720 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) |
| 721 | continue; |
| 722 | |
| 723 | DRM_DEBUG("disabling plane %d\n", plane->base.id); |
| 724 | |
| 725 | ret = __drm_atomic_helper_disable_plane(plane, plane_state); |
| 726 | if (ret != 0) |
| 727 | DRM_ERROR("error %d disabling plane %d\n", ret, |
| 728 | plane->base.id); |
| 729 | } |
| 730 | |
| 731 | drm_for_each_crtc(crtc, dev) { |
| 732 | struct drm_mode_set mode_set; |
| 733 | |
| 734 | memset(&mode_set, 0, sizeof(struct drm_mode_set)); |
| 735 | mode_set.crtc = crtc; |
| 736 | |
| 737 | DRM_DEBUG("disabling crtc %d\n", crtc->base.id); |
| 738 | |
| 739 | ret = __drm_atomic_helper_set_config(&mode_set, state); |
| 740 | if (ret != 0) |
| 741 | DRM_ERROR("error %d disabling crtc %d\n", ret, |
| 742 | crtc->base.id); |
| 743 | } |
| 744 | |
| 745 | DRM_DEBUG("committing disables\n"); |
| 746 | ret = drm_atomic_commit(state); |
| 747 | |
| 748 | fail: |
| 749 | drm_atomic_clean_old_fb(dev, plane_mask, ret); |
| 750 | DRM_DEBUG("disables result %d\n", ret); |
| 751 | return ret; |
| 752 | } |
| 753 | |
| 754 | /** |
| 755 | * msm_clear_all_modes - disables all planes and crtcs via an atomic commit |
| 756 | * based on restore_fbdev_mode_atomic in drm_fb_helper.c |
| 757 | * @dev: device pointer |
| 758 | * @Return: 0 on success, otherwise -error |
| 759 | */ |
| 760 | static int msm_disable_all_modes(struct drm_device *dev) |
| 761 | { |
| 762 | struct drm_atomic_state *state; |
| 763 | int ret, i; |
| 764 | |
| 765 | state = drm_atomic_state_alloc(dev); |
| 766 | if (!state) |
| 767 | return -ENOMEM; |
| 768 | |
| 769 | state->acquire_ctx = dev->mode_config.acquire_ctx; |
| 770 | |
| 771 | for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) { |
| 772 | ret = msm_disable_all_modes_commit(dev, state); |
| 773 | if (ret != -EDEADLK) |
| 774 | break; |
| 775 | drm_atomic_state_clear(state); |
| 776 | drm_atomic_legacy_backoff(state); |
| 777 | } |
| 778 | |
| 779 | /* on successful atomic commit state ownership transfers to framework */ |
| 780 | if (ret != 0) |
| 781 | drm_atomic_state_free(state); |
| 782 | |
| 783 | return ret; |
| 784 | } |
| 785 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 786 | static void msm_lastclose(struct drm_device *dev) |
| 787 | { |
| 788 | struct msm_drm_private *priv = dev->dev_private; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 789 | struct msm_kms *kms = priv->kms; |
Alan Kwong | 5a3ac75 | 2016-10-16 01:02:35 -0400 | [diff] [blame] | 790 | int i; |
| 791 | |
| 792 | /* |
| 793 | * clean up vblank disable immediately as this is the last close. |
| 794 | */ |
| 795 | for (i = 0; i < dev->num_crtcs; i++) { |
| 796 | struct drm_vblank_crtc *vblank = &dev->vblank[i]; |
| 797 | struct timer_list *disable_timer = &vblank->disable_timer; |
| 798 | |
| 799 | if (del_timer_sync(disable_timer)) |
| 800 | disable_timer->function(disable_timer->data); |
| 801 | } |
| 802 | |
| 803 | /* wait for pending vblank requests to be executed by worker thread */ |
| 804 | flush_workqueue(priv->wq); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 805 | |
| 806 | if (priv->fbdev) { |
Rob Clark | 5ea1f75 | 2014-05-30 12:29:48 -0400 | [diff] [blame] | 807 | drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 808 | } else { |
| 809 | drm_modeset_lock_all(dev); |
| 810 | msm_disable_all_modes(dev); |
| 811 | drm_modeset_unlock_all(dev); |
| 812 | if (kms && kms->funcs && kms->funcs->lastclose) |
| 813 | kms->funcs->lastclose(kms); |
| 814 | } |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 815 | } |
| 816 | |
Daniel Vetter | e9f0d76 | 2013-12-11 11:34:42 +0100 | [diff] [blame] | 817 | static irqreturn_t msm_irq(int irq, void *arg) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 818 | { |
| 819 | struct drm_device *dev = arg; |
| 820 | struct msm_drm_private *priv = dev->dev_private; |
| 821 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 822 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 823 | BUG_ON(!kms); |
| 824 | return kms->funcs->irq(kms); |
| 825 | } |
| 826 | |
| 827 | static void msm_irq_preinstall(struct drm_device *dev) |
| 828 | { |
| 829 | struct msm_drm_private *priv = dev->dev_private; |
| 830 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 831 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 832 | BUG_ON(!kms); |
| 833 | kms->funcs->irq_preinstall(kms); |
| 834 | } |
| 835 | |
| 836 | static int msm_irq_postinstall(struct drm_device *dev) |
| 837 | { |
| 838 | struct msm_drm_private *priv = dev->dev_private; |
| 839 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 840 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 841 | BUG_ON(!kms); |
| 842 | return kms->funcs->irq_postinstall(kms); |
| 843 | } |
| 844 | |
| 845 | static void msm_irq_uninstall(struct drm_device *dev) |
| 846 | { |
| 847 | struct msm_drm_private *priv = dev->dev_private; |
| 848 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 849 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 850 | BUG_ON(!kms); |
| 851 | kms->funcs->irq_uninstall(kms); |
| 852 | } |
| 853 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 854 | static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 855 | { |
| 856 | struct msm_drm_private *priv = dev->dev_private; |
| 857 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 858 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 859 | if (!kms) |
| 860 | return -ENXIO; |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 861 | DBG("dev=%p, crtc=%u", dev, pipe); |
| 862 | return vblank_ctrl_queue_work(priv, pipe, true); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 863 | } |
| 864 | |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 865 | static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 866 | { |
| 867 | struct msm_drm_private *priv = dev->dev_private; |
| 868 | struct msm_kms *kms = priv->kms; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 869 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 870 | if (!kms) |
| 871 | return; |
Thierry Reding | 88e7271 | 2015-09-24 18:35:31 +0200 | [diff] [blame] | 872 | DBG("dev=%p, crtc=%u", dev, pipe); |
| 873 | vblank_ctrl_queue_work(priv, pipe, false); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 874 | } |
| 875 | |
| 876 | /* |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 877 | * DRM ioctls: |
| 878 | */ |
| 879 | |
| 880 | static int msm_ioctl_get_param(struct drm_device *dev, void *data, |
| 881 | struct drm_file *file) |
| 882 | { |
| 883 | struct msm_drm_private *priv = dev->dev_private; |
| 884 | struct drm_msm_param *args = data; |
| 885 | struct msm_gpu *gpu; |
| 886 | |
| 887 | /* for now, we just have 3d pipe.. eventually this would need to |
| 888 | * be more clever to dispatch to appropriate gpu module: |
| 889 | */ |
| 890 | if (args->pipe != MSM_PIPE_3D0) |
| 891 | return -EINVAL; |
| 892 | |
| 893 | gpu = priv->gpu; |
| 894 | |
| 895 | if (!gpu) |
| 896 | return -ENXIO; |
| 897 | |
| 898 | return gpu->funcs->get_param(gpu, args->param, &args->value); |
| 899 | } |
| 900 | |
| 901 | static int msm_ioctl_gem_new(struct drm_device *dev, void *data, |
| 902 | struct drm_file *file) |
| 903 | { |
| 904 | struct drm_msm_gem_new *args = data; |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 905 | |
| 906 | if (args->flags & ~MSM_BO_FLAGS) { |
| 907 | DRM_ERROR("invalid flags: %08x\n", args->flags); |
| 908 | return -EINVAL; |
| 909 | } |
| 910 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 911 | return msm_gem_new_handle(dev, file, args->size, |
| 912 | args->flags, &args->handle); |
| 913 | } |
| 914 | |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 915 | static inline ktime_t to_ktime(struct drm_msm_timespec timeout) |
| 916 | { |
| 917 | return ktime_set(timeout.tv_sec, timeout.tv_nsec); |
| 918 | } |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 919 | |
| 920 | static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, |
| 921 | struct drm_file *file) |
| 922 | { |
| 923 | struct drm_msm_gem_cpu_prep *args = data; |
| 924 | struct drm_gem_object *obj; |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 925 | ktime_t timeout = to_ktime(args->timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 926 | int ret; |
| 927 | |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 928 | if (args->op & ~MSM_PREP_FLAGS) { |
| 929 | DRM_ERROR("invalid op: %08x\n", args->op); |
| 930 | return -EINVAL; |
| 931 | } |
| 932 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 933 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 934 | if (!obj) |
| 935 | return -ENOENT; |
| 936 | |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 937 | ret = msm_gem_cpu_prep(obj, args->op, &timeout); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 938 | |
| 939 | drm_gem_object_unreference_unlocked(obj); |
| 940 | |
| 941 | return ret; |
| 942 | } |
| 943 | |
| 944 | static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, |
| 945 | struct drm_file *file) |
| 946 | { |
| 947 | struct drm_msm_gem_cpu_fini *args = data; |
| 948 | struct drm_gem_object *obj; |
| 949 | int ret; |
| 950 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 951 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 952 | if (!obj) |
| 953 | return -ENOENT; |
| 954 | |
| 955 | ret = msm_gem_cpu_fini(obj); |
| 956 | |
| 957 | drm_gem_object_unreference_unlocked(obj); |
| 958 | |
| 959 | return ret; |
| 960 | } |
| 961 | |
| 962 | static int msm_ioctl_gem_info(struct drm_device *dev, void *data, |
| 963 | struct drm_file *file) |
| 964 | { |
| 965 | struct drm_msm_gem_info *args = data; |
| 966 | struct drm_gem_object *obj; |
| 967 | int ret = 0; |
| 968 | |
| 969 | if (args->pad) |
| 970 | return -EINVAL; |
| 971 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 972 | obj = drm_gem_object_lookup(file, args->handle); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 973 | if (!obj) |
| 974 | return -ENOENT; |
| 975 | |
| 976 | args->offset = msm_gem_mmap_offset(obj); |
| 977 | |
| 978 | drm_gem_object_unreference_unlocked(obj); |
| 979 | |
| 980 | return ret; |
| 981 | } |
| 982 | |
| 983 | static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, |
| 984 | struct drm_file *file) |
| 985 | { |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 986 | struct msm_drm_private *priv = dev->dev_private; |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 987 | struct drm_msm_wait_fence *args = data; |
Rob Clark | 56c2da8 | 2015-05-11 11:50:03 -0400 | [diff] [blame] | 988 | ktime_t timeout = to_ktime(args->timeout); |
Rob Clark | 93ddb0d | 2014-03-03 09:42:33 -0500 | [diff] [blame] | 989 | |
| 990 | if (args->pad) { |
| 991 | DRM_ERROR("invalid pad: %08x\n", args->pad); |
| 992 | return -EINVAL; |
| 993 | } |
| 994 | |
Rob Clark | ca762a8 | 2016-03-15 17:22:13 -0400 | [diff] [blame] | 995 | if (!priv->gpu) |
| 996 | return 0; |
| 997 | |
| 998 | return msm_wait_fence(priv->gpu->fctx, args->fence, &timeout, true); |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 999 | } |
| 1000 | |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 1001 | static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, |
| 1002 | struct drm_file *file) |
| 1003 | { |
| 1004 | struct drm_msm_gem_madvise *args = data; |
| 1005 | struct drm_gem_object *obj; |
| 1006 | int ret; |
| 1007 | |
| 1008 | switch (args->madv) { |
| 1009 | case MSM_MADV_DONTNEED: |
| 1010 | case MSM_MADV_WILLNEED: |
| 1011 | break; |
| 1012 | default: |
| 1013 | return -EINVAL; |
| 1014 | } |
| 1015 | |
| 1016 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1017 | if (ret) |
| 1018 | return ret; |
| 1019 | |
| 1020 | obj = drm_gem_object_lookup(file, args->handle); |
| 1021 | if (!obj) { |
| 1022 | ret = -ENOENT; |
| 1023 | goto unlock; |
| 1024 | } |
| 1025 | |
| 1026 | ret = msm_gem_madvise(obj, args->madv); |
| 1027 | if (ret >= 0) { |
| 1028 | args->retained = ret; |
| 1029 | ret = 0; |
| 1030 | } |
| 1031 | |
| 1032 | drm_gem_object_unreference(obj); |
| 1033 | |
| 1034 | unlock: |
| 1035 | mutex_unlock(&dev->struct_mutex); |
| 1036 | return ret; |
| 1037 | } |
| 1038 | |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1039 | static const struct drm_ioctl_desc msm_ioctls[] = { |
Daniel Vetter | f8c4714 | 2015-09-08 13:56:30 +0200 | [diff] [blame] | 1040 | DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1041 | DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1042 | DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1043 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1044 | DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1045 | DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), |
| 1046 | DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), |
Rob Clark | 4cd33c4 | 2016-05-17 15:44:49 -0400 | [diff] [blame] | 1047 | DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW), |
Alan Kwong | bb27c09 | 2016-07-20 16:41:25 -0400 | [diff] [blame] | 1048 | DRM_IOCTL_DEF_DRV(SDE_WB_CONFIG, sde_wb_config, DRM_UNLOCKED|DRM_AUTH), |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1049 | }; |
| 1050 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1051 | static const struct vm_operations_struct vm_ops = { |
| 1052 | .fault = msm_gem_fault, |
| 1053 | .open = drm_gem_vm_open, |
| 1054 | .close = drm_gem_vm_close, |
| 1055 | }; |
| 1056 | |
| 1057 | static const struct file_operations fops = { |
| 1058 | .owner = THIS_MODULE, |
| 1059 | .open = drm_open, |
| 1060 | .release = drm_release, |
| 1061 | .unlocked_ioctl = drm_ioctl, |
| 1062 | #ifdef CONFIG_COMPAT |
| 1063 | .compat_ioctl = drm_compat_ioctl, |
| 1064 | #endif |
| 1065 | .poll = drm_poll, |
| 1066 | .read = drm_read, |
| 1067 | .llseek = no_llseek, |
| 1068 | .mmap = msm_gem_mmap, |
| 1069 | }; |
| 1070 | |
| 1071 | static struct drm_driver msm_driver = { |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1072 | .driver_features = DRIVER_HAVE_IRQ | |
| 1073 | DRIVER_GEM | |
| 1074 | DRIVER_PRIME | |
Rob Clark | b4b15c8 | 2013-09-28 12:01:25 -0400 | [diff] [blame] | 1075 | DRIVER_RENDER | |
Rob Clark | a5436e1 | 2015-06-04 10:12:22 -0400 | [diff] [blame] | 1076 | DRIVER_ATOMIC | |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1077 | DRIVER_MODESET, |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1078 | .open = msm_open, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1079 | .preclose = msm_preclose, |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 1080 | .postclose = msm_postclose, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1081 | .lastclose = msm_lastclose, |
| 1082 | .irq_handler = msm_irq, |
| 1083 | .irq_preinstall = msm_irq_preinstall, |
| 1084 | .irq_postinstall = msm_irq_postinstall, |
| 1085 | .irq_uninstall = msm_irq_uninstall, |
Ville Syrjälä | b44f840 | 2015-09-30 16:46:48 +0300 | [diff] [blame] | 1086 | .get_vblank_counter = drm_vblank_no_hw_counter, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1087 | .enable_vblank = msm_enable_vblank, |
| 1088 | .disable_vblank = msm_disable_vblank, |
| 1089 | .gem_free_object = msm_gem_free_object, |
| 1090 | .gem_vm_ops = &vm_ops, |
| 1091 | .dumb_create = msm_gem_dumb_create, |
| 1092 | .dumb_map_offset = msm_gem_dumb_map_offset, |
Rob Clark | 30600a909 | 2013-09-28 10:13:04 -0400 | [diff] [blame] | 1093 | .dumb_destroy = drm_gem_dumb_destroy, |
Rob Clark | 05b8491 | 2013-09-28 11:28:35 -0400 | [diff] [blame] | 1094 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1095 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1096 | .gem_prime_export = drm_gem_prime_export, |
| 1097 | .gem_prime_import = drm_gem_prime_import, |
| 1098 | .gem_prime_pin = msm_gem_prime_pin, |
| 1099 | .gem_prime_unpin = msm_gem_prime_unpin, |
| 1100 | .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, |
| 1101 | .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, |
| 1102 | .gem_prime_vmap = msm_gem_prime_vmap, |
| 1103 | .gem_prime_vunmap = msm_gem_prime_vunmap, |
Daniel Thompson | 77a147e | 2014-11-12 11:38:14 +0000 | [diff] [blame] | 1104 | .gem_prime_mmap = msm_gem_prime_mmap, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1105 | #ifdef CONFIG_DEBUG_FS |
| 1106 | .debugfs_init = msm_debugfs_init, |
| 1107 | .debugfs_cleanup = msm_debugfs_cleanup, |
| 1108 | #endif |
Rob Clark | 7198e6b | 2013-07-19 12:59:32 -0400 | [diff] [blame] | 1109 | .ioctls = msm_ioctls, |
| 1110 | .num_ioctls = DRM_MSM_NUM_IOCTLS, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1111 | .fops = &fops, |
Stephane Viau | aa6ed8b | 2016-07-19 12:59:42 -0400 | [diff] [blame] | 1112 | .name = "msm_drm", |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1113 | .desc = "MSM Snapdragon DRM", |
| 1114 | .date = "20130625", |
Rob Clark | a8d854c | 2016-06-01 14:02:02 -0400 | [diff] [blame] | 1115 | .major = MSM_VERSION_MAJOR, |
| 1116 | .minor = MSM_VERSION_MINOR, |
| 1117 | .patchlevel = MSM_VERSION_PATCHLEVEL, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1118 | }; |
| 1119 | |
| 1120 | #ifdef CONFIG_PM_SLEEP |
| 1121 | static int msm_pm_suspend(struct device *dev) |
| 1122 | { |
| 1123 | struct drm_device *ddev = dev_get_drvdata(dev); |
| 1124 | |
| 1125 | drm_kms_helper_poll_disable(ddev); |
| 1126 | |
| 1127 | return 0; |
| 1128 | } |
| 1129 | |
| 1130 | static int msm_pm_resume(struct device *dev) |
| 1131 | { |
| 1132 | struct drm_device *ddev = dev_get_drvdata(dev); |
| 1133 | |
| 1134 | drm_kms_helper_poll_enable(ddev); |
| 1135 | |
| 1136 | return 0; |
| 1137 | } |
| 1138 | #endif |
| 1139 | |
| 1140 | static const struct dev_pm_ops msm_pm_ops = { |
| 1141 | SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) |
| 1142 | }; |
| 1143 | |
| 1144 | /* |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 1145 | * Componentized driver support: |
| 1146 | */ |
| 1147 | |
Archit Taneja | e9fbdaf | 2015-11-18 12:15:14 +0530 | [diff] [blame] | 1148 | /* |
| 1149 | * NOTE: duplication of the same code as exynos or imx (or probably any other). |
| 1150 | * so probably some room for some helpers |
Rob Clark | 060530f | 2014-03-03 14:19:12 -0500 | [diff] [blame] | 1151 | */ |
| 1152 | static int compare_of(struct device *dev, void *data) |
| 1153 | { |
| 1154 | return dev->of_node == data; |
| 1155 | } |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 1156 | |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1157 | /* |
| 1158 | * Identify what components need to be added by parsing what remote-endpoints |
| 1159 | * our MDP output ports are connected to. In the case of LVDS on MDP4, there |
| 1160 | * is no external component that we need to add since LVDS is within MDP4 |
| 1161 | * itself. |
| 1162 | */ |
| 1163 | static int add_components_mdp(struct device *mdp_dev, |
| 1164 | struct component_match **matchptr) |
| 1165 | { |
| 1166 | struct device_node *np = mdp_dev->of_node; |
| 1167 | struct device_node *ep_node; |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1168 | struct device *master_dev; |
| 1169 | |
| 1170 | /* |
| 1171 | * on MDP4 based platforms, the MDP platform device is the component |
| 1172 | * master that adds other display interface components to itself. |
| 1173 | * |
| 1174 | * on MDP5 based platforms, the MDSS platform device is the component |
| 1175 | * master that adds MDP5 and other display interface components to |
| 1176 | * itself. |
| 1177 | */ |
| 1178 | if (of_device_is_compatible(np, "qcom,mdp4")) |
| 1179 | master_dev = mdp_dev; |
| 1180 | else |
| 1181 | master_dev = mdp_dev->parent; |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1182 | |
| 1183 | for_each_endpoint_of_node(np, ep_node) { |
| 1184 | struct device_node *intf; |
| 1185 | struct of_endpoint ep; |
| 1186 | int ret; |
| 1187 | |
| 1188 | ret = of_graph_parse_endpoint(ep_node, &ep); |
| 1189 | if (ret) { |
| 1190 | dev_err(mdp_dev, "unable to parse port endpoint\n"); |
| 1191 | of_node_put(ep_node); |
| 1192 | return ret; |
| 1193 | } |
| 1194 | |
| 1195 | /* |
| 1196 | * The LCDC/LVDS port on MDP4 is a speacial case where the |
| 1197 | * remote-endpoint isn't a component that we need to add |
| 1198 | */ |
| 1199 | if (of_device_is_compatible(np, "qcom,mdp4") && |
| 1200 | ep.port == 0) { |
| 1201 | of_node_put(ep_node); |
| 1202 | continue; |
| 1203 | } |
| 1204 | |
| 1205 | /* |
| 1206 | * It's okay if some of the ports don't have a remote endpoint |
| 1207 | * specified. It just means that the port isn't connected to |
| 1208 | * any external interface. |
| 1209 | */ |
| 1210 | intf = of_graph_get_remote_port_parent(ep_node); |
| 1211 | if (!intf) { |
| 1212 | of_node_put(ep_node); |
| 1213 | continue; |
| 1214 | } |
| 1215 | |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1216 | component_match_add(master_dev, matchptr, compare_of, intf); |
Archit Taneja | 812070e | 2016-05-19 10:38:39 +0530 | [diff] [blame] | 1217 | |
| 1218 | of_node_put(intf); |
| 1219 | of_node_put(ep_node); |
| 1220 | } |
| 1221 | |
| 1222 | return 0; |
| 1223 | } |
| 1224 | |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1225 | static int compare_name_mdp(struct device *dev, void *data) |
| 1226 | { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1227 | return (strnstr(dev_name(dev), "mdp", strlen("mdp")) != NULL); |
| 1228 | } |
| 1229 | |
| 1230 | static int add_display_components(struct device *dev, |
| 1231 | struct component_match **matchptr) |
| 1232 | { |
| 1233 | struct device *mdp_dev = NULL; |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1234 | int ret; |
| 1235 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1236 | if (of_device_is_compatible(dev->of_node, "qcom,sde-kms")) { |
| 1237 | struct device_node *np = dev->of_node; |
| 1238 | unsigned int i; |
| 1239 | |
| 1240 | for (i = 0; ; i++) { |
| 1241 | struct device_node *node; |
| 1242 | |
| 1243 | node = of_parse_phandle(np, "connectors", i); |
| 1244 | if (!node) |
| 1245 | break; |
| 1246 | |
| 1247 | component_match_add(dev, matchptr, compare_of, node); |
| 1248 | } |
| 1249 | return 0; |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * MDP5 based devices don't have a flat hierarchy. There is a top level |
| 1254 | * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the |
| 1255 | * children devices, find the MDP5 node, and then add the interfaces |
| 1256 | * to our components list. |
| 1257 | */ |
| 1258 | if (of_device_is_compatible(dev->of_node, "qcom,mdss")) { |
| 1259 | ret = of_platform_populate(dev->of_node, NULL, NULL, dev); |
| 1260 | if (ret) { |
| 1261 | dev_err(dev, "failed to populate children devices\n"); |
| 1262 | return ret; |
| 1263 | } |
| 1264 | |
| 1265 | mdp_dev = device_find_child(dev, NULL, compare_name_mdp); |
| 1266 | if (!mdp_dev) { |
| 1267 | dev_err(dev, "failed to find MDSS MDP node\n"); |
| 1268 | of_platform_depopulate(dev); |
| 1269 | return -ENODEV; |
| 1270 | } |
| 1271 | |
| 1272 | put_device(mdp_dev); |
| 1273 | |
| 1274 | /* add the MDP component itself */ |
| 1275 | component_match_add(dev, matchptr, compare_of, |
| 1276 | mdp_dev->of_node); |
| 1277 | } else { |
| 1278 | /* MDP4 */ |
| 1279 | mdp_dev = dev; |
| 1280 | } |
| 1281 | |
| 1282 | ret = add_components_mdp(mdp_dev, matchptr); |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1283 | if (ret) |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1284 | of_platform_depopulate(dev); |
Archit Taneja | 54011e2 | 2016-06-06 13:45:34 +0530 | [diff] [blame] | 1285 | |
| 1286 | return ret; |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1287 | } |
| 1288 | |
Archit Taneja | dc3ea26 | 2016-05-19 13:33:52 +0530 | [diff] [blame] | 1289 | /* |
| 1290 | * We don't know what's the best binding to link the gpu with the drm device. |
| 1291 | * Fow now, we just hunt for all the possible gpus that we support, and add them |
| 1292 | * as components. |
| 1293 | */ |
| 1294 | static const struct of_device_id msm_gpu_match[] = { |
| 1295 | { .compatible = "qcom,adreno-3xx" }, |
| 1296 | { .compatible = "qcom,kgsl-3d0" }, |
| 1297 | { }, |
| 1298 | }; |
| 1299 | |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1300 | static int add_gpu_components(struct device *dev, |
| 1301 | struct component_match **matchptr) |
| 1302 | { |
Archit Taneja | dc3ea26 | 2016-05-19 13:33:52 +0530 | [diff] [blame] | 1303 | struct device_node *np; |
| 1304 | |
| 1305 | np = of_find_matching_node(NULL, msm_gpu_match); |
| 1306 | if (!np) |
| 1307 | return 0; |
| 1308 | |
| 1309 | component_match_add(dev, matchptr, compare_of, np); |
| 1310 | |
| 1311 | of_node_put(np); |
| 1312 | |
| 1313 | return 0; |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1314 | } |
| 1315 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1316 | static int msm_drm_bind(struct device *dev) |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1317 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 1318 | return msm_drm_init(dev, &msm_driver); |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1319 | } |
| 1320 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1321 | static void msm_drm_unbind(struct device *dev) |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1322 | { |
Archit Taneja | 2b66987 | 2016-05-02 11:05:54 +0530 | [diff] [blame] | 1323 | msm_drm_uninit(dev); |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1324 | } |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1325 | |
| 1326 | static const struct component_master_ops msm_drm_ops = { |
| 1327 | .bind = msm_drm_bind, |
| 1328 | .unbind = msm_drm_unbind, |
| 1329 | }; |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1330 | |
| 1331 | /* |
| 1332 | * Platform driver: |
| 1333 | */ |
| 1334 | |
| 1335 | static int msm_pdev_probe(struct platform_device *pdev) |
| 1336 | { |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 1337 | int ret; |
Russell King | 8444828 | 2014-04-19 11:20:42 +0100 | [diff] [blame] | 1338 | struct component_match *match = NULL; |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 1339 | |
Archit Taneja | 7d526fc | 2016-05-19 10:33:57 +0530 | [diff] [blame] | 1340 | ret = add_display_components(&pdev->dev, &match); |
| 1341 | if (ret) |
| 1342 | return ret; |
| 1343 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1344 | ret = add_gpu_components(&pdev->dev, &match); |
| 1345 | if (ret) |
| 1346 | return ret; |
Dhaval Patel | 3949f03 | 2016-06-20 16:24:33 -0700 | [diff] [blame] | 1347 | |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1348 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); |
| 1349 | return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1350 | } |
| 1351 | |
| 1352 | static int msm_pdev_remove(struct platform_device *pdev) |
| 1353 | { |
Lloyd Atkinson | 6f74f40 | 2016-10-04 10:07:36 -0400 | [diff] [blame] | 1354 | component_master_del(&pdev->dev, &msm_drm_ops); |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1355 | of_platform_depopulate(&pdev->dev); |
| 1356 | |
| 1357 | msm_drm_unbind(&pdev->dev); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1358 | return 0; |
| 1359 | } |
| 1360 | |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1361 | static const struct of_device_id dt_match[] = { |
Dhaval Patel | 5200c60 | 2017-01-17 15:53:37 -0800 | [diff] [blame] | 1362 | { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */ |
| 1363 | { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */ |
| 1364 | { .compatible = "qcom,sde-kms", .data = (void *)3 }, /* sde */ |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1365 | {} |
| 1366 | }; |
| 1367 | MODULE_DEVICE_TABLE(of, dt_match); |
| 1368 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1369 | static struct platform_driver msm_platform_driver = { |
| 1370 | .probe = msm_pdev_probe, |
| 1371 | .remove = msm_pdev_remove, |
| 1372 | .driver = { |
Stephane Viau | aa6ed8b | 2016-07-19 12:59:42 -0400 | [diff] [blame] | 1373 | .name = "msm_drm", |
Rob Clark | 06c0dd9 | 2013-11-30 17:51:47 -0500 | [diff] [blame] | 1374 | .of_match_table = dt_match, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1375 | .pm = &msm_pm_ops, |
| 1376 | }, |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1377 | }; |
| 1378 | |
Stephane Viau | 32f13f6 | 2015-04-29 15:57:29 -0400 | [diff] [blame] | 1379 | #ifdef CONFIG_QCOM_KGSL |
| 1380 | void __init adreno_register(void) |
| 1381 | { |
| 1382 | } |
| 1383 | |
| 1384 | void __exit adreno_unregister(void) |
| 1385 | { |
| 1386 | } |
| 1387 | #endif |
| 1388 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1389 | static int __init msm_drm_register(void) |
| 1390 | { |
| 1391 | DBG("init"); |
Hai Li | d5af49c | 2015-03-26 19:25:17 -0400 | [diff] [blame] | 1392 | msm_dsi_register(); |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 1393 | msm_edp_register(); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 1394 | msm_hdmi_register(); |
Rob Clark | bfd28b1 | 2014-09-05 13:06:37 -0400 | [diff] [blame] | 1395 | adreno_register(); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1396 | return platform_driver_register(&msm_platform_driver); |
| 1397 | } |
| 1398 | |
| 1399 | static void __exit msm_drm_unregister(void) |
| 1400 | { |
| 1401 | DBG("fini"); |
| 1402 | platform_driver_unregister(&msm_platform_driver); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 1403 | msm_hdmi_unregister(); |
Rob Clark | bfd28b1 | 2014-09-05 13:06:37 -0400 | [diff] [blame] | 1404 | adreno_unregister(); |
Hai Li | 0045398 | 2014-12-12 14:41:17 -0500 | [diff] [blame] | 1405 | msm_edp_unregister(); |
Hai Li | d5af49c | 2015-03-26 19:25:17 -0400 | [diff] [blame] | 1406 | msm_dsi_unregister(); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1407 | } |
| 1408 | |
| 1409 | module_init(msm_drm_register); |
| 1410 | module_exit(msm_drm_unregister); |
| 1411 | |
| 1412 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); |
| 1413 | MODULE_DESCRIPTION("MSM DRM Driver"); |
| 1414 | MODULE_LICENSE("GPL"); |