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gerrit-public.fairphone.software / kernel / msm-4.9 / 2b4973aa487356b6458824b811d5b76379a1df7d / . / arch / arm64 / boot / dts / qcom / sdm845-sde.dtsi
blob: 0dfe7ae6b29f90886aec16498c22a2d9e10151b7 [file] [log] [blame]
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]1/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]12#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]13
14&soc {
15 mdss_mdp: qcom,mdss_mdp@ae00000 {
16 compatible = "qcom,sde-kms";
Lloyd Atkinson8f2bd8c2017-04-06 11:55:49 -0700[diff] [blame]17 reg = <0x0ae00000 0x81d40>,
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]18 <0x0aeb0000 0x2008>,
19 <0x0aeac000 0xf0>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]20 reg-names = "mdp_phys",
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]21 "vbif_phys",
22 "regdma_phys";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]23
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]24 clocks =
25 <&clock_gcc GCC_DISP_AHB_CLK>,
26 <&clock_gcc GCC_DISP_AXI_CLK>,
27 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]28 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]29 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
30 <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
Dhaval Patel2cd94b12017-04-21 19:39:53 -0700[diff] [blame]31 clock-names = "gcc_iface", "gcc_bus", "iface_clk",
32 "bus_clk", "core_clk", "vsync_clk";
33 clock-rate = <0 0 0 0 300000000 19200000 0>;
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700[diff] [blame]34 clock-max-rate = <0 0 0 0 412500000 19200000 0>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]35
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]36 sde-vdd-supply = <&mdss_core_gdsc>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]37
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]38 /* interrupt config */
Archana Sathyakumar00a36ab2017-03-03 14:38:26 -0700[diff] [blame]39 interrupt-parent = <&pdc>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]40 interrupts = <0 83 0>;
41 interrupt-controller;
42 #interrupt-cells = <1>;
Patrick Dalycaf09c92017-04-18 16:30:52 -0700[diff] [blame]43 iommus = <&apps_smmu 0x880 0x8>,
44 <&apps_smmu 0xc80 0x8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]45
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]46 #address-cells = <1>;
47 #size-cells = <0>;
48
Alan Kwong78dbffd2017-09-19 17:07:11 -0400[diff] [blame]49 #power-domain-cells = <0>;
50
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]51 /* hw blocks */
52 qcom,sde-off = <0x1000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]53 qcom,sde-len = <0x45C>;
54
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]55 qcom,sde-ctl-off = <0x2000 0x2200 0x2400
56 0x2600 0x2800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]57 qcom,sde-ctl-size = <0xE4>;
Jeykumar Sankaran3ed2ec32017-09-13 15:02:40 -0700[diff] [blame]58 qcom,sde-ctl-display-pref = "primary", "primary", "none",
59 "none", "none";
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]60
Jeykumar Sankaran32c5f602017-09-13 14:03:10 -0700[diff] [blame]61 qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0 0 0x4a000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]62 qcom,sde-mixer-size = <0x320>;
Jeykumar Sankaran3ed2ec32017-09-13 15:02:40 -0700[diff] [blame]63 qcom,sde-mixer-display-pref = "primary", "primary", "none",
64 "none", "none", "none";
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]65
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]66 qcom,sde-dspp-top-off = <0x1300>;
67 qcom,sde-dspp-top-size = <0xc>;
68
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]69 qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
Ping Li2d6c5f92017-05-04 14:17:03 -0700[diff] [blame]70 qcom,sde-dspp-size = <0x17e0>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]71
Sravanthi Kollukudurua45d8e72017-07-19 20:41:27 +0530[diff] [blame]72 qcom,sde-dest-scaler-top-off = <0x00061000>;
73 qcom,sde-dest-scaler-top-size = <0xc>;
74 qcom,sde-dest-scaler-off = <0x800 0x1000>;
75 qcom,sde-dest-scaler-size = <0x800>;
76
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]77 qcom,sde-wb-off = <0x66000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]78 qcom,sde-wb-size = <0x2c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]79 qcom,sde-wb-xin-id = <6>;
80 qcom,sde-wb-id = <2>;
Steve Cohen76bc0982017-06-20 13:19:04 -0400[diff] [blame]81 qcom,sde-wb-clk-ctrl = <0x3b8 24>;
82
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]83 qcom,sde-intf-off = <0x6b000 0x6b800
84 0x6c000 0x6c800>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]85 qcom,sde-intf-size = <0x280>;
86
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]87 qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
88 qcom,sde-pp-off = <0x71000 0x71800
89 0x72000 0x72800 0x73000>;
90 qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x1>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]91 qcom,sde-pp-size = <0xd4>;
92
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]93 qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0>;
94 qcom,sde-cdm-off = <0x7a200>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]95 qcom,sde-cdm-size = <0x224>;
96
97 qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
98 qcom,sde-dsc-size = <0x140>;
99
Narendra Muppallaa0826c62017-06-12 11:55:33 -0700[diff] [blame]100 qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0 0x0>;
Ping Lic7dd65f2017-03-08 12:11:01 -0800[diff] [blame]101 qcom,sde-dither-version = <0x00010000>;
102 qcom,sde-dither-size = <0x20>;
103
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]104 qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
105 "dma", "dma", "dma", "dma";
106
107 qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
108 0x25000 0x27000 0x29000 0x2b000>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]109 qcom,sde-sspp-src-size = <0x1c8>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]110
111 qcom,sde-sspp-xin-id = <0 4 8 12
112 1 5 9 13>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]113 qcom,sde-sspp-excl-rect = <1 1 1 1
114 1 1 1 1>;
Jeykumar Sankaran07515162017-05-16 13:02:33 -0700[diff] [blame]115 qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
116 qcom,sde-smart-dma-rev = "smart_dma_v2";
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]117
Veera Sundaram Sankaran370b9912017-01-10 18:03:42 -0800[diff] [blame]118 qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
119
120 qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
121 0xb0 0xc8 0xe0 0xf8 0x110>;
122
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]123 /* offsets are relative to "mdp_phys + qcom,sde-off */
124 qcom,sde-sspp-clk-ctrl =
125 <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
126 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
127 qcom,sde-sspp-csc-off = <0x1a00>;
128 qcom,sde-csc-type = "csc-10bit";
129 qcom,sde-qseed-type = "qseedv3";
130 qcom,sde-sspp-qseed-off = <0xa00>;
131 qcom,sde-mixer-linewidth = <2560>;
132 qcom,sde-sspp-linewidth = <2560>;
Alan Kwongd939be42017-03-08 19:37:38 -0800[diff] [blame]133 qcom,sde-wb-linewidth = <4096>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]134 qcom,sde-mixer-blendstages = <0xb>;
135 qcom,sde-highest-bank-bit = <0x2>;
Clarence Ip03f2ffe2017-04-28 16:12:17 -0700[diff] [blame]136 qcom,sde-ubwc-version = <0x200>;
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]137 qcom,sde-panic-per-pipe;
138 qcom,sde-has-cdp;
139 qcom,sde-has-src-split;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]140 qcom,sde-has-dim-layer;
Veera Sundaram Sankarana92444a2017-04-07 15:48:07 -0700[diff] [blame]141 qcom,sde-has-idle-pc;
Sravanthi Kollukudurua45d8e72017-07-19 20:41:27 +0530[diff] [blame]142 qcom,sde-has-dest-scaler;
143 qcom,sde-max-dest-scaler-input-linewidth = <2048>;
144 qcom,sde-max-dest-scaler-output-linewidth = <2560>;
Narendra Muppallaf1f7ecc2017-08-07 14:23:56 -0700[diff] [blame]145 qcom,sde-max-bw-low-kbps = <6800000>;
146 qcom,sde-max-bw-high-kbps = <6800000>;
Narendra Muppalla86a46a02017-08-17 11:14:37 -0700[diff] [blame]147 qcom,sde-min-core-ib-kbps = <2400000>;
148 qcom,sde-min-llcc-ib-kbps = <800000>;
149 qcom,sde-min-dram-ib-kbps = <800000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]150 qcom,sde-dram-channels = <2>;
151 qcom,sde-num-nrt-paths = <0>;
Gopikrishnaiah Anandanaaf6dcd2017-02-08 14:10:18 -0800[diff] [blame]152 qcom,sde-dspp-ad-version = <0x00040000>;
153 qcom,sde-dspp-ad-off = <0x28000 0x27000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]154
155 qcom,sde-vbif-off = <0>;
156 qcom,sde-vbif-size = <0x1040>;
157 qcom,sde-vbif-id = <0>;
Clarence Ip0b5f4412017-05-17 11:29:24 -0400[diff] [blame]158 qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
159 qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]160
Alan Kwong1641b0b2017-04-19 09:01:13 -0700[diff] [blame]161 qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
162 qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
163
Alan Kwonge67b3792017-04-27 15:57:50 -0700[diff] [blame]164 qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
165 0x00000000>;
Ingrid Gallardoaf41bba2017-10-06 17:31:35 -0700[diff] [blame]166 qcom,sde-safe-lut-linear =
167 <4 0xfff8>,
168 <0 0xfff0>;
169 qcom,sde-safe-lut-macrotile =
170 <10 0xfe00>,
171 <11 0xfc00>,
172 <12 0xf800>,
173 <0 0xf000>;
174 qcom,sde-safe-lut-nrt =
175 <0 0xffff>;
176 qcom,sde-safe-lut-cwb =
177 <0 0xffff>;
Alan Kwonge67b3792017-04-27 15:57:50 -0700[diff] [blame]178 qcom,sde-qos-lut-linear =
179 <4 0x00000000 0x00000357>,
180 <5 0x00000000 0x00003357>,
181 <6 0x00000000 0x00023357>,
182 <7 0x00000000 0x00223357>,
183 <8 0x00000000 0x02223357>,
184 <9 0x00000000 0x22223357>,
185 <10 0x00000002 0x22223357>,
186 <11 0x00000022 0x22223357>,
187 <12 0x00000222 0x22223357>,
188 <13 0x00002222 0x22223357>,
189 <14 0x00012222 0x22223357>,
190 <0 0x00112222 0x22223357>;
191 qcom,sde-qos-lut-macrotile =
192 <10 0x00000003 0x44556677>,
193 <11 0x00000033 0x44556677>,
194 <12 0x00000233 0x44556677>,
195 <13 0x00002233 0x44556677>,
196 <14 0x00012233 0x44556677>,
197 <0 0x00112233 0x44556677>;
198 qcom,sde-qos-lut-nrt =
199 <0 0x00000000 0x00000000>;
200 qcom,sde-qos-lut-cwb =
201 <0 0x75300000 0x00000000>;
202
Alan Kwong23ef3f392017-04-28 11:09:06 -0700[diff] [blame]203 qcom,sde-cdp-setting = <1 1>, <1 0>;
204
Lloyd Atkinson2b4973a2017-10-11 11:40:22 -0400[diff] [blame^]205 qcom,sde-qos-cpu-mask = <0x3>;
206 qcom,sde-qos-cpu-dma-latency = <300>;
207
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]208 qcom,sde-inline-rotator = <&mdss_rotator 0>;
Veera Sundaram Sankaran5f9ef0d2017-05-24 18:49:53 -0700[diff] [blame]209 qcom,sde-inline-rot-xin = <10 11>;
210 qcom,sde-inline-rot-xin-type = "sspp", "wb";
211
212 /* offsets are relative to "mdp_phys + qcom,sde-off */
213 qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]214
Gopikrishnaiah Anandan06629532017-08-23 18:24:57 -0700[diff] [blame]215 qcom,sde-reg-dma-off = <0>;
216 qcom,sde-reg-dma-version = <0x1>;
217 qcom,sde-reg-dma-trigger-off = <0x119c>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]218
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]219 qcom,sde-sspp-vig-blocks {
220 qcom,sde-vig-csc-off = <0x1a00>;
221 qcom,sde-vig-qseed-off = <0xa00>;
Lloyd Atkinson216e3062017-01-31 08:42:38 -0800[diff] [blame]222 qcom,sde-vig-qseed-size = <0xa0>;
Veera Sundaram Sankaran0ea57f62017-01-16 18:08:04 -0800[diff] [blame]223 };
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]224
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]225 qcom,sde-dspp-blocks {
Rajesh Yadavec93afb2017-06-08 19:28:33 +0530[diff] [blame]226 qcom,sde-dspp-igc = <0x0 0x00030001>;
Rajesh Yadav284947c2017-07-21 20:32:13 +0530[diff] [blame]227 qcom,sde-dspp-hsic = <0x800 0x00010007>;
Rajesh Yadav7b8fbae2017-08-28 14:48:14 +0530[diff] [blame]228 qcom,sde-dspp-memcolor = <0x880 0x00010007>;
Rajesh Yadav0a92eea2017-07-18 18:18:55 +0530[diff] [blame]229 qcom,sde-dspp-sixzone= <0x900 0x00010007>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]230 qcom,sde-dspp-vlut = <0xa00 0x00010008>;
231 qcom,sde-dspp-gamut = <0x1000 0x00040000>;
Rajesh Yadavd490cb62017-07-04 13:20:42 +0530[diff] [blame]232 qcom,sde-dspp-pcc = <0x1700 0x00040000>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]233 qcom,sde-dspp-gc = <0x17c0 0x00010008>;
Xu Yang056d39b2017-07-11 16:34:13 +0800[diff] [blame]234 qcom,sde-dspp-hist = <0x800 0x00010007>;
Gopikrishnaiah Anandancd476032017-03-27 12:33:00 -0700[diff] [blame]235 };
236
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]237 qcom,platform-supply-entries {
238 #address-cells = <1>;
239 #size-cells = <0>;
240
241 qcom,platform-supply-entry@0 {
242 reg = <0>;
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]243 qcom,supply-name = "sde-vdd";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]244 qcom,supply-min-voltage = <0>;
245 qcom,supply-max-voltage = <0>;
246 qcom,supply-enable-load = <0>;
247 qcom,supply-disable-load = <0>;
248 };
249 };
250
Abhijit Kulkarni1774dac2017-05-01 10:51:02 -0700[diff] [blame]251 smmu_sde_sec: qcom,smmu_sde_sec_cb {
252 compatible = "qcom,smmu_sde_sec";
253 iommus = <&apps_smmu 0x881 0x8>,
254 <&apps_smmu 0xc81 0x8>;
255 };
256
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]257 /* data and reg bus scale settings */
258 qcom,sde-data-bus {
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]259 qcom,msm-bus,name = "mdss_sde_mnoc";
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]260 qcom,msm-bus,num-cases = <3>;
261 qcom,msm-bus,num-paths = <2>;
262 qcom,msm-bus,vectors-KBps =
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]263 <22 773 0 0>, <23 773 0 0>,
264 <22 773 0 6400000>, <23 773 0 6400000>,
265 <22 773 0 6400000>, <23 773 0 6400000>;
266 };
267
268 qcom,sde-llcc-bus {
269 qcom,msm-bus,name = "mdss_sde_llcc";
270 qcom,msm-bus,num-cases = <3>;
271 qcom,msm-bus,num-paths = <1>;
272 qcom,msm-bus,vectors-KBps =
273 <132 770 0 0>,
274 <132 770 0 6400000>,
275 <132 770 0 6400000>;
276 };
277
278 qcom,sde-ebi-bus {
279 qcom,msm-bus,name = "mdss_sde_ebi";
280 qcom,msm-bus,num-cases = <3>;
281 qcom,msm-bus,num-paths = <1>;
282 qcom,msm-bus,vectors-KBps =
283 <129 512 0 0>,
284 <129 512 0 6400000>,
285 <129 512 0 6400000>;
Alan Kwongd5e95342017-01-30 19:38:05 -0800[diff] [blame]286 };
287
288 qcom,sde-reg-bus {
289 qcom,msm-bus,name = "mdss_reg";
290 qcom,msm-bus,num-cases = <4>;
291 qcom,msm-bus,num-paths = <1>;
292 qcom,msm-bus,active-only;
293 qcom,msm-bus,vectors-KBps =
294 <1 590 0 0>,
295 <1 590 0 76800>,
296 <1 590 0 150000>,
297 <1 590 0 300000>;
298 };
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]299 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]300
301 sde_rscc: qcom,sde_rscc@af20000 {
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]302 cell-index = <0>;
303 compatible = "qcom,sde-rsc";
304 reg = <0xaf20000 0x1c44>,
305 <0xaf30000 0x3fd4>;
306 reg-names = "drv", "wrapper";
307 qcom,sde-rsc-version = <1>;
308
309 vdd-supply = <&mdss_core_gdsc>;
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]310 clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
311 <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
312 clock-names = "vsync_clk", "iface_clk";
Dhaval Patel2169d612017-01-30 19:38:05 -0800[diff] [blame]313 clock-rate = <0 0>;
314
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]315 qcom,sde-dram-channels = <2>;
316
Dhaval Patel7556ced2017-02-10 19:53:10 -0800[diff] [blame]317 mboxes = <&disp_rsc 0>;
318 mbox-names = "disp_rsc";
319
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]320 /* data and reg bus scale settings */
321 qcom,sde-data-bus {
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]322 qcom,msm-bus,name = "disp_rsc_mnoc";
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]323 qcom,msm-bus,active-only;
324 qcom,msm-bus,num-cases = <3>;
325 qcom,msm-bus,num-paths = <2>;
326 qcom,msm-bus,vectors-KBps =
Alan Kwonge9b257b2017-05-16 11:40:50 -0700[diff] [blame]327 <20003 20515 0 0>, <20004 20515 0 0>,
328 <20003 20515 0 6400000>, <20004 20515 0 6400000>,
329 <20003 20515 0 6400000>, <20004 20515 0 6400000>;
330 };
331
332 qcom,sde-llcc-bus {
333 qcom,msm-bus,name = "disp_rsc_llcc";
334 qcom,msm-bus,active-only;
335 qcom,msm-bus,num-cases = <3>;
336 qcom,msm-bus,num-paths = <1>;
337 qcom,msm-bus,vectors-KBps =
338 <20001 20513 0 0>,
339 <20001 20513 0 6400000>,
340 <20001 20513 0 6400000>;
341 };
342
343 qcom,sde-ebi-bus {
344 qcom,msm-bus,name = "disp_rsc_ebi";
345 qcom,msm-bus,active-only;
346 qcom,msm-bus,num-cases = <3>;
347 qcom,msm-bus,num-paths = <1>;
348 qcom,msm-bus,vectors-KBps =
349 <20000 20512 0 0>,
350 <20000 20512 0 6400000>,
351 <20000 20512 0 6400000>;
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]352 };
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]353 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]354
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]355 mdss_rotator: qcom,mdss_rotator@ae00000 {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]356 compatible = "qcom,sde_rotator";
357 reg = <0x0ae00000 0xac000>,
358 <0x0aeb8000 0x3000>;
359 reg-names = "mdp_phys",
360 "rot_vbif_phys";
361
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]362 #list-cells = <1>;
363
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]364 qcom,mdss-rot-mode = <1>;
365 qcom,mdss-highest-bank-bit = <0x2>;
366
367 /* Bus Scale Settings */
368 qcom,msm-bus,name = "mdss_rotator";
369 qcom,msm-bus,num-cases = <3>;
370 qcom,msm-bus,num-paths = <1>;
371 qcom,msm-bus,vectors-KBps =
372 <25 512 0 0>,
373 <25 512 0 6400000>,
374 <25 512 0 6400000>;
375
376 rot-vdd-supply = <&mdss_core_gdsc>;
377 qcom,supply-names = "rot-vdd";
378
379 clocks =
380 <&clock_gcc GCC_DISP_AHB_CLK>,
381 <&clock_gcc GCC_DISP_AXI_CLK>,
382 <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]383 <&clock_dispcc DISP_CC_MDSS_ROT_CLK>,
384 <&clock_dispcc DISP_CC_MDSS_AXI_CLK>;
385 clock-names = "gcc_iface", "gcc_bus",
Clarence Ip015924e2017-05-01 13:28:03 -0700[diff] [blame]386 "iface_clk", "rot_clk", "axi_clk";
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]387
388 interrupt-parent = <&mdss_mdp>;
389 interrupts = <2 0>;
390
Alan Kwong78dbffd2017-09-19 17:07:11 -0400[diff] [blame]391 power-domains = <&mdss_mdp>;
392
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]393 /* Offline rotator QoS setting */
Veera Sundaram Sankaranf28be032017-04-20 08:16:41 -0700[diff] [blame]394 qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
Alan Kwong8efe4a82017-06-30 16:05:50 -0400[diff] [blame]395 qcom,mdss-rot-vbif-memtype = <3 3>;
Veera Sundaram Sankaranfd4b37d2017-05-11 12:44:38 -0700[diff] [blame]396 qcom,mdss-rot-cdp-setting = <1 1>;
Veera Sundaram Sankaran04883492017-05-12 12:35:36 -0700[diff] [blame]397 qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
398 qcom,mdss-rot-danger-lut = <0x0 0x0>;
399 qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
400
401 /* Inline rotator QoS Setting */
402 /* setting default register values for RD - qos/danger/safe */
403 qcom,mdss-inline-rot-qos-lut = <0x44556677 0x00112233
404 0x44556677 0x00112233>;
405 qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>;
406 qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]407
408 qcom,mdss-default-ot-rd-limit = <32>;
409 qcom,mdss-default-ot-wr-limit = <32>;
410
Alan Kwong00187722017-02-04 19:09:17 -0800[diff] [blame]411 qcom,mdss-sbuf-headroom = <20>;
412
413 cache-slice-names = "rotator";
414 cache-slices = <&llcc 4>;
415
Veera Sundaram Sankaran06418032017-06-30 14:12:58 -0700[diff] [blame]416 /* reg bus scale settings */
417 rot_reg: qcom,rot-reg-bus {
418 qcom,msm-bus,name = "mdss_rot_reg";
419 qcom,msm-bus,num-cases = <2>;
420 qcom,msm-bus,num-paths = <1>;
421 qcom,msm-bus,active-only;
422 qcom,msm-bus,vectors-KBps =
423 <1 590 0 0>,
424 <1 590 0 76800>;
425 };
426
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]427 smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
428 compatible = "qcom,smmu_sde_rot_unsec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]429 iommus = <&apps_smmu 0x1090 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]430 };
431
432 smmu_rot_sec: qcom,smmu_rot_sec_cb {
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]433 compatible = "qcom,smmu_sde_rot_sec";
Patrick Dalyc4aaa902017-04-24 12:45:11 -0700[diff] [blame]434 iommus = <&apps_smmu 0x1091 0x0>;
Clarence Ip3b5b5ed2017-01-24 09:59:03 -0800[diff] [blame]435 };
Dhaval Pateld0a84042016-12-01 14:50:47 -0800[diff] [blame]436 };
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]437
438 mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]439 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]440 label = "dsi-ctrl-0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]441 cell-index = <0>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]442 reg = <0xae94000 0x400>,
443 <0xaf08000 0x4>;
444 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]445 interrupt-parent = <&mdss_mdp>;
446 interrupts = <4 0>;
447 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]448 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
449 <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
450 <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
451 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]452 <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
453 <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]454 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]455 "pixel_clk", "pixel_clk_rcg",
456 "esc_clk";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]457
458 qcom,ctrl-supply-entries {
459 #address-cells = <1>;
460 #size-cells = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]461
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]462 qcom,ctrl-supply-entry@0 {
463 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]464 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]465 qcom,supply-min-voltage = <1200000>;
466 qcom,supply-max-voltage = <1200000>;
467 qcom,supply-enable-load = <21800>;
468 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]469 };
470 };
471 };
472
473 mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]474 compatible = "qcom,dsi-ctrl-hw-v2.2";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]475 label = "dsi-ctrl-1";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]476 cell-index = <1>;
Shashank Babu Chinta Venkataafef8202017-04-21 13:49:56 -0700[diff] [blame]477 reg = <0xae96000 0x400>,
478 <0xaf08000 0x4>;
479 reg-names = "dsi_ctrl", "disp_cc_base";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]480 interrupt-parent = <&mdss_mdp>;
481 interrupts = <5 0>;
482 vdda-1p2-supply = <&pm8998_l26>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]483 clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
484 <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
485 <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
486 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
487 <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
488 <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]489 clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]490 "pixel_clk", "pixel_clk_rcg", "esc_clk";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]491 qcom,ctrl-supply-entries {
492 #address-cells = <1>;
493 #size-cells = <0>;
494
495 qcom,ctrl-supply-entry@0 {
496 reg = <0>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]497 qcom,supply-name = "vdda-1p2";
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]498 qcom,supply-min-voltage = <1200000>;
499 qcom,supply-max-voltage = <1200000>;
500 qcom,supply-enable-load = <21800>;
501 qcom,supply-disable-load = <4>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]502 };
503 };
504 };
505
506 mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
507 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]508 label = "dsi-phy-0";
509 cell-index = <0>;
510 reg = <0xae94400 0x7c0>;
511 reg-names = "dsi_phy";
512 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]513 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]514 qcom,platform-strength-ctrl = [55 03
515 55 03
516 55 03
517 55 03
518 55 00];
519 qcom,platform-lane-config = [00 00 00 00
520 00 00 00 00
521 00 00 00 00
522 00 00 00 00
523 00 00 00 80];
524 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]525 qcom,phy-supply-entries {
526 #address-cells = <1>;
527 #size-cells = <0>;
528 qcom,phy-supply-entry@0 {
529 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]530 qcom,supply-name = "vdda-0p9";
531 qcom,supply-min-voltage = <880000>;
532 qcom,supply-max-voltage = <880000>;
533 qcom,supply-enable-load = <36000>;
534 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]535 };
536 };
537 };
538
539 mdss_dsi_phy1: qcom,mdss_dsi_phy0@ae96400 {
540 compatible = "qcom,dsi-phy-v3.0";
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]541 label = "dsi-phy-1";
542 cell-index = <1>;
543 reg = <0xae96400 0x7c0>;
544 reg-names = "dsi_phy";
545 gdsc-supply = <&mdss_core_gdsc>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]546 vdda-0p9-supply = <&pm8998_l1>;
Shashank Babu Chinta Venkata5292d192017-04-05 15:19:17 -0700[diff] [blame]547 qcom,platform-strength-ctrl = [55 03
548 55 03
549 55 03
550 55 03
551 55 00];
552 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
553 qcom,platform-lane-config = [00 00 00 00
554 00 00 00 00
555 00 00 00 00
556 00 00 00 00
557 00 00 00 80];
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]558 qcom,phy-supply-entries {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 qcom,phy-supply-entry@0 {
562 reg = <0>;
Shashank Babu Chinta Venkataf84694c2017-04-05 12:14:18 -0700[diff] [blame]563 qcom,supply-name = "vdda-0p9";
564 qcom,supply-min-voltage = <880000>;
565 qcom,supply-max-voltage = <880000>;
566 qcom,supply-enable-load = <36000>;
567 qcom,supply-disable-load = <32>;
Shashank Babu Chinta Venkata24bdd052017-02-24 14:29:09 -0800[diff] [blame]568 };
569 };
570 };
571
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]572 sde_dp: qcom,dp_display@0{
573 cell-index = <0>;
574 compatible = "qcom,dp-display";
575
576 gdsc-supply = <&mdss_core_gdsc>;
577 vdda-1p2-supply = <&pm8998_l26>;
578 vdda-0p9-supply = <&pm8998_l1>;
579
580 reg = <0xae90000 0xa84>,
581 <0x88eaa00 0x200>,
582 <0x88ea200 0x200>,
583 <0x88ea600 0x200>,
584 <0xaf02000 0x1a0>,
585 <0x780000 0x621c>,
586 <0x88ea030 0x10>,
587 <0x88e8000 0x20>,
588 <0x0aee1000 0x034>;
589 reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
590 "dp_mmss_cc", "qfprom_physical", "dp_pll",
591 "usb3_dp_com", "hdcp_physical";
592
593 interrupt-parent = <&mdss_mdp>;
594 interrupts = <12 0>;
595
596 clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
597 <&clock_rpmh RPMH_CXO_CLK>,
598 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
599 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
600 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
601 <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
602 <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
603 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
604 <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
605 <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
606 <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
607 clock-names = "core_aux_clk", "core_usb_ref_clk_src",
608 "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
609 "core_usb_pipe_clk", "ctrl_link_clk",
610 "ctrl_link_iface_clk", "ctrl_pixel_clk",
611 "crypto_clk", "pixel_clk_rcg", "pixel_parent";
612
613 qcom,aux-cfg0-settings = [20 00];
614 qcom,aux-cfg1-settings = [24 13 23 1d];
615 qcom,aux-cfg2-settings = [28 24];
616 qcom,aux-cfg3-settings = [2c 00];
617 qcom,aux-cfg4-settings = [30 0a];
618 qcom,aux-cfg5-settings = [34 26];
619 qcom,aux-cfg6-settings = [38 0a];
620 qcom,aux-cfg7-settings = [3c 03];
621 qcom,aux-cfg8-settings = [40 bb];
622 qcom,aux-cfg9-settings = [44 03];
623
624 qcom,max-pclk-frequency-khz = <675000>;
625
Ingrid Gallardoc5b9c032017-09-11 16:10:43 -0700[diff] [blame]626 qcom,ctrl-supply-entries {
627 #address-cells = <1>;
628 #size-cells = <0>;
629
630 qcom,ctrl-supply-entry@0 {
631 reg = <0>;
632 qcom,supply-name = "vdda-1p2";
633 qcom,supply-min-voltage = <1200000>;
634 qcom,supply-max-voltage = <1200000>;
635 qcom,supply-enable-load = <21800>;
636 qcom,supply-disable-load = <4>;
637 };
638 };
639
640 qcom,phy-supply-entries {
641 #address-cells = <1>;
642 #size-cells = <0>;
643
644 qcom,phy-supply-entry@0 {
645 reg = <0>;
646 qcom,supply-name = "vdda-0p9";
647 qcom,supply-min-voltage = <880000>;
648 qcom,supply-max-voltage = <880000>;
649 qcom,supply-enable-load = <36000>;
650 qcom,supply-disable-load = <32>;
651 };
652 };
653 };
Dhaval Patel6a5bd8b2016-10-10 14:12:10 -0700[diff] [blame]654};