Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 2 | * (c) 2003, 2004, 2005 Advanced Micro Devices, Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Your use of this code is subject to the terms and conditions of the |
| 4 | * GNU general public license version 2. See "COPYING" or |
| 5 | * http://www.gnu.org/licenses/gpl.html |
| 6 | */ |
| 7 | |
| 8 | struct powernow_k8_data { |
| 9 | unsigned int cpu; |
| 10 | |
| 11 | u32 numps; /* number of p-states */ |
| 12 | u32 batps; /* number of p-states supported on battery */ |
| 13 | |
| 14 | /* these values are constant when the PSB is used to determine |
| 15 | * vid/fid pairings, but are modified during the ->target() call |
| 16 | * when ACPI is used */ |
| 17 | u32 rvo; /* ramp voltage offset */ |
| 18 | u32 irt; /* isochronous relief time */ |
| 19 | u32 vidmvs; /* usable value calculated from mvs */ |
| 20 | u32 vstable; /* voltage stabilization time, units 20 us */ |
| 21 | u32 plllock; /* pll lock time, units 1 us */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 22 | u32 exttype; /* extended interface = 1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | |
| 24 | /* keep track of the current fid / vid */ |
| 25 | u32 currvid, currfid; |
| 26 | |
| 27 | /* the powernow_table includes all frequency and vid/fid pairings: |
| 28 | * fid are the lower 8 bits of the index, vid are the upper 8 bits. |
| 29 | * frequency is in kHz */ |
| 30 | struct cpufreq_frequency_table *powernow_table; |
| 31 | |
| 32 | #ifdef CONFIG_X86_POWERNOW_K8_ACPI |
| 33 | /* the acpi table needs to be kept. it's only available if ACPI was |
| 34 | * used to determine valid frequency/vid/fid states */ |
| 35 | struct acpi_processor_performance acpi_data; |
| 36 | #endif |
| 37 | }; |
| 38 | |
| 39 | |
| 40 | /* processor's cpuid instruction support */ |
| 41 | #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ |
| 42 | #define CPUID_XFAM 0x0ff00000 /* extended family */ |
| 43 | #define CPUID_XFAM_K8 0 |
| 44 | #define CPUID_XMOD 0x000f0000 /* extended model */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 45 | #define CPUID_XMOD_REV_F 0x00040000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | #define CPUID_USE_XFAM_XMOD 0x00000f00 |
| 47 | #define CPUID_GET_MAX_CAPABILITIES 0x80000000 |
| 48 | #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 |
| 49 | #define P_STATE_TRANSITION_CAPABLE 6 |
| 50 | |
| 51 | /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ |
| 52 | /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ |
| 53 | /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */ |
| 54 | /* the register number is placed in ecx, and the data is returned in edx:eax. */ |
| 55 | |
| 56 | #define MSR_FIDVID_CTL 0xc0010041 |
| 57 | #define MSR_FIDVID_STATUS 0xc0010042 |
| 58 | |
| 59 | /* Field definitions within the FID VID Low Control MSR : */ |
| 60 | #define MSR_C_LO_INIT_FID_VID 0x00010000 |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 61 | #define MSR_C_LO_NEW_VID 0x00003f00 |
| 62 | #define MSR_C_LO_NEW_FID 0x0000003f |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | #define MSR_C_LO_VID_SHIFT 8 |
| 64 | |
| 65 | /* Field definitions within the FID VID High Control MSR : */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 66 | #define MSR_C_HI_STP_GNT_TO 0x000fffff |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | |
| 68 | /* Field definitions within the FID VID Low Status MSR : */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 69 | #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */ |
| 70 | #define MSR_S_LO_MAX_RAMP_VID 0x3f000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | #define MSR_S_LO_MAX_FID 0x003f0000 |
| 72 | #define MSR_S_LO_START_FID 0x00003f00 |
| 73 | #define MSR_S_LO_CURRENT_FID 0x0000003f |
| 74 | |
| 75 | /* Field definitions within the FID VID High Status MSR : */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 76 | #define MSR_S_HI_MIN_WORKING_VID 0x3f000000 |
| 77 | #define MSR_S_HI_MAX_WORKING_VID 0x003f0000 |
| 78 | #define MSR_S_HI_START_VID 0x00003f00 |
| 79 | #define MSR_S_HI_CURRENT_VID 0x0000003f |
| 80 | #define MSR_C_HI_STP_GNT_BENIGN 0x00000001 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * There are restrictions frequencies have to follow: |
| 84 | * - only 1 entry in the low fid table ( <=1.4GHz ) |
| 85 | * - lowest entry in the high fid table must be >= 2 * the entry in the |
| 86 | * low fid table |
| 87 | * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry |
| 88 | * in the low fid table |
| 89 | * - the parts can only step at 200 MHz intervals, so 1.9 GHz is never valid |
| 90 | * - lowest frequency must be >= interprocessor hypertransport link speed |
| 91 | * (only applies to MP systems obviously) |
| 92 | */ |
| 93 | |
| 94 | /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */ |
| 95 | #define LO_FID_TABLE_TOP 6 /* fid values marking the boundary */ |
| 96 | #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */ |
| 97 | |
| 98 | #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */ |
| 99 | #define HI_VCOFREQ_TABLE_BOTTOM 1600 |
| 100 | |
| 101 | #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */ |
| 102 | |
| 103 | #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 104 | #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | |
| 106 | #define MIN_FREQ 800 /* Min and max freqs, per spec */ |
| 107 | #define MAX_FREQ 5000 |
| 108 | |
| 109 | #define INVALID_FID_MASK 0xffffffc1 /* not a valid fid if these bits are set */ |
Dave Jones | 841e40b | 2005-07-28 09:40:04 -0700 | [diff] [blame] | 110 | #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */ |
| 111 | |
| 112 | #define VID_OFF 0x3f |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
| 114 | #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */ |
| 115 | |
| 116 | #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */ |
| 117 | |
| 118 | #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */ |
| 119 | #define VST_UNITS_20US 20 /* Voltage Stabalization Time is in units of 20us */ |
| 120 | |
| 121 | /* |
| 122 | * Most values of interest are enocoded in a single field of the _PSS |
| 123 | * entries: the "control" value. |
| 124 | */ |
| 125 | |
| 126 | #define IRT_SHIFT 30 |
| 127 | #define RVO_SHIFT 28 |
Dave Jones | 2bcad93 | 2005-07-29 09:56:41 -0700 | [diff] [blame^] | 128 | #define EXT_TYPE_SHIFT 27 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 129 | #define PLL_L_SHIFT 20 |
| 130 | #define MVS_SHIFT 18 |
| 131 | #define VST_SHIFT 11 |
| 132 | #define VID_SHIFT 6 |
| 133 | #define IRT_MASK 3 |
| 134 | #define RVO_MASK 3 |
Dave Jones | 2bcad93 | 2005-07-29 09:56:41 -0700 | [diff] [blame^] | 135 | #define EXT_TYPE_MASK 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | #define PLL_L_MASK 0x7f |
| 137 | #define MVS_MASK 3 |
| 138 | #define VST_MASK 0x7f |
| 139 | #define VID_MASK 0x1f |
| 140 | #define FID_MASK 0x3f |
| 141 | |
| 142 | |
| 143 | /* |
| 144 | * Version 1.4 of the PSB table. This table is constructed by BIOS and is |
| 145 | * to tell the OS's power management driver which VIDs and FIDs are |
| 146 | * supported by this particular processor. |
| 147 | * If the data in the PSB / PST is wrong, then this driver will program the |
| 148 | * wrong values into hardware, which is very likely to lead to a crash. |
| 149 | */ |
| 150 | |
| 151 | #define PSB_ID_STRING "AMDK7PNOW!" |
| 152 | #define PSB_ID_STRING_LEN 10 |
| 153 | |
| 154 | #define PSB_VERSION_1_4 0x14 |
| 155 | |
| 156 | struct psb_s { |
| 157 | u8 signature[10]; |
| 158 | u8 tableversion; |
| 159 | u8 flags1; |
| 160 | u16 vstable; |
| 161 | u8 flags2; |
| 162 | u8 num_tables; |
| 163 | u32 cpuid; |
| 164 | u8 plllocktime; |
| 165 | u8 maxfid; |
| 166 | u8 maxvid; |
| 167 | u8 numps; |
| 168 | }; |
| 169 | |
| 170 | /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */ |
| 171 | struct pst_s { |
| 172 | u8 fid; |
| 173 | u8 vid; |
| 174 | }; |
| 175 | |
| 176 | #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "powernow-k8", msg) |
| 177 | |
| 178 | static int core_voltage_pre_transition(struct powernow_k8_data *data, u32 reqvid); |
| 179 | static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid); |
| 180 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid); |
| 181 | |
| 182 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index); |
Dave Jones | 065b807 | 2005-05-31 19:03:46 -0700 | [diff] [blame] | 183 | |
| 184 | #ifndef for_each_cpu_mask |
| 185 | #define for_each_cpu_mask(i,mask) for (i=0;i<1;i++) |
| 186 | #endif |
| 187 | |
| 188 | #ifdef CONFIG_SMP |
| 189 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) |
| 190 | { |
| 191 | } |
| 192 | #else |
| 193 | static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[]) |
| 194 | { |
| 195 | cpu_set(0, cpu_sharedcore_mask[0]); |
| 196 | } |
| 197 | #endif |