Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 1 | #include <dt-bindings/clock/tegra114-car.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 4 | |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 5 | #include "skeleton.dtsi" |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 6 | |
| 7 | / { |
| 8 | compatible = "nvidia,tegra114"; |
| 9 | interrupt-parent = <&gic>; |
| 10 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 11 | aliases { |
| 12 | serial0 = &uarta; |
| 13 | serial1 = &uartb; |
| 14 | serial2 = &uartc; |
| 15 | serial3 = &uartd; |
| 16 | }; |
| 17 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 18 | gic: interrupt-controller { |
| 19 | compatible = "arm,cortex-a15-gic"; |
| 20 | #interrupt-cells = <3>; |
| 21 | interrupt-controller; |
| 22 | reg = <0x50041000 0x1000>, |
| 23 | <0x50042000 0x1000>, |
| 24 | <0x50044000 0x2000>, |
| 25 | <0x50046000 0x2000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 26 | interrupts = <GIC_PPI 9 |
| 27 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | timer@60005000 { |
| 31 | compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; |
| 32 | reg = <0x60005000 0x400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 33 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| 34 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| 35 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| 36 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| 37 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 38 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 39 | clocks = <&tegra_car TEGRA114_CLK_TIMER>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | tegra_car: clock { |
Peter De Schrijver | 672d889 | 2013-04-03 17:40:48 +0300 | [diff] [blame] | 43 | compatible = "nvidia,tegra114-car"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 44 | reg = <0x60006000 0x1000>; |
| 45 | #clock-cells = <1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 46 | #reset-cells = <1>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 47 | }; |
| 48 | |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 49 | apbdma: dma { |
| 50 | compatible = "nvidia,tegra114-apbdma"; |
| 51 | reg = <0x6000a000 0x1400>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 52 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 53 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 54 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 55 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 56 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 59 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 66 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 68 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 84 | clocks = <&tegra_car TEGRA114_CLK_APBDMA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 85 | resets = <&tegra_car 34>; |
| 86 | reset-names = "dma"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 87 | #dma-cells = <1>; |
Laxman Dewangan | c5d9da4 | 2013-03-14 01:19:50 +0530 | [diff] [blame] | 88 | }; |
| 89 | |
Hiroshi Doyu | 0dfe42e | 2013-01-15 10:17:27 +0200 | [diff] [blame] | 90 | ahb: ahb { |
| 91 | compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; |
| 92 | reg = <0x6000c004 0x14c>; |
| 93 | }; |
| 94 | |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 95 | gpio: gpio { |
| 96 | compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; |
| 97 | reg = <0x6000d000 0x1000>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 98 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| 99 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 100 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
| 101 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
| 102 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| 103 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, |
| 104 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, |
| 105 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | b16f918 | 2013-01-29 18:26:18 +0530 | [diff] [blame] | 106 | #gpio-cells = <2>; |
| 107 | gpio-controller; |
| 108 | #interrupt-cells = <2>; |
| 109 | interrupt-controller; |
| 110 | }; |
| 111 | |
Laxman Dewangan | 031b77a | 2013-01-29 18:26:20 +0530 | [diff] [blame] | 112 | pinmux: pinmux { |
| 113 | compatible = "nvidia,tegra114-pinmux"; |
| 114 | reg = <0x70000868 0x148 /* Pad control registers */ |
| 115 | 0x70003000 0x40c>; /* Mux registers */ |
| 116 | }; |
| 117 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 118 | /* |
| 119 | * There are two serial driver i.e. 8250 based simple serial |
| 120 | * driver and APB DMA based serial driver for higher baudrate |
| 121 | * and performace. To enable the 8250 based driver, the compatible |
| 122 | * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable |
| 123 | * the APB DMA based serial driver, the comptible is |
| 124 | * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". |
| 125 | */ |
| 126 | uarta: serial@70006000 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 127 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 128 | reg = <0x70006000 0x40>; |
| 129 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 130 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 131 | nvidia,dma-request-selector = <&apbdma 8>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 132 | clocks = <&tegra_car TEGRA114_CLK_UARTA>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 133 | resets = <&tegra_car 6>; |
| 134 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 135 | dmas = <&apbdma 8>, <&apbdma 8>; |
| 136 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 137 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 138 | }; |
| 139 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 140 | uartb: serial@70006040 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 141 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 142 | reg = <0x70006040 0x40>; |
| 143 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 144 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 145 | nvidia,dma-request-selector = <&apbdma 9>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 146 | clocks = <&tegra_car TEGRA114_CLK_UARTB>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 147 | resets = <&tegra_car 7>; |
| 148 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 149 | dmas = <&apbdma 9>, <&apbdma 9>; |
| 150 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 151 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 152 | }; |
| 153 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 154 | uartc: serial@70006200 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 155 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 156 | reg = <0x70006200 0x100>; |
| 157 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 158 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 159 | nvidia,dma-request-selector = <&apbdma 10>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 160 | clocks = <&tegra_car TEGRA114_CLK_UARTC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 161 | resets = <&tegra_car 55>; |
| 162 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 163 | dmas = <&apbdma 10>, <&apbdma 10>; |
| 164 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 165 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 166 | }; |
| 167 | |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 168 | uartd: serial@70006300 { |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 169 | compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; |
| 170 | reg = <0x70006300 0x100>; |
| 171 | reg-shift = <2>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 172 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 0fb2209 | 2013-03-14 01:19:52 +0530 | [diff] [blame] | 173 | nvidia,dma-request-selector = <&apbdma 19>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 174 | clocks = <&tegra_car TEGRA114_CLK_UARTD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 175 | resets = <&tegra_car 65>; |
| 176 | reset-names = "serial"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 177 | dmas = <&apbdma 19>, <&apbdma 19>; |
| 178 | dma-names = "rx", "tx"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 179 | status = "disabled"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 180 | }; |
| 181 | |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 182 | pwm: pwm { |
| 183 | compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; |
| 184 | reg = <0x7000a000 0x100>; |
| 185 | #pwm-cells = <2>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 186 | clocks = <&tegra_car TEGRA114_CLK_PWM>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 187 | resets = <&tegra_car 17>; |
| 188 | reset-names = "pwm"; |
Andrew Chew | 6c716db | 2013-03-12 16:40:50 -0700 | [diff] [blame] | 189 | status = "disabled"; |
| 190 | }; |
| 191 | |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 192 | i2c@7000c000 { |
| 193 | compatible = "nvidia,tegra114-i2c"; |
| 194 | reg = <0x7000c000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 195 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 196 | #address-cells = <1>; |
| 197 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 198 | clocks = <&tegra_car TEGRA114_CLK_I2C1>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 199 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 200 | resets = <&tegra_car 12>; |
| 201 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 202 | dmas = <&apbdma 21>, <&apbdma 21>; |
| 203 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 204 | status = "disabled"; |
| 205 | }; |
| 206 | |
| 207 | i2c@7000c400 { |
| 208 | compatible = "nvidia,tegra114-i2c"; |
| 209 | reg = <0x7000c400 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 210 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 211 | #address-cells = <1>; |
| 212 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 213 | clocks = <&tegra_car TEGRA114_CLK_I2C2>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 214 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 215 | resets = <&tegra_car 54>; |
| 216 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 217 | dmas = <&apbdma 22>, <&apbdma 22>; |
| 218 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 219 | status = "disabled"; |
| 220 | }; |
| 221 | |
| 222 | i2c@7000c500 { |
| 223 | compatible = "nvidia,tegra114-i2c"; |
| 224 | reg = <0x7000c500 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 225 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 226 | #address-cells = <1>; |
| 227 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 228 | clocks = <&tegra_car TEGRA114_CLK_I2C3>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 229 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 230 | resets = <&tegra_car 67>; |
| 231 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 232 | dmas = <&apbdma 23>, <&apbdma 23>; |
| 233 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 234 | status = "disabled"; |
| 235 | }; |
| 236 | |
| 237 | i2c@7000c700 { |
| 238 | compatible = "nvidia,tegra114-i2c"; |
| 239 | reg = <0x7000c700 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 240 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 241 | #address-cells = <1>; |
| 242 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 243 | clocks = <&tegra_car TEGRA114_CLK_I2C4>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 244 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 245 | resets = <&tegra_car 103>; |
| 246 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 247 | dmas = <&apbdma 26>, <&apbdma 26>; |
| 248 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 249 | status = "disabled"; |
| 250 | }; |
| 251 | |
| 252 | i2c@7000d000 { |
| 253 | compatible = "nvidia,tegra114-i2c"; |
| 254 | reg = <0x7000d000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 255 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 256 | #address-cells = <1>; |
| 257 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 258 | clocks = <&tegra_car TEGRA114_CLK_I2C5>; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 259 | clock-names = "div-clk"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 260 | resets = <&tegra_car 47>; |
| 261 | reset-names = "i2c"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 262 | dmas = <&apbdma 24>, <&apbdma 24>; |
| 263 | dma-names = "rx", "tx"; |
Laxman Dewangan | 3fc2f94 | 2013-03-14 01:19:51 +0530 | [diff] [blame] | 264 | status = "disabled"; |
| 265 | }; |
| 266 | |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 267 | spi@7000d400 { |
| 268 | compatible = "nvidia,tegra114-spi"; |
| 269 | reg = <0x7000d400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 270 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 271 | nvidia,dma-request-selector = <&apbdma 15>; |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 274 | clocks = <&tegra_car TEGRA114_CLK_SBC1>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 275 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 276 | resets = <&tegra_car 41>; |
| 277 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 278 | dmas = <&apbdma 15>, <&apbdma 15>; |
| 279 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 280 | status = "disabled"; |
| 281 | }; |
| 282 | |
| 283 | spi@7000d600 { |
| 284 | compatible = "nvidia,tegra114-spi"; |
| 285 | reg = <0x7000d600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 286 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 287 | nvidia,dma-request-selector = <&apbdma 16>; |
| 288 | #address-cells = <1>; |
| 289 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 290 | clocks = <&tegra_car TEGRA114_CLK_SBC2>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 291 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 292 | resets = <&tegra_car 44>; |
| 293 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 294 | dmas = <&apbdma 16>, <&apbdma 16>; |
| 295 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 296 | status = "disabled"; |
| 297 | }; |
| 298 | |
| 299 | spi@7000d800 { |
| 300 | compatible = "nvidia,tegra114-spi"; |
| 301 | reg = <0x7000d800 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 302 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 303 | nvidia,dma-request-selector = <&apbdma 17>; |
| 304 | #address-cells = <1>; |
| 305 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 306 | clocks = <&tegra_car TEGRA114_CLK_SBC3>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 307 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 308 | resets = <&tegra_car 46>; |
| 309 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 310 | dmas = <&apbdma 17>, <&apbdma 17>; |
| 311 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 312 | status = "disabled"; |
| 313 | }; |
| 314 | |
| 315 | spi@7000da00 { |
| 316 | compatible = "nvidia,tegra114-spi"; |
| 317 | reg = <0x7000da00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 318 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 319 | nvidia,dma-request-selector = <&apbdma 18>; |
| 320 | #address-cells = <1>; |
| 321 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 322 | clocks = <&tegra_car TEGRA114_CLK_SBC4>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 323 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 324 | resets = <&tegra_car 68>; |
| 325 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 326 | dmas = <&apbdma 18>, <&apbdma 18>; |
| 327 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 328 | status = "disabled"; |
| 329 | }; |
| 330 | |
| 331 | spi@7000dc00 { |
| 332 | compatible = "nvidia,tegra114-spi"; |
| 333 | reg = <0x7000dc00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 334 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 335 | nvidia,dma-request-selector = <&apbdma 27>; |
| 336 | #address-cells = <1>; |
| 337 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 338 | clocks = <&tegra_car TEGRA114_CLK_SBC5>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 339 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 340 | resets = <&tegra_car 104>; |
| 341 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 342 | dmas = <&apbdma 27>, <&apbdma 27>; |
| 343 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 344 | status = "disabled"; |
| 345 | }; |
| 346 | |
| 347 | spi@7000de00 { |
| 348 | compatible = "nvidia,tegra114-spi"; |
| 349 | reg = <0x7000de00 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 350 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 351 | nvidia,dma-request-selector = <&apbdma 28>; |
| 352 | #address-cells = <1>; |
| 353 | #size-cells = <0>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 354 | clocks = <&tegra_car TEGRA114_CLK_SBC6>; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 355 | clock-names = "spi"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 356 | resets = <&tegra_car 105>; |
| 357 | reset-names = "spi"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 358 | dmas = <&apbdma 28>, <&apbdma 28>; |
| 359 | dma-names = "rx", "tx"; |
Laxman Dewangan | 6ea0297 | 2013-03-15 12:37:25 -0600 | [diff] [blame] | 360 | status = "disabled"; |
| 361 | }; |
| 362 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 363 | rtc { |
| 364 | compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; |
| 365 | reg = <0x7000e000 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 366 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 367 | clocks = <&tegra_car TEGRA114_CLK_RTC>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 368 | }; |
| 369 | |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 370 | kbc { |
| 371 | compatible = "nvidia,tegra114-kbc"; |
| 372 | reg = <0x7000e200 0x100>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 373 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 374 | clocks = <&tegra_car TEGRA114_CLK_KBC>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 375 | resets = <&tegra_car 36>; |
| 376 | reset-names = "kbc"; |
Laxman Dewangan | cd467b7 | 2013-03-14 01:19:53 +0530 | [diff] [blame] | 377 | status = "disabled"; |
| 378 | }; |
| 379 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 380 | pmc { |
Joseph Lo | 2b84e53 | 2013-02-26 16:27:43 +0000 | [diff] [blame] | 381 | compatible = "nvidia,tegra114-pmc"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 382 | reg = <0x7000e400 0x400>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 383 | clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 384 | clock-names = "pclk", "clk32k_in"; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 385 | }; |
| 386 | |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 387 | iommu { |
| 388 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
Hiroshi Doyu | 4cca9593 | 2013-10-30 17:17:48 -0600 | [diff] [blame] | 389 | reg = <0x70019010 0x02c |
| 390 | 0x700191f0 0x010 |
| 391 | 0x70019228 0x074>; |
Hiroshi Doyu | 2da1396 | 2013-01-15 10:17:28 +0200 | [diff] [blame] | 392 | nvidia,#asids = <4>; |
| 393 | dma-window = <0 0x40000000>; |
| 394 | nvidia,swgroups = <0x18659fe>; |
| 395 | nvidia,ahb = <&ahb>; |
| 396 | }; |
| 397 | |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 398 | ahub { |
| 399 | compatible = "nvidia,tegra114-ahub"; |
| 400 | reg = <0x70080000 0x200>, |
| 401 | <0x70080200 0x100>, |
| 402 | <0x70081000 0x200>; |
| 403 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| 404 | nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, |
| 405 | <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, |
| 406 | <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, |
| 407 | <&apbdma 29>; |
| 408 | clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, |
Stephen Warren | 2bd541f | 2013-11-07 10:59:42 -0700 | [diff] [blame^] | 409 | <&tegra_car TEGRA114_CLK_APBIF>; |
| 410 | clock-names = "d_audio", "apbif"; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 411 | resets = <&tegra_car 106>, /* d_audio */ |
| 412 | <&tegra_car 107>, /* apbif */ |
| 413 | <&tegra_car 30>, /* i2s0 */ |
| 414 | <&tegra_car 11>, /* i2s1 */ |
| 415 | <&tegra_car 18>, /* i2s2 */ |
| 416 | <&tegra_car 101>, /* i2s3 */ |
| 417 | <&tegra_car 102>, /* i2s4 */ |
| 418 | <&tegra_car 108>, /* dam0 */ |
| 419 | <&tegra_car 109>, /* dam1 */ |
| 420 | <&tegra_car 110>, /* dam2 */ |
| 421 | <&tegra_car 10>, /* spdif */ |
| 422 | <&tegra_car 153>, /* amx */ |
| 423 | <&tegra_car 154>; /* adx */ |
| 424 | reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
| 425 | "i2s3", "i2s4", "dam0", "dam1", "dam2", |
| 426 | "spdif", "amx", "adx"; |
Stephen Warren | 034d023 | 2013-11-11 13:05:59 -0700 | [diff] [blame] | 427 | dmas = <&apbdma 1>, <&apbdma 1>, |
| 428 | <&apbdma 2>, <&apbdma 2>, |
| 429 | <&apbdma 3>, <&apbdma 3>, |
| 430 | <&apbdma 4>, <&apbdma 4>, |
| 431 | <&apbdma 6>, <&apbdma 6>, |
| 432 | <&apbdma 7>, <&apbdma 7>, |
| 433 | <&apbdma 12>, <&apbdma 12>, |
| 434 | <&apbdma 13>, <&apbdma 13>, |
| 435 | <&apbdma 14>, <&apbdma 14>, |
| 436 | <&apbdma 29>, <&apbdma 29>; |
| 437 | dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", |
| 438 | "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", |
| 439 | "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", |
| 440 | "rx9", "tx9"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 441 | ranges; |
| 442 | #address-cells = <1>; |
| 443 | #size-cells = <1>; |
| 444 | |
| 445 | tegra_i2s0: i2s@70080300 { |
| 446 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 447 | reg = <0x70080300 0x100>; |
| 448 | nvidia,ahub-cif-ids = <4 4>; |
| 449 | clocks = <&tegra_car TEGRA114_CLK_I2S0>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 450 | resets = <&tegra_car 30>; |
| 451 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 452 | status = "disabled"; |
| 453 | }; |
| 454 | |
| 455 | tegra_i2s1: i2s@70080400 { |
| 456 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 457 | reg = <0x70080400 0x100>; |
| 458 | nvidia,ahub-cif-ids = <5 5>; |
| 459 | clocks = <&tegra_car TEGRA114_CLK_I2S1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 460 | resets = <&tegra_car 11>; |
| 461 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 462 | status = "disabled"; |
| 463 | }; |
| 464 | |
| 465 | tegra_i2s2: i2s@70080500 { |
| 466 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 467 | reg = <0x70080500 0x100>; |
| 468 | nvidia,ahub-cif-ids = <6 6>; |
| 469 | clocks = <&tegra_car TEGRA114_CLK_I2S2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 470 | resets = <&tegra_car 18>; |
| 471 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
| 475 | tegra_i2s3: i2s@70080600 { |
| 476 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 477 | reg = <0x70080600 0x100>; |
| 478 | nvidia,ahub-cif-ids = <7 7>; |
| 479 | clocks = <&tegra_car TEGRA114_CLK_I2S3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 480 | resets = <&tegra_car 101>; |
| 481 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 482 | status = "disabled"; |
| 483 | }; |
| 484 | |
| 485 | tegra_i2s4: i2s@70080700 { |
| 486 | compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; |
| 487 | reg = <0x70080700 0x100>; |
| 488 | nvidia,ahub-cif-ids = <8 8>; |
| 489 | clocks = <&tegra_car TEGRA114_CLK_I2S4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 490 | resets = <&tegra_car 102>; |
| 491 | reset-names = "i2s"; |
Stephen Warren | 15e5c64 | 2013-03-12 17:03:30 -0600 | [diff] [blame] | 492 | status = "disabled"; |
| 493 | }; |
| 494 | }; |
| 495 | |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 496 | sdhci@78000000 { |
| 497 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 498 | reg = <0x78000000 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 499 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 500 | clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 501 | resets = <&tegra_car 14>; |
| 502 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 503 | status = "disable"; |
| 504 | }; |
| 505 | |
| 506 | sdhci@78000200 { |
| 507 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 508 | reg = <0x78000200 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 509 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 510 | clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 511 | resets = <&tegra_car 9>; |
| 512 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 513 | status = "disable"; |
| 514 | }; |
| 515 | |
| 516 | sdhci@78000400 { |
| 517 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 518 | reg = <0x78000400 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 519 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 520 | clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 521 | resets = <&tegra_car 69>; |
| 522 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 523 | status = "disable"; |
| 524 | }; |
| 525 | |
| 526 | sdhci@78000600 { |
| 527 | compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; |
| 528 | reg = <0x78000600 0x200>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 529 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
Hiroshi Doyu | a1c8586 | 2013-05-22 19:45:36 +0300 | [diff] [blame] | 530 | clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 531 | resets = <&tegra_car 15>; |
| 532 | reset-names = "sdhci"; |
Pritesh Raithatha | 933d87a | 2013-02-20 13:35:14 -0500 | [diff] [blame] | 533 | status = "disable"; |
| 534 | }; |
| 535 | |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 536 | usb@7d000000 { |
| 537 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 538 | reg = <0x7d000000 0x4000>; |
| 539 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| 540 | phy_type = "utmi"; |
| 541 | clocks = <&tegra_car TEGRA114_CLK_USBD>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 542 | resets = <&tegra_car 22>; |
| 543 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 544 | nvidia,phy = <&phy1>; |
| 545 | status = "disabled"; |
| 546 | }; |
| 547 | |
| 548 | phy1: usb-phy@7d000000 { |
| 549 | compatible = "nvidia,tegra30-usb-phy"; |
| 550 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; |
| 551 | phy_type = "utmi"; |
| 552 | clocks = <&tegra_car TEGRA114_CLK_USBD>, |
| 553 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 554 | <&tegra_car TEGRA114_CLK_USBD>; |
| 555 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 556 | nvidia,hssync-start-delay = <0>; |
| 557 | nvidia,idle-wait-delay = <17>; |
| 558 | nvidia,elastic-limit = <16>; |
| 559 | nvidia,term-range-adj = <6>; |
| 560 | nvidia,xcvr-setup = <9>; |
| 561 | nvidia,xcvr-lsfslew = <0>; |
| 562 | nvidia,xcvr-lsrslew = <3>; |
| 563 | nvidia,hssquelch-level = <2>; |
| 564 | nvidia,hsdiscon-level = <5>; |
| 565 | nvidia,xcvr-hsslew = <12>; |
| 566 | status = "disabled"; |
| 567 | }; |
| 568 | |
| 569 | usb@7d008000 { |
| 570 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
| 571 | reg = <0x7d008000 0x4000>; |
| 572 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 573 | phy_type = "utmi"; |
| 574 | clocks = <&tegra_car TEGRA114_CLK_USB3>; |
Stephen Warren | 3393d42 | 2013-11-06 14:01:16 -0700 | [diff] [blame] | 575 | resets = <&tegra_car 59>; |
| 576 | reset-names = "usb"; |
Mikko Perttunen | 328dc0e | 2013-08-01 18:00:18 +0300 | [diff] [blame] | 577 | nvidia,phy = <&phy3>; |
| 578 | status = "disabled"; |
| 579 | }; |
| 580 | |
| 581 | phy3: usb-phy@7d008000 { |
| 582 | compatible = "nvidia,tegra30-usb-phy"; |
| 583 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; |
| 584 | phy_type = "utmi"; |
| 585 | clocks = <&tegra_car TEGRA114_CLK_USB3>, |
| 586 | <&tegra_car TEGRA114_CLK_PLL_U>, |
| 587 | <&tegra_car TEGRA114_CLK_USBD>; |
| 588 | clock-names = "reg", "pll_u", "utmi-pads"; |
| 589 | nvidia,hssync-start-delay = <0>; |
| 590 | nvidia,idle-wait-delay = <17>; |
| 591 | nvidia,elastic-limit = <16>; |
| 592 | nvidia,term-range-adj = <6>; |
| 593 | nvidia,xcvr-setup = <9>; |
| 594 | nvidia,xcvr-lsfslew = <0>; |
| 595 | nvidia,xcvr-lsrslew = <3>; |
| 596 | nvidia,hssquelch-level = <2>; |
| 597 | nvidia,hsdiscon-level = <5>; |
| 598 | nvidia,xcvr-hsslew = <12>; |
| 599 | status = "disabled"; |
| 600 | }; |
| 601 | |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 602 | cpus { |
| 603 | #address-cells = <1>; |
| 604 | #size-cells = <0>; |
| 605 | |
| 606 | cpu@0 { |
| 607 | device_type = "cpu"; |
| 608 | compatible = "arm,cortex-a15"; |
| 609 | reg = <0>; |
| 610 | }; |
| 611 | |
| 612 | cpu@1 { |
| 613 | device_type = "cpu"; |
| 614 | compatible = "arm,cortex-a15"; |
| 615 | reg = <1>; |
| 616 | }; |
| 617 | |
| 618 | cpu@2 { |
| 619 | device_type = "cpu"; |
| 620 | compatible = "arm,cortex-a15"; |
| 621 | reg = <2>; |
| 622 | }; |
| 623 | |
| 624 | cpu@3 { |
| 625 | device_type = "cpu"; |
| 626 | compatible = "arm,cortex-a15"; |
| 627 | reg = <3>; |
| 628 | }; |
| 629 | }; |
| 630 | |
| 631 | timer { |
| 632 | compatible = "arm,armv7-timer"; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 633 | interrupts = |
| 634 | <GIC_PPI 13 |
| 635 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 636 | <GIC_PPI 14 |
| 637 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 638 | <GIC_PPI 11 |
| 639 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 640 | <GIC_PPI 10 |
| 641 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
Hiroshi Doyu | 18a4df7 | 2013-01-24 01:10:23 +0000 | [diff] [blame] | 642 | }; |
| 643 | }; |