blob: cc46811e2d37e01f5abfec85d320035090bf4427 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33#include "drmP.h"
34#include "drm.h"
35#include "drm_sarea.h"
Ben Skeggs6ee73862009-12-11 19:24:15 +100036
Francisco Jerezcbab95db2010-10-11 03:43:58 +020037#include "nouveau_drv.h"
38#include "nouveau_pm.h"
Ben Skeggs573a2a32010-08-25 15:26:04 +100039#include "nouveau_mm.h"
Ben Skeggsa11c3192010-08-27 10:00:25 +100040#include "nouveau_vm.h"
Roy Splieta845fff2010-10-04 23:01:08 +020041
Ben Skeggs6ee73862009-12-11 19:24:15 +100042/*
Francisco Jereza0af9ad2009-12-11 16:51:09 +010043 * NV10-NV40 tiling helpers
44 */
45
46static void
Francisco Jereza5cf68b2010-10-24 16:14:41 +020047nv10_mem_update_tile_region(struct drm_device *dev,
48 struct nouveau_tile_reg *tile, uint32_t addr,
49 uint32_t size, uint32_t pitch, uint32_t flags)
Francisco Jereza0af9ad2009-12-11 16:51:09 +010050{
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
53 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
Ben Skeggs96c50082011-04-01 13:10:45 +100054 int i = tile - dev_priv->tile.reg, j;
Francisco Jereza5cf68b2010-10-24 16:14:41 +020055 unsigned long save;
Francisco Jereza0af9ad2009-12-11 16:51:09 +010056
Marcin Slusarz382d62e2010-10-20 21:50:24 +020057 nouveau_fence_unref(&tile->fence);
Francisco Jereza0af9ad2009-12-11 16:51:09 +010058
Francisco Jereza5cf68b2010-10-24 16:14:41 +020059 if (tile->pitch)
60 pfb->free_tile_region(dev, i);
61
62 if (pitch)
63 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
64
65 spin_lock_irqsave(&dev_priv->context_switch_lock, save);
Francisco Jereza0af9ad2009-12-11 16:51:09 +010066 pfifo->reassign(dev, false);
Francisco Jereza0af9ad2009-12-11 16:51:09 +010067 pfifo->cache_pull(dev, false);
68
69 nouveau_wait_for_idle(dev);
70
Francisco Jereza5cf68b2010-10-24 16:14:41 +020071 pfb->set_tile_region(dev, i);
Ben Skeggs96c50082011-04-01 13:10:45 +100072 for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
73 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
74 dev_priv->eng[j]->set_tile_region(dev, i);
75 }
Francisco Jereza0af9ad2009-12-11 16:51:09 +010076
77 pfifo->cache_pull(dev, true);
78 pfifo->reassign(dev, true);
Francisco Jereza5cf68b2010-10-24 16:14:41 +020079 spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
80}
81
82static struct nouveau_tile_reg *
83nv10_mem_get_tile_region(struct drm_device *dev, int i)
84{
85 struct drm_nouveau_private *dev_priv = dev->dev_private;
86 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
87
88 spin_lock(&dev_priv->tile.lock);
89
90 if (!tile->used &&
91 (!tile->fence || nouveau_fence_signalled(tile->fence)))
92 tile->used = true;
93 else
94 tile = NULL;
95
96 spin_unlock(&dev_priv->tile.lock);
97 return tile;
98}
99
100void
101nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
102 struct nouveau_fence *fence)
103{
104 struct drm_nouveau_private *dev_priv = dev->dev_private;
105
106 if (tile) {
107 spin_lock(&dev_priv->tile.lock);
108 if (fence) {
109 /* Mark it as pending. */
110 tile->fence = fence;
111 nouveau_fence_ref(fence);
112 }
113
114 tile->used = false;
115 spin_unlock(&dev_priv->tile.lock);
116 }
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100117}
118
119struct nouveau_tile_reg *
120nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200121 uint32_t pitch, uint32_t flags)
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100122{
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200125 struct nouveau_tile_reg *tile, *found = NULL;
126 int i;
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100127
128 for (i = 0; i < pfb->num_tiles; i++) {
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200129 tile = nv10_mem_get_tile_region(dev, i);
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100130
131 if (pitch && !found) {
Francisco Jerez9f56b122010-09-07 18:24:52 +0200132 found = tile;
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200133 continue;
134
135 } else if (tile && tile->pitch) {
136 /* Kill an unused tile region. */
137 nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100138 }
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200139
140 nv10_mem_put_tile_region(dev, tile, NULL);
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100141 }
142
Francisco Jereza5cf68b2010-10-24 16:14:41 +0200143 if (found)
144 nv10_mem_update_tile_region(dev, found, addr, size,
145 pitch, flags);
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100146 return found;
147}
148
Francisco Jereza0af9ad2009-12-11 16:51:09 +0100149/*
Ben Skeggs6ee73862009-12-11 19:24:15 +1000150 * Cleanup everything
151 */
Ben Skeggsb833ac22010-06-01 15:32:24 +1000152void
Ben Skeggsfbd28952010-09-01 15:24:34 +1000153nouveau_mem_vram_fini(struct drm_device *dev)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000154{
155 struct drm_nouveau_private *dev_priv = dev->dev_private;
156
Ben Skeggs6ee73862009-12-11 19:24:15 +1000157 ttm_bo_device_release(&dev_priv->ttm.bdev);
158
159 nouveau_ttm_global_release(dev_priv);
160
Ben Skeggsfbd28952010-09-01 15:24:34 +1000161 if (dev_priv->fb_mtrr >= 0) {
162 drm_mtrr_del(dev_priv->fb_mtrr,
163 pci_resource_start(dev->pdev, 1),
164 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
165 dev_priv->fb_mtrr = -1;
166 }
167}
168
169void
170nouveau_mem_gart_fini(struct drm_device *dev)
171{
172 nouveau_sgdma_takedown(dev);
173
Ben Skeggscd0b0722010-06-01 15:56:22 +1000174 if (drm_core_has_AGP(dev) && dev->agp) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000175 struct drm_agp_mem *entry, *tempe;
176
177 /* Remove AGP resources, but leave dev->agp
178 intact until drv_cleanup is called. */
179 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
180 if (entry->bound)
181 drm_unbind_agp(entry->memory);
182 drm_free_agp(entry->memory, entry->pages);
183 kfree(entry);
184 }
185 INIT_LIST_HEAD(&dev->agp->memory);
186
187 if (dev->agp->acquired)
188 drm_agp_release(dev);
189
190 dev->agp->acquired = 0;
191 dev->agp->enabled = 0;
192 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000193}
194
Ben Skeggs60d2a882010-12-06 15:28:54 +1000195bool
196nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
197{
198 if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
199 return true;
200
201 return false;
202}
203
Francisco Jerez71d06182010-09-08 02:23:20 +0200204#if __OS_HAS_AGP
205static unsigned long
206get_agp_mode(struct drm_device *dev, unsigned long mode)
207{
208 struct drm_nouveau_private *dev_priv = dev->dev_private;
209
210 /*
211 * FW seems to be broken on nv18, it makes the card lock up
212 * randomly.
213 */
214 if (dev_priv->chipset == 0x18)
215 mode &= ~PCI_AGP_COMMAND_FW;
216
Francisco Jerezde5899b2010-09-08 02:28:23 +0200217 /*
218 * AGP mode set in the command line.
219 */
220 if (nouveau_agpmode > 0) {
221 bool agpv3 = mode & 0x8;
222 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
223
224 mode = (mode & ~0x7) | (rate & 0x7);
225 }
226
Francisco Jerez71d06182010-09-08 02:23:20 +0200227 return mode;
228}
229#endif
230
Francisco Jereze04d8e82010-07-23 20:29:13 +0200231int
232nouveau_mem_reset_agp(struct drm_device *dev)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000233{
Francisco Jereze04d8e82010-07-23 20:29:13 +0200234#if __OS_HAS_AGP
235 uint32_t saved_pci_nv_1, pmc_enable;
236 int ret;
237
238 /* First of all, disable fast writes, otherwise if it's
239 * already enabled in the AGP bridge and we disable the card's
240 * AGP controller we might be locking ourselves out of it. */
Francisco Jerez316f60a2010-08-26 16:13:49 +0200241 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
242 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
Francisco Jereze04d8e82010-07-23 20:29:13 +0200243 struct drm_agp_info info;
244 struct drm_agp_mode mode;
245
246 ret = drm_agp_info(dev, &info);
247 if (ret)
248 return ret;
249
Francisco Jerez71d06182010-09-08 02:23:20 +0200250 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
Francisco Jereze04d8e82010-07-23 20:29:13 +0200251 ret = drm_agp_enable(dev, mode);
252 if (ret)
253 return ret;
254 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000255
256 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000257
258 /* clear busmaster bit */
259 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
Francisco Jereze04d8e82010-07-23 20:29:13 +0200260 /* disable AGP */
261 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000262
263 /* power cycle pgraph, if enabled */
264 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
265 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
266 nv_wr32(dev, NV03_PMC_ENABLE,
267 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
268 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
269 NV_PMC_ENABLE_PGRAPH);
270 }
271
272 /* and restore (gives effect of resetting AGP) */
Ben Skeggs6ee73862009-12-11 19:24:15 +1000273 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
Ben Skeggsb694dfb2009-12-15 10:38:32 +1000274#endif
Ben Skeggs6ee73862009-12-11 19:24:15 +1000275
Francisco Jereze04d8e82010-07-23 20:29:13 +0200276 return 0;
277}
278
Ben Skeggs6ee73862009-12-11 19:24:15 +1000279int
280nouveau_mem_init_agp(struct drm_device *dev)
281{
Ben Skeggsb694dfb2009-12-15 10:38:32 +1000282#if __OS_HAS_AGP
Ben Skeggs6ee73862009-12-11 19:24:15 +1000283 struct drm_nouveau_private *dev_priv = dev->dev_private;
284 struct drm_agp_info info;
285 struct drm_agp_mode mode;
286 int ret;
287
Ben Skeggs6ee73862009-12-11 19:24:15 +1000288 if (!dev->agp->acquired) {
289 ret = drm_agp_acquire(dev);
290 if (ret) {
291 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
292 return ret;
293 }
294 }
295
Francisco Jerez2b495262010-07-30 13:57:54 +0200296 nouveau_mem_reset_agp(dev);
297
Ben Skeggs6ee73862009-12-11 19:24:15 +1000298 ret = drm_agp_info(dev, &info);
299 if (ret) {
300 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
301 return ret;
302 }
303
304 /* see agp.h for the AGPSTAT_* modes available */
Francisco Jerez71d06182010-09-08 02:23:20 +0200305 mode.mode = get_agp_mode(dev, info.mode);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000306 ret = drm_agp_enable(dev, mode);
307 if (ret) {
308 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
309 return ret;
310 }
311
312 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
313 dev_priv->gart_info.aper_base = info.aperture_base;
314 dev_priv->gart_info.aper_size = info.aperture_size;
Ben Skeggsb694dfb2009-12-15 10:38:32 +1000315#endif
Ben Skeggs6ee73862009-12-11 19:24:15 +1000316 return 0;
317}
318
Ben Skeggs7ad2d312011-12-11 00:30:05 +1000319static const struct vram_types {
320 int value;
321 const char *name;
322} vram_type_map[] = {
323 { NV_MEM_TYPE_STOLEN , "stolen system memory" },
324 { NV_MEM_TYPE_SGRAM , "SGRAM" },
325 { NV_MEM_TYPE_SDRAM , "SDRAM" },
326 { NV_MEM_TYPE_DDR1 , "DDR1" },
327 { NV_MEM_TYPE_DDR2 , "DDR2" },
328 { NV_MEM_TYPE_DDR3 , "DDR3" },
329 { NV_MEM_TYPE_GDDR2 , "GDDR2" },
330 { NV_MEM_TYPE_GDDR3 , "GDDR3" },
331 { NV_MEM_TYPE_GDDR4 , "GDDR4" },
332 { NV_MEM_TYPE_GDDR5 , "GDDR5" },
333 { NV_MEM_TYPE_UNKNOWN, "unknown type" }
334};
335
Ben Skeggs6ee73862009-12-11 19:24:15 +1000336int
Ben Skeggsfbd28952010-09-01 15:24:34 +1000337nouveau_mem_vram_init(struct drm_device *dev)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000338{
339 struct drm_nouveau_private *dev_priv = dev->dev_private;
340 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
Ben Skeggs7ad2d312011-12-11 00:30:05 +1000341 const struct vram_types *vram_type;
Ben Skeggsfbd28952010-09-01 15:24:34 +1000342 int ret, dma_bits;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000343
Ben Skeggse0435122011-01-11 15:50:26 +1000344 dma_bits = 32;
345 if (dev_priv->card_type >= NV_50) {
346 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
347 dma_bits = 40;
348 } else
Jon Mason58b65422011-06-27 16:07:50 +0000349 if (0 && pci_is_pcie(dev->pdev) &&
Ben Skeggs01d15332011-04-08 10:07:34 +1000350 dev_priv->chipset > 0x40 &&
Ben Skeggse0435122011-01-11 15:50:26 +1000351 dev_priv->chipset != 0x45) {
352 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
353 dma_bits = 39;
354 }
Ben Skeggs6ee73862009-12-11 19:24:15 +1000355
356 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
Ben Skeggsfbd28952010-09-01 15:24:34 +1000357 if (ret)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000358 return ret;
Konrad Rzeszutek Wilk3230cfc2011-10-17 17:14:26 -0400359 ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
360 if (ret) {
361 /* Reset to default value. */
362 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
363 }
364
Ben Skeggsfbd28952010-09-01 15:24:34 +1000365
Ben Skeggs6ee73862009-12-11 19:24:15 +1000366 ret = nouveau_ttm_global_init(dev_priv);
367 if (ret)
368 return ret;
369
370 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
371 dev_priv->ttm.bo_global_ref.ref.object,
372 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
373 dma_bits <= 32 ? true : false);
374 if (ret) {
375 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
376 return ret;
377 }
378
Ben Skeggs7ad2d312011-12-11 00:30:05 +1000379 vram_type = vram_type_map;
380 while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
381 if (nouveau_vram_type) {
382 if (!strcasecmp(nouveau_vram_type, vram_type->name))
383 break;
384 dev_priv->vram_type = vram_type->value;
385 } else {
386 if (vram_type->value == dev_priv->vram_type)
387 break;
388 }
389 vram_type++;
390 }
391
392 NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
393 (int)(dev_priv->vram_size >> 20), vram_type->name);
Ben Skeggs60d2a882010-12-06 15:28:54 +1000394 if (dev_priv->vram_sys_base) {
395 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
396 dev_priv->vram_sys_base);
397 }
398
Ben Skeggs573a2a32010-08-25 15:26:04 +1000399 dev_priv->fb_available_size = dev_priv->vram_size;
400 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
401 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
402 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
403 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
404
Ben Skeggs6ee73862009-12-11 19:24:15 +1000405 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
406 dev_priv->fb_aper_free = dev_priv->fb_available_size;
407
408 /* mappable vram */
409 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
410 dev_priv->fb_available_size >> PAGE_SHIFT);
411 if (ret) {
412 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
413 return ret;
414 }
415
Ben Skeggsd550c412011-02-16 08:41:56 +1000416 if (dev_priv->card_type < NV_50) {
Ben Skeggs7375c952011-06-07 14:21:29 +1000417 ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
Ben Skeggsd550c412011-02-16 08:41:56 +1000418 0, 0, &dev_priv->vga_ram);
419 if (ret == 0)
420 ret = nouveau_bo_pin(dev_priv->vga_ram,
421 TTM_PL_FLAG_VRAM);
422
423 if (ret) {
424 NV_WARN(dev, "failed to reserve VGA memory\n");
425 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
426 }
Ben Skeggsac8fb972010-01-15 09:24:20 +1000427 }
428
Ben Skeggsfbd28952010-09-01 15:24:34 +1000429 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
430 pci_resource_len(dev->pdev, 1),
431 DRM_MTRR_WC);
432 return 0;
433}
434
435int
436nouveau_mem_gart_init(struct drm_device *dev)
437{
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
440 int ret;
441
442 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
443
Ben Skeggs6ee73862009-12-11 19:24:15 +1000444#if !defined(__powerpc__) && !defined(__ia64__)
Dave Airlie8410ea32010-12-15 03:16:38 +1000445 if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000446 ret = nouveau_mem_init_agp(dev);
447 if (ret)
448 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
449 }
450#endif
451
452 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
453 ret = nouveau_sgdma_init(dev);
454 if (ret) {
455 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
456 return ret;
457 }
458 }
459
460 NV_INFO(dev, "%d MiB GART (aperture)\n",
461 (int)(dev_priv->gart_info.aper_size >> 20));
462 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
463
464 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
465 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
466 if (ret) {
467 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
468 return ret;
469 }
470
Ben Skeggs6ee73862009-12-11 19:24:15 +1000471 return 0;
472}
473
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000474static int
475nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
476 struct nouveau_pm_tbl_entry *e, u8 len,
477 struct nouveau_pm_memtiming *boot,
478 struct nouveau_pm_memtiming *t)
Martin Peresddb20052011-12-17 12:24:59 +0100479{
Roy Splietc7c039f2012-01-09 15:23:07 +1000480 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
Roy Spliet9a782482011-07-09 21:18:11 +0200481
482 /* XXX: I don't trust the -1's and +1's... they must come
483 * from somewhere! */
Roy Splietc7c039f2012-01-09 15:23:07 +1000484 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
485 1 << 16 |
486 (e->tWTR + 2 + (t->tCWL - 1)) << 8 |
487 (e->tCL + 2 - (t->tCWL - 1));
Roy Splietbfb31462011-11-25 15:52:22 +0100488
Roy Splietc7c039f2012-01-09 15:23:07 +1000489 t->reg[2] = 0x20200000 |
490 ((t->tCWL - 1) << 24 |
491 e->tRRD << 16 |
492 e->tRCDWR << 8 |
493 e->tRCDRD);
Roy Spliet9a782482011-07-09 21:18:11 +0200494
Roy Splietc7c039f2012-01-09 15:23:07 +1000495 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id,
496 t->reg[0], t->reg[1], t->reg[2]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000497 return 0;
Roy Spliet9a782482011-07-09 21:18:11 +0200498}
499
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000500static int
501nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
502 struct nouveau_pm_tbl_entry *e, u8 len,
503 struct nouveau_pm_memtiming *boot,
504 struct nouveau_pm_memtiming *t)
Martin Peresddb20052011-12-17 12:24:59 +0100505{
Roy Spliet9a782482011-07-09 21:18:11 +0200506 struct drm_nouveau_private *dev_priv = dev->dev_private;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000507 struct bit_entry P;
Roy Splietc7c039f2012-01-09 15:23:07 +1000508 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
Roy Spliet9a782482011-07-09 21:18:11 +0200509
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000510 if (bit_table(dev, 'P', &P))
511 return -EINVAL;
512
513 switch (min(len, (u8) 22)) {
Roy Spliet9a782482011-07-09 21:18:11 +0200514 case 22:
515 unk21 = e->tUNK_21;
516 case 21:
517 unk20 = e->tUNK_20;
518 case 20:
Roy Splietbfb31462011-11-25 15:52:22 +0100519 if (e->tCWL > 0)
Roy Splietc7c039f2012-01-09 15:23:07 +1000520 t->tCWL = e->tCWL;
Roy Spliet9a782482011-07-09 21:18:11 +0200521 case 19:
522 unk18 = e->tUNK_18;
523 break;
524 }
525
Roy Splietc7c039f2012-01-09 15:23:07 +1000526 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
Roy Spliet9a782482011-07-09 21:18:11 +0200527
Roy Splietc7c039f2012-01-09 15:23:07 +1000528 t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 |
Roy Splietbfb31462011-11-25 15:52:22 +0100529 max(unk18, (u8) 1) << 16 |
Roy Splietc7c039f2012-01-09 15:23:07 +1000530 (e->tWTR + 2 + (t->tCWL - 1)) << 8;
Martin Peresddb20052011-12-17 12:24:59 +0100531
Roy Splietc7c039f2012-01-09 15:23:07 +1000532 t->reg[2] = ((t->tCWL - 1) << 24 |
533 e->tRRD << 16 |
534 e->tRCDWR << 8 |
535 e->tRCDRD);
Roy Spliet9a782482011-07-09 21:18:11 +0200536
Roy Splietc7c039f2012-01-09 15:23:07 +1000537 t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13;
Roy Splietbfb31462011-11-25 15:52:22 +0100538
Roy Splietc7c039f2012-01-09 15:23:07 +1000539 t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP);
Roy Splietbfb31462011-11-25 15:52:22 +0100540
Roy Splietc7c039f2012-01-09 15:23:07 +1000541 t->reg[8] = boot->reg[8] & 0xffffff00;
Roy Spliet9a782482011-07-09 21:18:11 +0200542
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000543 if (P.version == 1) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000544 t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1));
Martin Peresddb20052011-12-17 12:24:59 +0100545
Roy Splietc7c039f2012-01-09 15:23:07 +1000546 t->reg[3] = (0x14 + e->tCL) << 24 |
547 0x16 << 16 |
548 (e->tCL - 1) << 8 |
549 (e->tCL - 1);
Martin Peresddb20052011-12-17 12:24:59 +0100550
Roy Splietc7c039f2012-01-09 15:23:07 +1000551 t->reg[4] |= boot->reg[4] & 0xffff0000;
Martin Peresddb20052011-12-17 12:24:59 +0100552
Roy Splietc7c039f2012-01-09 15:23:07 +1000553 t->reg[6] = (0x33 - t->tCWL) << 16 |
554 t->tCWL << 8 |
555 (0x2e + e->tCL - t->tCWL);
Martin Peresddb20052011-12-17 12:24:59 +0100556
Roy Splietc7c039f2012-01-09 15:23:07 +1000557 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
Roy Spliet9a782482011-07-09 21:18:11 +0200558
Roy Splietbfb31462011-11-25 15:52:22 +0100559 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
560 if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000561 t->reg[5] |= (e->tCL + 3) << 8;
562 t->reg[6] |= (t->tCWL - 2) << 8;
563 t->reg[8] |= (e->tCL - 4);
Roy Splietbfb31462011-11-25 15:52:22 +0100564 } else {
Roy Splietc7c039f2012-01-09 15:23:07 +1000565 t->reg[5] |= (e->tCL + 2) << 8;
566 t->reg[6] |= t->tCWL << 8;
567 t->reg[8] |= (e->tCL - 2);
Roy Splietbfb31462011-11-25 15:52:22 +0100568 }
569 } else {
Roy Splietc7c039f2012-01-09 15:23:07 +1000570 t->reg[1] |= (5 + e->tCL - (t->tCWL));
Roy Splietbfb31462011-11-25 15:52:22 +0100571
572 /* XXX: 0xb? 0x30? */
Roy Splietc7c039f2012-01-09 15:23:07 +1000573 t->reg[3] = (0x30 + e->tCL) << 24 |
574 (boot->reg[3] & 0x00ff0000)|
575 (0xb + e->tCL) << 8 |
576 (e->tCL - 1);
Roy Splietbfb31462011-11-25 15:52:22 +0100577
Roy Splietc7c039f2012-01-09 15:23:07 +1000578 t->reg[4] |= (unk20 << 24 | unk21 << 16);
Roy Splietbfb31462011-11-25 15:52:22 +0100579
580 /* XXX: +6? */
Roy Splietc7c039f2012-01-09 15:23:07 +1000581 t->reg[5] |= (t->tCWL + 6) << 8;
Roy Splietbfb31462011-11-25 15:52:22 +0100582
Roy Splietc7c039f2012-01-09 15:23:07 +1000583 t->reg[6] = (0x5a + e->tCL) << 16 |
584 (6 - e->tCL + t->tCWL) << 8 |
585 (0x50 + e->tCL - t->tCWL);
Roy Splietbfb31462011-11-25 15:52:22 +0100586
Roy Splietc7c039f2012-01-09 15:23:07 +1000587 tmp7_3 = (boot->reg[7] & 0xff000000) >> 24;
588 t->reg[7] = (tmp7_3 << 24) |
589 ((tmp7_3 - 6 + e->tCL) << 16) |
590 0x202;
Roy Spliet9a782482011-07-09 21:18:11 +0200591 }
592
Roy Splietc7c039f2012-01-09 15:23:07 +1000593 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
594 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
Roy Spliet9a782482011-07-09 21:18:11 +0200595 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
Roy Splietc7c039f2012-01-09 15:23:07 +1000596 t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
597 NV_DEBUG(dev, " 240: %08x\n", t->reg[8]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000598 return 0;
Roy Spliet9a782482011-07-09 21:18:11 +0200599}
600
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000601static int
602nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
603 struct nouveau_pm_tbl_entry *e, u8 len,
604 struct nouveau_pm_memtiming *boot,
605 struct nouveau_pm_memtiming *t)
Martin Peresddb20052011-12-17 12:24:59 +0100606{
Roy Splietc7c039f2012-01-09 15:23:07 +1000607 if (e->tCWL > 0)
608 t->tCWL = e->tCWL;
Roy Splietbfb31462011-11-25 15:52:22 +0100609
Roy Splietc7c039f2012-01-09 15:23:07 +1000610 t->reg[0] = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
611 e->tRFC << 8 | e->tRC);
Martin Peresddb20052011-12-17 12:24:59 +0100612
Roy Splietc7c039f2012-01-09 15:23:07 +1000613 t->reg[1] = (boot->reg[1] & 0xff000000) |
614 (e->tRCDWR & 0x0f) << 20 |
615 (e->tRCDRD & 0x0f) << 14 |
616 (e->tCWL << 7) |
617 (e->tCL & 0x0f);
Martin Peresddb20052011-12-17 12:24:59 +0100618
Roy Splietc7c039f2012-01-09 15:23:07 +1000619 t->reg[2] = (boot->reg[2] & 0xff0000ff) |
620 e->tWR << 16 | e->tWTR << 8;
Martin Peresddb20052011-12-17 12:24:59 +0100621
Roy Splietc7c039f2012-01-09 15:23:07 +1000622 t->reg[3] = (e->tUNK_20 & 0xf) << 9 |
623 (e->tUNK_21 & 0xf) << 5 |
624 (e->tUNK_13 & 0x1f);
Martin Peresddb20052011-12-17 12:24:59 +0100625
Roy Splietc7c039f2012-01-09 15:23:07 +1000626 t->reg[4] = (boot->reg[4] & 0xfff00fff) |
627 (e->tRRD&0x1f) << 15;
Martin Peresddb20052011-12-17 12:24:59 +0100628
Roy Splietc7c039f2012-01-09 15:23:07 +1000629 NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
630 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
631 NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000632 return 0;
Roy Splietbfb31462011-11-25 15:52:22 +0100633}
634
Roy Splietc7c039f2012-01-09 15:23:07 +1000635/**
636 * MR generation methods
637 */
638
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000639static int
640nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
641 struct nouveau_pm_tbl_entry *e, u8 len,
642 struct nouveau_pm_memtiming *boot,
643 struct nouveau_pm_memtiming *t)
Roy Splietbfb31462011-11-25 15:52:22 +0100644{
Roy Splietc7c039f2012-01-09 15:23:07 +1000645 t->drive_strength = 0;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000646 if (len < 15) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000647 t->odt = boot->odt;
648 } else {
649 t->odt = e->RAM_FT1 & 0x07;
Roy Splietbfb31462011-11-25 15:52:22 +0100650 }
Roy Splietc7c039f2012-01-09 15:23:07 +1000651
652 if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
653 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000654 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000655 }
656
657 if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
658 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000659 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000660 }
661
662 if (t->odt > 3) {
663 NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x",
664 t->id, t->odt);
665 t->odt = 0;
666 }
667
668 t->mr[0] = (boot->mr[0] & 0x100f) |
669 (e->tCL) << 4 |
670 (e->tWR - 1) << 9;
671 t->mr[1] = (boot->mr[1] & 0x101fbb) |
672 (t->odt & 0x1) << 2 |
673 (t->odt & 0x2) << 5;
674
675 NV_DEBUG(dev, "(%u) MR: %08x", t->id, t->mr[0]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000676 return 0;
Roy Splietc7c039f2012-01-09 15:23:07 +1000677}
678
679uint8_t nv_mem_wr_lut_ddr3[NV_MEM_WR_DDR3_MAX] = {
680 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
681
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000682static int
683nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
684 struct nouveau_pm_tbl_entry *e, u8 len,
685 struct nouveau_pm_memtiming *boot,
686 struct nouveau_pm_memtiming *t)
Roy Splietc7c039f2012-01-09 15:23:07 +1000687{
688 u8 cl = e->tCL - 4;
689
690 t->drive_strength = 0;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000691 if (len < 15) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000692 t->odt = boot->odt;
693 } else {
694 t->odt = e->RAM_FT1 & 0x07;
695 }
696
697 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
698 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000699 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000700 }
701
702 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
703 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000704 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000705 }
706
707 if (e->tCWL < 5) {
708 NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000709 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000710 }
711
712 t->mr[0] = (boot->mr[0] & 0x180b) |
713 /* CAS */
714 (cl & 0x7) << 4 |
715 (cl & 0x8) >> 1 |
716 (nv_mem_wr_lut_ddr3[e->tWR]) << 9;
717 t->mr[1] = (boot->mr[1] & 0x101dbb) |
718 (t->odt & 0x1) << 2 |
719 (t->odt & 0x2) << 5 |
720 (t->odt & 0x4) << 7;
721 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
722
723 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000724 return 0;
Roy Splietc7c039f2012-01-09 15:23:07 +1000725}
726
727uint8_t nv_mem_cl_lut_gddr3[NV_MEM_CL_GDDR3_MAX] = {
728 0, 0, 0, 0, 4, 5, 6, 7, 0, 1, 2, 3, 8, 9, 10, 11};
729uint8_t nv_mem_wr_lut_gddr3[NV_MEM_WR_GDDR3_MAX] = {
730 0, 0, 0, 0, 0, 2, 3, 8, 9, 10, 11, 0, 0, 1, 1, 0, 3};
731
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000732static int
733nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
734 struct nouveau_pm_tbl_entry *e, u8 len,
735 struct nouveau_pm_memtiming *boot,
736 struct nouveau_pm_memtiming *t)
Roy Splietc7c039f2012-01-09 15:23:07 +1000737{
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000738 if (len < 15) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000739 t->drive_strength = boot->drive_strength;
740 t->odt = boot->odt;
741 } else {
742 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
743 t->odt = e->RAM_FT1 & 0x07;
744 }
745
746 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
747 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000748 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000749 }
750
751 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
752 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000753 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000754 }
755
756 if (t->odt > 3) {
757 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
758 t->id, t->odt);
759 t->odt = 0;
760 }
761
762 t->mr[0] = (boot->mr[0] & 0xe0b) |
763 /* CAS */
764 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
765 ((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
766 t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
767 (t->odt << 2) |
768 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
769
770 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000771 return 0;
Roy Splietc7c039f2012-01-09 15:23:07 +1000772}
773
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000774static int
775nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
776 struct nouveau_pm_tbl_entry *e, u8 len,
777 struct nouveau_pm_memtiming *boot,
778 struct nouveau_pm_memtiming *t)
Roy Splietc7c039f2012-01-09 15:23:07 +1000779{
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000780 if (len < 15) {
Roy Splietc7c039f2012-01-09 15:23:07 +1000781 t->drive_strength = boot->drive_strength;
782 t->odt = boot->odt;
783 } else {
784 t->drive_strength = (e->RAM_FT1 & 0x30) >> 4;
785 t->odt = e->RAM_FT1 & 0x03;
786 }
787
788 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
789 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000790 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000791 }
792
793 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
794 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000795 return -ERANGE;
Roy Splietc7c039f2012-01-09 15:23:07 +1000796 }
797
798 if (t->odt > 3) {
799 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x",
800 t->id, t->odt);
801 t->odt = 0;
802 }
803
804 t->mr[0] = (boot->mr[0] & 0x007) |
805 ((e->tCL - 5) << 3) |
806 ((e->tWR - 4) << 8);
807 t->mr[1] = (boot->mr[1] & 0x1007f0) |
808 t->drive_strength |
809 (t->odt << 2);
810
811 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000812 return 0;
Roy Splietc7c039f2012-01-09 15:23:07 +1000813}
814
Ben Skeggs085028c2012-01-18 09:02:28 +1000815int
816nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
817 struct nouveau_pm_memtiming *t)
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000818{
819 struct drm_nouveau_private *dev_priv = dev->dev_private;
820 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
Ben Skeggs085028c2012-01-18 09:02:28 +1000821 struct nouveau_pm_memtiming *boot = &pm->boot.timing;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000822 struct nouveau_pm_tbl_entry *e;
823 u8 ver, len, *ptr;
824 int ret;
825
826 ptr = nouveau_perf_timing(dev, freq, &ver, &len);
Ben Skeggs085028c2012-01-18 09:02:28 +1000827 if (!ptr || ptr[0] == 0x00) {
828 *t = *boot;
829 return 0;
830 }
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000831 e = (struct nouveau_pm_tbl_entry *)ptr;
832
Ben Skeggs085028c2012-01-18 09:02:28 +1000833 t->tCWL = boot->tCWL;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000834
Ben Skeggs085028c2012-01-18 09:02:28 +1000835 switch (dev_priv->card_type) {
836 case NV_40:
837 ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
838 break;
839 case NV_50:
840 ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t);
841 break;
842 case NV_C0:
843 ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t);
844 break;
845 default:
846 ret = -ENODEV;
847 break;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000848 }
849
Ben Skeggs085028c2012-01-18 09:02:28 +1000850 switch (dev_priv->vram_type * !ret) {
851 case NV_MEM_TYPE_GDDR3:
852 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
853 break;
854 case NV_MEM_TYPE_GDDR5:
855 ret = nouveau_mem_gddr5_mr(dev, freq, e, len, boot, t);
856 break;
857 case NV_MEM_TYPE_DDR2:
858 ret = nouveau_mem_ddr2_mr(dev, freq, e, len, boot, t);
859 break;
860 case NV_MEM_TYPE_DDR3:
861 ret = nouveau_mem_ddr3_mr(dev, freq, e, len, boot, t);
862 break;
863 default:
864 ret = -EINVAL;
865 }
866
867 return ret;
Ben Skeggsfd99fd62012-01-17 21:10:58 +1000868}
869
870void
871nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
Roy Splietc7c039f2012-01-09 15:23:07 +1000872{
873 struct drm_nouveau_private *dev_priv = dev->dev_private;
874 u32 timing_base, timing_regs, mr_base;
875 int i;
876
877 if (dev_priv->card_type >= 0xC0) {
878 timing_base = 0x10f290;
879 mr_base = 0x10f300;
880 } else {
881 timing_base = 0x100220;
882 mr_base = 0x1002c0;
883 }
884
885 t->id = -1;
886
887 switch (dev_priv->card_type) {
888 case NV_50:
889 timing_regs = 9;
890 break;
891 case NV_C0:
892 case NV_D0:
893 timing_regs = 5;
894 break;
895 case NV_30:
896 case NV_40:
897 timing_regs = 3;
898 break;
899 default:
900 timing_regs = 0;
901 return;
902 }
903 for(i = 0; i < timing_regs; i++)
904 t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i));
905
906 t->tCWL = 0;
907 if (dev_priv->card_type < NV_C0) {
908 t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
909 }
910
911 t->mr[0] = nv_rd32(dev, mr_base);
912 t->mr[1] = nv_rd32(dev, mr_base + 0x04);
913 t->mr[2] = nv_rd32(dev, mr_base + 0x20);
914 t->mr[3] = nv_rd32(dev, mr_base + 0x24);
915
916 t->odt = 0;
917 t->drive_strength = 0;
918
919 switch (dev_priv->vram_type) {
920 case NV_MEM_TYPE_DDR3:
921 t->odt |= (t->mr[1] & 0x200) >> 7;
922 case NV_MEM_TYPE_DDR2:
923 t->odt |= (t->mr[1] & 0x04) >> 2 |
924 (t->mr[1] & 0x40) >> 5;
925 break;
926 case NV_MEM_TYPE_GDDR3:
927 case NV_MEM_TYPE_GDDR5:
928 t->drive_strength = t->mr[1] & 0x03;
929 t->odt = (t->mr[1] & 0x0c) >> 2;
930 break;
931 default:
932 break;
933 }
934}
935
Ben Skeggsc70c41e2011-12-13 11:57:55 +1000936int
937nouveau_mem_vbios_type(struct drm_device *dev)
938{
939 struct bit_entry M;
940 u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
941 if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
942 u8 *table = ROMPTR(dev, M.data[3]);
943 if (table && table[0] == 0x10 && ramcfg < table[3]) {
944 u8 *entry = table + table[1] + (ramcfg * table[2]);
945 switch (entry[0] & 0x0f) {
946 case 0: return NV_MEM_TYPE_DDR2;
947 case 1: return NV_MEM_TYPE_DDR3;
948 case 2: return NV_MEM_TYPE_GDDR3;
949 case 3: return NV_MEM_TYPE_GDDR5;
950 default:
951 break;
952 }
953
954 }
955 }
956 return NV_MEM_TYPE_UNKNOWN;
957}
958
Ben Skeggs573a2a32010-08-25 15:26:04 +1000959static int
Ben Skeggs24f246a2011-06-10 13:36:08 +1000960nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
Ben Skeggs573a2a32010-08-25 15:26:04 +1000961{
Ben Skeggs24f246a2011-06-10 13:36:08 +1000962 /* nothing to do */
Ben Skeggs573a2a32010-08-25 15:26:04 +1000963 return 0;
964}
965
966static int
967nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
968{
Ben Skeggs24f246a2011-06-10 13:36:08 +1000969 /* nothing to do */
Ben Skeggs573a2a32010-08-25 15:26:04 +1000970 return 0;
971}
972
Ben Skeggsd2f966662011-06-06 20:54:42 +1000973static inline void
974nouveau_mem_node_cleanup(struct nouveau_mem *node)
975{
976 if (node->vma[0].node) {
977 nouveau_vm_unmap(&node->vma[0]);
978 nouveau_vm_put(&node->vma[0]);
979 }
980
981 if (node->vma[1].node) {
982 nouveau_vm_unmap(&node->vma[1]);
983 nouveau_vm_put(&node->vma[1]);
984 }
985}
986
Ben Skeggs573a2a32010-08-25 15:26:04 +1000987static void
988nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
989 struct ttm_mem_reg *mem)
990{
991 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
Ben Skeggs60d2a882010-12-06 15:28:54 +1000992 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
Ben Skeggs573a2a32010-08-25 15:26:04 +1000993 struct drm_device *dev = dev_priv->dev;
994
Ben Skeggsd2f966662011-06-06 20:54:42 +1000995 nouveau_mem_node_cleanup(mem->mm_node);
Ben Skeggsd5f42392011-02-10 12:22:52 +1000996 vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
Ben Skeggs573a2a32010-08-25 15:26:04 +1000997}
998
999static int
1000nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
1001 struct ttm_buffer_object *bo,
1002 struct ttm_placement *placement,
1003 struct ttm_mem_reg *mem)
1004{
1005 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
Ben Skeggs60d2a882010-12-06 15:28:54 +10001006 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
Ben Skeggs573a2a32010-08-25 15:26:04 +10001007 struct drm_device *dev = dev_priv->dev;
1008 struct nouveau_bo *nvbo = nouveau_bo(bo);
Ben Skeggsd5f42392011-02-10 12:22:52 +10001009 struct nouveau_mem *node;
Ben Skeggs5f6fdca2010-11-12 15:13:59 +10001010 u32 size_nc = 0;
Ben Skeggs573a2a32010-08-25 15:26:04 +10001011 int ret;
1012
Ben Skeggs5f6fdca2010-11-12 15:13:59 +10001013 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
Ben Skeggsf91bac52011-06-06 14:15:46 +10001014 size_nc = 1 << nvbo->page_shift;
Ben Skeggs5f6fdca2010-11-12 15:13:59 +10001015
Ben Skeggs60d2a882010-12-06 15:28:54 +10001016 ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
1017 mem->page_alignment << PAGE_SHIFT, size_nc,
Ben Skeggs8f7286f2011-02-14 09:57:35 +10001018 (nvbo->tile_flags >> 8) & 0x3ff, &node);
Ben Skeggsef1b2872011-03-07 17:18:03 +10001019 if (ret) {
1020 mem->mm_node = NULL;
1021 return (ret == -ENOSPC) ? 0 : ret;
1022 }
Ben Skeggs573a2a32010-08-25 15:26:04 +10001023
Ben Skeggsf91bac52011-06-06 14:15:46 +10001024 node->page_shift = nvbo->page_shift;
Ben Skeggs4c74eb72010-11-10 14:10:04 +10001025
Ben Skeggs60d2a882010-12-06 15:28:54 +10001026 mem->mm_node = node;
1027 mem->start = node->offset >> PAGE_SHIFT;
Ben Skeggs573a2a32010-08-25 15:26:04 +10001028 return 0;
1029}
1030
1031void
1032nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
1033{
Ben Skeggs573a2a32010-08-25 15:26:04 +10001034 struct nouveau_mm *mm = man->priv;
1035 struct nouveau_mm_node *r;
Ben Skeggs8b464bf2011-01-14 15:46:30 +10001036 u32 total = 0, free = 0;
Ben Skeggs573a2a32010-08-25 15:26:04 +10001037
1038 mutex_lock(&mm->mutex);
1039 list_for_each_entry(r, &mm->nodes, nl_entry) {
Ben Skeggs8b464bf2011-01-14 15:46:30 +10001040 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
1041 prefix, r->type, ((u64)r->offset << 12),
Ben Skeggs573a2a32010-08-25 15:26:04 +10001042 (((u64)r->offset + r->length) << 12));
Ben Skeggs8b464bf2011-01-14 15:46:30 +10001043
Ben Skeggs573a2a32010-08-25 15:26:04 +10001044 total += r->length;
Ben Skeggs8b464bf2011-01-14 15:46:30 +10001045 if (!r->type)
1046 free += r->length;
Ben Skeggs573a2a32010-08-25 15:26:04 +10001047 }
1048 mutex_unlock(&mm->mutex);
1049
Ben Skeggs8b464bf2011-01-14 15:46:30 +10001050 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
1051 prefix, (u64)total << 12, (u64)free << 12);
1052 printk(KERN_DEBUG "%s block: 0x%08x\n",
1053 prefix, mm->block_size << 12);
Ben Skeggs573a2a32010-08-25 15:26:04 +10001054}
1055
1056const struct ttm_mem_type_manager_func nouveau_vram_manager = {
1057 nouveau_vram_manager_init,
1058 nouveau_vram_manager_fini,
1059 nouveau_vram_manager_new,
1060 nouveau_vram_manager_del,
1061 nouveau_vram_manager_debug
1062};
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001063
1064static int
1065nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
1066{
1067 return 0;
1068}
1069
1070static int
1071nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
1072{
1073 return 0;
1074}
1075
1076static void
1077nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
1078 struct ttm_mem_reg *mem)
1079{
Ben Skeggsd2f966662011-06-06 20:54:42 +10001080 nouveau_mem_node_cleanup(mem->mm_node);
Ben Skeggsd2f966662011-06-06 20:54:42 +10001081 kfree(mem->mm_node);
Marcin Slusarz0de53a52011-06-23 16:35:31 +02001082 mem->mm_node = NULL;
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001083}
1084
1085static int
1086nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
1087 struct ttm_buffer_object *bo,
1088 struct ttm_placement *placement,
1089 struct ttm_mem_reg *mem)
1090{
1091 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001092 struct nouveau_mem *node;
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001093
1094 if (unlikely((mem->num_pages << PAGE_SHIFT) >=
1095 dev_priv->gart_info.aper_size))
1096 return -ENOMEM;
1097
1098 node = kzalloc(sizeof(*node), GFP_KERNEL);
1099 if (!node)
1100 return -ENOMEM;
Ben Skeggsd2f966662011-06-06 20:54:42 +10001101 node->page_shift = 12;
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001102
Ben Skeggs26c0c9e2011-02-10 12:59:51 +10001103 mem->mm_node = node;
1104 mem->start = 0;
1105 return 0;
1106}
1107
1108void
1109nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
1110{
1111}
1112
1113const struct ttm_mem_type_manager_func nouveau_gart_manager = {
1114 nouveau_gart_manager_init,
1115 nouveau_gart_manager_fini,
1116 nouveau_gart_manager_new,
1117 nouveau_gart_manager_del,
1118 nouveau_gart_manager_debug
1119};