blob: de6da957a09d6ebe82f416370c84a7dc50acea8e [file] [log] [blame]
Steffen Trumtrar97259e92014-01-06 10:27:37 -06001/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Based from clk-highbank.c
16 *
17 */
18#include <linux/clk.h>
19#include <linux/clkdev.h>
20#include <linux/clk-provider.h>
21#include <linux/io.h>
22#include <linux/of.h>
Dinh Nguyena30d27e2014-04-14 07:59:32 -050023#include <linux/of_address.h>
Steffen Trumtrar97259e92014-01-06 10:27:37 -060024
25#include "clk.h"
26
27/* Clock bypass bits */
28#define MAINPLL_BYPASS (1<<0)
29#define SDRAMPLL_BYPASS (1<<1)
30#define SDRAMPLL_SRC_BYPASS (1<<2)
31#define PERPLL_BYPASS (1<<3)
32#define PERPLL_SRC_BYPASS (1<<4)
33
34#define SOCFPGA_PLL_BG_PWRDWN 0
35#define SOCFPGA_PLL_EXT_ENA 1
36#define SOCFPGA_PLL_PWR_DOWN 2
37#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
38#define SOCFPGA_PLL_DIVF_SHIFT 3
39#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
40#define SOCFPGA_PLL_DIVQ_SHIFT 16
41
Dinh Nguyenb89cd952014-02-19 15:11:11 -060042#define CLK_MGR_PLL_CLK_SRC_SHIFT 22
43#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
44
Steffen Trumtrar97259e92014-01-06 10:27:37 -060045#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
46
Dinh Nguyena30d27e2014-04-14 07:59:32 -050047void __iomem *clk_mgr_base_addr;
48
Steffen Trumtrar97259e92014-01-06 10:27:37 -060049static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
50 unsigned long parent_rate)
51{
52 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
Dinh Nguyen5585f732014-02-19 15:11:10 -060053 unsigned long divf, divq, reg;
54 unsigned long long vco_freq;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060055 unsigned long bypass;
56
57 reg = readl(socfpgaclk->hw.reg);
58 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
59 if (bypass & MAINPLL_BYPASS)
60 return parent_rate;
61
62 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
63 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
Dinh Nguyen5585f732014-02-19 15:11:10 -060064 vco_freq = (unsigned long long)parent_rate * (divf + 1);
65 do_div(vco_freq, (1 + divq));
66 return (unsigned long)vco_freq;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060067}
68
Dinh Nguyenb89cd952014-02-19 15:11:11 -060069static u8 clk_pll_get_parent(struct clk_hw *hwclk)
70{
71 u32 pll_src;
72 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
73
74 pll_src = readl(socfpgaclk->hw.reg);
75 return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
76 CLK_MGR_PLL_CLK_SRC_MASK;
77}
78
Steffen Trumtrar97259e92014-01-06 10:27:37 -060079static struct clk_ops clk_pll_ops = {
80 .recalc_rate = clk_pll_recalc_rate,
Dinh Nguyenb89cd952014-02-19 15:11:11 -060081 .get_parent = clk_pll_get_parent,
Steffen Trumtrar97259e92014-01-06 10:27:37 -060082};
83
84static __init struct clk *__socfpga_pll_init(struct device_node *node,
85 const struct clk_ops *ops)
86{
87 u32 reg;
88 struct clk *clk;
89 struct socfpga_pll *pll_clk;
90 const char *clk_name = node->name;
Dinh Nguyenb89cd952014-02-19 15:11:11 -060091 const char *parent_name[SOCFPGA_MAX_PARENTS];
Steffen Trumtrar97259e92014-01-06 10:27:37 -060092 struct clk_init_data init;
Dinh Nguyena30d27e2014-04-14 07:59:32 -050093 struct device_node *clkmgr_np;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060094 int rc;
Dinh Nguyenb89cd952014-02-19 15:11:11 -060095 int i = 0;
Steffen Trumtrar97259e92014-01-06 10:27:37 -060096
97 of_property_read_u32(node, "reg", &reg);
98
99 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
100 if (WARN_ON(!pll_clk))
101 return NULL;
102
Dinh Nguyena30d27e2014-04-14 07:59:32 -0500103 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
104 clk_mgr_base_addr = of_iomap(clkmgr_np, 0);
105 BUG_ON(!clk_mgr_base_addr);
Steffen Trumtrar97259e92014-01-06 10:27:37 -0600106 pll_clk->hw.reg = clk_mgr_base_addr + reg;
107
108 of_property_read_string(node, "clock-output-names", &clk_name);
109
110 init.name = clk_name;
111 init.ops = ops;
112 init.flags = 0;
Steffen Trumtrar97259e92014-01-06 10:27:37 -0600113
Dinh Nguyenb89cd952014-02-19 15:11:11 -0600114 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
115 of_clk_get_parent_name(node, i)) != NULL)
116 i++;
117
118 init.num_parents = i;
119 init.parent_names = parent_name;
Steffen Trumtrar97259e92014-01-06 10:27:37 -0600120 pll_clk->hw.hw.init = &init;
121
122 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
123 clk_pll_ops.enable = clk_gate_ops.enable;
124 clk_pll_ops.disable = clk_gate_ops.disable;
125
126 clk = clk_register(NULL, &pll_clk->hw.hw);
127 if (WARN_ON(IS_ERR(clk))) {
128 kfree(pll_clk);
129 return NULL;
130 }
131 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
132 return clk;
133}
134
135void __init socfpga_pll_init(struct device_node *node)
136{
137 __socfpga_pll_init(node, &clk_pll_ops);
138}