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gerrit-public.fairphone.software / kernel / msm-4.9 / 2fd149645eb46d26130d7070c6de037dddf34880 / . / arch / arm / plat-omap / include / plat / omap-serial.h
blob: 9ff444469f3d9a1add04cda94c4b7d9247b5ea4a [file] [log] [blame]
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
Govindraj.R2fd14962011-11-09 17:41:21 +0530[diff] [blame^]22#include <linux/pm_qos.h>
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]23
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]24#include <plat/mux.h>
25
Benoit Cousson374b8cf2010-12-09 14:24:17 +0000[diff] [blame]26#define DRIVER_NAME "omap_uart"
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]27
28/*
29 * Use tty device name as ttyO, [O -> OMAP]
30 * in bootargs we specify as console=ttyO0 if uart1
31 * is used as console uart.
32 */
33#define OMAP_SERIAL_NAME "ttyO"
34
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]35#define OMAP_MODE13X_SPEED 230400
36
Govindraj.R32212892011-11-07 18:58:55 +0530[diff] [blame]37#define OMAP_UART_SCR_TX_EMPTY 0x08
38
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]39/* WER = 0x7F
40 * Enable module level wakeup in WER reg
41 */
42#define OMAP_UART_WER_MOD_WKUP 0X7F
43
44/* Enable XON/XOFF flow control on output */
45#define OMAP_UART_SW_TX 0x04
46
47/* Enable XON/XOFF flow control on input */
48#define OMAP_UART_SW_RX 0x04
49
50#define OMAP_UART_SYSC_RESET 0X07
51#define OMAP_UART_TCR_TRIG 0X0F
52#define OMAP_UART_SW_CLR 0XF0
53#define OMAP_UART_FIFO_CLR 0X06
54
55#define OMAP_UART_DMA_CH_FREE -1
56
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]57#define OMAP_MAX_HSUART_PORTS 4
58
59#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
60
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]61#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
62#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
63
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]64struct omap_uart_port_info {
65 bool dma_enabled; /* To specify DMA Mode */
66 unsigned int uartclk; /* UART clock rate */
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]67 upf_t flags; /* UPF_* flags */
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]68 u32 errata;
Deepak Kc86845db2011-11-09 17:33:38 +0530[diff] [blame]69 unsigned int dma_rx_buf_size;
70 unsigned int dma_rx_timeout;
71 unsigned int autosuspend_timeout;
Jon Huntera9e210e2011-11-09 17:34:49 +0530[diff] [blame]72 unsigned int dma_rx_poll_rate;
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame]73
74 int (*get_context_loss_count)(struct device *);
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]75 void (*set_forceidle)(struct platform_device *);
76 void (*set_noidle)(struct platform_device *);
Govindraj.R62f3ec5f2011-10-13 14:11:09 +0530[diff] [blame]77 void (*enable_wakeup)(struct platform_device *, bool);
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]78};
79
80struct uart_omap_dma {
81 u8 uart_dma_tx;
82 u8 uart_dma_rx;
83 int rx_dma_channel;
84 int tx_dma_channel;
85 dma_addr_t rx_buf_dma_phys;
86 dma_addr_t tx_buf_dma_phys;
87 unsigned int uart_base;
88 /*
89 * Buffer for rx dma.It is not required for tx because the buffer
90 * comes from port structure.
91 */
92 unsigned char *rx_buf;
93 unsigned int prev_rx_dma_pos;
94 int tx_buf_size;
95 int tx_dma_used;
96 int rx_dma_used;
97 spinlock_t tx_lock;
98 spinlock_t rx_lock;
99 /* timer to poll activity on rx dma */
100 struct timer_list rx_timer;
Deepak Kc86845db2011-11-09 17:33:38 +0530[diff] [blame]101 unsigned int rx_buf_size;
Jon Huntera9e210e2011-11-09 17:34:49 +0530[diff] [blame]102 unsigned int rx_poll_rate;
Deepak Kc86845db2011-11-09 17:33:38 +0530[diff] [blame]103 unsigned int rx_timeout;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]104};
105
106struct uart_omap_port {
107 struct uart_port port;
108 struct uart_omap_dma uart_dma;
109 struct platform_device *pdev;
110
111 unsigned char ier;
112 unsigned char lcr;
113 unsigned char mcr;
114 unsigned char fcr;
115 unsigned char efr;
Govindraj.Rc538d202011-11-07 18:57:03 +0530[diff] [blame]116 unsigned char dll;
117 unsigned char dlh;
118 unsigned char mdr1;
119 unsigned char scr;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]120
121 int use_dma;
122 /*
123 * Some bits in registers are cleared on a read, so they must
124 * be saved whenever the register is read but the bits will not
125 * be immediately processed.
126 */
127 unsigned int lsr_break_flag;
128 unsigned char msr_saved_flags;
129 char name[20];
130 unsigned long port_activity;
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame]131 u32 context_loss_cnt;
Govindraj.R94734742011-11-07 19:00:33 +0530[diff] [blame]132 u32 errata;
Govindraj.R62f3ec5f2011-10-13 14:11:09 +0530[diff] [blame]133 u8 wakeups_enabled;
Govindraj.R2fd14962011-11-09 17:41:21 +0530[diff] [blame^]134
135 struct pm_qos_request pm_qos_request;
136 u32 latency;
137 u32 calc_latency;
138 struct work_struct qos_work;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]139};
140
141#endif /* __OMAP_SERIAL_H__ */