blob: b3807edb19365e79e61bf392a66c22156803859e [file] [log] [blame]
Dave Airlie551ebd82009-09-01 15:25:57 +10001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
Dave Airlie551ebd82009-09-01 15:25:57 +100030#include "radeon_reg.h"
31#include "radeon.h"
Daniel Vettere6990372010-03-11 21:19:17 +000032#include "radeon_asic.h"
Dave Airlie551ebd82009-09-01 15:25:57 +100033
Pauli Nieminen44ca7472010-02-11 17:25:47 +000034#include "r100d.h"
Dave Airlie551ebd82009-09-01 15:25:57 +100035#include "r200_reg_safe.h"
36
37#include "r100_track.h"
38
39static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
40{
41 int vtx_size, i;
42 vtx_size = 2;
43
44 if (vtx_fmt_0 & R200_VTX_Z0)
45 vtx_size++;
46 if (vtx_fmt_0 & R200_VTX_W0)
47 vtx_size++;
48 /* blend weight */
49 if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
50 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
51 if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
52 vtx_size++;
53 if (vtx_fmt_0 & R200_VTX_N0)
54 vtx_size += 3;
55 if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
56 vtx_size++;
57 if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
58 vtx_size++;
59 if (vtx_fmt_0 & R200_VTX_SHININESS_0)
60 vtx_size++;
61 if (vtx_fmt_0 & R200_VTX_SHININESS_1)
62 vtx_size++;
63 for (i = 0; i < 8; i++) {
64 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
65 switch (color_size) {
66 case 0: break;
67 case 1: vtx_size++; break;
68 case 2: vtx_size += 3; break;
69 case 3: vtx_size += 4; break;
70 }
71 }
72 if (vtx_fmt_0 & R200_VTX_XY1)
73 vtx_size += 2;
74 if (vtx_fmt_0 & R200_VTX_Z1)
75 vtx_size++;
76 if (vtx_fmt_0 & R200_VTX_W1)
77 vtx_size++;
78 if (vtx_fmt_0 & R200_VTX_N1)
79 vtx_size += 3;
80 return vtx_size;
81}
82
Pauli Nieminen44ca7472010-02-11 17:25:47 +000083int r200_copy_dma(struct radeon_device *rdev,
84 uint64_t src_offset,
85 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -040086 unsigned num_gpu_pages,
Christian König876dc9f2012-05-08 14:24:01 +020087 struct radeon_fence **fence)
Pauli Nieminen44ca7472010-02-11 17:25:47 +000088{
Christian Könige32eb502011-10-23 12:56:27 +020089 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
Pauli Nieminen44ca7472010-02-11 17:25:47 +000090 uint32_t size;
91 uint32_t cur_size;
92 int i, num_loops;
93 int r = 0;
94
95 /* radeon pitch is /64 */
Alex Deucher003cefe2011-09-16 12:04:08 -040096 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
Pauli Nieminen44ca7472010-02-11 17:25:47 +000097 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
Christian Könige32eb502011-10-23 12:56:27 +020098 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64);
Pauli Nieminen44ca7472010-02-11 17:25:47 +000099 if (r) {
100 DRM_ERROR("radeon: moving bo (%d).\n", r);
101 return r;
102 }
103 /* Must wait for 2D idle & clean before DMA or hangs might happen */
Christian Könige32eb502011-10-23 12:56:27 +0200104 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
105 radeon_ring_write(ring, (1 << 16));
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000106 for (i = 0; i < num_loops; i++) {
107 cur_size = size;
108 if (cur_size > 0x1FFFFF) {
109 cur_size = 0x1FFFFF;
110 }
111 size -= cur_size;
Christian Könige32eb502011-10-23 12:56:27 +0200112 radeon_ring_write(ring, PACKET0(0x720, 2));
113 radeon_ring_write(ring, src_offset);
114 radeon_ring_write(ring, dst_offset);
115 radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000116 src_offset += cur_size;
117 dst_offset += cur_size;
118 }
Christian Könige32eb502011-10-23 12:56:27 +0200119 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
120 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000121 if (fence) {
Christian König876dc9f2012-05-08 14:24:01 +0200122 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000123 }
Christian Könige32eb502011-10-23 12:56:27 +0200124 radeon_ring_unlock_commit(rdev, ring);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000125 return r;
126}
127
128
Dave Airlie551ebd82009-09-01 15:25:57 +1000129static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
130{
131 int vtx_size, i, tex_size;
132 vtx_size = 0;
133 for (i = 0; i < 6; i++) {
134 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
135 if (tex_size > 4)
136 continue;
137 vtx_size += tex_size;
138 }
139 return vtx_size;
140}
141
142int r200_packet0_check(struct radeon_cs_parser *p,
143 struct radeon_cs_packet *pkt,
144 unsigned idx, unsigned reg)
145{
Dave Airlie551ebd82009-09-01 15:25:57 +1000146 struct radeon_cs_reloc *reloc;
147 struct r100_cs_track *track;
148 volatile uint32_t *ib;
149 uint32_t tmp;
150 int r;
151 int i;
152 int face;
153 u32 tile_flags = 0;
Dave Airlie513bcb42009-09-23 16:56:27 +1000154 u32 idx_value;
Dave Airlie551ebd82009-09-01 15:25:57 +1000155
Jerome Glissef2e39222012-05-09 15:35:02 +0200156 ib = p->ib.ptr;
Dave Airlie551ebd82009-09-01 15:25:57 +1000157 track = (struct r100_cs_track *)p->track;
Dave Airlie513bcb42009-09-23 16:56:27 +1000158 idx_value = radeon_get_ib_value(p, idx);
Dave Airlie551ebd82009-09-01 15:25:57 +1000159 switch (reg) {
160 case RADEON_CRTC_GUI_TRIG_VLINE:
161 r = r100_cs_packet_parse_vline(p);
162 if (r) {
163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
164 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500165 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000166 return r;
167 }
168 break;
169 /* FIXME: only allow PACKET3 blit? easier to check for out of
170 * range access */
171 case RADEON_DST_PITCH_OFFSET:
172 case RADEON_SRC_PITCH_OFFSET:
173 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
174 if (r)
175 return r;
176 break;
177 case RADEON_RB3D_DEPTHOFFSET:
Ilija Hadzic012e9762013-01-02 18:27:47 -0500178 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000179 if (r) {
180 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
181 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500182 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000183 return r;
184 }
185 track->zb.robj = reloc->robj;
Dave Airlie513bcb42009-09-23 16:56:27 +1000186 track->zb.offset = idx_value;
Marek Olšák40b4a752011-02-12 19:21:35 +0100187 track->zb_dirty = true;
Dave Airlie513bcb42009-09-23 16:56:27 +1000188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
Dave Airlie551ebd82009-09-01 15:25:57 +1000189 break;
190 case RADEON_RB3D_COLOROFFSET:
Ilija Hadzic012e9762013-01-02 18:27:47 -0500191 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000192 if (r) {
193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
194 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500195 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000196 return r;
197 }
198 track->cb[0].robj = reloc->robj;
Dave Airlie513bcb42009-09-23 16:56:27 +1000199 track->cb[0].offset = idx_value;
Marek Olšák40b4a752011-02-12 19:21:35 +0100200 track->cb_dirty = true;
Dave Airlie513bcb42009-09-23 16:56:27 +1000201 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
Dave Airlie551ebd82009-09-01 15:25:57 +1000202 break;
203 case R200_PP_TXOFFSET_0:
204 case R200_PP_TXOFFSET_1:
205 case R200_PP_TXOFFSET_2:
206 case R200_PP_TXOFFSET_3:
207 case R200_PP_TXOFFSET_4:
208 case R200_PP_TXOFFSET_5:
209 i = (reg - R200_PP_TXOFFSET_0) / 24;
Ilija Hadzic012e9762013-01-02 18:27:47 -0500210 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000211 if (r) {
212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
213 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500214 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000215 return r;
216 }
Alex Deucherf2746f82012-02-02 10:11:12 -0500217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
218 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
219 tile_flags |= R200_TXO_MACRO_TILE;
220 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
221 tile_flags |= R200_TXO_MICRO_TILE;
222
223 tmp = idx_value & ~(0x7 << 2);
224 tmp |= tile_flags;
225 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
226 } else
227 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
Dave Airlie551ebd82009-09-01 15:25:57 +1000228 track->textures[i].robj = reloc->robj;
Marek Olšák40b4a752011-02-12 19:21:35 +0100229 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000230 break;
231 case R200_PP_CUBIC_OFFSET_F1_0:
232 case R200_PP_CUBIC_OFFSET_F2_0:
233 case R200_PP_CUBIC_OFFSET_F3_0:
234 case R200_PP_CUBIC_OFFSET_F4_0:
235 case R200_PP_CUBIC_OFFSET_F5_0:
236 case R200_PP_CUBIC_OFFSET_F1_1:
237 case R200_PP_CUBIC_OFFSET_F2_1:
238 case R200_PP_CUBIC_OFFSET_F3_1:
239 case R200_PP_CUBIC_OFFSET_F4_1:
240 case R200_PP_CUBIC_OFFSET_F5_1:
241 case R200_PP_CUBIC_OFFSET_F1_2:
242 case R200_PP_CUBIC_OFFSET_F2_2:
243 case R200_PP_CUBIC_OFFSET_F3_2:
244 case R200_PP_CUBIC_OFFSET_F4_2:
245 case R200_PP_CUBIC_OFFSET_F5_2:
246 case R200_PP_CUBIC_OFFSET_F1_3:
247 case R200_PP_CUBIC_OFFSET_F2_3:
248 case R200_PP_CUBIC_OFFSET_F3_3:
249 case R200_PP_CUBIC_OFFSET_F4_3:
250 case R200_PP_CUBIC_OFFSET_F5_3:
251 case R200_PP_CUBIC_OFFSET_F1_4:
252 case R200_PP_CUBIC_OFFSET_F2_4:
253 case R200_PP_CUBIC_OFFSET_F3_4:
254 case R200_PP_CUBIC_OFFSET_F4_4:
255 case R200_PP_CUBIC_OFFSET_F5_4:
256 case R200_PP_CUBIC_OFFSET_F1_5:
257 case R200_PP_CUBIC_OFFSET_F2_5:
258 case R200_PP_CUBIC_OFFSET_F3_5:
259 case R200_PP_CUBIC_OFFSET_F4_5:
260 case R200_PP_CUBIC_OFFSET_F5_5:
261 i = (reg - R200_PP_TXOFFSET_0) / 24;
262 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
Ilija Hadzic012e9762013-01-02 18:27:47 -0500263 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000264 if (r) {
265 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
266 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500267 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000268 return r;
269 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000270 track->textures[i].cube_info[face - 1].offset = idx_value;
271 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
Dave Airlie551ebd82009-09-01 15:25:57 +1000272 track->textures[i].cube_info[face - 1].robj = reloc->robj;
Marek Olšák40b4a752011-02-12 19:21:35 +0100273 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000274 break;
275 case RADEON_RE_WIDTH_HEIGHT:
Dave Airlie513bcb42009-09-23 16:56:27 +1000276 track->maxy = ((idx_value >> 16) & 0x7FF);
Marek Olšák40b4a752011-02-12 19:21:35 +0100277 track->cb_dirty = true;
278 track->zb_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000279 break;
280 case RADEON_RB3D_COLORPITCH:
Ilija Hadzic012e9762013-01-02 18:27:47 -0500281 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000282 if (r) {
283 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
284 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500285 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000286 return r;
287 }
288
Alex Deucherc9068eb2012-02-02 10:11:11 -0500289 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
290 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
291 tile_flags |= RADEON_COLOR_TILE_ENABLE;
292 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
293 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
Dave Airlie551ebd82009-09-01 15:25:57 +1000294
Alex Deucherc9068eb2012-02-02 10:11:11 -0500295 tmp = idx_value & ~(0x7 << 16);
296 tmp |= tile_flags;
297 ib[idx] = tmp;
298 } else
299 ib[idx] = idx_value;
Dave Airlie551ebd82009-09-01 15:25:57 +1000300
Dave Airlie513bcb42009-09-23 16:56:27 +1000301 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
Marek Olšák40b4a752011-02-12 19:21:35 +0100302 track->cb_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000303 break;
304 case RADEON_RB3D_DEPTHPITCH:
Dave Airlie513bcb42009-09-23 16:56:27 +1000305 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
Marek Olšák40b4a752011-02-12 19:21:35 +0100306 track->zb_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000307 break;
308 case RADEON_RB3D_CNTL:
Dave Airlie513bcb42009-09-23 16:56:27 +1000309 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
Dave Airlie551ebd82009-09-01 15:25:57 +1000310 case 7:
311 case 8:
312 case 9:
313 case 11:
314 case 12:
315 track->cb[0].cpp = 1;
316 break;
317 case 3:
318 case 4:
319 case 15:
320 track->cb[0].cpp = 2;
321 break;
322 case 6:
323 track->cb[0].cpp = 4;
324 break;
325 default:
326 DRM_ERROR("Invalid color buffer format (%d) !\n",
Dave Airlie513bcb42009-09-23 16:56:27 +1000327 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
Dave Airlie551ebd82009-09-01 15:25:57 +1000328 return -EINVAL;
329 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000330 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
Dave Airlie551ebd82009-09-01 15:25:57 +1000331 DRM_ERROR("No support for depth xy offset in kms\n");
332 return -EINVAL;
333 }
334
Dave Airlie513bcb42009-09-23 16:56:27 +1000335 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
Marek Olšák40b4a752011-02-12 19:21:35 +0100336 track->cb_dirty = true;
337 track->zb_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000338 break;
339 case RADEON_RB3D_ZSTENCILCNTL:
Dave Airlie513bcb42009-09-23 16:56:27 +1000340 switch (idx_value & 0xf) {
Dave Airlie551ebd82009-09-01 15:25:57 +1000341 case 0:
342 track->zb.cpp = 2;
343 break;
344 case 2:
345 case 3:
346 case 4:
347 case 5:
348 case 9:
349 case 11:
350 track->zb.cpp = 4;
351 break;
352 default:
353 break;
354 }
Marek Olšák40b4a752011-02-12 19:21:35 +0100355 track->zb_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000356 break;
357 case RADEON_RB3D_ZPASS_ADDR:
Ilija Hadzic012e9762013-01-02 18:27:47 -0500358 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
Dave Airlie551ebd82009-09-01 15:25:57 +1000359 if (r) {
360 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
361 idx, reg);
Ilija Hadzicc3ad63a2013-01-02 18:27:45 -0500362 radeon_cs_dump_packet(p, pkt);
Dave Airlie551ebd82009-09-01 15:25:57 +1000363 return r;
364 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000365 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
Dave Airlie551ebd82009-09-01 15:25:57 +1000366 break;
367 case RADEON_PP_CNTL:
368 {
Dave Airlie513bcb42009-09-23 16:56:27 +1000369 uint32_t temp = idx_value >> 4;
Dave Airlie551ebd82009-09-01 15:25:57 +1000370 for (i = 0; i < track->num_texture; i++)
371 track->textures[i].enabled = !!(temp & (1 << i));
Marek Olšák40b4a752011-02-12 19:21:35 +0100372 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000373 }
374 break;
375 case RADEON_SE_VF_CNTL:
Dave Airlie513bcb42009-09-23 16:56:27 +1000376 track->vap_vf_cntl = idx_value;
Dave Airlie551ebd82009-09-01 15:25:57 +1000377 break;
378 case 0x210c:
379 /* VAP_VF_MAX_VTX_INDX */
Dave Airlie513bcb42009-09-23 16:56:27 +1000380 track->max_indx = idx_value & 0x00FFFFFFUL;
Dave Airlie551ebd82009-09-01 15:25:57 +1000381 break;
382 case R200_SE_VTX_FMT_0:
Dave Airlie513bcb42009-09-23 16:56:27 +1000383 track->vtx_size = r200_get_vtx_size_0(idx_value);
Dave Airlie551ebd82009-09-01 15:25:57 +1000384 break;
385 case R200_SE_VTX_FMT_1:
Dave Airlie513bcb42009-09-23 16:56:27 +1000386 track->vtx_size += r200_get_vtx_size_1(idx_value);
Dave Airlie551ebd82009-09-01 15:25:57 +1000387 break;
388 case R200_PP_TXSIZE_0:
389 case R200_PP_TXSIZE_1:
390 case R200_PP_TXSIZE_2:
391 case R200_PP_TXSIZE_3:
392 case R200_PP_TXSIZE_4:
393 case R200_PP_TXSIZE_5:
394 i = (reg - R200_PP_TXSIZE_0) / 32;
Dave Airlie513bcb42009-09-23 16:56:27 +1000395 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
396 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
Marek Olšák40b4a752011-02-12 19:21:35 +0100397 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000398 break;
399 case R200_PP_TXPITCH_0:
400 case R200_PP_TXPITCH_1:
401 case R200_PP_TXPITCH_2:
402 case R200_PP_TXPITCH_3:
403 case R200_PP_TXPITCH_4:
404 case R200_PP_TXPITCH_5:
405 i = (reg - R200_PP_TXPITCH_0) / 32;
Dave Airlie513bcb42009-09-23 16:56:27 +1000406 track->textures[i].pitch = idx_value + 32;
Marek Olšák40b4a752011-02-12 19:21:35 +0100407 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000408 break;
409 case R200_PP_TXFILTER_0:
410 case R200_PP_TXFILTER_1:
411 case R200_PP_TXFILTER_2:
412 case R200_PP_TXFILTER_3:
413 case R200_PP_TXFILTER_4:
414 case R200_PP_TXFILTER_5:
415 i = (reg - R200_PP_TXFILTER_0) / 32;
Dave Airlie513bcb42009-09-23 16:56:27 +1000416 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
Dave Airlie551ebd82009-09-01 15:25:57 +1000417 >> R200_MAX_MIP_LEVEL_SHIFT);
Dave Airlie513bcb42009-09-23 16:56:27 +1000418 tmp = (idx_value >> 23) & 0x7;
Dave Airlie551ebd82009-09-01 15:25:57 +1000419 if (tmp == 2 || tmp == 6)
420 track->textures[i].roundup_w = false;
Dave Airlie513bcb42009-09-23 16:56:27 +1000421 tmp = (idx_value >> 27) & 0x7;
Dave Airlie551ebd82009-09-01 15:25:57 +1000422 if (tmp == 2 || tmp == 6)
423 track->textures[i].roundup_h = false;
Marek Olšák40b4a752011-02-12 19:21:35 +0100424 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000425 break;
426 case R200_PP_TXMULTI_CTL_0:
427 case R200_PP_TXMULTI_CTL_1:
428 case R200_PP_TXMULTI_CTL_2:
429 case R200_PP_TXMULTI_CTL_3:
430 case R200_PP_TXMULTI_CTL_4:
431 case R200_PP_TXMULTI_CTL_5:
432 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
433 break;
434 case R200_PP_TXFORMAT_X_0:
435 case R200_PP_TXFORMAT_X_1:
436 case R200_PP_TXFORMAT_X_2:
437 case R200_PP_TXFORMAT_X_3:
438 case R200_PP_TXFORMAT_X_4:
439 case R200_PP_TXFORMAT_X_5:
440 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
Dave Airlie513bcb42009-09-23 16:56:27 +1000441 track->textures[i].txdepth = idx_value & 0x7;
442 tmp = (idx_value >> 16) & 0x3;
Dave Airlie551ebd82009-09-01 15:25:57 +1000443 /* 2D, 3D, CUBE */
444 switch (tmp) {
445 case 0:
Roland Scheidegger688acaa2010-06-12 13:31:10 -0400446 case 3:
447 case 4:
Dave Airlie551ebd82009-09-01 15:25:57 +1000448 case 5:
449 case 6:
450 case 7:
Andrew Randrianasuluf3d1ccc2010-01-20 11:36:30 -0500451 /* 1D/2D */
Dave Airlie551ebd82009-09-01 15:25:57 +1000452 track->textures[i].tex_coord_type = 0;
453 break;
454 case 1:
Andrew Randrianasuluf3d1ccc2010-01-20 11:36:30 -0500455 /* CUBE */
456 track->textures[i].tex_coord_type = 2;
Dave Airlie551ebd82009-09-01 15:25:57 +1000457 break;
458 case 2:
Andrew Randrianasuluf3d1ccc2010-01-20 11:36:30 -0500459 /* 3D */
460 track->textures[i].tex_coord_type = 1;
Dave Airlie551ebd82009-09-01 15:25:57 +1000461 break;
462 }
Marek Olšák40b4a752011-02-12 19:21:35 +0100463 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000464 break;
465 case R200_PP_TXFORMAT_0:
466 case R200_PP_TXFORMAT_1:
467 case R200_PP_TXFORMAT_2:
468 case R200_PP_TXFORMAT_3:
469 case R200_PP_TXFORMAT_4:
470 case R200_PP_TXFORMAT_5:
471 i = (reg - R200_PP_TXFORMAT_0) / 32;
Dave Airlie513bcb42009-09-23 16:56:27 +1000472 if (idx_value & R200_TXFORMAT_NON_POWER2) {
Dave Airlie551ebd82009-09-01 15:25:57 +1000473 track->textures[i].use_pitch = 1;
474 } else {
475 track->textures[i].use_pitch = 0;
Dave Airlie513bcb42009-09-23 16:56:27 +1000476 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
477 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
Dave Airlie551ebd82009-09-01 15:25:57 +1000478 }
Alex Deucher43b93fb2010-10-27 01:02:35 -0400479 if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
480 track->textures[i].lookup_disable = true;
Dave Airlie513bcb42009-09-23 16:56:27 +1000481 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
Dave Airlie551ebd82009-09-01 15:25:57 +1000482 case R200_TXFORMAT_I8:
483 case R200_TXFORMAT_RGB332:
484 case R200_TXFORMAT_Y8:
485 track->textures[i].cpp = 1;
Roland Scheideggerf9da52d2010-06-12 12:12:37 -0400486 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
Dave Airlie551ebd82009-09-01 15:25:57 +1000487 break;
Dave Airlie551ebd82009-09-01 15:25:57 +1000488 case R200_TXFORMAT_AI88:
489 case R200_TXFORMAT_ARGB1555:
490 case R200_TXFORMAT_RGB565:
491 case R200_TXFORMAT_ARGB4444:
492 case R200_TXFORMAT_VYUY422:
493 case R200_TXFORMAT_YVYU422:
494 case R200_TXFORMAT_LDVDU655:
495 case R200_TXFORMAT_DVDU88:
496 case R200_TXFORMAT_AVYU4444:
497 track->textures[i].cpp = 2;
Roland Scheideggerf9da52d2010-06-12 12:12:37 -0400498 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
Dave Airlie551ebd82009-09-01 15:25:57 +1000499 break;
500 case R200_TXFORMAT_ARGB8888:
501 case R200_TXFORMAT_RGBA8888:
502 case R200_TXFORMAT_ABGR8888:
503 case R200_TXFORMAT_BGR111110:
504 case R200_TXFORMAT_LDVDU8888:
Dave Airlied785d782009-12-07 13:16:06 +1000505 track->textures[i].cpp = 4;
Roland Scheideggerf9da52d2010-06-12 12:12:37 -0400506 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
Dave Airlied785d782009-12-07 13:16:06 +1000507 break;
508 case R200_TXFORMAT_DXT1:
509 track->textures[i].cpp = 1;
510 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
511 break;
Dave Airlie551ebd82009-09-01 15:25:57 +1000512 case R200_TXFORMAT_DXT23:
513 case R200_TXFORMAT_DXT45:
Dave Airlied785d782009-12-07 13:16:06 +1000514 track->textures[i].cpp = 1;
515 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
Dave Airlie551ebd82009-09-01 15:25:57 +1000516 break;
517 }
Dave Airlie513bcb42009-09-23 16:56:27 +1000518 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
519 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
Marek Olšák40b4a752011-02-12 19:21:35 +0100520 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000521 break;
522 case R200_PP_CUBIC_FACES_0:
523 case R200_PP_CUBIC_FACES_1:
524 case R200_PP_CUBIC_FACES_2:
525 case R200_PP_CUBIC_FACES_3:
526 case R200_PP_CUBIC_FACES_4:
527 case R200_PP_CUBIC_FACES_5:
Dave Airlie513bcb42009-09-23 16:56:27 +1000528 tmp = idx_value;
Dave Airlie551ebd82009-09-01 15:25:57 +1000529 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
530 for (face = 0; face < 4; face++) {
531 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
532 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
533 }
Marek Olšák40b4a752011-02-12 19:21:35 +0100534 track->tex_dirty = true;
Dave Airlie551ebd82009-09-01 15:25:57 +1000535 break;
536 default:
537 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
538 reg, idx);
539 return -EINVAL;
540 }
541 return 0;
542}
543
Jerome Glissed4550902009-10-01 10:12:06 +0200544void r200_set_safe_registers(struct radeon_device *rdev)
Dave Airlie551ebd82009-09-01 15:25:57 +1000545{
546 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
547 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
Dave Airlie551ebd82009-09-01 15:25:57 +1000548}