R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 10 | #include "dra74x.dtsi" |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 12 | #include <dt-bindings/clk/ti-dra7-atl.h> |
Grygorii Strashko | 863987a | 2015-08-27 18:20:47 +0300 | [diff] [blame] | 13 | #include <dt-bindings/input/input.h> |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 14 | |
| 15 | / { |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 16 | model = "TI DRA742"; |
| 17 | compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 18 | |
Javier Martinez Canillas | 5c4d9f0 | 2016-08-31 12:35:37 +0200 | [diff] [blame] | 19 | memory@0 { |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 20 | device_type = "memory"; |
Lokesh Vutla | dae320e | 2016-02-24 15:41:04 +0530 | [diff] [blame] | 21 | reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 22 | }; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 23 | |
Balaji T K | 4b93521 | 2015-07-30 13:43:35 +0530 | [diff] [blame] | 24 | evm_3v3_sd: fixedregulator-sd { |
| 25 | compatible = "regulator-fixed"; |
| 26 | regulator-name = "evm_3v3_sd"; |
| 27 | regulator-min-microvolt = <3300000>; |
| 28 | regulator-max-microvolt = <3300000>; |
| 29 | enable-active-high; |
| 30 | gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; |
| 31 | }; |
| 32 | |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 33 | evm_3v3_sw: fixedregulator-evm_3v3_sw { |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 34 | compatible = "regulator-fixed"; |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 35 | regulator-name = "evm_3v3_sw"; |
Nishanth Menon | 8695add | 2016-03-03 08:49:48 +0530 | [diff] [blame] | 36 | vin-supply = <&sysen1>; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 37 | regulator-min-microvolt = <3300000>; |
| 38 | regulator-max-microvolt = <3300000>; |
| 39 | }; |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 40 | |
Peter Ujfalusi | d681822 | 2015-08-24 10:20:00 +0300 | [diff] [blame] | 41 | aic_dvdd: fixedregulator-aic_dvdd { |
| 42 | /* TPS77018DBVT */ |
| 43 | compatible = "regulator-fixed"; |
| 44 | regulator-name = "aic_dvdd"; |
| 45 | vin-supply = <&evm_3v3_sw>; |
| 46 | regulator-min-microvolt = <1800000>; |
| 47 | regulator-max-microvolt = <1800000>; |
| 48 | }; |
| 49 | |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 50 | extcon_usb1: extcon_usb1 { |
| 51 | compatible = "linux,extcon-usb-gpio"; |
| 52 | id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; |
| 53 | }; |
| 54 | |
| 55 | extcon_usb2: extcon_usb2 { |
| 56 | compatible = "linux,extcon-usb-gpio"; |
| 57 | id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; |
| 58 | }; |
| 59 | |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 60 | vtt_fixed: fixedregulator-vtt { |
| 61 | compatible = "regulator-fixed"; |
| 62 | regulator-name = "vtt_fixed"; |
| 63 | regulator-min-microvolt = <1350000>; |
| 64 | regulator-max-microvolt = <1350000>; |
| 65 | regulator-always-on; |
| 66 | regulator-boot-on; |
| 67 | enable-active-high; |
Nishanth Menon | 8695add | 2016-03-03 08:49:48 +0530 | [diff] [blame] | 68 | vin-supply = <&sysen2>; |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 69 | gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; |
| 70 | }; |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 71 | |
Javier Martinez Canillas | 4e8603e | 2016-04-01 16:20:21 -0400 | [diff] [blame] | 72 | sound0: sound0 { |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 73 | compatible = "simple-audio-card"; |
| 74 | simple-audio-card,name = "DRA7xx-EVM"; |
| 75 | simple-audio-card,widgets = |
| 76 | "Headphone", "Headphone Jack", |
| 77 | "Line", "Line Out", |
| 78 | "Microphone", "Mic Jack", |
| 79 | "Line", "Line In"; |
| 80 | simple-audio-card,routing = |
| 81 | "Headphone Jack", "HPLOUT", |
| 82 | "Headphone Jack", "HPROUT", |
| 83 | "Line Out", "LLOUT", |
| 84 | "Line Out", "RLOUT", |
| 85 | "MIC3L", "Mic Jack", |
| 86 | "MIC3R", "Mic Jack", |
| 87 | "Mic Jack", "Mic Bias", |
| 88 | "LINE1L", "Line In", |
| 89 | "LINE1R", "Line In"; |
| 90 | simple-audio-card,format = "dsp_b"; |
| 91 | simple-audio-card,bitclock-master = <&sound0_master>; |
| 92 | simple-audio-card,frame-master = <&sound0_master>; |
| 93 | simple-audio-card,bitclock-inversion; |
| 94 | |
| 95 | sound0_master: simple-audio-card,cpu { |
| 96 | sound-dai = <&mcasp3>; |
| 97 | system-clock-frequency = <5644800>; |
| 98 | }; |
| 99 | |
| 100 | simple-audio-card,codec { |
| 101 | sound-dai = <&tlv320aic3106>; |
| 102 | clocks = <&atl_clkin2_ck>; |
| 103 | }; |
| 104 | }; |
Grygorii Strashko | a96e880 | 2015-08-27 18:20:46 +0300 | [diff] [blame] | 105 | |
| 106 | leds { |
| 107 | compatible = "gpio-leds"; |
Javier Martinez Canillas | 08ef980 | 2016-08-01 12:47:04 -0400 | [diff] [blame] | 108 | led0 { |
Grygorii Strashko | a96e880 | 2015-08-27 18:20:46 +0300 | [diff] [blame] | 109 | label = "dra7:usr1"; |
| 110 | gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; |
| 111 | default-state = "off"; |
| 112 | }; |
| 113 | |
Javier Martinez Canillas | 08ef980 | 2016-08-01 12:47:04 -0400 | [diff] [blame] | 114 | led1 { |
Grygorii Strashko | a96e880 | 2015-08-27 18:20:46 +0300 | [diff] [blame] | 115 | label = "dra7:usr2"; |
| 116 | gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; |
| 117 | default-state = "off"; |
| 118 | }; |
| 119 | |
Javier Martinez Canillas | 08ef980 | 2016-08-01 12:47:04 -0400 | [diff] [blame] | 120 | led2 { |
Grygorii Strashko | a96e880 | 2015-08-27 18:20:46 +0300 | [diff] [blame] | 121 | label = "dra7:usr3"; |
| 122 | gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; |
| 123 | default-state = "off"; |
| 124 | }; |
| 125 | |
Javier Martinez Canillas | 08ef980 | 2016-08-01 12:47:04 -0400 | [diff] [blame] | 126 | led3 { |
Grygorii Strashko | a96e880 | 2015-08-27 18:20:46 +0300 | [diff] [blame] | 127 | label = "dra7:usr4"; |
| 128 | gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; |
| 129 | default-state = "off"; |
| 130 | }; |
| 131 | }; |
Grygorii Strashko | 863987a | 2015-08-27 18:20:47 +0300 | [diff] [blame] | 132 | |
| 133 | gpio_keys { |
| 134 | compatible = "gpio-keys"; |
| 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; |
| 137 | autorepeat; |
| 138 | |
| 139 | USER1 { |
| 140 | label = "btnUser1"; |
| 141 | linux,code = <BTN_0>; |
| 142 | gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>; |
| 143 | }; |
| 144 | |
| 145 | USER2 { |
| 146 | label = "btnUser2"; |
| 147 | linux,code = <BTN_1>; |
| 148 | gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>; |
| 149 | }; |
| 150 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | &dra7_pmx_core { |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 154 | pinctrl-names = "default"; |
| 155 | pinctrl-0 = <&vtt_pin>; |
| 156 | |
| 157 | vtt_pin: pinmux_vtt_pin { |
| 158 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 159 | DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */ |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 160 | >; |
| 161 | }; |
| 162 | |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 163 | i2c1_pins: pinmux_i2c1_pins { |
| 164 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 165 | DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */ |
| 166 | DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 167 | >; |
| 168 | }; |
| 169 | |
| 170 | i2c2_pins: pinmux_i2c2_pins { |
| 171 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 172 | DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ |
| 173 | DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 174 | >; |
| 175 | }; |
| 176 | |
| 177 | i2c3_pins: pinmux_i2c3_pins { |
| 178 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 179 | DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */ |
| 180 | DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 181 | >; |
| 182 | }; |
| 183 | |
| 184 | mcspi1_pins: pinmux_mcspi1_pins { |
| 185 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 186 | DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */ |
| 187 | DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */ |
| 188 | DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */ |
| 189 | DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */ |
| 190 | DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */ |
| 191 | DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 192 | >; |
| 193 | }; |
| 194 | |
| 195 | mcspi2_pins: pinmux_mcspi2_pins { |
| 196 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 197 | DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */ |
| 198 | DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| 199 | DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */ |
| 200 | DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 201 | >; |
| 202 | }; |
| 203 | |
| 204 | uart1_pins: pinmux_uart1_pins { |
| 205 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 206 | DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */ |
| 207 | DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */ |
| 208 | DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */ |
| 209 | DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 210 | >; |
| 211 | }; |
| 212 | |
| 213 | uart2_pins: pinmux_uart2_pins { |
| 214 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 215 | DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */ |
| 216 | DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */ |
| 217 | DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */ |
| 218 | DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 219 | >; |
| 220 | }; |
| 221 | |
| 222 | uart3_pins: pinmux_uart3_pins { |
| 223 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 224 | DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */ |
| 225 | DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 226 | >; |
| 227 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 228 | |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 229 | usb1_pins: pinmux_usb1_pins { |
| 230 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 231 | DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 232 | >; |
| 233 | }; |
| 234 | |
| 235 | usb2_pins: pinmux_usb2_pins { |
| 236 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 237 | DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 238 | >; |
| 239 | }; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 240 | |
| 241 | nand_flash_x16: nand_flash_x16 { |
| 242 | /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch |
| 243 | * So NAND flash requires following switch settings: |
Roger Quadros | 91d075c | 2016-03-03 13:28:20 +0200 | [diff] [blame] | 244 | * SW5.1 (NAND_BOOTn) = ON (LOW) |
| 245 | * SW5.9 (GPMC_WPN) = OFF (HIGH) |
| 246 | */ |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 247 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 248 | DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
| 249 | DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
| 250 | DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
| 251 | DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
| 252 | DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
| 253 | DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
| 254 | DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
| 255 | DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
| 256 | DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
| 257 | DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
| 258 | DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
| 259 | DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
| 260 | DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
| 261 | DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
| 262 | DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
| 263 | DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
| 264 | DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */ |
| 265 | DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
| 266 | DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */ |
| 267 | DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
| 268 | DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
| 269 | DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 270 | >; |
| 271 | }; |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 272 | |
| 273 | cpsw_default: cpsw_default { |
| 274 | pinctrl-single,pins = < |
| 275 | /* Slave 1 */ |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 276 | DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ |
| 277 | DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ |
| 278 | DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ |
| 279 | DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ |
| 280 | DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ |
| 281 | DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ |
| 282 | DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ |
| 283 | DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ |
| 284 | DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ |
| 285 | DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ |
| 286 | DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ |
| 287 | DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 288 | |
| 289 | /* Slave 2 */ |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 290 | DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ |
| 291 | DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ |
| 292 | DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ |
| 293 | DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ |
| 294 | DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ |
| 295 | DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ |
| 296 | DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ |
| 297 | DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ |
| 298 | DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ |
| 299 | DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ |
| 300 | DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ |
| 301 | DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 302 | >; |
| 303 | |
| 304 | }; |
| 305 | |
| 306 | cpsw_sleep: cpsw_sleep { |
| 307 | pinctrl-single,pins = < |
| 308 | /* Slave 1 */ |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 309 | DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15) |
| 310 | DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15) |
| 311 | DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15) |
| 312 | DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15) |
| 313 | DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15) |
| 314 | DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15) |
| 315 | DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15) |
| 316 | DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15) |
| 317 | DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15) |
| 318 | DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15) |
| 319 | DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15) |
| 320 | DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15) |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 321 | |
| 322 | /* Slave 2 */ |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 323 | DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) |
| 324 | DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) |
| 325 | DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) |
| 326 | DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) |
| 327 | DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) |
| 328 | DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) |
| 329 | DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) |
| 330 | DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) |
| 331 | DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) |
| 332 | DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) |
| 333 | DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) |
| 334 | DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 335 | >; |
| 336 | }; |
| 337 | |
| 338 | davinci_mdio_default: davinci_mdio_default { |
| 339 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 340 | DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ |
| 341 | DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 342 | >; |
| 343 | }; |
| 344 | |
| 345 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 346 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 347 | DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) |
| 348 | DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 349 | >; |
| 350 | }; |
| 351 | |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 352 | dcan1_pins_default: dcan1_pins_default { |
| 353 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 354 | DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ |
| 355 | DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 356 | >; |
| 357 | }; |
| 358 | |
| 359 | dcan1_pins_sleep: dcan1_pins_sleep { |
| 360 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 361 | DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ |
| 362 | DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 363 | >; |
| 364 | }; |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 365 | |
| 366 | atl_pins: pinmux_atl_pins { |
| 367 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 368 | DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ |
| 369 | DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 370 | >; |
| 371 | }; |
| 372 | |
| 373 | mcasp3_pins: pinmux_mcasp3_pins { |
| 374 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 375 | DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ |
| 376 | DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ |
| 377 | DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ |
| 378 | DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 379 | >; |
| 380 | }; |
| 381 | |
| 382 | mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { |
| 383 | pinctrl-single,pins = < |
Javier Martinez Canillas | c78be3d | 2015-11-13 01:53:59 -0300 | [diff] [blame] | 384 | DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15) |
| 385 | DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15) |
| 386 | DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15) |
| 387 | DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15) |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 388 | >; |
| 389 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 390 | }; |
| 391 | |
| 392 | &i2c1 { |
| 393 | status = "okay"; |
| 394 | pinctrl-names = "default"; |
| 395 | pinctrl-0 = <&i2c1_pins>; |
| 396 | clock-frequency = <400000>; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 397 | |
| 398 | tps659038: tps659038@58 { |
| 399 | compatible = "ti,tps659038"; |
| 400 | reg = <0x58>; |
| 401 | |
| 402 | tps659038_pmic { |
| 403 | compatible = "ti,tps659038-pmic"; |
| 404 | |
| 405 | regulators { |
| 406 | smps123_reg: smps123 { |
| 407 | /* VDD_MPU */ |
| 408 | regulator-name = "smps123"; |
| 409 | regulator-min-microvolt = < 850000>; |
| 410 | regulator-max-microvolt = <1250000>; |
| 411 | regulator-always-on; |
| 412 | regulator-boot-on; |
| 413 | }; |
| 414 | |
| 415 | smps45_reg: smps45 { |
| 416 | /* VDD_DSPEVE */ |
| 417 | regulator-name = "smps45"; |
| 418 | regulator-min-microvolt = < 850000>; |
Nishanth Menon | 54d03c5 | 2016-04-20 03:18:39 -0500 | [diff] [blame] | 419 | regulator-max-microvolt = <1250000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 420 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 421 | regulator-boot-on; |
| 422 | }; |
| 423 | |
| 424 | smps6_reg: smps6 { |
| 425 | /* VDD_GPU - over VDD_SMPS6 */ |
| 426 | regulator-name = "smps6"; |
| 427 | regulator-min-microvolt = <850000>; |
Ravikumar Kattekola | d114e85 | 2014-12-03 17:33:56 +0530 | [diff] [blame] | 428 | regulator-max-microvolt = <1250000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 429 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 430 | regulator-boot-on; |
| 431 | }; |
| 432 | |
| 433 | smps7_reg: smps7 { |
| 434 | /* CORE_VDD */ |
| 435 | regulator-name = "smps7"; |
| 436 | regulator-min-microvolt = <850000>; |
Nishanth Menon | 54d03c5 | 2016-04-20 03:18:39 -0500 | [diff] [blame] | 437 | regulator-max-microvolt = <1150000>; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 438 | regulator-always-on; |
| 439 | regulator-boot-on; |
| 440 | }; |
| 441 | |
| 442 | smps8_reg: smps8 { |
| 443 | /* VDD_IVAHD */ |
| 444 | regulator-name = "smps8"; |
| 445 | regulator-min-microvolt = < 850000>; |
| 446 | regulator-max-microvolt = <1250000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 447 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 448 | regulator-boot-on; |
| 449 | }; |
| 450 | |
| 451 | smps9_reg: smps9 { |
| 452 | /* VDDS1V8 */ |
| 453 | regulator-name = "smps9"; |
| 454 | regulator-min-microvolt = <1800000>; |
| 455 | regulator-max-microvolt = <1800000>; |
| 456 | regulator-always-on; |
| 457 | regulator-boot-on; |
| 458 | }; |
| 459 | |
| 460 | ldo1_reg: ldo1 { |
| 461 | /* LDO1_OUT --> SDIO */ |
| 462 | regulator-name = "ldo1"; |
| 463 | regulator-min-microvolt = <1800000>; |
| 464 | regulator-max-microvolt = <3300000>; |
Kishon Vijay Abraham I | 9f04cee | 2015-07-30 13:43:39 +0530 | [diff] [blame] | 465 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 466 | regulator-boot-on; |
| 467 | }; |
| 468 | |
| 469 | ldo2_reg: ldo2 { |
| 470 | /* VDD_RTCIO */ |
| 471 | /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ |
| 472 | regulator-name = "ldo2"; |
| 473 | regulator-min-microvolt = <3300000>; |
| 474 | regulator-max-microvolt = <3300000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 475 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 476 | regulator-boot-on; |
| 477 | }; |
| 478 | |
| 479 | ldo3_reg: ldo3 { |
| 480 | /* VDDA_1V8_PHY */ |
| 481 | regulator-name = "ldo3"; |
| 482 | regulator-min-microvolt = <1800000>; |
| 483 | regulator-max-microvolt = <1800000>; |
Roger Quadros | e120fb4 | 2014-07-04 12:55:43 +0300 | [diff] [blame] | 484 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 485 | regulator-boot-on; |
| 486 | }; |
| 487 | |
| 488 | ldo9_reg: ldo9 { |
| 489 | /* VDD_RTC */ |
| 490 | regulator-name = "ldo9"; |
| 491 | regulator-min-microvolt = <1050000>; |
| 492 | regulator-max-microvolt = <1050000>; |
Nishanth Menon | 395b23c | 2014-10-21 09:38:10 -0500 | [diff] [blame] | 493 | regulator-always-on; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 494 | regulator-boot-on; |
Keerthy | fcf5895 | 2015-12-14 12:06:57 +0530 | [diff] [blame] | 495 | regulator-allow-bypass; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 496 | }; |
| 497 | |
| 498 | ldoln_reg: ldoln { |
| 499 | /* VDDA_1V8_PLL */ |
| 500 | regulator-name = "ldoln"; |
| 501 | regulator-min-microvolt = <1800000>; |
| 502 | regulator-max-microvolt = <1800000>; |
| 503 | regulator-always-on; |
| 504 | regulator-boot-on; |
| 505 | }; |
| 506 | |
| 507 | ldousb_reg: ldousb { |
| 508 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
| 509 | regulator-name = "ldousb"; |
| 510 | regulator-min-microvolt = <3300000>; |
| 511 | regulator-max-microvolt = <3300000>; |
| 512 | regulator-boot-on; |
| 513 | }; |
Nishanth Menon | 8695add | 2016-03-03 08:49:48 +0530 | [diff] [blame] | 514 | |
| 515 | /* REGEN1 is unused */ |
| 516 | |
| 517 | regen2: regen2 { |
| 518 | /* Needed for PMIC internal resources */ |
| 519 | regulator-name = "regen2"; |
| 520 | regulator-boot-on; |
| 521 | regulator-always-on; |
| 522 | }; |
| 523 | |
| 524 | /* REGEN3 is unused */ |
| 525 | |
| 526 | sysen1: sysen1 { |
| 527 | /* PMIC_REGEN_3V3 */ |
| 528 | regulator-name = "sysen1"; |
| 529 | regulator-boot-on; |
| 530 | regulator-always-on; |
| 531 | }; |
| 532 | |
| 533 | sysen2: sysen2 { |
| 534 | /* PMIC_REGEN_DDR */ |
| 535 | regulator-name = "sysen2"; |
| 536 | regulator-boot-on; |
| 537 | regulator-always-on; |
| 538 | }; |
Keerthy | c56a831 | 2013-08-26 11:06:51 +0530 | [diff] [blame] | 539 | }; |
| 540 | }; |
| 541 | }; |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 542 | |
Grygorii Strashko | 4fbdc6a | 2015-08-27 18:20:45 +0300 | [diff] [blame] | 543 | pcf_lcd: gpio@20 { |
Roger Quadros | 86f196f | 2016-04-25 15:53:54 +0300 | [diff] [blame] | 544 | compatible = "ti,pcf8575", "nxp,pcf8575"; |
Grygorii Strashko | 4fbdc6a | 2015-08-27 18:20:45 +0300 | [diff] [blame] | 545 | reg = <0x20>; |
| 546 | gpio-controller; |
| 547 | #gpio-cells = <2>; |
| 548 | interrupt-parent = <&gpio6>; |
| 549 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 550 | interrupt-controller; |
| 551 | #interrupt-cells = <2>; |
| 552 | }; |
| 553 | |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 554 | pcf_gpio_21: gpio@21 { |
Roger Quadros | 86f196f | 2016-04-25 15:53:54 +0300 | [diff] [blame] | 555 | compatible = "ti,pcf8575", "nxp,pcf8575"; |
Roger Quadros | 87517d2 | 2015-01-26 14:15:28 +0200 | [diff] [blame] | 556 | reg = <0x21>; |
| 557 | lines-initial-states = <0x1408>; |
| 558 | gpio-controller; |
| 559 | #gpio-cells = <2>; |
| 560 | interrupt-parent = <&gpio6>; |
| 561 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 562 | interrupt-controller; |
| 563 | #interrupt-cells = <2>; |
| 564 | }; |
| 565 | |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 566 | tlv320aic3106: tlv320aic3106@19 { |
| 567 | #sound-dai-cells = <0>; |
| 568 | compatible = "ti,tlv320aic3106"; |
| 569 | reg = <0x19>; |
| 570 | adc-settle-ms = <40>; |
| 571 | ai3x-micbias-vg = <1>; /* 2.0V */ |
| 572 | status = "okay"; |
| 573 | |
| 574 | /* Regulators */ |
| 575 | AVDD-supply = <&evm_3v3_sw>; |
| 576 | IOVDD-supply = <&evm_3v3_sw>; |
| 577 | DRVDD-supply = <&evm_3v3_sw>; |
| 578 | DVDD-supply = <&aic_dvdd>; |
| 579 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 580 | }; |
| 581 | |
| 582 | &i2c2 { |
| 583 | status = "okay"; |
| 584 | pinctrl-names = "default"; |
| 585 | pinctrl-0 = <&i2c2_pins>; |
| 586 | clock-frequency = <400000>; |
Peter Ujfalusi | c5d294d | 2015-08-24 10:20:01 +0300 | [diff] [blame] | 587 | |
| 588 | pcf_hdmi: gpio@26 { |
Roger Quadros | 86f196f | 2016-04-25 15:53:54 +0300 | [diff] [blame] | 589 | compatible = "ti,pcf8575", "nxp,pcf8575"; |
Peter Ujfalusi | c5d294d | 2015-08-24 10:20:01 +0300 | [diff] [blame] | 590 | reg = <0x26>; |
| 591 | gpio-controller; |
| 592 | #gpio-cells = <2>; |
| 593 | p1 { |
| 594 | /* vin6_sel_s0: high: VIN6, low: audio */ |
| 595 | gpio-hog; |
| 596 | gpios = <1 GPIO_ACTIVE_HIGH>; |
| 597 | output-low; |
| 598 | line-name = "vin6_sel_s0"; |
| 599 | }; |
| 600 | }; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 601 | }; |
| 602 | |
| 603 | &i2c3 { |
| 604 | status = "okay"; |
| 605 | pinctrl-names = "default"; |
| 606 | pinctrl-0 = <&i2c3_pins>; |
Roger Quadros | 544d63d | 2014-09-03 14:17:31 +0300 | [diff] [blame] | 607 | clock-frequency = <400000>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 608 | }; |
| 609 | |
| 610 | &mcspi1 { |
| 611 | status = "okay"; |
| 612 | pinctrl-names = "default"; |
| 613 | pinctrl-0 = <&mcspi1_pins>; |
| 614 | }; |
| 615 | |
| 616 | &mcspi2 { |
| 617 | status = "okay"; |
| 618 | pinctrl-names = "default"; |
| 619 | pinctrl-0 = <&mcspi2_pins>; |
| 620 | }; |
| 621 | |
| 622 | &uart1 { |
| 623 | status = "okay"; |
| 624 | pinctrl-names = "default"; |
| 625 | pinctrl-0 = <&uart1_pins>; |
Marc Zyngier | 783d318 | 2015-03-11 15:43:44 +0000 | [diff] [blame] | 626 | interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, |
Nishanth Menon | 66b0436 | 2014-06-06 20:53:22 -0500 | [diff] [blame] | 627 | <&dra7_pmx_core 0x3e0>; |
R Sricharan | 6e58b8f | 2013-08-14 19:08:20 +0530 | [diff] [blame] | 628 | }; |
| 629 | |
| 630 | &uart2 { |
| 631 | status = "okay"; |
| 632 | pinctrl-names = "default"; |
| 633 | pinctrl-0 = <&uart2_pins>; |
| 634 | }; |
| 635 | |
| 636 | &uart3 { |
| 637 | status = "okay"; |
| 638 | pinctrl-names = "default"; |
| 639 | pinctrl-0 = <&uart3_pins>; |
| 640 | }; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 641 | |
| 642 | &mmc1 { |
| 643 | status = "okay"; |
Balaji T K | 4b93521 | 2015-07-30 13:43:35 +0530 | [diff] [blame] | 644 | vmmc-supply = <&evm_3v3_sd>; |
| 645 | vmmc_aux-supply = <&ldo1_reg>; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 646 | bus-width = <4>; |
Nishanth Menon | f4eaf9e | 2015-07-30 13:43:37 +0530 | [diff] [blame] | 647 | /* |
| 648 | * SDCD signal is not being used here - using the fact that GPIO mode |
| 649 | * is always hardwired. |
| 650 | */ |
Mugunthan V N | 267068d | 2015-10-12 14:37:12 +0530 | [diff] [blame] | 651 | cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; |
Balaji T K | bf1788d | 2013-10-07 21:55:03 +0530 | [diff] [blame] | 652 | }; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 653 | |
| 654 | &mmc2 { |
| 655 | status = "okay"; |
Peter Ujfalusi | 27f39e5 | 2015-08-24 10:19:59 +0300 | [diff] [blame] | 656 | vmmc-supply = <&evm_3v3_sw>; |
Balaji T K | 6cf02db | 2013-10-07 21:55:04 +0530 | [diff] [blame] | 657 | bus-width = <8>; |
| 658 | }; |
J Keerthy | 22f1e7e | 2013-10-16 10:39:05 -0500 | [diff] [blame] | 659 | |
| 660 | &cpu0 { |
| 661 | cpu0-supply = <&smps123_reg>; |
| 662 | }; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 663 | |
| 664 | &qspi { |
| 665 | status = "okay"; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 666 | |
Vignesh R | a0b83af | 2016-08-01 18:36:55 +0530 | [diff] [blame] | 667 | spi-max-frequency = <76800000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 668 | m25p80@0 { |
| 669 | compatible = "s25fl256s1"; |
Vignesh R | a0b83af | 2016-08-01 18:36:55 +0530 | [diff] [blame] | 670 | spi-max-frequency = <76800000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 671 | reg = <0>; |
| 672 | spi-tx-bus-width = <1>; |
| 673 | spi-rx-bus-width = <4>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 674 | #address-cells = <1>; |
| 675 | #size-cells = <1>; |
| 676 | |
| 677 | /* MTD partition table. |
| 678 | * The ROM checks the first four physical blocks |
| 679 | * for a valid file to boot and the flash here is |
| 680 | * 64KiB block size. |
| 681 | */ |
| 682 | partition@0 { |
| 683 | label = "QSPI.SPL"; |
| 684 | reg = <0x00000000 0x000010000>; |
| 685 | }; |
| 686 | partition@1 { |
| 687 | label = "QSPI.SPL.backup1"; |
| 688 | reg = <0x00010000 0x00010000>; |
| 689 | }; |
| 690 | partition@2 { |
| 691 | label = "QSPI.SPL.backup2"; |
| 692 | reg = <0x00020000 0x00010000>; |
| 693 | }; |
| 694 | partition@3 { |
| 695 | label = "QSPI.SPL.backup3"; |
| 696 | reg = <0x00030000 0x00010000>; |
| 697 | }; |
| 698 | partition@4 { |
| 699 | label = "QSPI.u-boot"; |
| 700 | reg = <0x00040000 0x00100000>; |
| 701 | }; |
| 702 | partition@5 { |
| 703 | label = "QSPI.u-boot-spl-os"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 704 | reg = <0x00140000 0x00080000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 705 | }; |
| 706 | partition@6 { |
| 707 | label = "QSPI.u-boot-env"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 708 | reg = <0x001c0000 0x00010000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 709 | }; |
| 710 | partition@7 { |
| 711 | label = "QSPI.u-boot-env.backup1"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 712 | reg = <0x001d0000 0x0010000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 713 | }; |
| 714 | partition@8 { |
| 715 | label = "QSPI.kernel"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 716 | reg = <0x001e0000 0x0800000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 717 | }; |
| 718 | partition@9 { |
| 719 | label = "QSPI.file-system"; |
Mugunthan V N | 69d2626 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 720 | reg = <0x009e0000 0x01620000>; |
Sourav Poddar | dc2dd5b | 2014-05-06 16:37:24 +0530 | [diff] [blame] | 721 | }; |
| 722 | }; |
| 723 | }; |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 724 | |
Roger Quadros | a7b0aa1 | 2015-03-17 11:43:51 +0200 | [diff] [blame] | 725 | &omap_dwc3_1 { |
| 726 | extcon = <&extcon_usb1>; |
| 727 | }; |
| 728 | |
| 729 | &omap_dwc3_2 { |
| 730 | extcon = <&extcon_usb2>; |
| 731 | }; |
| 732 | |
Roger Quadros | 4b4437c | 2014-05-14 10:58:13 +0300 | [diff] [blame] | 733 | &usb1 { |
| 734 | dr_mode = "peripheral"; |
| 735 | pinctrl-names = "default"; |
| 736 | pinctrl-0 = <&usb1_pins>; |
| 737 | }; |
| 738 | |
| 739 | &usb2 { |
| 740 | dr_mode = "host"; |
| 741 | pinctrl-names = "default"; |
| 742 | pinctrl-0 = <&usb2_pins>; |
| 743 | }; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 744 | |
| 745 | &elm { |
| 746 | status = "okay"; |
| 747 | }; |
| 748 | |
| 749 | &gpmc { |
| 750 | status = "okay"; |
| 751 | pinctrl-names = "default"; |
| 752 | pinctrl-0 = <&nand_flash_x16>; |
Roger Quadros | 488f270 | 2016-02-23 18:37:17 +0200 | [diff] [blame] | 753 | ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 754 | nand@0,0 { |
Roger Quadros | 488f270 | 2016-02-23 18:37:17 +0200 | [diff] [blame] | 755 | compatible = "ti,omap2-nand"; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 756 | reg = <0 0 4>; /* device IO registers */ |
Roger Quadros | 488f270 | 2016-02-23 18:37:17 +0200 | [diff] [blame] | 757 | interrupt-parent = <&gpmc>; |
| 758 | interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| 759 | <1 IRQ_TYPE_NONE>; /* termcount */ |
Roger Quadros | a23fc15 | 2016-04-07 13:25:37 +0300 | [diff] [blame] | 760 | rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 761 | ti,nand-ecc-opt = "bch8"; |
| 762 | ti,elm-id = <&elm>; |
| 763 | nand-bus-width = <16>; |
| 764 | gpmc,device-width = <2>; |
| 765 | gpmc,sync-clk-ps = <0>; |
| 766 | gpmc,cs-on-ns = <0>; |
Roger Quadros | 5990047 | 2014-09-10 08:57:11 -0700 | [diff] [blame] | 767 | gpmc,cs-rd-off-ns = <80>; |
| 768 | gpmc,cs-wr-off-ns = <80>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 769 | gpmc,adv-on-ns = <0>; |
Roger Quadros | 5990047 | 2014-09-10 08:57:11 -0700 | [diff] [blame] | 770 | gpmc,adv-rd-off-ns = <60>; |
| 771 | gpmc,adv-wr-off-ns = <60>; |
| 772 | gpmc,we-on-ns = <10>; |
| 773 | gpmc,we-off-ns = <50>; |
| 774 | gpmc,oe-on-ns = <4>; |
| 775 | gpmc,oe-off-ns = <40>; |
| 776 | gpmc,access-ns = <40>; |
| 777 | gpmc,wr-access-ns = <80>; |
| 778 | gpmc,rd-cycle-ns = <80>; |
| 779 | gpmc,wr-cycle-ns = <80>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 780 | gpmc,bus-turnaround-ns = <0>; |
| 781 | gpmc,cycle2cycle-delay-ns = <0>; |
| 782 | gpmc,clk-activation-ns = <0>; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 783 | gpmc,wr-data-mux-bus-ns = <0>; |
| 784 | /* MTD partition table */ |
| 785 | /* All SPL-* partitions are sized to minimal length |
| 786 | * which can be independently programmable. For |
| 787 | * NAND flash this is equal to size of erase-block */ |
| 788 | #address-cells = <1>; |
| 789 | #size-cells = <1>; |
| 790 | partition@0 { |
| 791 | label = "NAND.SPL"; |
| 792 | reg = <0x00000000 0x000020000>; |
| 793 | }; |
| 794 | partition@1 { |
| 795 | label = "NAND.SPL.backup1"; |
| 796 | reg = <0x00020000 0x00020000>; |
| 797 | }; |
| 798 | partition@2 { |
| 799 | label = "NAND.SPL.backup2"; |
| 800 | reg = <0x00040000 0x00020000>; |
| 801 | }; |
| 802 | partition@3 { |
| 803 | label = "NAND.SPL.backup3"; |
| 804 | reg = <0x00060000 0x00020000>; |
| 805 | }; |
| 806 | partition@4 { |
| 807 | label = "NAND.u-boot-spl-os"; |
| 808 | reg = <0x00080000 0x00040000>; |
| 809 | }; |
| 810 | partition@5 { |
| 811 | label = "NAND.u-boot"; |
| 812 | reg = <0x000c0000 0x00100000>; |
| 813 | }; |
| 814 | partition@6 { |
| 815 | label = "NAND.u-boot-env"; |
| 816 | reg = <0x001c0000 0x00020000>; |
| 817 | }; |
| 818 | partition@7 { |
Roger Quadros | f0e9fab | 2014-09-03 14:17:32 +0300 | [diff] [blame] | 819 | label = "NAND.u-boot-env.backup1"; |
Minal Shah | ff66a3c | 2014-05-19 14:45:47 +0530 | [diff] [blame] | 820 | reg = <0x001e0000 0x00020000>; |
| 821 | }; |
| 822 | partition@8 { |
| 823 | label = "NAND.kernel"; |
| 824 | reg = <0x00200000 0x00800000>; |
| 825 | }; |
| 826 | partition@9 { |
| 827 | label = "NAND.file-system"; |
| 828 | reg = <0x00a00000 0x0f600000>; |
| 829 | }; |
| 830 | }; |
| 831 | }; |
Roger Quadros | ae28ea8 | 2014-06-30 14:00:38 +0300 | [diff] [blame] | 832 | |
| 833 | &usb2_phy1 { |
| 834 | phy-supply = <&ldousb_reg>; |
| 835 | }; |
| 836 | |
| 837 | &usb2_phy2 { |
| 838 | phy-supply = <&ldousb_reg>; |
| 839 | }; |
Lokesh Vutla | c7cc9ba | 2014-09-04 08:23:28 -0500 | [diff] [blame] | 840 | |
| 841 | &gpio7 { |
| 842 | ti,no-reset-on-init; |
| 843 | ti,no-idle-on-init; |
| 844 | }; |
Mugunthan V N | 8d03929 | 2014-10-21 15:31:01 +0530 | [diff] [blame] | 845 | |
| 846 | &mac { |
| 847 | status = "okay"; |
| 848 | pinctrl-names = "default", "sleep"; |
| 849 | pinctrl-0 = <&cpsw_default>; |
| 850 | pinctrl-1 = <&cpsw_sleep>; |
| 851 | dual_emac; |
| 852 | }; |
| 853 | |
| 854 | &cpsw_emac0 { |
| 855 | phy_id = <&davinci_mdio>, <2>; |
| 856 | phy-mode = "rgmii"; |
| 857 | dual_emac_res_vlan = <1>; |
| 858 | }; |
| 859 | |
| 860 | &cpsw_emac1 { |
| 861 | phy_id = <&davinci_mdio>, <3>; |
| 862 | phy-mode = "rgmii"; |
| 863 | dual_emac_res_vlan = <2>; |
| 864 | }; |
| 865 | |
| 866 | &davinci_mdio { |
| 867 | pinctrl-names = "default", "sleep"; |
| 868 | pinctrl-0 = <&davinci_mdio_default>; |
| 869 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 870 | }; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 871 | |
| 872 | &dcan1 { |
| 873 | status = "ok"; |
Roger Quadros | 2acb5c3 | 2015-07-07 17:27:57 +0300 | [diff] [blame] | 874 | pinctrl-names = "default", "sleep", "active"; |
| 875 | pinctrl-0 = <&dcan1_pins_sleep>; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 876 | pinctrl-1 = <&dcan1_pins_sleep>; |
Roger Quadros | 2acb5c3 | 2015-07-07 17:27:57 +0300 | [diff] [blame] | 877 | pinctrl-2 = <&dcan1_pins_default>; |
Roger Quadros | b41502e | 2014-08-15 16:09:19 +0300 | [diff] [blame] | 878 | }; |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 879 | |
| 880 | &atl { |
| 881 | pinctrl-names = "default"; |
| 882 | pinctrl-0 = <&atl_pins>; |
| 883 | |
| 884 | assigned-clocks = <&abe_dpll_sys_clk_mux>, |
| 885 | <&atl_gfclk_mux>, |
| 886 | <&dpll_abe_ck>, |
| 887 | <&dpll_abe_m2x2_ck>, |
| 888 | <&atl_clkin2_ck>; |
| 889 | assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; |
| 890 | assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; |
| 891 | |
| 892 | status = "okay"; |
| 893 | |
| 894 | atl2 { |
| 895 | bws = <DRA7_ATL_WS_MCASP2_FSX>; |
| 896 | aws = <DRA7_ATL_WS_MCASP3_FSX>; |
| 897 | }; |
| 898 | }; |
| 899 | |
| 900 | &mcasp3 { |
| 901 | #sound-dai-cells = <0>; |
| 902 | pinctrl-names = "default", "sleep"; |
| 903 | pinctrl-0 = <&mcasp3_pins>; |
| 904 | pinctrl-1 = <&mcasp3_sleep_pins>; |
| 905 | |
| 906 | assigned-clocks = <&mcasp3_ahclkx_mux>; |
| 907 | assigned-clock-parents = <&atl_clkin2_ck>; |
| 908 | |
| 909 | status = "okay"; |
| 910 | |
| 911 | op-mode = <0>; /* MCASP_IIS_MODE */ |
| 912 | tdm-slots = <2>; |
| 913 | /* 4 serializer */ |
| 914 | serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ |
| 915 | 1 2 0 0 |
| 916 | >; |
Peter Ujfalusi | 27701fc2 | 2016-03-07 17:17:31 +0200 | [diff] [blame] | 917 | tx-num-evt = <32>; |
| 918 | rx-num-evt = <32>; |
Peter Ujfalusi | a9347bf | 2015-08-24 10:20:02 +0300 | [diff] [blame] | 919 | }; |
Suman Anna | 2bee867 | 2015-09-18 13:16:32 -0500 | [diff] [blame] | 920 | |
| 921 | &mailbox5 { |
| 922 | status = "okay"; |
| 923 | mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { |
| 924 | status = "okay"; |
| 925 | }; |
| 926 | mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { |
| 927 | status = "okay"; |
| 928 | }; |
| 929 | }; |
| 930 | |
| 931 | &mailbox6 { |
| 932 | status = "okay"; |
| 933 | mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { |
| 934 | status = "okay"; |
| 935 | }; |
| 936 | mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { |
| 937 | status = "okay"; |
| 938 | }; |
| 939 | }; |