Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Carsten Langgaard, carstenl@mips.com |
| 3 | * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. |
| 4 | * Copyright (C) 2001 Ralf Baechle |
| 5 | * |
| 6 | * This program is free software; you can distribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License (Version 2) as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 13 | * for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 18 | * |
| 19 | * Routines for generic manipulation of the interrupts found on the MIPS |
| 20 | * Malta board. |
| 21 | * The interrupt controller is located in the South Bridge a PIIX4 device |
| 22 | * with two internal 82C95 interrupt controllers. |
| 23 | */ |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/slab.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/kernel_stat.h> |
| 30 | #include <linux/random.h> |
| 31 | |
| 32 | #include <asm/i8259.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 33 | #include <asm/irq_cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include <asm/io.h> |
| 35 | #include <asm/mips-boards/malta.h> |
| 36 | #include <asm/mips-boards/maltaint.h> |
| 37 | #include <asm/mips-boards/piix4.h> |
| 38 | #include <asm/gt64120.h> |
| 39 | #include <asm/mips-boards/generic.h> |
| 40 | #include <asm/mips-boards/msc01_pci.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 41 | #include <asm/msc01_ic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 43 | extern void mips_timer_interrupt(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
| 45 | static DEFINE_SPINLOCK(mips_irq_lock); |
| 46 | |
| 47 | static inline int mips_pcibios_iack(void) |
| 48 | { |
| 49 | int irq; |
| 50 | u32 dummy; |
| 51 | |
| 52 | /* |
| 53 | * Determine highest priority pending interrupt by performing |
| 54 | * a PCI Interrupt Acknowledge cycle. |
| 55 | */ |
| 56 | switch(mips_revision_corid) { |
| 57 | case MIPS_REVISION_CORID_CORE_MSC: |
| 58 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 59 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 60 | case MIPS_REVISION_CORID_CORE_24K: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 62 | MSC_READ(MSC01_PCI_IACK, irq); |
| 63 | irq &= 0xff; |
| 64 | break; |
| 65 | case MIPS_REVISION_CORID_QED_RM5261: |
| 66 | case MIPS_REVISION_CORID_CORE_LV: |
| 67 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 68 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 69 | irq = GT_READ(GT_PCI0_IACK_OFS); |
| 70 | irq &= 0xff; |
| 71 | break; |
| 72 | case MIPS_REVISION_CORID_BONITO64: |
| 73 | case MIPS_REVISION_CORID_CORE_20K: |
| 74 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
| 75 | /* The following will generate a PCI IACK cycle on the |
| 76 | * Bonito controller. It's a little bit kludgy, but it |
| 77 | * was the easiest way to implement it in hardware at |
| 78 | * the given time. |
| 79 | */ |
| 80 | BONITO_PCIMAP_CFG = 0x20000; |
| 81 | |
| 82 | /* Flush Bonito register block */ |
| 83 | dummy = BONITO_PCIMAP_CFG; |
| 84 | iob(); /* sync */ |
| 85 | |
| 86 | irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg); |
| 87 | iob(); /* sync */ |
| 88 | irq &= 0xff; |
| 89 | BONITO_PCIMAP_CFG = 0; |
| 90 | break; |
| 91 | default: |
| 92 | printk("Unknown Core card, don't know the system controller.\n"); |
| 93 | return -1; |
| 94 | } |
| 95 | return irq; |
| 96 | } |
| 97 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 98 | static inline int get_int(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 99 | { |
| 100 | unsigned long flags; |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 101 | int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | spin_lock_irqsave(&mips_irq_lock, flags); |
| 103 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 104 | irq = mips_pcibios_iack(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | |
| 106 | /* |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 107 | * The only way we can decide if an interrupt is spurious |
| 108 | * is by checking the 8259 registers. This needs a spinlock |
| 109 | * on an SMP system, so leave it up to the generic code... |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | |
| 112 | spin_unlock_irqrestore(&mips_irq_lock, flags); |
| 113 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 114 | return irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | } |
| 116 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 117 | static void malta_hw0_irqdispatch(struct pt_regs *regs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | { |
| 119 | int irq; |
| 120 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 121 | irq = get_int(); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 122 | if (irq < 0) { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 123 | return; /* interrupt has already been cleared */ |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 124 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 126 | do_IRQ(MALTA_INT_BASE+irq, regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | void corehi_irqdispatch(struct pt_regs *regs) |
| 130 | { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 131 | unsigned int intrcause,datalo,datahi; |
| 132 | unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | |
| 134 | printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); |
| 135 | printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" |
| 136 | , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 137 | |
| 138 | /* Read all the registers and then print them as there is a |
| 139 | problem with interspersed printk's upsetting the Bonito controller. |
| 140 | Do it for the others too. |
| 141 | */ |
| 142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | switch(mips_revision_corid) { |
| 144 | case MIPS_REVISION_CORID_CORE_MSC: |
| 145 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 146 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 147 | case MIPS_REVISION_CORID_CORE_24K: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 148 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 149 | ll_msc_irq(regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | break; |
| 151 | case MIPS_REVISION_CORID_QED_RM5261: |
| 152 | case MIPS_REVISION_CORID_CORE_LV: |
| 153 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 154 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 155 | intrcause = GT_READ(GT_INTRCAUSE_OFS); |
| 156 | datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 157 | datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 158 | printk("GT_INTRCAUSE = %08x\n", intrcause); |
| 159 | printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | break; |
| 161 | case MIPS_REVISION_CORID_BONITO64: |
| 162 | case MIPS_REVISION_CORID_CORE_20K: |
| 163 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 164 | pcibadaddr = BONITO_PCIBADADDR; |
| 165 | pcimstat = BONITO_PCIMSTAT; |
| 166 | intisr = BONITO_INTISR; |
| 167 | inten = BONITO_INTEN; |
| 168 | intpol = BONITO_INTPOL; |
| 169 | intedge = BONITO_INTEDGE; |
| 170 | intsteer = BONITO_INTSTEER; |
| 171 | pcicmd = BONITO_PCICMD; |
| 172 | printk("BONITO_INTISR = %08x\n", intisr); |
| 173 | printk("BONITO_INTEN = %08x\n", inten); |
| 174 | printk("BONITO_INTPOL = %08x\n", intpol); |
| 175 | printk("BONITO_INTEDGE = %08x\n", intedge); |
| 176 | printk("BONITO_INTSTEER = %08x\n", intsteer); |
| 177 | printk("BONITO_PCICMD = %08x\n", pcicmd); |
| 178 | printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); |
| 179 | printk("BONITO_PCIMSTAT = %08x\n", pcimstat); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | break; |
| 181 | } |
| 182 | |
| 183 | /* We die here*/ |
| 184 | die("CoreHi interrupt", regs); |
| 185 | } |
| 186 | |
Ralf Baechle | e4ac58a | 2006-04-03 17:56:36 +0100 | [diff] [blame] | 187 | static inline int clz(unsigned long x) |
| 188 | { |
| 189 | __asm__ ( |
| 190 | " .set push \n" |
| 191 | " .set mips32 \n" |
| 192 | " clz %0, %1 \n" |
| 193 | " .set pop \n" |
| 194 | : "=r" (x) |
| 195 | : "r" (x)); |
| 196 | |
| 197 | return x; |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * Version of ffs that only looks at bits 12..15. |
| 202 | */ |
| 203 | static inline unsigned int irq_ffs(unsigned int pending) |
| 204 | { |
| 205 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
| 206 | return -clz(pending) + 31 - CAUSEB_IP; |
| 207 | #else |
| 208 | unsigned int a0 = 7; |
| 209 | unsigned int t0; |
| 210 | |
| 211 | t0 = s0 & 0xf000; |
| 212 | t0 = t0 < 1; |
| 213 | t0 = t0 << 2; |
| 214 | a0 = a0 - t0; |
| 215 | s0 = s0 << t0; |
| 216 | |
| 217 | t0 = s0 & 0xc000; |
| 218 | t0 = t0 < 1; |
| 219 | t0 = t0 << 1; |
| 220 | a0 = a0 - t0; |
| 221 | s0 = s0 << t0; |
| 222 | |
| 223 | t0 = s0 & 0x8000; |
| 224 | t0 = t0 < 1; |
| 225 | //t0 = t0 << 2; |
| 226 | a0 = a0 - t0; |
| 227 | //s0 = s0 << t0; |
| 228 | |
| 229 | return a0; |
| 230 | #endif |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * IRQs on the Malta board look basically (barring software IRQs which we |
| 235 | * don't use at all and all external interrupt sources are combined together |
| 236 | * on hardware interrupt 0 (MIPS IRQ 2)) like: |
| 237 | * |
| 238 | * MIPS IRQ Source |
| 239 | * -------- ------ |
| 240 | * 0 Software (ignored) |
| 241 | * 1 Software (ignored) |
| 242 | * 2 Combined hardware interrupt (hw0) |
| 243 | * 3 Hardware (ignored) |
| 244 | * 4 Hardware (ignored) |
| 245 | * 5 Hardware (ignored) |
| 246 | * 6 Hardware (ignored) |
| 247 | * 7 R4k timer (what we use) |
| 248 | * |
| 249 | * We handle the IRQ according to _our_ priority which is: |
| 250 | * |
| 251 | * Highest ---- R4k Timer |
| 252 | * Lowest ---- Combined hardware interrupt |
| 253 | * |
| 254 | * then we just return, if multiple IRQs are pending then we will just take |
| 255 | * another exception, big deal. |
| 256 | */ |
| 257 | |
| 258 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
| 259 | { |
| 260 | unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; |
| 261 | int irq; |
| 262 | |
| 263 | irq = irq_ffs(pending); |
| 264 | |
| 265 | if (irq == MIPSCPU_INT_I8259A) |
| 266 | malta_hw0_irqdispatch(regs); |
| 267 | else if (irq > 0) |
| 268 | do_IRQ(MIPSCPU_INT_BASE + irq, regs); |
| 269 | else |
| 270 | spurious_interrupt(regs); |
| 271 | } |
| 272 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 273 | static struct irqaction i8259irq = { |
| 274 | .handler = no_action, |
| 275 | .name = "XT-PIC cascade" |
| 276 | }; |
| 277 | |
| 278 | static struct irqaction corehi_irqaction = { |
| 279 | .handler = no_action, |
| 280 | .name = "CoreHi" |
| 281 | }; |
| 282 | |
| 283 | msc_irqmap_t __initdata msc_irqmap[] = { |
| 284 | {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 285 | {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 286 | }; |
| 287 | int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t); |
| 288 | |
| 289 | msc_irqmap_t __initdata msc_eicirqmap[] = { |
| 290 | {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, |
| 291 | {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, |
| 292 | {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, |
| 293 | {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0}, |
| 294 | {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0}, |
| 295 | {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0}, |
| 296 | {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0}, |
| 297 | {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0}, |
| 298 | {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0}, |
| 299 | {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} |
| 300 | }; |
| 301 | int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t); |
| 302 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | void __init arch_init_irq(void) |
| 304 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | init_i8259_irqs(); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 306 | |
| 307 | if (!cpu_has_veic) |
| 308 | mips_cpu_irq_init (MIPSCPU_INT_BASE); |
| 309 | |
| 310 | switch(mips_revision_corid) { |
| 311 | case MIPS_REVISION_CORID_CORE_MSC: |
| 312 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Ralf Baechle | 479a0e3 | 2005-08-16 15:44:06 +0000 | [diff] [blame] | 313 | case MIPS_REVISION_CORID_CORE_FPGA3: |
Chris Dearman | 7a83419 | 2006-04-15 00:31:16 +0100 | [diff] [blame] | 314 | case MIPS_REVISION_CORID_CORE_24K: |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 315 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
| 316 | if (cpu_has_veic) |
| 317 | init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); |
| 318 | else |
| 319 | init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); |
| 320 | } |
| 321 | |
| 322 | if (cpu_has_veic) { |
| 323 | set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); |
| 324 | set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); |
| 325 | setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); |
| 326 | setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); |
| 327 | } |
| 328 | else if (cpu_has_vint) { |
| 329 | set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); |
| 330 | set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 331 | #ifdef CONFIG_MIPS_MT_SMTC |
| 332 | setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq, |
| 333 | (0x100 << MIPSCPU_INT_I8259A)); |
| 334 | setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, |
| 335 | &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); |
| 336 | #else /* Not SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 337 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
| 338 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 339 | #endif /* CONFIG_MIPS_MT_SMTC */ |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 340 | } |
| 341 | else { |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 342 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); |
| 343 | setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); |
| 344 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | } |