Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * MPC85xx CDS board specific routines |
| 3 | * |
Kumar Gala | 4c8d3d9 | 2005-11-13 16:06:30 -0800 | [diff] [blame] | 4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Copyright 2004 Freescale Semiconductor, Inc |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/stddef.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/errno.h> |
| 18 | #include <linux/reboot.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/kdev_t.h> |
| 21 | #include <linux/major.h> |
| 22 | #include <linux/console.h> |
| 23 | #include <linux/delay.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/seq_file.h> |
| 25 | #include <linux/serial.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/root_dev.h> |
| 28 | #include <linux/initrd.h> |
| 29 | #include <linux/tty.h> |
| 30 | #include <linux/serial_core.h> |
| 31 | #include <linux/fsl_devices.h> |
| 32 | |
| 33 | #include <asm/system.h> |
| 34 | #include <asm/pgtable.h> |
| 35 | #include <asm/page.h> |
| 36 | #include <asm/atomic.h> |
| 37 | #include <asm/time.h> |
| 38 | #include <asm/todc.h> |
| 39 | #include <asm/io.h> |
| 40 | #include <asm/machdep.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #include <asm/open_pic.h> |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 42 | #include <asm/i8259.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <asm/bootinfo.h> |
| 44 | #include <asm/pci-bridge.h> |
| 45 | #include <asm/mpc85xx.h> |
| 46 | #include <asm/irq.h> |
| 47 | #include <asm/immap_85xx.h> |
Kumar Gala | d054b5a | 2005-07-27 11:44:06 -0700 | [diff] [blame] | 48 | #include <asm/cpm2.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | #include <asm/ppc_sys.h> |
| 50 | #include <asm/kgdb.h> |
| 51 | |
| 52 | #include <mm/mmu_decl.h> |
| 53 | #include <syslib/cpm2_pic.h> |
| 54 | #include <syslib/ppc85xx_common.h> |
| 55 | #include <syslib/ppc85xx_setup.h> |
| 56 | |
| 57 | |
| 58 | #ifndef CONFIG_PCI |
| 59 | unsigned long isa_io_base = 0; |
| 60 | unsigned long isa_mem_base = 0; |
| 61 | #endif |
| 62 | |
| 63 | extern unsigned long total_memory; /* in mm/init */ |
| 64 | |
| 65 | unsigned char __res[sizeof (bd_t)]; |
| 66 | |
| 67 | static int cds_pci_slot = 2; |
| 68 | static volatile u8 * cadmus; |
| 69 | |
| 70 | /* Internal interrupts are all Level Sensitive, and Positive Polarity */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | static u_char mpc85xx_cds_openpic_initsenses[] __initdata = { |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 72 | MPC85XX_INTERNAL_IRQ_SENSES, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | #if defined(CONFIG_PCI) |
| 74 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */ |
| 75 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */ |
| 76 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */ |
| 77 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */ |
| 78 | #else |
| 79 | 0x0, /* External 0: */ |
| 80 | 0x0, /* External 1: */ |
| 81 | 0x0, /* External 2: */ |
| 82 | 0x0, /* External 3: */ |
| 83 | #endif |
| 84 | 0x0, /* External 4: */ |
| 85 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */ |
| 86 | 0x0, /* External 6: */ |
| 87 | 0x0, /* External 7: */ |
| 88 | 0x0, /* External 8: */ |
| 89 | 0x0, /* External 9: */ |
| 90 | 0x0, /* External 10: */ |
| 91 | #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI) |
| 92 | (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */ |
| 93 | #else |
| 94 | 0x0, /* External 11: */ |
| 95 | #endif |
| 96 | }; |
| 97 | |
| 98 | /* ************************************************************************ */ |
| 99 | int |
| 100 | mpc85xx_cds_show_cpuinfo(struct seq_file *m) |
| 101 | { |
| 102 | uint pvid, svid, phid1; |
| 103 | uint memsize = total_memory; |
| 104 | bd_t *binfo = (bd_t *) __res; |
| 105 | unsigned int freq; |
| 106 | |
| 107 | /* get the core frequency */ |
| 108 | freq = binfo->bi_intfreq; |
| 109 | |
| 110 | pvid = mfspr(SPRN_PVR); |
| 111 | svid = mfspr(SPRN_SVR); |
| 112 | |
| 113 | seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); |
| 114 | seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]); |
| 115 | seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000); |
| 116 | seq_printf(m, "PVR\t\t: 0x%x\n", pvid); |
| 117 | seq_printf(m, "SVR\t\t: 0x%x\n", svid); |
| 118 | |
| 119 | /* Display cpu Pll setting */ |
| 120 | phid1 = mfspr(SPRN_HID1); |
| 121 | seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f)); |
| 122 | |
| 123 | /* Display the amount of memory */ |
| 124 | seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024)); |
| 125 | |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | #ifdef CONFIG_CPM2 |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 130 | static irqreturn_t cpm2_cascade(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | { |
Olaf Hering | 35a84c2 | 2006-10-07 22:08:26 +1000 | [diff] [blame] | 132 | while((irq = cpm2_get_irq()) >= 0) |
| 133 | __do_IRQ(irq); |
Edson Seabra | b273ed2 | 2005-12-19 09:16:50 -0600 | [diff] [blame] | 134 | return IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static struct irqaction cpm2_irqaction = { |
| 138 | .handler = cpm2_cascade, |
Thomas Gleixner | bc59d28 | 2006-07-01 19:29:22 -0700 | [diff] [blame] | 139 | .flags = IRQF_DISABLED, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | .mask = CPU_MASK_NONE, |
| 141 | .name = "cpm2_cascade", |
| 142 | }; |
| 143 | #endif /* CONFIG_CPM2 */ |
| 144 | |
| 145 | void __init |
| 146 | mpc85xx_cds_init_IRQ(void) |
| 147 | { |
| 148 | bd_t *binfo = (bd_t *) __res; |
Kumar Gala | f1b0477 | 2005-06-22 15:10:02 -0500 | [diff] [blame] | 149 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | |
| 151 | /* Determine the Physical Address of the OpenPIC regs */ |
| 152 | phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET; |
| 153 | OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE); |
| 154 | OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses; |
| 155 | OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses); |
| 156 | |
| 157 | /* Skip reserved space and internal sources */ |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 158 | #ifdef CONFIG_MPC8548 |
| 159 | openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200); |
| 160 | #else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200); |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 162 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | /* Map PIC IRQs 0-11 */ |
Kumar Gala | 65145e0 | 2005-06-21 17:15:25 -0700 | [diff] [blame] | 164 | openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | |
| 166 | /* we let openpic interrupts starting from an offset, to |
| 167 | * leave space for cascading interrupts underneath. |
| 168 | */ |
| 169 | openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET); |
| 170 | |
Kumar Gala | 6cf2b3f | 2005-05-28 15:52:15 -0700 | [diff] [blame] | 171 | #ifdef CONFIG_PCI |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 172 | openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq); |
| 173 | |
Paul Mackerras | f9bd170 | 2005-10-26 16:47:42 +1000 | [diff] [blame] | 174 | i8259_init(0, 0); |
Kumar Gala | 6cf2b3f | 2005-05-28 15:52:15 -0700 | [diff] [blame] | 175 | #endif |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 176 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | #ifdef CONFIG_CPM2 |
| 178 | /* Setup CPM2 PIC */ |
| 179 | cpm2_init_IRQ(); |
| 180 | |
| 181 | setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction); |
| 182 | #endif |
| 183 | |
| 184 | return; |
| 185 | } |
| 186 | |
| 187 | #ifdef CONFIG_PCI |
| 188 | /* |
| 189 | * interrupt routing |
| 190 | */ |
| 191 | int |
| 192 | mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 193 | { |
| 194 | struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); |
| 195 | |
| 196 | if (!hose->index) |
| 197 | { |
| 198 | /* Handle PCI1 interrupts */ |
| 199 | char pci_irq_table[][4] = |
| 200 | /* |
| 201 | * PCI IDSEL/INTPIN->INTLINE |
| 202 | * A B C D |
| 203 | */ |
| 204 | |
| 205 | /* Note IRQ assignment for slots is based on which slot the elysium is |
| 206 | * in -- in this setup elysium is in slot #2 (this PIRQA as first |
| 207 | * interrupt on slot */ |
| 208 | { |
| 209 | { 0, 1, 2, 3 }, /* 16 - PMC */ |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 210 | { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | { 0, 1, 2, 3 }, /* 18 - Slot 1 */ |
| 212 | { 1, 2, 3, 0 }, /* 19 - Slot 2 */ |
| 213 | { 2, 3, 0, 1 }, /* 20 - Slot 3 */ |
| 214 | { 3, 0, 1, 2 }, /* 21 - Slot 4 */ |
| 215 | }; |
| 216 | |
| 217 | const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4; |
| 218 | int i, j; |
| 219 | |
| 220 | for (i = 0; i < 6; i++) |
| 221 | for (j = 0; j < 4; j++) |
| 222 | pci_irq_table[i][j] = |
| 223 | ((pci_irq_table[i][j] + 5 - |
| 224 | cds_pci_slot) & 0x3) + PIRQ0A; |
| 225 | |
| 226 | return PCI_IRQ_TABLE_LOOKUP; |
| 227 | } else { |
| 228 | /* Handle PCI2 interrupts (if we have one) */ |
| 229 | char pci_irq_table[][4] = |
| 230 | { |
| 231 | /* |
| 232 | * We only have one slot and one interrupt |
| 233 | * going to PIRQA - PIRQD */ |
| 234 | { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */ |
| 235 | }; |
| 236 | |
| 237 | const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4; |
| 238 | |
| 239 | return PCI_IRQ_TABLE_LOOKUP; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | #define ARCADIA_HOST_BRIDGE_IDSEL 17 |
| 244 | #define ARCADIA_2ND_BRIDGE_IDSEL 3 |
| 245 | |
| 246 | extern int mpc85xx_pci1_last_busno; |
| 247 | |
| 248 | int |
| 249 | mpc85xx_exclude_device(u_char bus, u_char devfn) |
| 250 | { |
| 251 | if (bus == 0 && PCI_SLOT(devfn) == 0) |
| 252 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 253 | #ifdef CONFIG_85xx_PCI2 |
| 254 | if (mpc85xx_pci1_last_busno) |
| 255 | if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0) |
| 256 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 257 | #endif |
| 258 | /* We explicitly do not go past the Tundra 320 Bridge */ |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 259 | if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 261 | if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) |
| 262 | return PCIBIOS_DEVICE_NOT_FOUND; |
| 263 | else |
| 264 | return PCIBIOS_SUCCESSFUL; |
| 265 | } |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 266 | |
| 267 | void __init |
| 268 | mpc85xx_cds_enable_via(struct pci_controller *hose) |
| 269 | { |
| 270 | u32 pci_class; |
| 271 | u16 vid, did; |
| 272 | |
| 273 | early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class); |
| 274 | if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI) |
| 275 | return; |
| 276 | |
| 277 | /* Configure P2P so that we can reach bus 1 */ |
| 278 | early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0); |
| 279 | early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1); |
| 280 | early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff); |
| 281 | |
| 282 | early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid); |
| 283 | early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did); |
| 284 | |
| 285 | if ((vid != PCI_VENDOR_ID_VIA) || |
| 286 | (did != PCI_DEVICE_ID_VIA_82C686)) |
| 287 | return; |
| 288 | |
| 289 | /* Enable USB and IDE functions */ |
| 290 | early_write_config_byte(hose, 1, 0x10, 0x48, 0x08); |
| 291 | } |
| 292 | |
| 293 | void __init |
| 294 | mpc85xx_cds_fixup_via(struct pci_controller *hose) |
| 295 | { |
| 296 | u32 pci_class; |
| 297 | u16 vid, did; |
| 298 | |
| 299 | early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class); |
| 300 | if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI) |
| 301 | return; |
| 302 | |
| 303 | /* |
| 304 | * Force the backplane P2P bridge to have a window |
| 305 | * open from 0x00000000-0x00001fff in PCI I/O space. |
| 306 | * This allows legacy I/O (i8259, etc) on the VIA |
| 307 | * southbridge to be accessed. |
| 308 | */ |
| 309 | early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00); |
| 310 | early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000); |
| 311 | early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10); |
| 312 | early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000); |
| 313 | |
| 314 | early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid); |
| 315 | early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did); |
| 316 | if ((vid != PCI_VENDOR_ID_VIA) || |
| 317 | (did != PCI_DEVICE_ID_VIA_82C686)) |
| 318 | return; |
| 319 | |
| 320 | /* |
| 321 | * Since the P2P window was forced to cover the fixed |
| 322 | * legacy I/O addresses, it is necessary to manually |
| 323 | * place the base addresses for the IDE and USB functions |
| 324 | * within this window. |
| 325 | */ |
| 326 | /* Function 1, IDE */ |
| 327 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8); |
| 328 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4); |
| 329 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8); |
| 330 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4); |
| 331 | early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0); |
| 332 | |
| 333 | /* Function 2, USB ports 0-1 */ |
| 334 | early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0); |
| 335 | |
| 336 | /* Function 3, USB ports 2-3 */ |
| 337 | early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80); |
| 338 | |
| 339 | /* Function 5, Power Management */ |
| 340 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00); |
| 341 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc); |
| 342 | early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8); |
| 343 | |
| 344 | /* Function 6, AC97 Interface */ |
| 345 | early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00); |
| 346 | } |
| 347 | |
| 348 | void __init |
| 349 | mpc85xx_cds_pcibios_fixup(void) |
| 350 | { |
Jiri Slaby | 48d6877 | 2005-11-06 23:39:35 -0800 | [diff] [blame] | 351 | struct pci_dev *dev; |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 352 | u_char c; |
| 353 | |
Jiri Slaby | 48d6877 | 2005-11-06 23:39:35 -0800 | [diff] [blame] | 354 | if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 355 | PCI_DEVICE_ID_VIA_82C586_1, NULL))) { |
| 356 | /* |
| 357 | * U-Boot does not set the enable bits |
| 358 | * for the IDE device. Force them on here. |
| 359 | */ |
| 360 | pci_read_config_byte(dev, 0x40, &c); |
| 361 | c |= 0x03; /* IDE: Chip Enable Bits */ |
| 362 | pci_write_config_byte(dev, 0x40, c); |
| 363 | |
| 364 | /* |
| 365 | * Since only primary interface works, force the |
| 366 | * IDE function to standard primary IDE interrupt |
| 367 | * w/ 8259 offset |
| 368 | */ |
| 369 | dev->irq = 14; |
| 370 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); |
Jiri Slaby | 48d6877 | 2005-11-06 23:39:35 -0800 | [diff] [blame] | 371 | pci_dev_put(dev); |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 372 | } |
| 373 | |
| 374 | /* |
| 375 | * Force legacy USB interrupt routing |
| 376 | */ |
Jiri Slaby | 48d6877 | 2005-11-06 23:39:35 -0800 | [diff] [blame] | 377 | if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 378 | PCI_DEVICE_ID_VIA_82C586_2, NULL))) { |
| 379 | dev->irq = 10; |
| 380 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10); |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 381 | |
Greg Kroah-Hartman | 4d15a17 | 2006-06-06 16:58:25 -0400 | [diff] [blame] | 382 | if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 383 | PCI_DEVICE_ID_VIA_82C586_2, dev))) { |
Greg Kroah-Hartman | 4d15a17 | 2006-06-06 16:58:25 -0400 | [diff] [blame] | 384 | dev->irq = 11; |
| 385 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); |
| 386 | } |
Jiri Slaby | 48d6877 | 2005-11-06 23:39:35 -0800 | [diff] [blame] | 387 | pci_dev_put(dev); |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 388 | } |
| 389 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | #endif /* CONFIG_PCI */ |
| 391 | |
| 392 | TODC_ALLOC(); |
| 393 | |
| 394 | /* ************************************************************************ |
| 395 | * |
| 396 | * Setup the architecture |
| 397 | * |
| 398 | */ |
| 399 | static void __init |
| 400 | mpc85xx_cds_setup_arch(void) |
| 401 | { |
| 402 | bd_t *binfo = (bd_t *) __res; |
| 403 | unsigned int freq; |
| 404 | struct gianfar_platform_data *pdata; |
Andy Fleming | b37665e | 2005-10-28 17:46:27 -0700 | [diff] [blame] | 405 | struct gianfar_mdio_data *mdata; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | |
| 407 | /* get the core frequency */ |
| 408 | freq = binfo->bi_intfreq; |
| 409 | |
| 410 | printk("mpc85xx_cds_setup_arch\n"); |
| 411 | |
| 412 | #ifdef CONFIG_CPM2 |
| 413 | cpm2_reset(); |
| 414 | #endif |
| 415 | |
| 416 | cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); |
| 417 | cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; |
| 418 | printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot); |
| 419 | |
| 420 | /* Setup TODC access */ |
| 421 | TODC_INIT(TODC_TYPE_DS1743, |
| 422 | 0, |
| 423 | 0, |
| 424 | ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE), |
| 425 | 8); |
| 426 | |
| 427 | /* Set loops_per_jiffy to a half-way reasonable value, |
| 428 | for use until calibrate_delay gets called. */ |
| 429 | loops_per_jiffy = freq / HZ; |
| 430 | |
| 431 | #ifdef CONFIG_PCI |
Kumar Gala | 91f9855 | 2005-05-28 15:52:12 -0700 | [diff] [blame] | 432 | /* VIA IDE configuration */ |
| 433 | ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup; |
| 434 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | /* setup PCI host bridges */ |
| 436 | mpc85xx_setup_hose(); |
| 437 | #endif |
| 438 | |
| 439 | #ifdef CONFIG_SERIAL_8250 |
| 440 | mpc85xx_early_serial_map(); |
| 441 | #endif |
| 442 | |
| 443 | #ifdef CONFIG_SERIAL_TEXT_DEBUG |
| 444 | /* Invalidate the entry we stole earlier the serial ports |
| 445 | * should be properly mapped */ |
Kumar Gala | 5be061e | 2005-06-21 17:15:26 -0700 | [diff] [blame] | 446 | invalidate_tlbcam_entry(num_tlbcam_entries - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | #endif |
| 448 | |
Andy Fleming | b37665e | 2005-10-28 17:46:27 -0700 | [diff] [blame] | 449 | /* setup the board related info for the MDIO bus */ |
| 450 | mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO); |
| 451 | |
| 452 | mdata->irq[0] = MPC85xx_IRQ_EXT5; |
| 453 | mdata->irq[1] = MPC85xx_IRQ_EXT5; |
Andy Fleming | a9b1497 | 2006-10-19 19:52:26 -0500 | [diff] [blame] | 454 | mdata->irq[2] = PHY_POLL; |
| 455 | mdata->irq[3] = PHY_POLL; |
| 456 | mdata->irq[31] = PHY_POLL; |
Andy Fleming | b37665e | 2005-10-28 17:46:27 -0700 | [diff] [blame] | 457 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 458 | /* setup the board related information for the enet controllers */ |
| 459 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1); |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 460 | if (pdata) { |
| 461 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 462 | pdata->bus_id = 0; |
| 463 | pdata->phy_id = 0; |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 464 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
| 465 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 466 | |
| 467 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2); |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 468 | if (pdata) { |
| 469 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 470 | pdata->bus_id = 0; |
| 471 | pdata->phy_id = 1; |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 472 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
| 473 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 475 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1); |
| 476 | if (pdata) { |
| 477 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 478 | pdata->bus_id = 0; |
| 479 | pdata->phy_id = 0; |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 480 | memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6); |
| 481 | } |
| 482 | |
| 483 | pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2); |
| 484 | if (pdata) { |
| 485 | pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; |
Kumar Gala | 7e78e5e | 2006-01-12 21:04:23 -0600 | [diff] [blame] | 486 | pdata->bus_id = 0; |
| 487 | pdata->phy_id = 1; |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 488 | memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6); |
| 489 | } |
| 490 | |
| 491 | ppc_sys_device_remove(MPC85xx_eTSEC3); |
| 492 | ppc_sys_device_remove(MPC85xx_eTSEC4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | |
| 494 | #ifdef CONFIG_BLK_DEV_INITRD |
| 495 | if (initrd_start) |
| 496 | ROOT_DEV = Root_RAM0; |
| 497 | else |
| 498 | #endif |
| 499 | #ifdef CONFIG_ROOT_NFS |
| 500 | ROOT_DEV = Root_NFS; |
| 501 | #else |
| 502 | ROOT_DEV = Root_HDA1; |
| 503 | #endif |
| 504 | } |
| 505 | |
| 506 | /* ************************************************************************ */ |
| 507 | void __init |
| 508 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 509 | unsigned long r6, unsigned long r7) |
| 510 | { |
| 511 | /* parse_bootinfo must always be called first */ |
| 512 | parse_bootinfo(find_bootinfo()); |
| 513 | |
| 514 | /* |
| 515 | * If we were passed in a board information, copy it into the |
| 516 | * residual data area. |
| 517 | */ |
| 518 | if (r3) { |
| 519 | memcpy((void *) __res, (void *) (r3 + KERNELBASE), |
| 520 | sizeof (bd_t)); |
| 521 | |
| 522 | } |
| 523 | #ifdef CONFIG_SERIAL_TEXT_DEBUG |
| 524 | { |
| 525 | bd_t *binfo = (bd_t *) __res; |
| 526 | struct uart_port p; |
| 527 | |
| 528 | /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */ |
Kumar Gala | 5be061e | 2005-06-21 17:15:26 -0700 | [diff] [blame] | 529 | settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0); |
| 531 | |
| 532 | memset(&p, 0, sizeof (p)); |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 533 | p.iotype = UPIO_MEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET; |
| 535 | p.uartclk = binfo->bi_busfreq; |
| 536 | |
| 537 | gen550_init(0, &p); |
| 538 | |
| 539 | memset(&p, 0, sizeof (p)); |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 540 | p.iotype = UPIO_MEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET; |
| 542 | p.uartclk = binfo->bi_busfreq; |
| 543 | |
| 544 | gen550_init(1, &p); |
| 545 | } |
| 546 | #endif |
| 547 | |
| 548 | #if defined(CONFIG_BLK_DEV_INITRD) |
| 549 | /* |
| 550 | * If the init RAM disk has been configured in, and there's a valid |
| 551 | * starting address for it, set it up. |
| 552 | */ |
| 553 | if (r4) { |
| 554 | initrd_start = r4 + KERNELBASE; |
| 555 | initrd_end = r5 + KERNELBASE; |
| 556 | } |
| 557 | #endif /* CONFIG_BLK_DEV_INITRD */ |
| 558 | |
| 559 | /* Copy the kernel command line arguments to a safe place. */ |
| 560 | |
| 561 | if (r6) { |
| 562 | *(char *) (r7 + KERNELBASE) = 0; |
| 563 | strcpy(cmd_line, (char *) (r6 + KERNELBASE)); |
| 564 | } |
| 565 | |
| 566 | identify_ppc_sys_by_id(mfspr(SPRN_SVR)); |
| 567 | |
| 568 | /* setup the PowerPC module struct */ |
| 569 | ppc_md.setup_arch = mpc85xx_cds_setup_arch; |
| 570 | ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo; |
| 571 | |
| 572 | ppc_md.init_IRQ = mpc85xx_cds_init_IRQ; |
| 573 | ppc_md.get_irq = openpic_get_irq; |
| 574 | |
| 575 | ppc_md.restart = mpc85xx_restart; |
| 576 | ppc_md.power_off = mpc85xx_power_off; |
| 577 | ppc_md.halt = mpc85xx_halt; |
| 578 | |
| 579 | ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory; |
| 580 | |
| 581 | ppc_md.calibrate_decr = mpc85xx_calibrate_decr; |
| 582 | |
| 583 | ppc_md.time_init = todc_time_init; |
| 584 | ppc_md.set_rtc_time = todc_set_rtc_time; |
| 585 | ppc_md.get_rtc_time = todc_get_rtc_time; |
| 586 | |
| 587 | ppc_md.nvram_read_val = todc_direct_read_val; |
| 588 | ppc_md.nvram_write_val = todc_direct_write_val; |
| 589 | |
| 590 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG) |
| 591 | ppc_md.progress = gen550_progress; |
| 592 | #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */ |
Kumar Gala | 252fcae | 2005-05-28 15:52:06 -0700 | [diff] [blame] | 593 | #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB) |
| 594 | ppc_md.early_serial_map = mpc85xx_early_serial_map; |
| 595 | #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | |
| 597 | if (ppc_md.progress) |
| 598 | ppc_md.progress("mpc85xx_cds_init(): exit", 0); |
| 599 | |
| 600 | return; |
| 601 | } |