Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Disk Array driver for HP Smart Array SAS controllers |
Scott Teel | 51c3513 | 2014-02-18 13:57:26 -0600 | [diff] [blame] | 3 | * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 12 | * NON INFRINGEMENT. See the GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 17 | * |
| 18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com |
| 19 | * |
| 20 | */ |
| 21 | #ifndef HPSA_H |
| 22 | #define HPSA_H |
| 23 | |
| 24 | #include <scsi/scsicam.h> |
| 25 | |
| 26 | #define IO_OK 0 |
| 27 | #define IO_ERROR 1 |
| 28 | |
| 29 | struct ctlr_info; |
| 30 | |
| 31 | struct access_method { |
| 32 | void (*submit_command)(struct ctlr_info *h, |
| 33 | struct CommandList *c); |
| 34 | void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); |
| 35 | unsigned long (*fifo_full)(struct ctlr_info *h); |
Stephen M. Cameron | 900c544 | 2010-02-04 08:42:35 -0600 | [diff] [blame] | 36 | bool (*intr_pending)(struct ctlr_info *h); |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 37 | unsigned long (*command_completed)(struct ctlr_info *h, u8 q); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | struct hpsa_scsi_dev_t { |
| 41 | int devtype; |
| 42 | int bus, target, lun; /* as presented to the OS */ |
| 43 | unsigned char scsi3addr[8]; /* as presented to the HW */ |
| 44 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" |
| 45 | unsigned char device_id[16]; /* from inquiry pg. 0x83 */ |
| 46 | unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ |
| 47 | unsigned char model[16]; /* bytes 16-31 of inquiry data */ |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 48 | unsigned char raid_level; /* from inquiry page 0xC1 */ |
Stephen M. Cameron | 9846590 | 2014-02-21 16:25:00 -0600 | [diff] [blame] | 49 | unsigned char volume_offline; /* discovered via TUR or VPD */ |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 50 | u32 ioaccel_handle; |
Stephen M. Cameron | 283b4a9 | 2014-02-18 13:55:33 -0600 | [diff] [blame] | 51 | int offload_config; /* I/O accel RAID offload configured */ |
| 52 | int offload_enabled; /* I/O accel RAID offload enabled */ |
| 53 | int offload_to_mirror; /* Send next I/O accelerator RAID |
| 54 | * offload request to mirror drive |
| 55 | */ |
| 56 | struct raid_map_data raid_map; /* I/O accelerator RAID map */ |
| 57 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 58 | }; |
| 59 | |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 60 | struct reply_pool { |
| 61 | u64 *head; |
| 62 | size_t size; |
| 63 | u8 wraparound; |
| 64 | u32 current_entry; |
| 65 | }; |
| 66 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 67 | struct ctlr_info { |
| 68 | int ctlr; |
| 69 | char devname[8]; |
| 70 | char *product_name; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 71 | struct pci_dev *pdev; |
Stephen M. Cameron | 01a02ff | 2010-02-04 08:41:33 -0600 | [diff] [blame] | 72 | u32 board_id; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 73 | void __iomem *vaddr; |
| 74 | unsigned long paddr; |
| 75 | int nr_cmds; /* Number of commands allowed on this controller */ |
| 76 | struct CfgTable __iomem *cfgtable; |
| 77 | int interrupts_enabled; |
| 78 | int major; |
| 79 | int max_commands; |
| 80 | int commands_outstanding; |
| 81 | int max_outstanding; /* Debug */ |
| 82 | int usage_count; /* number of opens all all minor devices */ |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 83 | # define PERF_MODE_INT 0 |
| 84 | # define DOORBELL_INT 1 |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 85 | # define SIMPLE_MODE_INT 2 |
| 86 | # define MEMQ_MODE_INT 3 |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 87 | unsigned int intr[MAX_REPLY_QUEUES]; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 88 | unsigned int msix_vector; |
| 89 | unsigned int msi_vector; |
Stephen M. Cameron | a9a3a27 | 2011-02-15 15:32:53 -0600 | [diff] [blame] | 90 | int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 91 | struct access_method access; |
| 92 | |
| 93 | /* queue and queue Info */ |
Stephen M. Cameron | 9e0fc76 | 2011-02-15 15:32:48 -0600 | [diff] [blame] | 94 | struct list_head reqQ; |
| 95 | struct list_head cmpQ; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 96 | unsigned int Qdepth; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 97 | unsigned int maxSG; |
| 98 | spinlock_t lock; |
Stephen M. Cameron | 33a2ffc | 2010-02-25 14:03:27 -0600 | [diff] [blame] | 99 | int maxsgentries; |
| 100 | u8 max_cmd_sg_entries; |
| 101 | int chainsize; |
| 102 | struct SGDescriptor **cmd_sg_list; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 103 | |
| 104 | /* pointers to command and error info pool */ |
| 105 | struct CommandList *cmd_pool; |
| 106 | dma_addr_t cmd_pool_dhandle; |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 107 | struct io_accel1_cmd *ioaccel_cmd_pool; |
| 108 | dma_addr_t ioaccel_cmd_pool_dhandle; |
Stephen M. Cameron | aca9012 | 2014-02-18 13:56:14 -0600 | [diff] [blame] | 109 | struct io_accel2_cmd *ioaccel2_cmd_pool; |
| 110 | dma_addr_t ioaccel2_cmd_pool_dhandle; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 111 | struct ErrorInfo *errinfo_pool; |
| 112 | dma_addr_t errinfo_pool_dhandle; |
| 113 | unsigned long *cmd_pool_bits; |
Stephen M. Cameron | a08a847 | 2010-02-04 08:43:16 -0600 | [diff] [blame] | 114 | int scan_finished; |
| 115 | spinlock_t scan_lock; |
| 116 | wait_queue_head_t scan_wait_queue; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 117 | |
| 118 | struct Scsi_Host *scsi_host; |
| 119 | spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ |
| 120 | int ndevices; /* number of used elements in .dev[] array. */ |
Scott Teel | cfe5bad | 2011-10-26 16:21:07 -0500 | [diff] [blame] | 121 | struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 122 | /* |
| 123 | * Performant mode tables. |
| 124 | */ |
| 125 | u32 trans_support; |
| 126 | u32 trans_offset; |
| 127 | struct TransTable_struct *transtable; |
| 128 | unsigned long transMethod; |
| 129 | |
Stephen M. Cameron | 0390f0c | 2013-09-23 13:34:12 -0500 | [diff] [blame] | 130 | /* cap concurrent passthrus at some reasonable maximum */ |
| 131 | #define HPSA_MAX_CONCURRENT_PASSTHRUS (20) |
| 132 | spinlock_t passthru_count_lock; /* protects passthru_count */ |
| 133 | int passthru_count; |
| 134 | |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 135 | /* |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 136 | * Performant mode completion buffers |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 137 | */ |
| 138 | u64 *reply_pool; |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 139 | size_t reply_pool_size; |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 140 | struct reply_pool reply_queue[MAX_REPLY_QUEUES]; |
| 141 | u8 nreply_queues; |
| 142 | dma_addr_t reply_pool_dhandle; |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 143 | u32 *blockFetchTable; |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 144 | u32 *ioaccel1_blockFetchTable; |
Stephen M. Cameron | aca9012 | 2014-02-18 13:56:14 -0600 | [diff] [blame] | 145 | u32 *ioaccel2_blockFetchTable; |
Stephen M. Cameron | b9af493 | 2014-02-18 13:56:29 -0600 | [diff] [blame] | 146 | u32 *ioaccel2_bft2_regs; |
Stephen M. Cameron | 339b2b1 | 2010-02-04 08:42:50 -0600 | [diff] [blame] | 147 | unsigned char *hba_inquiry_data; |
Stephen M. Cameron | 283b4a9 | 2014-02-18 13:55:33 -0600 | [diff] [blame] | 148 | u32 driver_support; |
| 149 | u32 fw_support; |
| 150 | int ioaccel_support; |
| 151 | int ioaccel_maxsg; |
Stephen M. Cameron | a0c1241 | 2011-10-26 16:22:04 -0500 | [diff] [blame] | 152 | u64 last_intr_timestamp; |
| 153 | u32 last_heartbeat; |
| 154 | u64 last_heartbeat_timestamp; |
Stephen M. Cameron | e85c597 | 2012-05-01 11:43:42 -0500 | [diff] [blame] | 155 | u32 heartbeat_sample_interval; |
| 156 | atomic_t firmware_flash_in_progress; |
Stephen M. Cameron | a0c1241 | 2011-10-26 16:22:04 -0500 | [diff] [blame] | 157 | u32 lockup_detected; |
Stephen M. Cameron | 8a98db73 | 2013-12-04 17:10:07 -0600 | [diff] [blame] | 158 | struct delayed_work monitor_ctlr_work; |
| 159 | int remove_in_progress; |
Stephen M. Cameron | 396883e | 2013-09-23 13:34:17 -0500 | [diff] [blame] | 160 | u32 fifo_recently_full; |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 161 | /* Address of h->q[x] is passed to intr handler to know which queue */ |
| 162 | u8 q[MAX_REPLY_QUEUES]; |
Stephen M. Cameron | 75167d2 | 2012-05-01 11:42:51 -0500 | [diff] [blame] | 163 | u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ |
| 164 | #define HPSATMF_BITS_SUPPORTED (1 << 0) |
| 165 | #define HPSATMF_PHYS_LUN_RESET (1 << 1) |
| 166 | #define HPSATMF_PHYS_NEX_RESET (1 << 2) |
| 167 | #define HPSATMF_PHYS_TASK_ABORT (1 << 3) |
| 168 | #define HPSATMF_PHYS_TSET_ABORT (1 << 4) |
| 169 | #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) |
| 170 | #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) |
| 171 | #define HPSATMF_PHYS_QRY_TASK (1 << 7) |
| 172 | #define HPSATMF_PHYS_QRY_TSET (1 << 8) |
| 173 | #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) |
| 174 | #define HPSATMF_MASK_SUPPORTED (1 << 16) |
| 175 | #define HPSATMF_LOG_LUN_RESET (1 << 17) |
| 176 | #define HPSATMF_LOG_NEX_RESET (1 << 18) |
| 177 | #define HPSATMF_LOG_TASK_ABORT (1 << 19) |
| 178 | #define HPSATMF_LOG_TSET_ABORT (1 << 20) |
| 179 | #define HPSATMF_LOG_CLEAR_ACA (1 << 21) |
| 180 | #define HPSATMF_LOG_CLEAR_TSET (1 << 22) |
| 181 | #define HPSATMF_LOG_QRY_TASK (1 << 23) |
| 182 | #define HPSATMF_LOG_QRY_TSET (1 << 24) |
| 183 | #define HPSATMF_LOG_QRY_ASYNC (1 << 25) |
Stephen M. Cameron | 76438d0 | 2014-02-18 13:55:43 -0600 | [diff] [blame] | 184 | u32 events; |
Stephen M. Cameron | faff6ee | 2014-02-18 13:57:42 -0600 | [diff] [blame] | 185 | #define CTLR_STATE_CHANGE_EVENT (1 << 0) |
| 186 | #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) |
| 187 | #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) |
| 188 | #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) |
| 189 | #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) |
| 190 | #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) |
| 191 | #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) |
| 192 | |
| 193 | #define RESCAN_REQUIRED_EVENT_BITS \ |
| 194 | (CTLR_STATE_CHANGE_EVENT | \ |
| 195 | CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ |
| 196 | CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ |
| 197 | CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ |
| 198 | CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL | \ |
| 199 | CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ |
| 200 | CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) |
Stephen M. Cameron | 9846590 | 2014-02-21 16:25:00 -0600 | [diff] [blame] | 201 | spinlock_t offline_device_lock; |
| 202 | struct list_head offline_device_list; |
Scott Teel | da0697b | 2014-02-18 13:57:00 -0600 | [diff] [blame] | 203 | int acciopath_status; |
Scott Teel | e863d68 | 2014-02-18 13:57:05 -0600 | [diff] [blame] | 204 | int drv_req_rescan; /* flag for driver to request rescan event */ |
Stephen M. Cameron | 2ba8bfc | 2014-02-18 13:57:52 -0600 | [diff] [blame] | 205 | int raid_offload_debug; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 206 | }; |
Stephen M. Cameron | 9846590 | 2014-02-21 16:25:00 -0600 | [diff] [blame] | 207 | |
| 208 | struct offline_device_entry { |
| 209 | unsigned char scsi3addr[8]; |
| 210 | struct list_head offline_list; |
| 211 | }; |
| 212 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 213 | #define HPSA_ABORT_MSG 0 |
| 214 | #define HPSA_DEVICE_RESET_MSG 1 |
Stephen M. Cameron | 64670ac | 2011-05-03 14:59:51 -0500 | [diff] [blame] | 215 | #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
| 216 | #define HPSA_RESET_TYPE_BUS 0x01 |
| 217 | #define HPSA_RESET_TYPE_TARGET 0x03 |
| 218 | #define HPSA_RESET_TYPE_LUN 0x04 |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 219 | #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
Stephen M. Cameron | 516fda4 | 2011-05-03 14:59:15 -0500 | [diff] [blame] | 220 | #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 221 | |
| 222 | /* Maximum time in seconds driver will wait for command completions |
| 223 | * when polling before giving up. |
| 224 | */ |
| 225 | #define HPSA_MAX_POLL_TIME_SECS (20) |
| 226 | |
| 227 | /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines |
| 228 | * how many times to retry TEST UNIT READY on a device |
| 229 | * while waiting for it to become ready before giving up. |
| 230 | * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval |
| 231 | * between sending TURs while waiting for a device |
| 232 | * to become ready. |
| 233 | */ |
| 234 | #define HPSA_TUR_RETRY_LIMIT (20) |
| 235 | #define HPSA_MAX_WAIT_INTERVAL_SECS (30) |
| 236 | |
| 237 | /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board |
| 238 | * to become ready, in seconds, before giving up on it. |
| 239 | * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait |
| 240 | * between polling the board to see if it is ready, in |
| 241 | * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and |
| 242 | * HPSA_BOARD_READY_ITERATIONS are derived from those. |
| 243 | */ |
| 244 | #define HPSA_BOARD_READY_WAIT_SECS (120) |
Stephen M. Cameron | 2ed7127 | 2011-05-03 14:59:31 -0500 | [diff] [blame] | 245 | #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 246 | #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
| 247 | #define HPSA_BOARD_READY_POLL_INTERVAL \ |
| 248 | ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) |
| 249 | #define HPSA_BOARD_READY_ITERATIONS \ |
| 250 | ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ |
| 251 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) |
Stephen M. Cameron | fe5389c | 2011-01-06 14:48:03 -0600 | [diff] [blame] | 252 | #define HPSA_BOARD_NOT_READY_ITERATIONS \ |
| 253 | ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ |
| 254 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 255 | #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
| 256 | #define HPSA_POST_RESET_NOOP_RETRIES (12) |
| 257 | |
| 258 | /* Defining the diffent access_menthods */ |
| 259 | /* |
| 260 | * Memory mapped FIFO interface (SMART 53xx cards) |
| 261 | */ |
| 262 | #define SA5_DOORBELL 0x20 |
| 263 | #define SA5_REQUEST_PORT_OFFSET 0x40 |
| 264 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
| 265 | #define SA5_REPLY_PORT_OFFSET 0x44 |
| 266 | #define SA5_INTR_STATUS 0x30 |
| 267 | #define SA5_SCRATCHPAD_OFFSET 0xB0 |
| 268 | |
| 269 | #define SA5_CTCFG_OFFSET 0xB4 |
| 270 | #define SA5_CTMEM_OFFSET 0xB8 |
| 271 | |
| 272 | #define SA5_INTR_OFF 0x08 |
| 273 | #define SA5B_INTR_OFF 0x04 |
| 274 | #define SA5_INTR_PENDING 0x08 |
| 275 | #define SA5B_INTR_PENDING 0x04 |
| 276 | #define FIFO_EMPTY 0xffffffff |
| 277 | #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ |
| 278 | |
| 279 | #define HPSA_ERROR_BIT 0x02 |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 280 | |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 281 | /* Performant mode flags */ |
| 282 | #define SA5_PERF_INTR_PENDING 0x04 |
| 283 | #define SA5_PERF_INTR_OFF 0x05 |
| 284 | #define SA5_OUTDB_STATUS_PERF_BIT 0x01 |
| 285 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| 286 | #define SA5_OUTDB_CLEAR 0xA0 |
| 287 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 |
| 288 | #define SA5_OUTDB_STATUS 0x9C |
| 289 | |
| 290 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 291 | #define HPSA_INTR_ON 1 |
| 292 | #define HPSA_INTR_OFF 0 |
Mike Miller | b66cc25 | 2014-02-18 13:56:04 -0600 | [diff] [blame] | 293 | |
| 294 | /* |
| 295 | * Inbound Post Queue offsets for IO Accelerator Mode 2 |
| 296 | */ |
| 297 | #define IOACCEL2_INBOUND_POSTQ_32 0x48 |
| 298 | #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 |
| 299 | #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 |
| 300 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 301 | /* |
| 302 | Send the command to the hardware |
| 303 | */ |
| 304 | static void SA5_submit_command(struct ctlr_info *h, |
| 305 | struct CommandList *c) |
| 306 | { |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 307 | dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, |
| 308 | c->Header.Tag.lower); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 309 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
Stephen M. Cameron | fec62c3 | 2011-07-21 13:16:05 -0500 | [diff] [blame] | 310 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 311 | } |
| 312 | |
Scott Teel | c349775 | 2014-02-18 13:56:34 -0600 | [diff] [blame] | 313 | static void SA5_submit_command_ioaccel2(struct ctlr_info *h, |
| 314 | struct CommandList *c) |
| 315 | { |
| 316 | dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, |
| 317 | c->Header.Tag.lower); |
| 318 | if (c->cmd_type == CMD_IOACCEL2) |
| 319 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); |
| 320 | else |
| 321 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
| 322 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
| 323 | } |
| 324 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 325 | /* |
| 326 | * This card is the opposite of the other cards. |
| 327 | * 0 turns interrupts on... |
| 328 | * 0x08 turns them off... |
| 329 | */ |
| 330 | static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) |
| 331 | { |
| 332 | if (val) { /* Turn interrupts on */ |
| 333 | h->interrupts_enabled = 1; |
| 334 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | 8cd21da | 2011-05-03 14:58:55 -0500 | [diff] [blame] | 335 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 336 | } else { /* Turn them off */ |
| 337 | h->interrupts_enabled = 0; |
| 338 | writel(SA5_INTR_OFF, |
| 339 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | 8cd21da | 2011-05-03 14:58:55 -0500 | [diff] [blame] | 340 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 341 | } |
| 342 | } |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 343 | |
| 344 | static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) |
| 345 | { |
| 346 | if (val) { /* turn on interrupts */ |
| 347 | h->interrupts_enabled = 1; |
| 348 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | 8cd21da | 2011-05-03 14:58:55 -0500 | [diff] [blame] | 349 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 350 | } else { |
| 351 | h->interrupts_enabled = 0; |
| 352 | writel(SA5_PERF_INTR_OFF, |
| 353 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Stephen M. Cameron | 8cd21da | 2011-05-03 14:58:55 -0500 | [diff] [blame] | 354 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 355 | } |
| 356 | } |
| 357 | |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 358 | static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 359 | { |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 360 | struct reply_pool *rq = &h->reply_queue[q]; |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 361 | unsigned long flags, register_value = FIFO_EMPTY; |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 362 | |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 363 | /* msi auto clears the interrupt pending bit. */ |
| 364 | if (!(h->msi_vector || h->msix_vector)) { |
Stephen M. Cameron | 2c17d2d | 2012-05-01 11:42:30 -0500 | [diff] [blame] | 365 | /* flush the controller write of the reply queue by reading |
| 366 | * outbound doorbell status register. |
| 367 | */ |
| 368 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 369 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
| 370 | /* Do a read in order to flush the write to the controller |
| 371 | * (as per spec.) |
| 372 | */ |
| 373 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); |
| 374 | } |
| 375 | |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 376 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
| 377 | register_value = rq->head[rq->current_entry]; |
| 378 | rq->current_entry++; |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 379 | spin_lock_irqsave(&h->lock, flags); |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 380 | h->commands_outstanding--; |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 381 | spin_unlock_irqrestore(&h->lock, flags); |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 382 | } else { |
| 383 | register_value = FIFO_EMPTY; |
| 384 | } |
| 385 | /* Check for wraparound */ |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 386 | if (rq->current_entry == h->max_commands) { |
| 387 | rq->current_entry = 0; |
| 388 | rq->wraparound ^= 1; |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 389 | } |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 390 | return register_value; |
| 391 | } |
| 392 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 393 | /* |
| 394 | * Returns true if fifo is full. |
| 395 | * |
| 396 | */ |
| 397 | static unsigned long SA5_fifo_full(struct ctlr_info *h) |
| 398 | { |
| 399 | if (h->commands_outstanding >= h->max_commands) |
| 400 | return 1; |
| 401 | else |
| 402 | return 0; |
| 403 | |
| 404 | } |
| 405 | /* |
| 406 | * returns value read from hardware. |
| 407 | * returns FIFO_EMPTY if there is nothing to read |
| 408 | */ |
Matt Gates | 254f796 | 2012-05-01 11:43:06 -0500 | [diff] [blame] | 409 | static unsigned long SA5_completed(struct ctlr_info *h, |
| 410 | __attribute__((unused)) u8 q) |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 411 | { |
| 412 | unsigned long register_value |
| 413 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 414 | unsigned long flags; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 415 | |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 416 | if (register_value != FIFO_EMPTY) { |
| 417 | spin_lock_irqsave(&h->lock, flags); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 418 | h->commands_outstanding--; |
Matt Gates | e16a33a | 2012-05-01 11:43:11 -0500 | [diff] [blame] | 419 | spin_unlock_irqrestore(&h->lock, flags); |
| 420 | } |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 421 | |
| 422 | #ifdef HPSA_DEBUG |
| 423 | if (register_value != FIFO_EMPTY) |
Stephen M. Cameron | 84ca0be | 2010-02-04 08:42:30 -0600 | [diff] [blame] | 424 | dev_dbg(&h->pdev->dev, "Read %lx back from board\n", |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 425 | register_value); |
| 426 | else |
Stephen M. Cameron | f79cfec | 2012-01-19 14:00:59 -0600 | [diff] [blame] | 427 | dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 428 | #endif |
| 429 | |
| 430 | return register_value; |
| 431 | } |
| 432 | /* |
| 433 | * Returns true if an interrupt is pending.. |
| 434 | */ |
Stephen M. Cameron | 900c544 | 2010-02-04 08:42:35 -0600 | [diff] [blame] | 435 | static bool SA5_intr_pending(struct ctlr_info *h) |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 436 | { |
| 437 | unsigned long register_value = |
| 438 | readl(h->vaddr + SA5_INTR_STATUS); |
Stephen M. Cameron | 84ca0be | 2010-02-04 08:42:30 -0600 | [diff] [blame] | 439 | dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value); |
Stephen M. Cameron | 900c544 | 2010-02-04 08:42:35 -0600 | [diff] [blame] | 440 | return register_value & SA5_INTR_PENDING; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 441 | } |
| 442 | |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 443 | static bool SA5_performant_intr_pending(struct ctlr_info *h) |
| 444 | { |
| 445 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); |
| 446 | |
| 447 | if (!register_value) |
| 448 | return false; |
| 449 | |
| 450 | if (h->msi_vector || h->msix_vector) |
| 451 | return true; |
| 452 | |
| 453 | /* Read outbound doorbell to flush */ |
| 454 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); |
| 455 | return register_value & SA5_OUTDB_STATUS_PERF_BIT; |
| 456 | } |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 457 | |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 458 | #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 |
| 459 | |
| 460 | static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) |
| 461 | { |
| 462 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); |
| 463 | |
| 464 | return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? |
| 465 | true : false; |
| 466 | } |
| 467 | |
| 468 | #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 |
| 469 | #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 |
| 470 | #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC |
| 471 | #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL |
| 472 | |
Stephen M. Cameron | 283b4a9 | 2014-02-18 13:55:33 -0600 | [diff] [blame] | 473 | static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 474 | { |
| 475 | u64 register_value; |
| 476 | struct reply_pool *rq = &h->reply_queue[q]; |
| 477 | unsigned long flags; |
| 478 | |
| 479 | BUG_ON(q >= h->nreply_queues); |
| 480 | |
| 481 | register_value = rq->head[rq->current_entry]; |
| 482 | if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { |
| 483 | rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; |
| 484 | if (++rq->current_entry == rq->size) |
| 485 | rq->current_entry = 0; |
Stephen M. Cameron | 283b4a9 | 2014-02-18 13:55:33 -0600 | [diff] [blame] | 486 | /* |
| 487 | * @todo |
| 488 | * |
| 489 | * Don't really need to write the new index after each command, |
| 490 | * but with current driver design this is easiest. |
| 491 | */ |
| 492 | wmb(); |
| 493 | writel((q << 24) | rq->current_entry, h->vaddr + |
| 494 | IOACCEL_MODE1_CONSUMER_INDEX); |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 495 | spin_lock_irqsave(&h->lock, flags); |
| 496 | h->commands_outstanding--; |
| 497 | spin_unlock_irqrestore(&h->lock, flags); |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 498 | } |
| 499 | return (unsigned long) register_value; |
| 500 | } |
| 501 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 502 | static struct access_method SA5_access = { |
| 503 | SA5_submit_command, |
| 504 | SA5_intr_mask, |
| 505 | SA5_fifo_full, |
| 506 | SA5_intr_pending, |
| 507 | SA5_completed, |
| 508 | }; |
| 509 | |
Matt Gates | e1f7de0 | 2014-02-18 13:55:17 -0600 | [diff] [blame] | 510 | static struct access_method SA5_ioaccel_mode1_access = { |
| 511 | SA5_submit_command, |
| 512 | SA5_performant_intr_mask, |
| 513 | SA5_fifo_full, |
| 514 | SA5_ioaccel_mode1_intr_pending, |
| 515 | SA5_ioaccel_mode1_completed, |
| 516 | }; |
| 517 | |
Scott Teel | c349775 | 2014-02-18 13:56:34 -0600 | [diff] [blame] | 518 | static struct access_method SA5_ioaccel_mode2_access = { |
| 519 | SA5_submit_command_ioaccel2, |
| 520 | SA5_performant_intr_mask, |
| 521 | SA5_fifo_full, |
| 522 | SA5_performant_intr_pending, |
| 523 | SA5_performant_completed, |
| 524 | }; |
| 525 | |
Don Brace | 303932f | 2010-02-04 08:42:40 -0600 | [diff] [blame] | 526 | static struct access_method SA5_performant_access = { |
| 527 | SA5_submit_command, |
| 528 | SA5_performant_intr_mask, |
| 529 | SA5_fifo_full, |
| 530 | SA5_performant_intr_pending, |
| 531 | SA5_performant_completed, |
| 532 | }; |
| 533 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 534 | struct board_type { |
Stephen M. Cameron | 01a02ff | 2010-02-04 08:41:33 -0600 | [diff] [blame] | 535 | u32 board_id; |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 536 | char *product_name; |
| 537 | struct access_method *access; |
| 538 | }; |
| 539 | |
Stephen M. Cameron | edd1636 | 2009-12-08 14:09:11 -0800 | [diff] [blame] | 540 | #endif /* HPSA_H */ |
| 541 | |