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Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
3config CPU_32
4 bool
5 default y
6
7# Select CPU types depending on the architecture selected. This selects
8# which CPUs we support in the kernel image, and the compiler instruction
9# optimiser behaviour.
10
11# ARM610
12config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
18 select CPU_COPY_V3
19 select CPU_TLB_V3
20 help
21 The ARM610 is the successor to the ARM3 processor
22 and was produced by VLSI Technology Inc.
23
24 Say Y if you want support for the ARM610 processor.
25 Otherwise, say N.
26
27# ARM710
28config CPU_ARM710
29 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
30 default y if ARCH_CLPS7500
31 select CPU_32v3
32 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT
34 select CPU_COPY_V3
35 select CPU_TLB_V3
36 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 designed by Advanced RISC Machines Ltd. The ARM710 is the
39 successor to the ARM610 processor. It was released in
40 July 1994 by VLSI Technology Inc.
41
42 Say Y if you want support for the ARM710 processor.
43 Otherwise, say N.
44
45# ARM720T
46config CPU_ARM720T
47 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
48 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
49 select CPU_32v4
50 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT
53 select CPU_COPY_V4WT
54 select CPU_TLB_V4WT
55 help
56 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
57 MMU built around an ARM7TDMI core.
58
59 Say Y if you want support for the ARM720T processor.
60 Otherwise, say N.
61
62# ARM920T
63config CPU_ARM920T
64 bool "Support ARM920T processor" if !ARCH_S3C2410
Bellido Nicolas038c5b62005-06-20 18:51:05 +010065 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 default y if ARCH_S3C2410
67 select CPU_32v4
68 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT
71 select CPU_COPY_V4WB
72 select CPU_TLB_V4WBI
73 help
74 The ARM920T is licensed to be produced by numerous vendors,
75 and is used in the Maverick EP9312 and the Samsung S3C2410.
76
77 More information on the Maverick EP9312 at
78 <http://linuxdevices.com/products/PD2382866068.html>.
79
80 Say Y if you want support for the ARM920T processor.
81 Otherwise, say N.
82
83# ARM922T
84config CPU_ARM922T
85 bool "Support ARM922T processor" if ARCH_INTEGRATOR
86 depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR
87 default y if ARCH_CAMELOT || ARCH_LH7A40X
88 select CPU_32v4
89 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT
92 select CPU_COPY_V4WB
93 select CPU_TLB_V4WBI
94 help
95 The ARM922T is a version of the ARM920T, but with smaller
96 instruction and data caches. It is used in Altera's
97 Excalibur XA device family.
98
99 Say Y if you want support for the ARM922T processor.
100 Otherwise, say N.
101
102# ARM925T
103config CPU_ARM925T
Tony Lindgrenb288f752005-07-10 19:58:08 +0100104 bool "Support ARM925T processor" if ARCH_OMAP1
Tony Lindgren3179a012005-11-10 14:26:48 +0000105 depends on ARCH_OMAP15XX
106 default y if ARCH_OMAP15XX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107 select CPU_32v4
108 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT
111 select CPU_COPY_V4WB
112 select CPU_TLB_V4WBI
113 help
114 The ARM925T is a mix between the ARM920T and ARM926T, but with
115 different instruction and data caches. It is used in TI's OMAP
116 device family.
117
118 Say Y if you want support for the ARM925T processor.
119 Otherwise, say N.
120
121# ARM926T
122config CPU_ARM926T
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000123 bool "Support ARM926T processor"
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX
126 select CPU_32v5
127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT
129 select CPU_COPY_V4WB
130 select CPU_TLB_V4WBI
131 help
132 This is a variant of the ARM920. It has slightly different
133 instruction sequences for cache and TLB operations. Curiously,
134 there is no documentation on it at the ARM corporate website.
135
136 Say Y if you want support for the ARM926T processor.
137 Otherwise, say N.
138
139# ARM1020 - needs validating
140config CPU_ARM1020
141 bool "Support ARM1020T (rev 0) processor"
142 depends on ARCH_INTEGRATOR
143 select CPU_32v5
144 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT
147 select CPU_COPY_V4WB
148 select CPU_TLB_V4WBI
149 help
150 The ARM1020 is the 32K cached version of the ARM10 processor,
151 with an addition of a floating-point unit.
152
153 Say Y if you want support for the ARM1020 processor.
154 Otherwise, say N.
155
156# ARM1020E - needs validating
157config CPU_ARM1020E
158 bool "Support ARM1020E processor"
159 depends on ARCH_INTEGRATOR
160 select CPU_32v5
161 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT
164 select CPU_COPY_V4WB
165 select CPU_TLB_V4WBI
166 depends on n
167
168# ARM1022E
169config CPU_ARM1022
170 bool "Support ARM1022E processor"
171 depends on ARCH_INTEGRATOR
172 select CPU_32v5
173 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT
175 select CPU_COPY_V4WB # can probably do better
176 select CPU_TLB_V4WBI
177 help
178 The ARM1022E is an implementation of the ARMv5TE architecture
179 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
180 embedded trace macrocell, and a floating-point unit.
181
182 Say Y if you want support for the ARM1022E processor.
183 Otherwise, say N.
184
185# ARM1026EJ-S
186config CPU_ARM1026
187 bool "Support ARM1026EJ-S processor"
188 depends on ARCH_INTEGRATOR
189 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT
192 select CPU_COPY_V4WB # can probably do better
193 select CPU_TLB_V4WBI
194 help
195 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
196 based upon the ARM10 integer core.
197
198 Say Y if you want support for the ARM1026EJ-S processor.
199 Otherwise, say N.
200
201# SA110
202config CPU_SA110
203 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
204 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
205 select CPU_32v3 if ARCH_RPC
206 select CPU_32v4 if !ARCH_RPC
207 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT
210 select CPU_COPY_V4WB
211 select CPU_TLB_V4WB
212 help
213 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
214 is available at five speeds ranging from 100 MHz to 233 MHz.
215 More information is available at
216 <http://developer.intel.com/design/strong/sa110.htm>.
217
218 Say Y if you want support for the SA-110 processor.
219 Otherwise, say N.
220
221# SA1100
222config CPU_SA1100
223 bool
224 depends on ARCH_SA1100
225 default y
226 select CPU_32v4
227 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT
230 select CPU_TLB_V4WB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231
232# XScale
233config CPU_XSCALE
234 bool
235 depends on ARCH_IOP3XX || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
236 default y
237 select CPU_32v5
238 select CPU_ABRT_EV5T
239 select CPU_CACHE_VIVT
240 select CPU_TLB_V4WBI
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
242# ARMv6
243config CPU_V6
244 bool "Support ARM V6 processor"
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000245 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 select CPU_32v6
247 select CPU_ABRT_EV6
248 select CPU_CACHE_V6
249 select CPU_CACHE_VIPT
250 select CPU_COPY_V6
251 select CPU_TLB_V6
252
Russell King4a5f79e2005-11-03 15:48:21 +0000253# ARMv6k
254config CPU_32v6K
255 bool "Support ARM V6K processor extensions" if !SMP
256 depends on CPU_V6
257 default y if SMP
258 help
259 Say Y here if your ARMv6 processor supports the 'K' extension.
260 This enables the kernel to use some instructions not present
261 on previous processors, and as such a kernel build with this
262 enabled will not boot on processors with do not support these
263 instructions.
264
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265# Figure out what processor architecture version we should be using.
266# This defines the compiler instruction set which depends on the machine type.
267config CPU_32v3
268 bool
269
270config CPU_32v4
271 bool
272
273config CPU_32v5
274 bool
275
276config CPU_32v6
277 bool
278
279# The abort model
280config CPU_ABRT_EV4
281 bool
282
283config CPU_ABRT_EV4T
284 bool
285
286config CPU_ABRT_LV4T
287 bool
288
289config CPU_ABRT_EV5T
290 bool
291
292config CPU_ABRT_EV5TJ
293 bool
294
295config CPU_ABRT_EV6
296 bool
297
298# The cache model
299config CPU_CACHE_V3
300 bool
301
302config CPU_CACHE_V4
303 bool
304
305config CPU_CACHE_V4WT
306 bool
307
308config CPU_CACHE_V4WB
309 bool
310
311config CPU_CACHE_V6
312 bool
313
314config CPU_CACHE_VIVT
315 bool
316
317config CPU_CACHE_VIPT
318 bool
319
320# The copy-page model
321config CPU_COPY_V3
322 bool
323
324config CPU_COPY_V4WT
325 bool
326
327config CPU_COPY_V4WB
328 bool
329
330config CPU_COPY_V6
331 bool
332
333# This selects the TLB model
334config CPU_TLB_V3
335 bool
336 help
337 ARM Architecture Version 3 TLB.
338
339config CPU_TLB_V4WT
340 bool
341 help
342 ARM Architecture Version 4 TLB with writethrough cache.
343
344config CPU_TLB_V4WB
345 bool
346 help
347 ARM Architecture Version 4 TLB with writeback cache.
348
349config CPU_TLB_V4WBI
350 bool
351 help
352 ARM Architecture Version 4 TLB with writeback cache and invalidate
353 instruction cache entry.
354
355config CPU_TLB_V6
356 bool
357
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358comment "Processor Features"
359
360config ARM_THUMB
361 bool "Support Thumb user binaries"
362 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6
363 default y
364 help
365 Say Y if you want to include kernel support for running user space
366 Thumb binaries.
367
368 The Thumb instruction set is a compressed form of the standard ARM
369 instruction set resulting in smaller binaries at the expense of
370 slightly less efficient code.
371
372 If you don't know what this all is, saying Y is a safe choice.
373
374config CPU_BIG_ENDIAN
375 bool "Build big-endian kernel"
376 depends on ARCH_SUPPORTS_BIG_ENDIAN
377 help
378 Say Y if you plan on running a kernel in big-endian mode.
379 Note that your board must be properly built and your board
380 port must properly enable any big-endian related features
381 of your chipset/board/processor.
382
383config CPU_ICACHE_DISABLE
384 bool "Disable I-Cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100385 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 help
387 Say Y here to disable the processor instruction cache. Unless
388 you have a reason not to or are unsure, say N.
389
390config CPU_DCACHE_DISABLE
391 bool "Disable D-Cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100392 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700393 help
394 Say Y here to disable the processor data cache. Unless
395 you have a reason not to or are unsure, say N.
396
397config CPU_DCACHE_WRITETHROUGH
398 bool "Force write through D-cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100399 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 default y if CPU_ARM925T
401 help
402 Say Y here to use the data cache in writethrough mode. Unless you
403 specifically require this or are unsure, say N.
404
405config CPU_CACHE_ROUND_ROBIN
406 bool "Round robin I and D cache replacement algorithm"
407 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
408 help
409 Say Y here to use the predictable round-robin cache replacement
410 policy. Unless you specifically require this or are unsure, say N.
411
412config CPU_BPREDICT_DISABLE
413 bool "Disable branch prediction"
Catalin Marinase03eb522005-10-05 23:06:36 +0100414 depends on CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 help
416 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100417
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100418config TLS_REG_EMUL
419 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100420 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100421 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100422 An SMP system using a pre-ARMv6 processor (there are apparently
423 a few prototypes like that in existence) and therefore access to
424 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100425
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100426config HAS_TLS_REG
427 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100428 depends on !TLS_REG_EMUL
429 default y if SMP || CPU_32v7
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100430 help
431 This selects support for the CP15 thread register.
Nicolas Pitre70489c82005-05-12 19:27:12 +0100432 It is defined to be available on some ARMv6 processors (including
433 all SMP capable ARMv6's) or later processors. User space may
434 assume directly accessing that register and always obtain the
435 expected value only on ARMv7 and above.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100436
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100437config NEEDS_SYSCALL_FOR_CMPXCHG
438 bool
439 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
440 help
441 SMP on a pre-ARMv6 processor? Well OK then.
442 Forget about fast user space cmpxchg support.
443 It is just not possible.
444