Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Broadcom BCM63xx SPI controller support |
| 3 | * |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 4 | * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 5 | * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version 2 |
| 10 | * of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the |
| 19 | * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, |
| 20 | */ |
| 21 | |
| 22 | #include <linux/kernel.h> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 23 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> |
| 25 | #include <linux/module.h> |
| 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/spi/spi.h> |
| 30 | #include <linux/completion.h> |
| 31 | #include <linux/err.h> |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 32 | #include <linux/pm_runtime.h> |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 33 | |
| 34 | #include <bcm63xx_dev_spi.h> |
| 35 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 36 | #define BCM63XX_SPI_MAX_PREPEND 15 |
| 37 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 38 | struct bcm63xx_spi { |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 39 | struct completion done; |
| 40 | |
| 41 | void __iomem *regs; |
| 42 | int irq; |
| 43 | |
| 44 | /* Platform data */ |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 45 | unsigned fifo_size; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 46 | unsigned int msg_type_shift; |
| 47 | unsigned int msg_ctl_width; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 48 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 49 | /* data iomem */ |
| 50 | u8 __iomem *tx_io; |
| 51 | const u8 __iomem *rx_io; |
| 52 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 53 | struct clk *clk; |
| 54 | struct platform_device *pdev; |
| 55 | }; |
| 56 | |
| 57 | static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs, |
| 58 | unsigned int offset) |
| 59 | { |
| 60 | return bcm_readb(bs->regs + bcm63xx_spireg(offset)); |
| 61 | } |
| 62 | |
| 63 | static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs, |
| 64 | unsigned int offset) |
| 65 | { |
| 66 | return bcm_readw(bs->regs + bcm63xx_spireg(offset)); |
| 67 | } |
| 68 | |
| 69 | static inline void bcm_spi_writeb(struct bcm63xx_spi *bs, |
| 70 | u8 value, unsigned int offset) |
| 71 | { |
| 72 | bcm_writeb(value, bs->regs + bcm63xx_spireg(offset)); |
| 73 | } |
| 74 | |
| 75 | static inline void bcm_spi_writew(struct bcm63xx_spi *bs, |
| 76 | u16 value, unsigned int offset) |
| 77 | { |
| 78 | bcm_writew(value, bs->regs + bcm63xx_spireg(offset)); |
| 79 | } |
| 80 | |
| 81 | static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = { |
| 82 | { 20000000, SPI_CLK_20MHZ }, |
| 83 | { 12500000, SPI_CLK_12_50MHZ }, |
| 84 | { 6250000, SPI_CLK_6_250MHZ }, |
| 85 | { 3125000, SPI_CLK_3_125MHZ }, |
| 86 | { 1563000, SPI_CLK_1_563MHZ }, |
| 87 | { 781000, SPI_CLK_0_781MHZ }, |
| 88 | { 391000, SPI_CLK_0_391MHZ } |
| 89 | }; |
| 90 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 91 | static void bcm63xx_spi_setup_transfer(struct spi_device *spi, |
| 92 | struct spi_transfer *t) |
| 93 | { |
| 94 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 95 | u8 clk_cfg, reg; |
| 96 | int i; |
| 97 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 98 | /* Find the closest clock configuration */ |
| 99 | for (i = 0; i < SPI_CLK_MASK; i++) { |
Jonas Gorski | 68792e2 | 2013-03-12 00:13:46 +0100 | [diff] [blame] | 100 | if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) { |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 101 | clk_cfg = bcm63xx_spi_freq_table[i][1]; |
| 102 | break; |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | /* No matching configuration found, default to lowest */ |
| 107 | if (i == SPI_CLK_MASK) |
| 108 | clk_cfg = SPI_CLK_0_391MHZ; |
| 109 | |
| 110 | /* clear existing clock configuration bits of the register */ |
| 111 | reg = bcm_spi_readb(bs, SPI_CLK_CFG); |
| 112 | reg &= ~SPI_CLK_MASK; |
| 113 | reg |= clk_cfg; |
| 114 | |
| 115 | bcm_spi_writeb(bs, reg, SPI_CLK_CFG); |
| 116 | dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n", |
Jonas Gorski | 68792e2 | 2013-03-12 00:13:46 +0100 | [diff] [blame] | 117 | clk_cfg, t->speed_hz); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | /* the spi->mode bits understood by this driver: */ |
| 121 | #define MODEBITS (SPI_CPOL | SPI_CPHA) |
| 122 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 123 | static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first, |
| 124 | unsigned int num_transfers) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 125 | { |
| 126 | struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master); |
| 127 | u16 msg_ctl; |
| 128 | u16 cmd; |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 129 | u8 rx_tail; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 130 | unsigned int i, timeout = 0, prepend_len = 0, len = 0; |
| 131 | struct spi_transfer *t = first; |
| 132 | bool do_rx = false; |
| 133 | bool do_tx = false; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 134 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 135 | /* Disable the CMD_DONE interrupt */ |
| 136 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
| 137 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 138 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
| 139 | t->tx_buf, t->rx_buf, t->len); |
| 140 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 141 | if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND) |
| 142 | prepend_len = t->len; |
| 143 | |
| 144 | /* prepare the buffer */ |
| 145 | for (i = 0; i < num_transfers; i++) { |
| 146 | if (t->tx_buf) { |
| 147 | do_tx = true; |
| 148 | memcpy_toio(bs->tx_io + len, t->tx_buf, t->len); |
| 149 | |
| 150 | /* don't prepend more than one tx */ |
| 151 | if (t != first) |
| 152 | prepend_len = 0; |
| 153 | } |
| 154 | |
| 155 | if (t->rx_buf) { |
| 156 | do_rx = true; |
| 157 | /* prepend is half-duplex write only */ |
| 158 | if (t == first) |
| 159 | prepend_len = 0; |
| 160 | } |
| 161 | |
| 162 | len += t->len; |
| 163 | |
| 164 | t = list_entry(t->transfer_list.next, struct spi_transfer, |
| 165 | transfer_list); |
| 166 | } |
| 167 | |
Axel Lin | aa0fe82 | 2014-02-09 11:06:04 +0800 | [diff] [blame] | 168 | reinit_completion(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 169 | |
| 170 | /* Fill in the Message control register */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 171 | msg_ctl = (len << SPI_BYTE_CNT_SHIFT); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 172 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 173 | if (do_rx && do_tx && prepend_len == 0) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 174 | msg_ctl |= (SPI_FD_RW << bs->msg_type_shift); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 175 | else if (do_rx) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 176 | msg_ctl |= (SPI_HD_R << bs->msg_type_shift); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 177 | else if (do_tx) |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 178 | msg_ctl |= (SPI_HD_W << bs->msg_type_shift); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 179 | |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 180 | switch (bs->msg_ctl_width) { |
| 181 | case 8: |
| 182 | bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL); |
| 183 | break; |
| 184 | case 16: |
| 185 | bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL); |
| 186 | break; |
| 187 | } |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 188 | |
| 189 | /* Issue the transfer */ |
| 190 | cmd = SPI_CMD_START_IMMEDIATE; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 191 | cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 192 | cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT); |
| 193 | bcm_spi_writew(bs, cmd, SPI_CMD); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 194 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 195 | /* Enable the CMD_DONE interrupt */ |
| 196 | bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 197 | |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 198 | timeout = wait_for_completion_timeout(&bs->done, HZ); |
| 199 | if (!timeout) |
| 200 | return -ETIMEDOUT; |
| 201 | |
Jonas Gorski | 20e9e78 | 2013-12-17 21:42:08 +0100 | [diff] [blame] | 202 | if (!do_rx) |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 203 | return 0; |
| 204 | |
| 205 | len = 0; |
| 206 | t = first; |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 207 | /* Read out all the data */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 208 | for (i = 0; i < num_transfers; i++) { |
| 209 | if (t->rx_buf) |
| 210 | memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len); |
| 211 | |
| 212 | if (t != first || prepend_len == 0) |
| 213 | len += t->len; |
| 214 | |
| 215 | t = list_entry(t->transfer_list.next, struct spi_transfer, |
| 216 | transfer_list); |
| 217 | } |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 218 | |
| 219 | return 0; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 220 | } |
| 221 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 222 | static int bcm63xx_spi_transfer_one(struct spi_master *master, |
| 223 | struct spi_message *m) |
| 224 | { |
| 225 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 226 | struct spi_transfer *t, *first = NULL; |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 227 | struct spi_device *spi = m->spi; |
| 228 | int status = 0; |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 229 | unsigned int n_transfers = 0, total_len = 0; |
| 230 | bool can_use_prepend = false; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 231 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 232 | /* |
| 233 | * This SPI controller does not support keeping CS active after a |
| 234 | * transfer. |
| 235 | * Work around this by merging as many transfers we can into one big |
| 236 | * full-duplex transfers. |
| 237 | */ |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 238 | list_for_each_entry(t, &m->transfers, transfer_list) { |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 239 | if (!first) |
| 240 | first = t; |
| 241 | |
| 242 | n_transfers++; |
| 243 | total_len += t->len; |
| 244 | |
| 245 | if (n_transfers == 2 && !first->rx_buf && !t->tx_buf && |
| 246 | first->len <= BCM63XX_SPI_MAX_PREPEND) |
| 247 | can_use_prepend = true; |
| 248 | else if (can_use_prepend && t->tx_buf) |
| 249 | can_use_prepend = false; |
| 250 | |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 251 | /* we can only transfer one fifo worth of data */ |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 252 | if ((can_use_prepend && |
| 253 | total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) || |
| 254 | (!can_use_prepend && total_len > bs->fifo_size)) { |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 255 | dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n", |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 256 | total_len, bs->fifo_size); |
| 257 | status = -EINVAL; |
| 258 | goto exit; |
| 259 | } |
| 260 | |
| 261 | /* all combined transfers have to have the same speed */ |
| 262 | if (t->speed_hz != first->speed_hz) { |
| 263 | dev_err(&spi->dev, "unable to change speed between transfers\n"); |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 264 | status = -EINVAL; |
| 265 | goto exit; |
| 266 | } |
| 267 | |
| 268 | /* CS will be deasserted directly after transfer */ |
| 269 | if (t->delay_usecs) { |
| 270 | dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); |
| 271 | status = -EINVAL; |
| 272 | goto exit; |
| 273 | } |
| 274 | |
Jonas Gorski | b17de07 | 2013-02-03 15:15:13 +0100 | [diff] [blame] | 275 | if (t->cs_change || |
| 276 | list_is_last(&t->transfer_list, &m->transfers)) { |
| 277 | /* configure adapter for a new transfer */ |
| 278 | bcm63xx_spi_setup_transfer(spi, first); |
| 279 | |
| 280 | /* send the data */ |
| 281 | status = bcm63xx_txrx_bufs(spi, first, n_transfers); |
| 282 | if (status) |
| 283 | goto exit; |
| 284 | |
| 285 | m->actual_length += total_len; |
| 286 | |
| 287 | first = NULL; |
| 288 | n_transfers = 0; |
| 289 | total_len = 0; |
| 290 | can_use_prepend = false; |
Jonas Gorski | c0fde3b | 2013-02-03 15:15:12 +0100 | [diff] [blame] | 291 | } |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 292 | } |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 293 | exit: |
| 294 | m->status = status; |
| 295 | spi_finalize_current_message(master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 296 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 297 | return 0; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | /* This driver supports single master mode only. Hence |
| 301 | * CMD_DONE is the only interrupt we care about |
| 302 | */ |
| 303 | static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id) |
| 304 | { |
| 305 | struct spi_master *master = (struct spi_master *)dev_id; |
| 306 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 307 | u8 intr; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 308 | |
| 309 | /* Read interupts and clear them immediately */ |
| 310 | intr = bcm_spi_readb(bs, SPI_INT_STATUS); |
| 311 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
| 312 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
| 313 | |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 314 | /* A transfer completed */ |
| 315 | if (intr & SPI_INTR_CMD_DONE) |
| 316 | complete(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 317 | |
| 318 | return IRQ_HANDLED; |
| 319 | } |
| 320 | |
| 321 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 322 | static int bcm63xx_spi_probe(struct platform_device *pdev) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 323 | { |
| 324 | struct resource *r; |
| 325 | struct device *dev = &pdev->dev; |
Jingoo Han | 8074cf0 | 2013-07-30 16:58:59 +0900 | [diff] [blame] | 326 | struct bcm63xx_spi_pdata *pdata = dev_get_platdata(&pdev->dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 327 | int irq; |
| 328 | struct spi_master *master; |
| 329 | struct clk *clk; |
| 330 | struct bcm63xx_spi *bs; |
| 331 | int ret; |
| 332 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 333 | irq = platform_get_irq(pdev, 0); |
| 334 | if (irq < 0) { |
| 335 | dev_err(dev, "no irq\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 336 | return -ENXIO; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 337 | } |
| 338 | |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 339 | clk = devm_clk_get(dev, "spi"); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 340 | if (IS_ERR(clk)) { |
| 341 | dev_err(dev, "no clock for device\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 342 | return PTR_ERR(clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | master = spi_alloc_master(dev, sizeof(*bs)); |
| 346 | if (!master) { |
| 347 | dev_err(dev, "out of memory\n"); |
Jingoo Han | acf4fc6 | 2013-12-09 19:20:15 +0900 | [diff] [blame] | 348 | return -ENOMEM; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | bs = spi_master_get_devdata(master); |
Axel Lin | aa0fe82 | 2014-02-09 11:06:04 +0800 | [diff] [blame] | 352 | init_completion(&bs->done); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 353 | |
| 354 | platform_set_drvdata(pdev, master); |
| 355 | bs->pdev = pdev; |
| 356 | |
Julia Lawall | de0fa83 | 2013-08-14 11:11:09 +0200 | [diff] [blame] | 357 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jonas Gorski | b66c773 | 2013-03-12 00:13:47 +0100 | [diff] [blame] | 358 | bs->regs = devm_ioremap_resource(&pdev->dev, r); |
| 359 | if (IS_ERR(bs->regs)) { |
| 360 | ret = PTR_ERR(bs->regs); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 361 | goto out_err; |
| 362 | } |
| 363 | |
| 364 | bs->irq = irq; |
| 365 | bs->clk = clk; |
| 366 | bs->fifo_size = pdata->fifo_size; |
| 367 | |
| 368 | ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0, |
| 369 | pdev->name, master); |
| 370 | if (ret) { |
| 371 | dev_err(dev, "unable to request irq\n"); |
| 372 | goto out_err; |
| 373 | } |
| 374 | |
| 375 | master->bus_num = pdata->bus_num; |
| 376 | master->num_chipselect = pdata->num_chipselect; |
Florian Fainelli | cde4384 | 2012-04-20 15:37:33 +0200 | [diff] [blame] | 377 | master->transfer_one_message = bcm63xx_spi_transfer_one; |
Florian Fainelli | 88a3a25 | 2012-04-20 15:37:35 +0200 | [diff] [blame] | 378 | master->mode_bits = MODEBITS; |
Stephen Warren | 24778be | 2013-05-21 20:36:35 -0600 | [diff] [blame] | 379 | master->bits_per_word_mask = SPI_BPW_MASK(8); |
Mark Brown | 5355d96 | 2013-07-28 15:34:06 +0100 | [diff] [blame] | 380 | master->auto_runtime_pm = true; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 381 | bs->msg_type_shift = pdata->msg_type_shift; |
| 382 | bs->msg_ctl_width = pdata->msg_ctl_width; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 383 | bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA)); |
| 384 | bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA)); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 385 | |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 386 | switch (bs->msg_ctl_width) { |
| 387 | case 8: |
| 388 | case 16: |
| 389 | break; |
| 390 | default: |
| 391 | dev_err(dev, "unsupported MSG_CTL width: %d\n", |
| 392 | bs->msg_ctl_width); |
Jonas Gorski | b435ff2 | 2013-03-12 00:13:37 +0100 | [diff] [blame] | 393 | goto out_err; |
Florian Fainelli | 5a67044 | 2012-06-18 12:07:51 +0200 | [diff] [blame] | 394 | } |
| 395 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 396 | /* Initialize hardware */ |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 397 | ret = clk_prepare_enable(bs->clk); |
| 398 | if (ret) |
| 399 | goto out_err; |
| 400 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 401 | bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS); |
| 402 | |
| 403 | /* register and we are done */ |
Jingoo Han | bca7693 | 2013-09-24 13:24:57 +0900 | [diff] [blame] | 404 | ret = devm_spi_register_master(dev, master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 405 | if (ret) { |
| 406 | dev_err(dev, "spi register failed\n"); |
| 407 | goto out_clk_disable; |
| 408 | } |
| 409 | |
Florian Fainelli | 61d1596 | 2012-10-03 11:56:53 +0200 | [diff] [blame] | 410 | dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d)\n", |
| 411 | r->start, irq, bs->fifo_size); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 412 | |
| 413 | return 0; |
| 414 | |
| 415 | out_clk_disable: |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 416 | clk_disable_unprepare(clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 417 | out_err: |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 418 | spi_master_put(master); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 419 | return ret; |
| 420 | } |
| 421 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 422 | static int bcm63xx_spi_remove(struct platform_device *pdev) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 423 | { |
Wei Yongjun | 9637b86 | 2013-11-15 15:50:59 +0800 | [diff] [blame] | 424 | struct spi_master *master = platform_get_drvdata(pdev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 425 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 426 | |
| 427 | /* reset spi block */ |
| 428 | bcm_spi_writeb(bs, 0, SPI_INT_MASK); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 429 | |
| 430 | /* HW shutdown */ |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 431 | clk_disable_unprepare(bs->clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 432 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 433 | return 0; |
| 434 | } |
| 435 | |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 436 | #ifdef CONFIG_PM_SLEEP |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 437 | static int bcm63xx_spi_suspend(struct device *dev) |
| 438 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 439 | struct spi_master *master = dev_get_drvdata(dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 440 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
| 441 | |
Florian Fainelli | 9651995 | 2012-10-03 11:56:54 +0200 | [diff] [blame] | 442 | spi_master_suspend(master); |
| 443 | |
Jonas Gorski | 4fbb82a | 2013-03-12 00:13:38 +0100 | [diff] [blame] | 444 | clk_disable_unprepare(bs->clk); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static int bcm63xx_spi_resume(struct device *dev) |
| 450 | { |
Axel Lin | a1216394 | 2013-08-09 15:35:16 +0800 | [diff] [blame] | 451 | struct spi_master *master = dev_get_drvdata(dev); |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 452 | struct bcm63xx_spi *bs = spi_master_get_devdata(master); |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 453 | int ret; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 454 | |
Jonas Gorski | ea01e8a | 2013-12-17 21:42:09 +0100 | [diff] [blame] | 455 | ret = clk_prepare_enable(bs->clk); |
| 456 | if (ret) |
| 457 | return ret; |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 458 | |
Florian Fainelli | 9651995 | 2012-10-03 11:56:54 +0200 | [diff] [blame] | 459 | spi_master_resume(master); |
| 460 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 461 | return 0; |
| 462 | } |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 463 | #endif |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 464 | |
| 465 | static const struct dev_pm_ops bcm63xx_spi_pm_ops = { |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 466 | SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume) |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 467 | }; |
| 468 | |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 469 | static struct platform_driver bcm63xx_spi_driver = { |
| 470 | .driver = { |
| 471 | .name = "bcm63xx-spi", |
| 472 | .owner = THIS_MODULE, |
Jonas Gorski | 1bae202 | 2013-12-17 21:42:10 +0100 | [diff] [blame] | 473 | .pm = &bcm63xx_spi_pm_ops, |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 474 | }, |
| 475 | .probe = bcm63xx_spi_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 476 | .remove = bcm63xx_spi_remove, |
Florian Fainelli | b42dfed | 2012-02-01 11:14:09 +0100 | [diff] [blame] | 477 | }; |
| 478 | |
| 479 | module_platform_driver(bcm63xx_spi_driver); |
| 480 | |
| 481 | MODULE_ALIAS("platform:bcm63xx_spi"); |
| 482 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); |
| 483 | MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>"); |
| 484 | MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver"); |
| 485 | MODULE_LICENSE("GPL"); |