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Mark Brown9a76f1f2010-08-05 13:20:59 +01001/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
Mark Brown3367b8d2010-09-20 17:34:58 +010020#include <linux/gpio.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +010021#include <linux/i2c.h>
22#include <linux/input.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34#include <sound/wm8962.h>
35
36#include "wm8962.h"
37
Mark Brown9a76f1f2010-08-05 13:20:59 +010038#define WM8962_NUM_SUPPLIES 8
39static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
40 "DCVDD",
41 "DBVDD",
42 "AVDD",
43 "CPVDD",
44 "MICVDD",
45 "PLLVDD",
46 "SPKVDD1",
47 "SPKVDD2",
48};
49
50/* codec private data */
51struct wm8962_priv {
Mark Brown54d8d0a2010-08-12 15:02:11 +010052 struct snd_soc_codec *codec;
53
Mark Brown9a76f1f2010-08-05 13:20:59 +010054 u16 reg_cache[WM8962_MAX_REGISTER + 1];
55
56 int sysclk;
57 int sysclk_rate;
58
59 int bclk; /* Desired BCLK */
60 int lrclk;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
67 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
68
69#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
70 struct input_dev *beep;
71 struct work_struct beep_work;
72 int beep_rate;
73#endif
Mark Brown3367b8d2010-09-20 17:34:58 +010074
75#ifdef CONFIG_GPIOLIB
76 struct gpio_chip gpio_chip;
77#endif
Mark Brown9a76f1f2010-08-05 13:20:59 +010078};
79
80/* We can't use the same notifier block for more than one supply and
81 * there's no way I can see to get from a callback to the caller
82 * except container_of().
83 */
84#define WM8962_REGULATOR_EVENT(n) \
85static int wm8962_regulator_event_##n(struct notifier_block *nb, \
86 unsigned long event, void *data) \
87{ \
88 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
89 disable_nb[n]); \
90 if (event & REGULATOR_EVENT_DISABLE) { \
Mark Brown54d8d0a2010-08-12 15:02:11 +010091 wm8962->codec->cache_sync = 1; \
Mark Brown9a76f1f2010-08-05 13:20:59 +010092 } \
93 return 0; \
94}
95
96WM8962_REGULATOR_EVENT(0)
97WM8962_REGULATOR_EVENT(1)
98WM8962_REGULATOR_EVENT(2)
99WM8962_REGULATOR_EVENT(3)
100WM8962_REGULATOR_EVENT(4)
101WM8962_REGULATOR_EVENT(5)
102WM8962_REGULATOR_EVENT(6)
103WM8962_REGULATOR_EVENT(7)
104
105static int wm8962_volatile_register(unsigned int reg)
106{
107 if (wm8962_reg_access[reg].vol)
108 return 1;
109 else
110 return 0;
111}
112
Mark Brown54d8d0a2010-08-12 15:02:11 +0100113static int wm8962_readable_register(unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100114{
115 if (wm8962_reg_access[reg].read)
116 return 1;
117 else
118 return 0;
119}
120
121static int wm8962_reset(struct snd_soc_codec *codec)
122{
123 return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
124}
125
126static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
127static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
128static const unsigned int mixinpga_tlv[] = {
129 TLV_DB_RANGE_HEAD(7),
130 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
131 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
132 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
133 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
134 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
135};
136static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
137static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
138static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
139static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
140static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
141static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
142static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
143static const unsigned int classd_tlv[] = {
144 TLV_DB_RANGE_HEAD(7),
145 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
146 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
147};
148
149/* The VU bits for the headphones are in a different register to the mute
150 * bits and only take effect on the PGA if it is actually powered.
151 */
152static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
153 struct snd_ctl_elem_value *ucontrol)
154{
155 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100156 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
157 u16 *reg_cache = wm8962->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100158 int ret;
159
160 /* Apply the update (if any) */
161 ret = snd_soc_put_volsw(kcontrol, ucontrol);
162 if (ret == 0)
163 return 0;
164
165 /* If the left PGA is enabled hit that VU bit... */
166 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
167 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
168 reg_cache[WM8962_HPOUTL_VOLUME]);
169
170 /* ...otherwise the right. The VU is stereo. */
171 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
172 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
173 reg_cache[WM8962_HPOUTR_VOLUME]);
174
175 return 0;
176}
177
178/* The VU bits for the speakers are in a different register to the mute
179 * bits and only take effect on the PGA if it is actually powered.
180 */
181static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
182 struct snd_ctl_elem_value *ucontrol)
183{
184 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100185 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
186 u16 *reg_cache = wm8962->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100187 int ret;
188
189 /* Apply the update (if any) */
190 ret = snd_soc_put_volsw(kcontrol, ucontrol);
191 if (ret == 0)
192 return 0;
193
194 /* If the left PGA is enabled hit that VU bit... */
195 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
196 return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
197 reg_cache[WM8962_SPKOUTL_VOLUME]);
198
199 /* ...otherwise the right. The VU is stereo. */
200 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
201 return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
202 reg_cache[WM8962_SPKOUTR_VOLUME]);
203
204 return 0;
205}
206
207static const struct snd_kcontrol_new wm8962_snd_controls[] = {
208SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
209
210SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
211 mixin_tlv),
212SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
213 mixinpga_tlv),
214SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
215 mixin_tlv),
216
217SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
218 mixin_tlv),
219SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
220 mixinpga_tlv),
221SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
222 mixin_tlv),
223
224SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
225 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
226SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
227 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
228SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
229 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
230SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
231 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
232
233SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
234 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
235
236SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
237 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
238SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
239
240SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
241 5, 1, 0),
242
243SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
244
245SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
246 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
247SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
248 snd_soc_get_volsw, wm8962_put_hp_sw),
249SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
250 7, 1, 0),
251SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
252 hp_tlv),
253
254SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
255 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
256
257SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
258 3, 7, 0, bypass_tlv),
259SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
260 0, 7, 0, bypass_tlv),
261SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
262 7, 1, 1, inmix_tlv),
263SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
264 6, 1, 1, inmix_tlv),
265
266SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
267 3, 7, 0, bypass_tlv),
268SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
269 0, 7, 0, bypass_tlv),
270SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
271 7, 1, 1, inmix_tlv),
272SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
273 6, 1, 1, inmix_tlv),
274
275SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
276 classd_tlv),
277};
278
279static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
280SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
281SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
282 snd_soc_get_volsw, wm8962_put_spk_sw),
283SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
284
285SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
286SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
287 3, 7, 0, bypass_tlv),
288SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
289 0, 7, 0, bypass_tlv),
290SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
291 7, 1, 1, inmix_tlv),
292SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
293 6, 1, 1, inmix_tlv),
294SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
295 7, 1, 0, inmix_tlv),
296SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
297 6, 1, 0, inmix_tlv),
298};
299
300static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
301SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
302 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
303SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
304 snd_soc_get_volsw, wm8962_put_spk_sw),
305SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
306 7, 1, 0),
307
308SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
309 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
310
311SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
312 3, 7, 0, bypass_tlv),
313SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
314 0, 7, 0, bypass_tlv),
315SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
316 7, 1, 1, inmix_tlv),
317SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
318 6, 1, 1, inmix_tlv),
319SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
320 7, 1, 0, inmix_tlv),
321SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
322 6, 1, 0, inmix_tlv),
323
324SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
325 3, 7, 0, bypass_tlv),
326SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
327 0, 7, 0, bypass_tlv),
328SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
329 7, 1, 1, inmix_tlv),
330SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
331 6, 1, 1, inmix_tlv),
332SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
333 5, 1, 0, inmix_tlv),
334SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
335 4, 1, 0, inmix_tlv),
336};
337
338static int sysclk_event(struct snd_soc_dapm_widget *w,
339 struct snd_kcontrol *kcontrol, int event)
340{
341 struct snd_soc_codec *codec = w->codec;
342 int src;
343 int fll;
344
345 src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
346
347 switch (src) {
348 case 0: /* MCLK */
349 fll = 0;
350 break;
351 case 0x200: /* FLL */
352 fll = 1;
353 break;
354 default:
355 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
356 return -EINVAL;
357 }
358
359 switch (event) {
360 case SND_SOC_DAPM_PRE_PMU:
361 if (fll)
362 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
363 WM8962_FLL_ENA, WM8962_FLL_ENA);
364 break;
365
366 case SND_SOC_DAPM_POST_PMD:
367 if (fll)
368 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
369 WM8962_FLL_ENA, 0);
370 break;
371
372 default:
373 BUG();
374 return -EINVAL;
375 }
376
377 return 0;
378}
379
380static int cp_event(struct snd_soc_dapm_widget *w,
381 struct snd_kcontrol *kcontrol, int event)
382{
383 switch (event) {
384 case SND_SOC_DAPM_POST_PMU:
385 msleep(5);
386 break;
387
388 default:
389 BUG();
390 return -EINVAL;
391 }
392
393 return 0;
394}
395
396static int hp_event(struct snd_soc_dapm_widget *w,
397 struct snd_kcontrol *kcontrol, int event)
398{
399 struct snd_soc_codec *codec = w->codec;
400 int timeout;
401 int reg;
402 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
403 WM8962_DCS_STARTUP_DONE_HP1R);
404
405 switch (event) {
406 case SND_SOC_DAPM_POST_PMU:
407 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
408 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
409 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
410 udelay(20);
411
412 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
413 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
414 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
415
416 /* Start the DC servo */
417 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
418 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
419 WM8962_HP1L_DCS_STARTUP |
420 WM8962_HP1R_DCS_STARTUP,
421 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
422 WM8962_HP1L_DCS_STARTUP |
423 WM8962_HP1R_DCS_STARTUP);
424
425 /* Wait for it to complete, should be well under 100ms */
426 timeout = 0;
427 do {
428 msleep(1);
429 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
430 if (reg < 0) {
431 dev_err(codec->dev,
432 "Failed to read DCS status: %d\n",
433 reg);
434 continue;
435 }
436 dev_dbg(codec->dev, "DCS status: %x\n", reg);
437 } while (++timeout < 200 && (reg & expected) != expected);
438
439 if ((reg & expected) != expected)
440 dev_err(codec->dev, "DC servo timed out\n");
441 else
442 dev_dbg(codec->dev, "DC servo complete after %dms\n",
443 timeout);
444
445 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
446 WM8962_HP1L_ENA_OUTP |
447 WM8962_HP1R_ENA_OUTP,
448 WM8962_HP1L_ENA_OUTP |
449 WM8962_HP1R_ENA_OUTP);
450 udelay(20);
451
452 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
453 WM8962_HP1L_RMV_SHORT |
454 WM8962_HP1R_RMV_SHORT,
455 WM8962_HP1L_RMV_SHORT |
456 WM8962_HP1R_RMV_SHORT);
457 break;
458
459 case SND_SOC_DAPM_PRE_PMD:
460 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
461 WM8962_HP1L_RMV_SHORT |
462 WM8962_HP1R_RMV_SHORT, 0);
463
464 udelay(20);
465
466 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
467 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
468 WM8962_HP1L_DCS_STARTUP |
469 WM8962_HP1R_DCS_STARTUP,
470 0);
471
472 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
473 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
474 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
475 WM8962_HP1L_ENA_OUTP |
476 WM8962_HP1R_ENA_OUTP, 0);
477
478 break;
479
480 default:
481 BUG();
482 return -EINVAL;
483
484 }
485
486 return 0;
487}
488
489/* VU bits for the output PGAs only take effect while the PGA is powered */
490static int out_pga_event(struct snd_soc_dapm_widget *w,
491 struct snd_kcontrol *kcontrol, int event)
492{
493 struct snd_soc_codec *codec = w->codec;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100494 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
495 u16 *reg_cache = wm8962->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100496 int reg;
497
498 switch (w->shift) {
499 case WM8962_HPOUTR_PGA_ENA_SHIFT:
500 reg = WM8962_HPOUTR_VOLUME;
501 break;
502 case WM8962_HPOUTL_PGA_ENA_SHIFT:
503 reg = WM8962_HPOUTL_VOLUME;
504 break;
505 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
506 reg = WM8962_SPKOUTR_VOLUME;
507 break;
508 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
509 reg = WM8962_SPKOUTL_VOLUME;
510 break;
511 default:
512 BUG();
513 return -EINVAL;
514 }
515
516 switch (event) {
517 case SND_SOC_DAPM_POST_PMU:
518 return snd_soc_write(codec, reg, reg_cache[reg]);
519 default:
520 BUG();
521 return -EINVAL;
522 }
523}
524
525static const char *st_text[] = { "None", "Right", "Left" };
526
527static const struct soc_enum str_enum =
528 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
529
530static const struct snd_kcontrol_new str_mux =
531 SOC_DAPM_ENUM("Right Sidetone", str_enum);
532
533static const struct soc_enum stl_enum =
534 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
535
536static const struct snd_kcontrol_new stl_mux =
537 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
538
539static const char *outmux_text[] = { "DAC", "Mixer" };
540
541static const struct soc_enum spkoutr_enum =
542 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
543
544static const struct snd_kcontrol_new spkoutr_mux =
545 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
546
547static const struct soc_enum spkoutl_enum =
548 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
549
550static const struct snd_kcontrol_new spkoutl_mux =
551 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
552
553static const struct soc_enum hpoutr_enum =
554 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
555
556static const struct snd_kcontrol_new hpoutr_mux =
557 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
558
559static const struct soc_enum hpoutl_enum =
560 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
561
562static const struct snd_kcontrol_new hpoutl_mux =
563 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
564
565static const struct snd_kcontrol_new inpgal[] = {
566SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
567SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
568SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
569SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
570};
571
572static const struct snd_kcontrol_new inpgar[] = {
573SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
574SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
575SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
576SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
577};
578
579static const struct snd_kcontrol_new mixinl[] = {
580SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
581SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
582SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
583};
584
585static const struct snd_kcontrol_new mixinr[] = {
586SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
587SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
588SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
589};
590
591static const struct snd_kcontrol_new hpmixl[] = {
592SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
593SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
594SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
595SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
596SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
597SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
598};
599
600static const struct snd_kcontrol_new hpmixr[] = {
601SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
602SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
603SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
604SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
605SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
606SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
607};
608
609static const struct snd_kcontrol_new spkmixl[] = {
610SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
611SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
612SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
613SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
614SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
615SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
616};
617
618static const struct snd_kcontrol_new spkmixr[] = {
619SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
620SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
621SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
622SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
623SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
624SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
625};
626
627static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
628SND_SOC_DAPM_INPUT("IN1L"),
629SND_SOC_DAPM_INPUT("IN1R"),
630SND_SOC_DAPM_INPUT("IN2L"),
631SND_SOC_DAPM_INPUT("IN2R"),
632SND_SOC_DAPM_INPUT("IN3L"),
633SND_SOC_DAPM_INPUT("IN3R"),
634SND_SOC_DAPM_INPUT("IN4L"),
635SND_SOC_DAPM_INPUT("IN4R"),
636SND_SOC_DAPM_INPUT("Beep"),
637
Mark Browna4f28c02010-09-29 13:24:35 -0700638SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
639
Mark Brown9a76f1f2010-08-05 13:20:59 +0100640SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
641SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
642 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
643SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
644 SND_SOC_DAPM_POST_PMU),
645SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
646
647SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
648 inpgal, ARRAY_SIZE(inpgal)),
649SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
650 inpgar, ARRAY_SIZE(inpgar)),
651SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
652 mixinl, ARRAY_SIZE(mixinl)),
653SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
654 mixinr, ARRAY_SIZE(mixinr)),
655
656SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
657SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
658
659SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
660SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
661
662SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
663SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
664
665SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
666SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
667
668SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
669 hpmixl, ARRAY_SIZE(hpmixl)),
670SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
671 hpmixr, ARRAY_SIZE(hpmixr)),
672
673SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
674 out_pga_event, SND_SOC_DAPM_POST_PMU),
675SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
676 out_pga_event, SND_SOC_DAPM_POST_PMU),
677
678SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
679 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
680
681SND_SOC_DAPM_OUTPUT("HPOUTL"),
682SND_SOC_DAPM_OUTPUT("HPOUTR"),
683};
684
685static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
686SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
687 spkmixl, ARRAY_SIZE(spkmixl)),
688SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
689 out_pga_event, SND_SOC_DAPM_POST_PMU),
690SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
691SND_SOC_DAPM_OUTPUT("SPKOUT"),
692};
693
694static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
695SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
696 spkmixl, ARRAY_SIZE(spkmixl)),
697SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
698 spkmixr, ARRAY_SIZE(spkmixr)),
699
700SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
701 out_pga_event, SND_SOC_DAPM_POST_PMU),
702SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
703 out_pga_event, SND_SOC_DAPM_POST_PMU),
704
705SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
706SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
707
708SND_SOC_DAPM_OUTPUT("SPKOUTL"),
709SND_SOC_DAPM_OUTPUT("SPKOUTR"),
710};
711
712static const struct snd_soc_dapm_route wm8962_intercon[] = {
713 { "INPGAL", "IN1L Switch", "IN1L" },
714 { "INPGAL", "IN2L Switch", "IN2L" },
715 { "INPGAL", "IN3L Switch", "IN3L" },
716 { "INPGAL", "IN4L Switch", "IN4L" },
717
718 { "INPGAR", "IN1R Switch", "IN1R" },
719 { "INPGAR", "IN2R Switch", "IN2R" },
720 { "INPGAR", "IN3R Switch", "IN3R" },
721 { "INPGAR", "IN4R Switch", "IN4R" },
722
723 { "MIXINL", "IN2L Switch", "IN2L" },
724 { "MIXINL", "IN3L Switch", "IN3L" },
725 { "MIXINL", "PGA Switch", "INPGAL" },
726
727 { "MIXINR", "IN2R Switch", "IN2R" },
728 { "MIXINR", "IN3R Switch", "IN3R" },
729 { "MIXINR", "PGA Switch", "INPGAR" },
730
731 { "ADCL", NULL, "SYSCLK" },
732 { "ADCL", NULL, "TOCLK" },
733 { "ADCL", NULL, "MIXINL" },
734
735 { "ADCR", NULL, "SYSCLK" },
736 { "ADCR", NULL, "TOCLK" },
737 { "ADCR", NULL, "MIXINR" },
738
739 { "STL", "Left", "ADCL" },
740 { "STL", "Right", "ADCR" },
741
742 { "STR", "Left", "ADCL" },
743 { "STR", "Right", "ADCR" },
744
745 { "DACL", NULL, "SYSCLK" },
746 { "DACL", NULL, "TOCLK" },
747 { "DACL", NULL, "Beep" },
748 { "DACL", NULL, "STL" },
749
750 { "DACR", NULL, "SYSCLK" },
751 { "DACR", NULL, "TOCLK" },
752 { "DACR", NULL, "Beep" },
753 { "DACR", NULL, "STR" },
754
755 { "HPMIXL", "IN4L Switch", "IN4L" },
756 { "HPMIXL", "IN4R Switch", "IN4R" },
757 { "HPMIXL", "DACL Switch", "DACL" },
758 { "HPMIXL", "DACR Switch", "DACR" },
759 { "HPMIXL", "MIXINL Switch", "MIXINL" },
760 { "HPMIXL", "MIXINR Switch", "MIXINR" },
761
762 { "HPMIXR", "IN4L Switch", "IN4L" },
763 { "HPMIXR", "IN4R Switch", "IN4R" },
764 { "HPMIXR", "DACL Switch", "DACL" },
765 { "HPMIXR", "DACR Switch", "DACR" },
766 { "HPMIXR", "MIXINL Switch", "MIXINL" },
767 { "HPMIXR", "MIXINR Switch", "MIXINR" },
768
769 { "Left Bypass", NULL, "HPMIXL" },
770 { "Left Bypass", NULL, "Class G" },
771
772 { "Right Bypass", NULL, "HPMIXR" },
773 { "Right Bypass", NULL, "Class G" },
774
775 { "HPOUTL PGA", "Mixer", "Left Bypass" },
776 { "HPOUTL PGA", "DAC", "DACL" },
777
778 { "HPOUTR PGA", "Mixer", "Right Bypass" },
779 { "HPOUTR PGA", "DAC", "DACR" },
780
781 { "HPOUT", NULL, "HPOUTL PGA" },
782 { "HPOUT", NULL, "HPOUTR PGA" },
783 { "HPOUT", NULL, "Charge Pump" },
784 { "HPOUT", NULL, "SYSCLK" },
785 { "HPOUT", NULL, "TOCLK" },
786
787 { "HPOUTL", NULL, "HPOUT" },
788 { "HPOUTR", NULL, "HPOUT" },
789};
790
791static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
792 { "Speaker Mixer", "IN4L Switch", "IN4L" },
793 { "Speaker Mixer", "IN4R Switch", "IN4R" },
794 { "Speaker Mixer", "DACL Switch", "DACL" },
795 { "Speaker Mixer", "DACR Switch", "DACR" },
796 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
797 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
798
799 { "Speaker PGA", "Mixer", "Speaker Mixer" },
800 { "Speaker PGA", "DAC", "DACL" },
801
802 { "Speaker Output", NULL, "Speaker PGA" },
803 { "Speaker Output", NULL, "SYSCLK" },
804 { "Speaker Output", NULL, "TOCLK" },
805
806 { "SPKOUT", NULL, "Speaker Output" },
807};
808
809static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
810 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
811 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
812 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
813 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
814 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
815 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
816
817 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
818 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
819 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
820 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
821 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
822 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
823
824 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
825 { "SPKOUTL PGA", "DAC", "DACL" },
826
827 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
828 { "SPKOUTR PGA", "DAC", "DACR" },
829
830 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
831 { "SPKOUTL Output", NULL, "SYSCLK" },
832 { "SPKOUTL Output", NULL, "TOCLK" },
833
834 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
835 { "SPKOUTR Output", NULL, "SYSCLK" },
836 { "SPKOUTR Output", NULL, "TOCLK" },
837
838 { "SPKOUTL", NULL, "SPKOUTL Output" },
839 { "SPKOUTR", NULL, "SPKOUTR Output" },
840};
841
842static int wm8962_add_widgets(struct snd_soc_codec *codec)
843{
844 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
845
846 snd_soc_add_controls(codec, wm8962_snd_controls,
847 ARRAY_SIZE(wm8962_snd_controls));
848 if (pdata && pdata->spk_mono)
849 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
850 ARRAY_SIZE(wm8962_spk_mono_controls));
851 else
852 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
853 ARRAY_SIZE(wm8962_spk_stereo_controls));
854
855
856 snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
857 ARRAY_SIZE(wm8962_dapm_widgets));
858 if (pdata && pdata->spk_mono)
859 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
860 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
861 else
862 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
863 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
864
865 snd_soc_dapm_add_routes(codec, wm8962_intercon,
866 ARRAY_SIZE(wm8962_intercon));
867 if (pdata && pdata->spk_mono)
868 snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
869 ARRAY_SIZE(wm8962_spk_mono_intercon));
870 else
871 snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
872 ARRAY_SIZE(wm8962_spk_stereo_intercon));
873
874
875 snd_soc_dapm_disable_pin(codec, "Beep");
876
877 return 0;
878}
879
880static void wm8962_sync_cache(struct snd_soc_codec *codec)
881{
882 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
883 int i;
884
885 if (!codec->cache_sync)
886 return;
887
888 dev_dbg(codec->dev, "Syncing cache\n");
889
890 codec->cache_only = 0;
891
892 /* Sync back cached values if they're different from the
893 * hardware default.
894 */
895 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
896 if (i == WM8962_SOFTWARE_RESET)
897 continue;
898 if (wm8962->reg_cache[i] == wm8962_reg[i])
899 continue;
900
901 snd_soc_write(codec, i, wm8962->reg_cache[i]);
902 }
903
904 codec->cache_sync = 0;
905}
906
907/* -1 for reserved values */
908static const int bclk_divs[] = {
909 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
910};
911
912static void wm8962_configure_bclk(struct snd_soc_codec *codec)
913{
914 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
915 int dspclk, i;
916 int clocking2 = 0;
917 int aif2 = 0;
918
Mark Brown9a76f1f2010-08-05 13:20:59 +0100919 if (!wm8962->bclk) {
920 dev_dbg(codec->dev, "No BCLK rate configured\n");
921 return;
922 }
923
924 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
925 if (dspclk < 0) {
926 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
927 return;
928 }
929
930 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
931 switch (dspclk) {
932 case 0:
933 dspclk = wm8962->sysclk_rate;
934 break;
935 case 1:
936 dspclk = wm8962->sysclk_rate / 2;
937 break;
938 case 2:
939 dspclk = wm8962->sysclk_rate / 4;
940 break;
941 default:
942 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
943 dspclk = wm8962->sysclk;
944 }
945
946 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
947
948 /* We're expecting an exact match */
949 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
950 if (bclk_divs[i] < 0)
951 continue;
952
953 if (dspclk / bclk_divs[i] == wm8962->bclk) {
954 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
955 bclk_divs[i], wm8962->bclk);
956 clocking2 |= i;
957 break;
958 }
959 }
960 if (i == ARRAY_SIZE(bclk_divs)) {
961 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
962 dspclk / wm8962->bclk);
963 return;
964 }
965
966 aif2 |= wm8962->bclk / wm8962->lrclk;
967 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
968 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
969
970 snd_soc_update_bits(codec, WM8962_CLOCKING2,
971 WM8962_BCLK_DIV_MASK, clocking2);
972 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
973 WM8962_AIF_RATE_MASK, aif2);
974}
975
976static int wm8962_set_bias_level(struct snd_soc_codec *codec,
977 enum snd_soc_bias_level level)
978{
979 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
980 int ret;
981
982 if (level == codec->bias_level)
983 return 0;
984
985 switch (level) {
986 case SND_SOC_BIAS_ON:
987 break;
988
989 case SND_SOC_BIAS_PREPARE:
990 /* VMID 2*50k */
991 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
992 WM8962_VMID_SEL_MASK, 0x80);
993 break;
994
995 case SND_SOC_BIAS_STANDBY:
996 if (codec->bias_level == SND_SOC_BIAS_OFF) {
997 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
998 wm8962->supplies);
999 if (ret != 0) {
1000 dev_err(codec->dev,
1001 "Failed to enable supplies: %d\n",
1002 ret);
1003 return ret;
1004 }
1005
1006 wm8962_sync_cache(codec);
1007
1008 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1009 WM8962_STARTUP_BIAS_ENA |
1010 WM8962_VMID_BUF_ENA,
1011 WM8962_STARTUP_BIAS_ENA |
1012 WM8962_VMID_BUF_ENA);
1013
1014 /* Bias enable at 2*50k for ramp */
1015 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1016 WM8962_VMID_SEL_MASK |
1017 WM8962_BIAS_ENA,
1018 WM8962_BIAS_ENA | 0x180);
1019
1020 msleep(5);
1021
1022 snd_soc_update_bits(codec, WM8962_CLOCKING2,
1023 WM8962_CLKREG_OVD,
1024 WM8962_CLKREG_OVD);
1025
1026 wm8962_configure_bclk(codec);
1027 }
1028
1029 /* VMID 2*250k */
1030 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1031 WM8962_VMID_SEL_MASK, 0x100);
1032 break;
1033
1034 case SND_SOC_BIAS_OFF:
1035 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1036 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
1037
1038 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1039 WM8962_STARTUP_BIAS_ENA |
1040 WM8962_VMID_BUF_ENA, 0);
1041
1042 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
1043 wm8962->supplies);
1044 break;
1045 }
1046 codec->bias_level = level;
1047 return 0;
1048}
1049
1050static const struct {
1051 int rate;
1052 int reg;
1053} sr_vals[] = {
1054 { 48000, 0 },
1055 { 44100, 0 },
1056 { 32000, 1 },
1057 { 22050, 2 },
1058 { 24000, 2 },
1059 { 16000, 3 },
1060 { 11025, 4 },
1061 { 12000, 4 },
1062 { 8000, 5 },
1063 { 88200, 6 },
1064 { 96000, 6 },
1065};
1066
1067static const int sysclk_rates[] = {
1068 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
1069};
1070
1071static int wm8962_hw_params(struct snd_pcm_substream *substream,
1072 struct snd_pcm_hw_params *params,
1073 struct snd_soc_dai *dai)
1074{
1075 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Mark Brown54d8d0a2010-08-12 15:02:11 +01001076 struct snd_soc_codec *codec = rtd->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001077 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1078 int rate = params_rate(params);
1079 int i;
1080 int aif0 = 0;
1081 int adctl3 = 0;
1082 int clocking4 = 0;
1083
1084 wm8962->bclk = snd_soc_params_to_bclk(params);
1085 wm8962->lrclk = params_rate(params);
1086
1087 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
1088 if (sr_vals[i].rate == rate) {
1089 adctl3 |= sr_vals[i].reg;
1090 break;
1091 }
1092 }
1093 if (i == ARRAY_SIZE(sr_vals)) {
1094 dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
1095 return -EINVAL;
1096 }
1097
1098 if (rate % 8000 == 0)
1099 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
1100
1101 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
1102 if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
1103 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
1104 break;
1105 }
1106 }
1107 if (i == ARRAY_SIZE(sysclk_rates)) {
1108 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
1109 wm8962->sysclk_rate / rate);
1110 return -EINVAL;
1111 }
1112
1113 switch (params_format(params)) {
1114 case SNDRV_PCM_FORMAT_S16_LE:
1115 break;
1116 case SNDRV_PCM_FORMAT_S20_3LE:
1117 aif0 |= 0x40;
1118 break;
1119 case SNDRV_PCM_FORMAT_S24_LE:
1120 aif0 |= 0x80;
1121 break;
1122 case SNDRV_PCM_FORMAT_S32_LE:
1123 aif0 |= 0xc0;
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1130 WM8962_WL_MASK, aif0);
1131 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
1132 WM8962_SAMPLE_RATE_INT_MODE |
1133 WM8962_SAMPLE_RATE_MASK, adctl3);
1134 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
1135 WM8962_SYSCLK_RATE_MASK, clocking4);
1136
1137 wm8962_configure_bclk(codec);
1138
1139 return 0;
1140}
1141
1142static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1143 unsigned int freq, int dir)
1144{
1145 struct snd_soc_codec *codec = dai->codec;
1146 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1147 int src;
1148
1149 switch (clk_id) {
1150 case WM8962_SYSCLK_MCLK:
1151 wm8962->sysclk = WM8962_SYSCLK_MCLK;
1152 src = 0;
1153 break;
1154 case WM8962_SYSCLK_FLL:
1155 wm8962->sysclk = WM8962_SYSCLK_FLL;
1156 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
1157 WARN_ON(freq != wm8962->fll_fout);
1158 break;
1159 default:
1160 return -EINVAL;
1161 }
1162
1163 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
1164 src);
1165
1166 wm8962->sysclk_rate = freq;
1167
1168 return 0;
1169}
1170
1171static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1172{
1173 struct snd_soc_codec *codec = dai->codec;
1174 int aif0 = 0;
1175
1176 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1177 case SND_SOC_DAIFMT_DSP_A:
1178 aif0 |= WM8962_LRCLK_INV;
1179 case SND_SOC_DAIFMT_DSP_B:
1180 aif0 |= 3;
1181
1182 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1183 case SND_SOC_DAIFMT_NB_NF:
1184 case SND_SOC_DAIFMT_IB_NF:
1185 break;
1186 default:
1187 return -EINVAL;
1188 }
1189 break;
1190
1191 case SND_SOC_DAIFMT_RIGHT_J:
1192 break;
1193 case SND_SOC_DAIFMT_LEFT_J:
1194 aif0 |= 1;
1195 break;
1196 case SND_SOC_DAIFMT_I2S:
1197 aif0 |= 2;
1198 break;
1199 default:
1200 return -EINVAL;
1201 }
1202
1203 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1204 case SND_SOC_DAIFMT_NB_NF:
1205 break;
1206 case SND_SOC_DAIFMT_IB_NF:
1207 aif0 |= WM8962_BCLK_INV;
1208 break;
1209 case SND_SOC_DAIFMT_NB_IF:
1210 aif0 |= WM8962_LRCLK_INV;
1211 break;
1212 case SND_SOC_DAIFMT_IB_IF:
1213 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
1214 break;
1215 default:
1216 return -EINVAL;
1217 }
1218
1219 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1220 case SND_SOC_DAIFMT_CBM_CFM:
1221 aif0 |= WM8962_MSTR;
1222 break;
1223 case SND_SOC_DAIFMT_CBS_CFS:
1224 break;
1225 default:
1226 return -EINVAL;
1227 }
1228
1229 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1230 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
1231 WM8962_LRCLK_INV, aif0);
1232
1233 return 0;
1234}
1235
1236struct _fll_div {
1237 u16 fll_fratio;
1238 u16 fll_outdiv;
1239 u16 fll_refclk_div;
1240 u16 n;
1241 u16 theta;
1242 u16 lambda;
1243};
1244
1245/* The size in bits of the FLL divide multiplied by 10
1246 * to allow rounding later */
1247#define FIXED_FLL_SIZE ((1 << 16) * 10)
1248
1249static struct {
1250 unsigned int min;
1251 unsigned int max;
1252 u16 fll_fratio;
1253 int ratio;
1254} fll_fratios[] = {
1255 { 0, 64000, 4, 16 },
1256 { 64000, 128000, 3, 8 },
1257 { 128000, 256000, 2, 4 },
1258 { 256000, 1000000, 1, 2 },
1259 { 1000000, 13500000, 0, 1 },
1260};
1261
1262static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1263 unsigned int Fout)
1264{
1265 unsigned int target;
1266 unsigned int div;
1267 unsigned int fratio, gcd_fll;
1268 int i;
1269
1270 /* Fref must be <=13.5MHz */
1271 div = 1;
1272 fll_div->fll_refclk_div = 0;
1273 while ((Fref / div) > 13500000) {
1274 div *= 2;
1275 fll_div->fll_refclk_div++;
1276
1277 if (div > 4) {
1278 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1279 Fref);
1280 return -EINVAL;
1281 }
1282 }
1283
1284 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1285
1286 /* Apply the division for our remaining calculations */
1287 Fref /= div;
1288
1289 /* Fvco should be 90-100MHz; don't check the upper bound */
1290 div = 2;
1291 while (Fout * div < 90000000) {
1292 div++;
1293 if (div > 64) {
1294 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1295 Fout);
1296 return -EINVAL;
1297 }
1298 }
1299 target = Fout * div;
1300 fll_div->fll_outdiv = div - 1;
1301
1302 pr_debug("FLL Fvco=%dHz\n", target);
1303
1304 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1305 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1306 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1307 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1308 fratio = fll_fratios[i].ratio;
1309 break;
1310 }
1311 }
1312 if (i == ARRAY_SIZE(fll_fratios)) {
1313 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1314 return -EINVAL;
1315 }
1316
1317 fll_div->n = target / (fratio * Fref);
1318
1319 if (target % Fref == 0) {
1320 fll_div->theta = 0;
1321 fll_div->lambda = 0;
1322 } else {
1323 gcd_fll = gcd(target, fratio * Fref);
1324
1325 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1326 / gcd_fll;
1327 fll_div->lambda = (fratio * Fref) / gcd_fll;
1328 }
1329
1330 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1331 fll_div->n, fll_div->theta, fll_div->lambda);
1332 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1333 fll_div->fll_fratio, fll_div->fll_outdiv,
1334 fll_div->fll_refclk_div);
1335
1336 return 0;
1337}
1338
1339static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1340 unsigned int Fref, unsigned int Fout)
1341{
1342 struct snd_soc_codec *codec = dai->codec;
1343 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1344 struct _fll_div fll_div;
1345 int ret;
Mark Brown61371122010-09-27 17:20:11 -07001346 int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001347
1348 /* Any change? */
1349 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
1350 Fout == wm8962->fll_fout)
1351 return 0;
1352
1353 if (Fout == 0) {
1354 dev_dbg(codec->dev, "FLL disabled\n");
1355
1356 wm8962->fll_fref = 0;
1357 wm8962->fll_fout = 0;
1358
1359 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1360 WM8962_FLL_ENA, 0);
1361
1362 return 0;
1363 }
1364
1365 ret = fll_factors(&fll_div, Fref, Fout);
1366 if (ret != 0)
1367 return ret;
1368
1369 switch (fll_id) {
1370 case WM8962_FLL_MCLK:
1371 case WM8962_FLL_BCLK:
1372 case WM8962_FLL_OSC:
1373 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
1374 break;
1375 case WM8962_FLL_INT:
1376 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1377 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
1378 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
1379 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
1380 break;
1381 default:
1382 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
1383 return -EINVAL;
1384 }
1385
1386 if (fll_div.theta || fll_div.lambda)
1387 fll1 |= WM8962_FLL_FRAC;
1388
1389 /* Stop the FLL while we reconfigure */
1390 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
1391
1392 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
1393 WM8962_FLL_OUTDIV_MASK |
1394 WM8962_FLL_REFCLK_DIV_MASK,
1395 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
1396 (fll_div.fll_refclk_div));
1397
1398 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
1399 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
1400
1401 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
1402 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
1403 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
1404
1405 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1406 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
1407 WM8962_FLL_ENA, fll1);
1408
1409 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1410
1411 wm8962->fll_fref = Fref;
1412 wm8962->fll_fout = Fout;
1413 wm8962->fll_src = source;
1414
1415 return 0;
1416}
1417
1418static int wm8962_mute(struct snd_soc_dai *dai, int mute)
1419{
1420 struct snd_soc_codec *codec = dai->codec;
1421 int val;
1422
1423 if (mute)
1424 val = WM8962_DAC_MUTE;
1425 else
1426 val = 0;
1427
1428 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1429 WM8962_DAC_MUTE, val);
1430}
1431
1432#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
1433
1434#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1435 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1436
1437static struct snd_soc_dai_ops wm8962_dai_ops = {
1438 .hw_params = wm8962_hw_params,
1439 .set_sysclk = wm8962_set_dai_sysclk,
1440 .set_fmt = wm8962_set_dai_fmt,
1441 .set_pll = wm8962_set_fll,
1442 .digital_mute = wm8962_mute,
1443};
1444
Mark Brown54d8d0a2010-08-12 15:02:11 +01001445static struct snd_soc_dai_driver wm8962_dai = {
1446 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +01001447 .playback = {
1448 .stream_name = "Playback",
1449 .channels_min = 2,
1450 .channels_max = 2,
1451 .rates = WM8962_RATES,
1452 .formats = WM8962_FORMATS,
1453 },
1454 .capture = {
1455 .stream_name = "Capture",
1456 .channels_min = 2,
1457 .channels_max = 2,
1458 .rates = WM8962_RATES,
1459 .formats = WM8962_FORMATS,
1460 },
1461 .ops = &wm8962_dai_ops,
1462 .symmetric_rates = 1,
1463};
Mark Brown9a76f1f2010-08-05 13:20:59 +01001464
Mark Brown45e65502010-09-28 16:01:20 -07001465static irqreturn_t wm8962_irq(int irq, void *data)
1466{
1467 struct snd_soc_codec *codec = data;
1468 int mask;
1469 int active;
1470
1471 mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1472
1473 active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1474 active &= ~mask;
1475
1476 if (active & WM8962_FIFOS_ERR_EINT)
1477 dev_err(codec->dev, "FIFO error\n");
1478
1479 if (active & WM8962_TEMP_SHUT_EINT)
1480 dev_crit(codec->dev, "Thermal shutdown\n");
1481
1482 /* Acknowledge the interrupts */
1483 snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
1484
1485 return IRQ_HANDLED;
1486}
1487
Mark Brown9a76f1f2010-08-05 13:20:59 +01001488#ifdef CONFIG_PM
Mark Brown54d8d0a2010-08-12 15:02:11 +01001489static int wm8962_resume(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +01001490{
Mark Brown9a76f1f2010-08-05 13:20:59 +01001491 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1492 u16 *reg_cache = codec->reg_cache;
1493 int i;
1494
1495 /* Restore the registers */
1496 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
1497 switch (i) {
1498 case WM8962_SOFTWARE_RESET:
1499 continue;
1500 default:
1501 break;
1502 }
1503
1504 if (reg_cache[i] != wm8962_reg[i])
1505 snd_soc_write(codec, i, reg_cache[i]);
1506 }
1507
1508 return 0;
1509}
1510#else
1511#define wm8962_resume NULL
1512#endif
1513
Mark Brown9a76f1f2010-08-05 13:20:59 +01001514#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
1515static int beep_rates[] = {
1516 500, 1000, 2000, 4000,
1517};
1518
1519static void wm8962_beep_work(struct work_struct *work)
1520{
1521 struct wm8962_priv *wm8962 =
1522 container_of(work, struct wm8962_priv, beep_work);
Mark Brown54d8d0a2010-08-12 15:02:11 +01001523 struct snd_soc_codec *codec = wm8962->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001524 int i;
1525 int reg = 0;
1526 int best = 0;
1527
1528 if (wm8962->beep_rate) {
1529 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
1530 if (abs(wm8962->beep_rate - beep_rates[i]) <
1531 abs(wm8962->beep_rate - beep_rates[best]))
1532 best = i;
1533 }
1534
1535 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
1536 beep_rates[best], wm8962->beep_rate);
1537
1538 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
1539
1540 snd_soc_dapm_enable_pin(codec, "Beep");
1541 } else {
1542 dev_dbg(codec->dev, "Disabling beep\n");
1543 snd_soc_dapm_disable_pin(codec, "Beep");
1544 }
1545
1546 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
1547 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
1548
1549 snd_soc_dapm_sync(codec);
1550}
1551
1552/* For usability define a way of injecting beep events for the device -
1553 * many systems will not have a keyboard.
1554 */
1555static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
1556 unsigned int code, int hz)
1557{
1558 struct snd_soc_codec *codec = input_get_drvdata(dev);
1559 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1560
1561 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1562
1563 switch (code) {
1564 case SND_BELL:
1565 if (hz)
1566 hz = 1000;
1567 case SND_TONE:
1568 break;
1569 default:
1570 return -1;
1571 }
1572
1573 /* Kick the beep from a workqueue */
1574 wm8962->beep_rate = hz;
1575 schedule_work(&wm8962->beep_work);
1576 return 0;
1577}
1578
1579static ssize_t wm8962_beep_set(struct device *dev,
1580 struct device_attribute *attr,
1581 const char *buf, size_t count)
1582{
1583 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
1584 long int time;
1585
1586 strict_strtol(buf, 10, &time);
1587
1588 input_event(wm8962->beep, EV_SND, SND_TONE, time);
1589
1590 return count;
1591}
1592
1593static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
1594
1595static void wm8962_init_beep(struct snd_soc_codec *codec)
1596{
1597 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1598 int ret;
1599
1600 wm8962->beep = input_allocate_device();
1601 if (!wm8962->beep) {
1602 dev_err(codec->dev, "Failed to allocate beep device\n");
1603 return;
1604 }
1605
1606 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
1607 wm8962->beep_rate = 0;
1608
1609 wm8962->beep->name = "WM8962 Beep Generator";
1610 wm8962->beep->phys = dev_name(codec->dev);
1611 wm8962->beep->id.bustype = BUS_I2C;
1612
1613 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
1614 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1615 wm8962->beep->event = wm8962_beep_event;
1616 wm8962->beep->dev.parent = codec->dev;
1617 input_set_drvdata(wm8962->beep, codec);
1618
1619 ret = input_register_device(wm8962->beep);
1620 if (ret != 0) {
1621 input_free_device(wm8962->beep);
1622 wm8962->beep = NULL;
1623 dev_err(codec->dev, "Failed to register beep device\n");
1624 }
1625
1626 ret = device_create_file(codec->dev, &dev_attr_beep);
1627 if (ret != 0) {
1628 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1629 ret);
1630 }
1631}
1632
1633static void wm8962_free_beep(struct snd_soc_codec *codec)
1634{
1635 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1636
1637 device_remove_file(codec->dev, &dev_attr_beep);
1638 input_unregister_device(wm8962->beep);
1639 cancel_work_sync(&wm8962->beep_work);
1640 wm8962->beep = NULL;
1641
1642 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
1643}
1644#else
1645static void wm8962_init_beep(struct snd_soc_codec *codec)
1646{
1647}
1648
1649static void wm8962_free_beep(struct snd_soc_codec *codec)
1650{
1651}
1652#endif
1653
Mark Brown3367b8d2010-09-20 17:34:58 +01001654#ifdef CONFIG_GPIOLIB
1655static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
1656{
1657 return container_of(chip, struct wm8962_priv, gpio_chip);
1658}
1659
1660static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
1661{
1662 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1663 struct snd_soc_codec *codec = wm8962->codec;
1664 int mask = 0;
1665 int val;
1666
1667 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
1668 * we export linear numbers and error out if the unsupported
1669 * ones are requsted.
1670 */
1671 switch (offset + 1) {
1672 case 2:
1673 mask = WM8962_CLKOUT2_SEL_MASK;
1674 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
1675 break;
1676 case 3:
1677 mask = WM8962_CLKOUT3_SEL_MASK;
1678 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
1679 break;
1680 case 5:
1681 case 6:
1682 break;
1683 default:
1684 return -EINVAL;
1685 }
1686
1687 /* Some of the GPIOs are behind MFP configuration */
1688 if (mask)
1689 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
1690 mask, val);
1691
1692 return 0;
1693}
1694
1695static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1696{
1697 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1698 struct snd_soc_codec *codec = wm8962->codec;
1699
1700 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
1701 WM8962_GP2_LVL, value << WM8962_GP2_LVL_SHIFT);
1702}
1703
1704static int wm8962_gpio_direction_out(struct gpio_chip *chip,
1705 unsigned offset, int value)
1706{
1707 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1708 struct snd_soc_codec *codec = wm8962->codec;
1709 int val;
1710
1711 /* Force function 1 (logic output) */
1712 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
1713
1714 return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
1715 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
1716}
1717
1718static struct gpio_chip wm8962_template_chip = {
1719 .label = "wm8962",
1720 .owner = THIS_MODULE,
1721 .request = wm8962_gpio_request,
1722 .direction_output = wm8962_gpio_direction_out,
1723 .set = wm8962_gpio_set,
1724 .can_sleep = 1,
1725};
1726
1727static void wm8962_init_gpio(struct snd_soc_codec *codec)
1728{
1729 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1730 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
1731 int ret;
1732
1733 wm8962->gpio_chip = wm8962_template_chip;
1734 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
1735 wm8962->gpio_chip.dev = codec->dev;
1736
1737 if (pdata && pdata->gpio_base)
1738 wm8962->gpio_chip.base = pdata->gpio_base;
1739 else
1740 wm8962->gpio_chip.base = -1;
1741
1742 ret = gpiochip_add(&wm8962->gpio_chip);
1743 if (ret != 0)
1744 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1745}
1746
1747static void wm8962_free_gpio(struct snd_soc_codec *codec)
1748{
1749 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1750 int ret;
1751
1752 ret = gpiochip_remove(&wm8962->gpio_chip);
1753 if (ret != 0)
1754 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1755}
1756#else
1757static void wm8962_init_gpio(struct snd_soc_codec *codec)
1758{
1759}
1760
1761static void wm8962_free_gpio(struct snd_soc_codec *codec)
1762{
1763}
1764#endif
1765
Mark Brown54d8d0a2010-08-12 15:02:11 +01001766static int wm8962_probe(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +01001767{
1768 int ret;
Mark Brown54d8d0a2010-08-12 15:02:11 +01001769 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001770 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Mark Brown45e65502010-09-28 16:01:20 -07001771 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
1772 dev);
1773 int i, trigger, irq_pol;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001774
Mark Brown54d8d0a2010-08-12 15:02:11 +01001775 wm8962->codec = codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001776
Mark Brown9a76f1f2010-08-05 13:20:59 +01001777 codec->cache_sync = 1;
1778 codec->idle_bias_off = 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001779
Mark Brown54d8d0a2010-08-12 15:02:11 +01001780 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001781 if (ret != 0) {
1782 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1783 goto err;
1784 }
1785
1786 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1787 wm8962->supplies[i].supply = wm8962_supply_names[i];
1788
1789 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
1790 wm8962->supplies);
1791 if (ret != 0) {
1792 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1793 goto err;
1794 }
1795
1796 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
1797 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
1798 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
1799 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
1800 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
1801 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
1802 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
1803 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
1804
1805 /* This should really be moved into the regulator core */
1806 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
1807 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
1808 &wm8962->disable_nb[i]);
1809 if (ret != 0) {
1810 dev_err(codec->dev,
1811 "Failed to register regulator notifier: %d\n",
1812 ret);
1813 }
1814 }
1815
1816 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
1817 wm8962->supplies);
1818 if (ret != 0) {
1819 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1820 goto err_get;
1821 }
1822
1823 ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
1824 if (ret < 0) {
1825 dev_err(codec->dev, "Failed to read ID register\n");
1826 goto err_enable;
1827 }
1828 if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
1829 dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
1830 ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
1831 ret = -EINVAL;
1832 goto err_enable;
1833 }
1834
1835 ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
1836 if (ret < 0) {
1837 dev_err(codec->dev, "Failed to read device revision: %d\n",
1838 ret);
1839 goto err_enable;
1840 }
1841
1842 dev_info(codec->dev, "customer id %x revision %c\n",
1843 (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
1844 ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
1845 + 'A');
1846
1847 ret = wm8962_reset(codec);
1848 if (ret < 0) {
1849 dev_err(codec->dev, "Failed to issue reset\n");
1850 goto err_enable;
1851 }
1852
1853 /* SYSCLK defaults to on; make sure it is off so we can safely
1854 * write to registers if the device is declocked.
1855 */
1856 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
1857
1858 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1859
1860 if (pdata) {
1861 /* Apply static configuration for GPIOs */
1862 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
1863 if (pdata->gpio_init[i])
1864 snd_soc_write(codec, 0x200 + i,
1865 pdata->gpio_init[i] & 0xffff);
1866
1867 /* Put the speakers into mono mode? */
1868 if (pdata->spk_mono)
1869 wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
1870 |= WM8962_SPK_MONO;
Mark Browna4f28c02010-09-29 13:24:35 -07001871
1872 /* Micbias setup, detection enable and detection
1873 * threasholds. */
1874 if (pdata->mic_cfg)
1875 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
1876 WM8962_MICDET_ENA |
1877 WM8962_MICDET_THR_MASK |
1878 WM8962_MICSHORT_THR_MASK |
1879 WM8962_MICBIAS_LVL,
1880 pdata->mic_cfg);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001881 }
1882
1883 /* Latch volume update bits */
1884 wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
1885 wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
1886 wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
1887 wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
1888 wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
1889 wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
1890 wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
1891 wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
1892 wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
1893 wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
1894
Mark Brown54d8d0a2010-08-12 15:02:11 +01001895 wm8962_add_widgets(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001896
1897 wm8962_init_beep(codec);
Mark Brown3367b8d2010-09-20 17:34:58 +01001898 wm8962_init_gpio(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001899
Mark Brown45e65502010-09-28 16:01:20 -07001900 if (i2c->irq) {
1901 if (pdata && pdata->irq_active_low) {
1902 trigger = IRQF_TRIGGER_LOW;
1903 irq_pol = WM8962_IRQ_POL;
1904 } else {
1905 trigger = IRQF_TRIGGER_HIGH;
1906 irq_pol = 0;
1907 }
1908
1909 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
1910 WM8962_IRQ_POL, irq_pol);
1911
1912 ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
1913 trigger | IRQF_ONESHOT,
1914 "wm8962", codec);
1915 if (ret != 0) {
1916 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
1917 i2c->irq, ret);
1918 /* Non-fatal */
1919 } else {
1920 /* Enable error reporting IRQs by default */
1921 snd_soc_update_bits(codec,
1922 WM8962_INTERRUPT_STATUS_2_MASK,
1923 WM8962_TEMP_SHUT_EINT |
1924 WM8962_FIFOS_ERR_EINT, 0);
1925 }
1926 }
1927
Mark Brown9a76f1f2010-08-05 13:20:59 +01001928 return 0;
1929
1930err_enable:
1931 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1932err_get:
1933 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1934err:
1935 kfree(wm8962);
1936 return ret;
1937}
1938
Mark Brown54d8d0a2010-08-12 15:02:11 +01001939static int wm8962_remove(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +01001940{
Mark Brown54d8d0a2010-08-12 15:02:11 +01001941 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown45e65502010-09-28 16:01:20 -07001942 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
1943 dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001944 int i;
1945
Mark Brown45e65502010-09-28 16:01:20 -07001946 if (i2c->irq)
1947 free_irq(i2c->irq, codec);
1948
Mark Brown3367b8d2010-09-20 17:34:58 +01001949 wm8962_free_gpio(codec);
Mark Brown54d8d0a2010-08-12 15:02:11 +01001950 wm8962_free_beep(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001951 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1952 regulator_unregister_notifier(wm8962->supplies[i].consumer,
1953 &wm8962->disable_nb[i]);
1954 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brown54d8d0a2010-08-12 15:02:11 +01001955
1956 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001957}
1958
Mark Brown54d8d0a2010-08-12 15:02:11 +01001959static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
1960 .probe = wm8962_probe,
1961 .remove = wm8962_remove,
1962 .resume = wm8962_resume,
1963 .set_bias_level = wm8962_set_bias_level,
Dimitris Papastamos6946e032010-09-10 18:24:08 +01001964 .reg_cache_size = WM8962_MAX_REGISTER + 1,
Mark Brown54d8d0a2010-08-12 15:02:11 +01001965 .reg_word_size = sizeof(u16),
1966 .reg_cache_default = wm8962_reg,
1967 .volatile_register = wm8962_volatile_register,
1968 .readable_register = wm8962_readable_register,
1969};
1970
Mark Brown9a76f1f2010-08-05 13:20:59 +01001971#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1972static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
1973 const struct i2c_device_id *id)
1974{
1975 struct wm8962_priv *wm8962;
Mark Brown54d8d0a2010-08-12 15:02:11 +01001976 int ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001977
1978 wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
1979 if (wm8962 == NULL)
1980 return -ENOMEM;
1981
Mark Brown9a76f1f2010-08-05 13:20:59 +01001982 i2c_set_clientdata(i2c, wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001983
Mark Brown54d8d0a2010-08-12 15:02:11 +01001984 ret = snd_soc_register_codec(&i2c->dev,
1985 &soc_codec_dev_wm8962, &wm8962_dai, 1);
1986 if (ret < 0)
1987 kfree(wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +01001988
Mark Brown54d8d0a2010-08-12 15:02:11 +01001989 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +01001990}
1991
1992static __devexit int wm8962_i2c_remove(struct i2c_client *client)
1993{
Mark Brown54d8d0a2010-08-12 15:02:11 +01001994 snd_soc_unregister_codec(&client->dev);
1995 kfree(i2c_get_clientdata(client));
Mark Brown9a76f1f2010-08-05 13:20:59 +01001996 return 0;
1997}
1998
1999static const struct i2c_device_id wm8962_i2c_id[] = {
2000 { "wm8962", 0 },
2001 { }
2002};
2003MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
2004
2005static struct i2c_driver wm8962_i2c_driver = {
2006 .driver = {
Mark Brownea738ba2010-09-20 20:36:19 +01002007 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +01002008 .owner = THIS_MODULE,
2009 },
2010 .probe = wm8962_i2c_probe,
2011 .remove = __devexit_p(wm8962_i2c_remove),
2012 .id_table = wm8962_i2c_id,
2013};
2014#endif
2015
2016static int __init wm8962_modinit(void)
2017{
2018 int ret;
2019#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2020 ret = i2c_add_driver(&wm8962_i2c_driver);
2021 if (ret != 0) {
2022 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
2023 ret);
2024 }
2025#endif
2026 return 0;
2027}
2028module_init(wm8962_modinit);
2029
2030static void __exit wm8962_exit(void)
2031{
2032#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2033 i2c_del_driver(&wm8962_i2c_driver);
2034#endif
2035}
2036module_exit(wm8962_exit);
2037
2038MODULE_DESCRIPTION("ASoC WM8962 driver");
2039MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2040MODULE_LICENSE("GPL");