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gerrit-public.fairphone.software / kernel / msm-4.9 / 33b385873297e43e9beba7eb2fb515dd6848444c / . / arch / arm / boot / dts / imx6q.dtsi
blob: d907d062e5dd36416d6e063c2c590da29a0642b4 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40
41 cpu@1 {
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 next-level-cache = <&L2>;
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a9";
49 reg = <2>;
50 next-level-cache = <&L2>;
51 };
52
53 cpu@3 {
54 compatible = "arm,cortex-a9";
55 reg = <3>;
56 next-level-cache = <&L2>;
57 };
58 };
59
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
63 #address-cells = <1>;
64 #size-cells = <1>;
65 interrupt-controller;
66 reg = <0x00a01000 0x1000>,
67 <0x00a00100 0x100>;
68 };
69
70 clocks {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 ckil {
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
77 };
78
79 ckih1 {
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
82 };
83
84 osc {
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
87 };
88 };
89
90 soc {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
95 ranges;
96
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]97 dma-apbh@00110000 {
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]100 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]101 };
102
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]103 gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 13 0x04>, <0 15 0x04>;
110 interrupt-names = "gpmi-dma", "bch";
111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
116 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]117 };
118
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]119 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x00a00600 0x20>;
122 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]123 };
124
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 0x04>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 aips-bus@02000000 { /* AIPS1 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 reg = <0x02000000 0x100000>;
138 ranges;
139
140 spba-bus@02000000 {
141 compatible = "fsl,spba-bus", "simple-bus";
142 #address-cells = <1>;
143 #size-cells = <1>;
144 reg = <0x02000000 0x40000>;
145 ranges;
146
147 spdif@02004000 {
148 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>;
150 };
151
152 ecspi@02008000 { /* eCSPI1 */
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]160 status = "disabled";
161 };
162
163 ecspi@0200c000 { /* eCSPI2 */
164 #address-cells = <1>;
165 #size-cells = <0>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x0200c000 0x4000>;
168 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]171 status = "disabled";
172 };
173
174 ecspi@02010000 { /* eCSPI3 */
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02010000 0x4000>;
179 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]182 status = "disabled";
183 };
184
185 ecspi@02014000 { /* eCSPI4 */
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02014000 0x4000>;
190 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]193 status = "disabled";
194 };
195
196 ecspi@02018000 { /* eCSPI5 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02018000 0x4000>;
201 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 status = "disabled";
205 };
206
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]207 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02020000 0x4000>;
210 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]213 status = "disabled";
214 };
215
216 esai@02024000 {
217 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>;
219 };
220
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]221 ssi1: ssi@02028000 {
222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]223 reg = <0x02028000 0x4000>;
224 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]225 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
228 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]229 };
230
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]231 ssi2: ssi@0202c000 {
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]235 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]236 fsl,fifo-depth = <15>;
237 fsl,ssi-dma-events = <42 41>;
238 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 };
240
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]241 ssi3: ssi@02030000 {
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]243 reg = <0x02030000 0x4000>;
244 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]245 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]246 fsl,fifo-depth = <15>;
247 fsl,ssi-dma-events = <46 45>;
248 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 };
250
251 asrc@02034000 {
252 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>;
254 };
255
256 spba@0203c000 {
257 reg = <0x0203c000 0x4000>;
258 };
259 };
260
261 vpu@02040000 {
262 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>;
264 };
265
266 aipstz@0207c000 { /* AIPSTZ1 */
267 reg = <0x0207c000 0x4000>;
268 };
269
270 pwm@02080000 { /* PWM1 */
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]271 #pwm-cells = <2>;
272 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]273 reg = <0x02080000 0x4000>;
274 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]275 clocks = <&clks 62>, <&clks 145>;
276 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]277 };
278
279 pwm@02084000 { /* PWM2 */
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]280 #pwm-cells = <2>;
281 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]282 reg = <0x02084000 0x4000>;
283 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]284 clocks = <&clks 62>, <&clks 146>;
285 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]286 };
287
288 pwm@02088000 { /* PWM3 */
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]289 #pwm-cells = <2>;
290 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]291 reg = <0x02088000 0x4000>;
292 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]293 clocks = <&clks 62>, <&clks 147>;
294 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]295 };
296
297 pwm@0208c000 { /* PWM4 */
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]298 #pwm-cells = <2>;
299 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]300 reg = <0x0208c000 0x4000>;
301 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame^]302 clocks = <&clks 62>, <&clks 148>;
303 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]304 };
305
306 flexcan@02090000 { /* CAN1 */
307 reg = <0x02090000 0x4000>;
308 interrupts = <0 110 0x04>;
309 };
310
311 flexcan@02094000 { /* CAN2 */
312 reg = <0x02094000 0x4000>;
313 interrupts = <0 111 0x04>;
314 };
315
316 gpt@02098000 {
317 compatible = "fsl,imx6q-gpt";
318 reg = <0x02098000 0x4000>;
319 interrupts = <0 55 0x04>;
320 };
321
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]322 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]323 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]324 reg = <0x0209c000 0x4000>;
325 interrupts = <0 66 0x04 0 67 0x04>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]329 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]330 };
331
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]332 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]333 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]334 reg = <0x020a0000 0x4000>;
335 interrupts = <0 68 0x04 0 69 0x04>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]339 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]340 };
341
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]342 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]343 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]344 reg = <0x020a4000 0x4000>;
345 interrupts = <0 70 0x04 0 71 0x04>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]349 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]350 };
351
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]352 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]353 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]354 reg = <0x020a8000 0x4000>;
355 interrupts = <0 72 0x04 0 73 0x04>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]359 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]360 };
361
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]362 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]363 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]364 reg = <0x020ac000 0x4000>;
365 interrupts = <0 74 0x04 0 75 0x04>;
366 gpio-controller;
367 #gpio-cells = <2>;
368 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]369 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]370 };
371
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]372 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]373 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]374 reg = <0x020b0000 0x4000>;
375 interrupts = <0 76 0x04 0 77 0x04>;
376 gpio-controller;
377 #gpio-cells = <2>;
378 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]379 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]380 };
381
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]382 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]383 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]384 reg = <0x020b4000 0x4000>;
385 interrupts = <0 78 0x04 0 79 0x04>;
386 gpio-controller;
387 #gpio-cells = <2>;
388 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]389 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]390 };
391
392 kpp@020b8000 {
393 reg = <0x020b8000 0x4000>;
394 interrupts = <0 82 0x04>;
395 };
396
397 wdog@020bc000 { /* WDOG1 */
398 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
399 reg = <0x020bc000 0x4000>;
400 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]401 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]402 };
403
404 wdog@020c0000 { /* WDOG2 */
405 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
406 reg = <0x020c0000 0x4000>;
407 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]408 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]409 status = "disabled";
410 };
411
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]412 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]413 compatible = "fsl,imx6q-ccm";
414 reg = <0x020c4000 0x4000>;
415 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]416 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]417 };
418
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]419 anatop: anatop@020c8000 {
420 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]421 reg = <0x020c8000 0x1000>;
422 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]423
424 regulator-1p1@110 {
425 compatible = "fsl,anatop-regulator";
426 regulator-name = "vdd1p1";
427 regulator-min-microvolt = <800000>;
428 regulator-max-microvolt = <1375000>;
429 regulator-always-on;
430 anatop-reg-offset = <0x110>;
431 anatop-vol-bit-shift = <8>;
432 anatop-vol-bit-width = <5>;
433 anatop-min-bit-val = <4>;
434 anatop-min-voltage = <800000>;
435 anatop-max-voltage = <1375000>;
436 };
437
438 regulator-3p0@120 {
439 compatible = "fsl,anatop-regulator";
440 regulator-name = "vdd3p0";
441 regulator-min-microvolt = <2800000>;
442 regulator-max-microvolt = <3150000>;
443 regulator-always-on;
444 anatop-reg-offset = <0x120>;
445 anatop-vol-bit-shift = <8>;
446 anatop-vol-bit-width = <5>;
447 anatop-min-bit-val = <0>;
448 anatop-min-voltage = <2625000>;
449 anatop-max-voltage = <3400000>;
450 };
451
452 regulator-2p5@130 {
453 compatible = "fsl,anatop-regulator";
454 regulator-name = "vdd2p5";
455 regulator-min-microvolt = <2000000>;
456 regulator-max-microvolt = <2750000>;
457 regulator-always-on;
458 anatop-reg-offset = <0x130>;
459 anatop-vol-bit-shift = <8>;
460 anatop-vol-bit-width = <5>;
461 anatop-min-bit-val = <0>;
462 anatop-min-voltage = <2000000>;
463 anatop-max-voltage = <2750000>;
464 };
465
466 regulator-vddcore@140 {
467 compatible = "fsl,anatop-regulator";
468 regulator-name = "cpu";
469 regulator-min-microvolt = <725000>;
470 regulator-max-microvolt = <1450000>;
471 regulator-always-on;
472 anatop-reg-offset = <0x140>;
473 anatop-vol-bit-shift = <0>;
474 anatop-vol-bit-width = <5>;
475 anatop-min-bit-val = <1>;
476 anatop-min-voltage = <725000>;
477 anatop-max-voltage = <1450000>;
478 };
479
480 regulator-vddpu@140 {
481 compatible = "fsl,anatop-regulator";
482 regulator-name = "vddpu";
483 regulator-min-microvolt = <725000>;
484 regulator-max-microvolt = <1450000>;
485 regulator-always-on;
486 anatop-reg-offset = <0x140>;
487 anatop-vol-bit-shift = <9>;
488 anatop-vol-bit-width = <5>;
489 anatop-min-bit-val = <1>;
490 anatop-min-voltage = <725000>;
491 anatop-max-voltage = <1450000>;
492 };
493
494 regulator-vddsoc@140 {
495 compatible = "fsl,anatop-regulator";
496 regulator-name = "vddsoc";
497 regulator-min-microvolt = <725000>;
498 regulator-max-microvolt = <1450000>;
499 regulator-always-on;
500 anatop-reg-offset = <0x140>;
501 anatop-vol-bit-shift = <18>;
502 anatop-vol-bit-width = <5>;
503 anatop-min-bit-val = <1>;
504 anatop-min-voltage = <725000>;
505 anatop-max-voltage = <1450000>;
506 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]507 };
508
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]509 usbphy1: usbphy@020c9000 {
510 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]511 reg = <0x020c9000 0x1000>;
512 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]513 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]514 };
515
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]516 usbphy2: usbphy@020ca000 {
517 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]518 reg = <0x020ca000 0x1000>;
519 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]520 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]521 };
522
523 snvs@020cc000 {
524 reg = <0x020cc000 0x4000>;
525 interrupts = <0 19 0x04 0 20 0x04>;
526 };
527
528 epit@020d0000 { /* EPIT1 */
529 reg = <0x020d0000 0x4000>;
530 interrupts = <0 56 0x04>;
531 };
532
533 epit@020d4000 { /* EPIT2 */
534 reg = <0x020d4000 0x4000>;
535 interrupts = <0 57 0x04>;
536 };
537
538 src@020d8000 {
539 compatible = "fsl,imx6q-src";
540 reg = <0x020d8000 0x4000>;
541 interrupts = <0 91 0x04 0 96 0x04>;
542 };
543
544 gpc@020dc000 {
545 compatible = "fsl,imx6q-gpc";
546 reg = <0x020dc000 0x4000>;
547 interrupts = <0 89 0x04 0 90 0x04>;
548 };
549
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]550 gpr: iomuxc-gpr@020e0000 {
551 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
552 reg = <0x020e0000 0x38>;
553 };
554
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]555 iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]556 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]557 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]558
559 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]560 audmux {
561 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]562 fsl,pins = <
563 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
564 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
565 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
566 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
567 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]568 };
569 };
570
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]571 ecspi1 {
572 pinctrl_ecspi1_1: ecspi1grp-1 {
573 fsl,pins = <
574 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
575 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
576 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
577 >;
578 };
579 };
580
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]581 enet {
582 pinctrl_enet_1: enetgrp-1 {
583 fsl,pins = <
584 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
585 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
586 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
587 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
588 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
589 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
590 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
591 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
592 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
593 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
594 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
595 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
596 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
597 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
598 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
599 >;
600 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]601
602 pinctrl_enet_2: enetgrp-2 {
603 fsl,pins = <
604 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
605 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
606 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
607 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
608 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
609 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
610 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
611 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
612 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
613 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
614 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
615 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
616 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
617 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
618 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
619 >;
620 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]621 };
622
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]623 gpmi-nand {
624 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]625 fsl,pins = <
626 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
627 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
628 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
629 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
630 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
631 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
632 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
633 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
634 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
635 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
636 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
637 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
638 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
639 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
640 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
641 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
642 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
643 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
644 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
645 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]646 };
647 };
648
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]649 i2c1 {
650 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]651 fsl,pins = <
652 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
653 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
654 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]655 };
656 };
657
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]658 uart1 {
659 pinctrl_uart1_1: uart1grp-1 {
660 fsl,pins = <
661 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
662 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
663 >;
664 };
665 };
666
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]667 uart2 {
668 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]669 fsl,pins = <
670 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
671 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
672 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]673 };
674 };
675
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]676 uart4 {
677 pinctrl_uart4_1: uart4grp-1 {
678 fsl,pins = <
679 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
680 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
681 >;
682 };
683 };
684
Richard Zhao97a53092012-09-19 11:25:16 +0800[diff] [blame]685 usbotg {
686 pinctrl_usbotg_1: usbotggrp-1 {
687 fsl,pins = <
688 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
689 >;
690 };
691 };
692
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]693 usdhc2 {
694 pinctrl_usdhc2_1: usdhc2grp-1 {
695 fsl,pins = <
696 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
697 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
698 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
699 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
700 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
701 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
702 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
703 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
704 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
705 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
706 >;
707 };
708 };
709
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]710 usdhc3 {
711 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]712 fsl,pins = <
713 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
714 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
715 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
716 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
717 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
718 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
719 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
720 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
721 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
722 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
723 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]724 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]725
726 pinctrl_usdhc3_2: usdhc3grp-2 {
727 fsl,pins = <
728 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
729 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
730 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
731 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
732 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
733 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
734 >;
735 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]736 };
737
738 usdhc4 {
739 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]740 fsl,pins = <
741 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
742 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
743 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
744 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
745 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
746 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
747 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
748 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
749 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
750 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
751 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]752 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]753
754 pinctrl_usdhc4_2: usdhc4grp-2 {
755 fsl,pins = <
756 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
757 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
758 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
759 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
760 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
761 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
762 >;
763 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]764 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]765 };
766
767 dcic@020e4000 { /* DCIC1 */
768 reg = <0x020e4000 0x4000>;
769 interrupts = <0 124 0x04>;
770 };
771
772 dcic@020e8000 { /* DCIC2 */
773 reg = <0x020e8000 0x4000>;
774 interrupts = <0 125 0x04>;
775 };
776
777 sdma@020ec000 {
778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
779 reg = <0x020ec000 0x4000>;
780 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]781 clocks = <&clks 155>, <&clks 155>;
782 clock-names = "ipg", "ahb";
783 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]784 };
785 };
786
787 aips-bus@02100000 { /* AIPS2 */
788 compatible = "fsl,aips-bus", "simple-bus";
789 #address-cells = <1>;
790 #size-cells = <1>;
791 reg = <0x02100000 0x100000>;
792 ranges;
793
794 caam@02100000 {
795 reg = <0x02100000 0x40000>;
796 interrupts = <0 105 0x04 0 106 0x04>;
797 };
798
799 aipstz@0217c000 { /* AIPSTZ2 */
800 reg = <0x0217c000 0x4000>;
801 };
802
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]803 usb@02184000 { /* USB OTG */
804 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
805 reg = <0x02184000 0x200>;
806 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]807 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]808 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]809 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]810 status = "disabled";
811 };
812
813 usb@02184200 { /* USB1 */
814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
815 reg = <0x02184200 0x200>;
816 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]817 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]818 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]819 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]820 status = "disabled";
821 };
822
823 usb@02184400 { /* USB2 */
824 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
825 reg = <0x02184400 0x200>;
826 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]827 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]828 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]829 status = "disabled";
830 };
831
832 usb@02184600 { /* USB3 */
833 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
834 reg = <0x02184600 0x200>;
835 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]836 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]837 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]838 status = "disabled";
839 };
840
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]841 usbmisc: usbmisc@02184800 {
842 #index-cells = <1>;
843 compatible = "fsl,imx6q-usbmisc";
844 reg = <0x02184800 0x200>;
845 clocks = <&clks 162>;
846 };
847
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]848 ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]849 compatible = "fsl,imx6q-fec";
850 reg = <0x02188000 0x4000>;
851 interrupts = <0 118 0x04 0 119 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]852 clocks = <&clks 117>, <&clks 117>;
853 clock-names = "ipg", "ahb";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]854 status = "disabled";
855 };
856
857 mlb@0218c000 {
858 reg = <0x0218c000 0x4000>;
859 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
860 };
861
862 usdhc@02190000 { /* uSDHC1 */
863 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02190000 0x4000>;
865 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]866 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
867 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]868 status = "disabled";
869 };
870
871 usdhc@02194000 { /* uSDHC2 */
872 compatible = "fsl,imx6q-usdhc";
873 reg = <0x02194000 0x4000>;
874 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]875 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
876 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]877 status = "disabled";
878 };
879
880 usdhc@02198000 { /* uSDHC3 */
881 compatible = "fsl,imx6q-usdhc";
882 reg = <0x02198000 0x4000>;
883 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]884 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
885 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]886 status = "disabled";
887 };
888
889 usdhc@0219c000 { /* uSDHC4 */
890 compatible = "fsl,imx6q-usdhc";
891 reg = <0x0219c000 0x4000>;
892 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]893 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
894 clock-names = "ipg", "ahb", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]895 status = "disabled";
896 };
897
898 i2c@021a0000 { /* I2C1 */
899 #address-cells = <1>;
900 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]901 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]902 reg = <0x021a0000 0x4000>;
903 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]904 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]905 status = "disabled";
906 };
907
908 i2c@021a4000 { /* I2C2 */
909 #address-cells = <1>;
910 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]911 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]912 reg = <0x021a4000 0x4000>;
913 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]914 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]915 status = "disabled";
916 };
917
918 i2c@021a8000 { /* I2C3 */
919 #address-cells = <1>;
920 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]921 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]922 reg = <0x021a8000 0x4000>;
923 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]924 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]925 status = "disabled";
926 };
927
928 romcp@021ac000 {
929 reg = <0x021ac000 0x4000>;
930 };
931
932 mmdc@021b0000 { /* MMDC0 */
933 compatible = "fsl,imx6q-mmdc";
934 reg = <0x021b0000 0x4000>;
935 };
936
937 mmdc@021b4000 { /* MMDC1 */
938 reg = <0x021b4000 0x4000>;
939 };
940
941 weim@021b8000 {
942 reg = <0x021b8000 0x4000>;
943 interrupts = <0 14 0x04>;
944 };
945
946 ocotp@021bc000 {
947 reg = <0x021bc000 0x4000>;
948 };
949
950 ocotp@021c0000 {
951 reg = <0x021c0000 0x4000>;
952 interrupts = <0 21 0x04>;
953 };
954
955 tzasc@021d0000 { /* TZASC1 */
956 reg = <0x021d0000 0x4000>;
957 interrupts = <0 108 0x04>;
958 };
959
960 tzasc@021d4000 { /* TZASC2 */
961 reg = <0x021d4000 0x4000>;
962 interrupts = <0 109 0x04>;
963 };
964
965 audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]966 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]967 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]968 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]969 };
970
971 mipi@021dc000 { /* MIPI-CSI */
972 reg = <0x021dc000 0x4000>;
973 };
974
975 mipi@021e0000 { /* MIPI-DSI */
976 reg = <0x021e0000 0x4000>;
977 };
978
979 vdoa@021e4000 {
980 reg = <0x021e4000 0x4000>;
981 interrupts = <0 18 0x04>;
982 };
983
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]984 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]985 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
986 reg = <0x021e8000 0x4000>;
987 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]988 clocks = <&clks 160>, <&clks 161>;
989 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]990 status = "disabled";
991 };
992
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]993 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]994 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
995 reg = <0x021ec000 0x4000>;
996 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]997 clocks = <&clks 160>, <&clks 161>;
998 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]999 status = "disabled";
1000 };
1001
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1002 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1003 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1004 reg = <0x021f0000 0x4000>;
1005 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1006 clocks = <&clks 160>, <&clks 161>;
1007 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1008 status = "disabled";
1009 };
1010
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1011 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1012 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1013 reg = <0x021f4000 0x4000>;
1014 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1015 clocks = <&clks 160>, <&clks 161>;
1016 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1017 status = "disabled";
1018 };
1019 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1020
1021 ipu1: ipu@02400000 {
1022 #crtc-cells = <1>;
1023 compatible = "fsl,imx6q-ipu";
1024 reg = <0x02400000 0x400000>;
1025 interrupts = <0 6 0x4 0 5 0x4>;
1026 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1027 clock-names = "bus", "di0", "di1";
1028 };
1029
1030 ipu2: ipu@02800000 {
1031 #crtc-cells = <1>;
1032 compatible = "fsl,imx6q-ipu";
1033 reg = <0x02800000 0x400000>;
1034 interrupts = <0 8 0x4 0 7 0x4>;
1035 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1036 clock-names = "bus", "di0", "di1";
1037 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1038 };
1039};