blob: 24fb989593f030f98c81ed13f11a014b2a467b1a [file] [log] [blame]
Daniel Vetter76aaf222010-11-05 22:23:30 +01001/*
2 * Copyright © 2010 Daniel Vetter
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
David Howells760285e2012-10-02 18:01:07 +010025#include <drm/drmP.h>
26#include <drm/i915_drm.h>
Daniel Vetter76aaf222010-11-05 22:23:30 +010027#include "i915_drv.h"
28#include "i915_trace.h"
29#include "intel_drv.h"
30
Ben Widawsky6670a5a2013-06-27 16:30:04 -070031#define GEN6_PPGTT_PD_ENTRIES 512
32#define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
33
Ben Widawsky26b1ff32012-11-04 09:21:31 -080034/* PPGTT stuff */
35#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
Ben Widawsky0d8ff152013-07-04 11:02:03 -070036#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
Ben Widawsky26b1ff32012-11-04 09:21:31 -080037
38#define GEN6_PDE_VALID (1 << 0)
39/* gen6+ has bit 11-4 for physical addr bit 39-32 */
40#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
41
42#define GEN6_PTE_VALID (1 << 0)
43#define GEN6_PTE_UNCACHED (1 << 1)
44#define HSW_PTE_UNCACHED (0)
45#define GEN6_PTE_CACHE_LLC (2 << 1)
Chris Wilson350ec882013-08-06 13:17:02 +010046#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
Ben Widawsky26b1ff32012-11-04 09:21:31 -080047#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
Ben Widawsky0d8ff152013-07-04 11:02:03 -070048#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
49
50/* Cacheability Control is a 4-bit value. The low three bits are stored in *
51 * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
52 */
53#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
54 (((bits) & 0x8) << (11 - 3)))
Ben Widawsky87a6b682013-08-04 23:47:29 -070055#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
Ben Widawsky0d8ff152013-07-04 11:02:03 -070056#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
Ben Widawsky4d15c142013-07-04 11:02:06 -070057#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
Ben Widawsky26b1ff32012-11-04 09:21:31 -080058
Chris Wilson350ec882013-08-06 13:17:02 +010059static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
60 enum i915_cache_level level)
Ben Widawsky54d12522012-09-24 16:44:32 -070061{
Ben Widawskye7c2b582013-04-08 18:43:48 -070062 gen6_gtt_pte_t pte = GEN6_PTE_VALID;
Ben Widawsky54d12522012-09-24 16:44:32 -070063 pte |= GEN6_PTE_ADDR_ENCODE(addr);
Ben Widawskye7210c32012-10-19 09:33:22 -070064
65 switch (level) {
Chris Wilson350ec882013-08-06 13:17:02 +010066 case I915_CACHE_L3_LLC:
67 case I915_CACHE_LLC:
68 pte |= GEN6_PTE_CACHE_LLC;
69 break;
70 case I915_CACHE_NONE:
71 pte |= GEN6_PTE_UNCACHED;
72 break;
73 default:
74 WARN_ON(1);
75 }
76
77 return pte;
78}
79
80static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
81 enum i915_cache_level level)
82{
83 gen6_gtt_pte_t pte = GEN6_PTE_VALID;
84 pte |= GEN6_PTE_ADDR_ENCODE(addr);
85
86 switch (level) {
87 case I915_CACHE_L3_LLC:
88 pte |= GEN7_PTE_CACHE_L3_LLC;
Ben Widawskye7210c32012-10-19 09:33:22 -070089 break;
90 case I915_CACHE_LLC:
91 pte |= GEN6_PTE_CACHE_LLC;
92 break;
93 case I915_CACHE_NONE:
Kenneth Graunke91197082013-04-22 00:53:51 -070094 pte |= GEN6_PTE_UNCACHED;
Ben Widawskye7210c32012-10-19 09:33:22 -070095 break;
96 default:
Chris Wilson350ec882013-08-06 13:17:02 +010097 WARN_ON(1);
Ben Widawskye7210c32012-10-19 09:33:22 -070098 }
99
Ben Widawsky54d12522012-09-24 16:44:32 -0700100 return pte;
101}
102
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700103#define BYT_PTE_WRITEABLE (1 << 1)
104#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
105
Ben Widawsky80a74f72013-06-27 16:30:19 -0700106static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700107 enum i915_cache_level level)
108{
109 gen6_gtt_pte_t pte = GEN6_PTE_VALID;
110 pte |= GEN6_PTE_ADDR_ENCODE(addr);
111
112 /* Mark the page as writeable. Other platforms don't have a
113 * setting for read-only/writable, so this matches that behavior.
114 */
115 pte |= BYT_PTE_WRITEABLE;
116
117 if (level != I915_CACHE_NONE)
118 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
119
120 return pte;
121}
122
Ben Widawsky80a74f72013-06-27 16:30:19 -0700123static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
Kenneth Graunke91197082013-04-22 00:53:51 -0700124 enum i915_cache_level level)
125{
126 gen6_gtt_pte_t pte = GEN6_PTE_VALID;
Ben Widawsky0d8ff152013-07-04 11:02:03 -0700127 pte |= HSW_PTE_ADDR_ENCODE(addr);
Kenneth Graunke91197082013-04-22 00:53:51 -0700128
129 if (level != I915_CACHE_NONE)
Ben Widawsky87a6b682013-08-04 23:47:29 -0700130 pte |= HSW_WB_LLC_AGE3;
Kenneth Graunke91197082013-04-22 00:53:51 -0700131
132 return pte;
133}
134
Ben Widawsky4d15c142013-07-04 11:02:06 -0700135static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
136 enum i915_cache_level level)
137{
138 gen6_gtt_pte_t pte = GEN6_PTE_VALID;
139 pte |= HSW_PTE_ADDR_ENCODE(addr);
140
141 if (level != I915_CACHE_NONE)
142 pte |= HSW_WB_ELLC_LLC_AGE0;
143
144 return pte;
145}
146
Ben Widawsky3e302542013-04-23 23:15:32 -0700147static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky61973492013-04-08 18:43:54 -0700148{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700149 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
Ben Widawsky61973492013-04-08 18:43:54 -0700150 gen6_gtt_pte_t __iomem *pd_addr;
151 uint32_t pd_entry;
152 int i;
153
Ben Widawsky0a732872013-04-23 23:15:30 -0700154 WARN_ON(ppgtt->pd_offset & 0x3f);
Ben Widawsky61973492013-04-08 18:43:54 -0700155 pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
156 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
157 for (i = 0; i < ppgtt->num_pd_entries; i++) {
158 dma_addr_t pt_addr;
159
160 pt_addr = ppgtt->pt_dma_addr[i];
161 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
162 pd_entry |= GEN6_PDE_VALID;
163
164 writel(pd_entry, pd_addr + i);
165 }
166 readl(pd_addr);
Ben Widawsky3e302542013-04-23 23:15:32 -0700167}
168
169static int gen6_ppgtt_enable(struct drm_device *dev)
170{
171 drm_i915_private_t *dev_priv = dev->dev_private;
172 uint32_t pd_offset;
173 struct intel_ring_buffer *ring;
174 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
175 int i;
176
177 BUG_ON(ppgtt->pd_offset & 0x3f);
178
179 gen6_write_pdes(ppgtt);
Ben Widawsky61973492013-04-08 18:43:54 -0700180
181 pd_offset = ppgtt->pd_offset;
182 pd_offset /= 64; /* in cachelines, */
183 pd_offset <<= 16;
184
185 if (INTEL_INFO(dev)->gen == 6) {
186 uint32_t ecochk, gab_ctl, ecobits;
187
188 ecobits = I915_READ(GAC_ECO_BITS);
Ville Syrjälä3b9d7882013-04-04 15:13:40 +0300189 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
190 ECOBITS_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -0700191
192 gab_ctl = I915_READ(GAB_CTL);
193 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
194
195 ecochk = I915_READ(GAM_ECOCHK);
196 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
197 ECOCHK_PPGTT_CACHE64B);
198 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
199 } else if (INTEL_INFO(dev)->gen >= 7) {
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300200 uint32_t ecochk, ecobits;
Ville Syrjäläa65c2fc2013-04-04 15:13:41 +0300201
202 ecobits = I915_READ(GAC_ECO_BITS);
203 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
204
Ville Syrjäläa6f429a2013-04-04 15:13:42 +0300205 ecochk = I915_READ(GAM_ECOCHK);
206 if (IS_HASWELL(dev)) {
207 ecochk |= ECOCHK_PPGTT_WB_HSW;
208 } else {
209 ecochk |= ECOCHK_PPGTT_LLC_IVB;
210 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
211 }
212 I915_WRITE(GAM_ECOCHK, ecochk);
Ben Widawsky61973492013-04-08 18:43:54 -0700213 /* GFX_MODE is per-ring on gen7+ */
214 }
215
216 for_each_ring(ring, dev_priv, i) {
217 if (INTEL_INFO(dev)->gen >= 7)
218 I915_WRITE(RING_MODE_GEN7(ring),
219 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
220
221 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
222 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
223 }
Ben Widawskyb7c36d22013-04-08 18:43:56 -0700224 return 0;
Ben Widawsky61973492013-04-08 18:43:54 -0700225}
226
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100227/* PPGTT support for Sandybdrige/Gen6 and later */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700228static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100229 unsigned first_entry,
230 unsigned num_entries)
231{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700232 struct i915_hw_ppgtt *ppgtt =
233 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawskye7c2b582013-04-08 18:43:48 -0700234 gen6_gtt_pte_t *pt_vaddr, scratch_pte;
Daniel Vettera15326a2013-03-19 23:48:39 +0100235 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
Daniel Vetter7bddb012012-02-09 17:15:47 +0100236 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
237 unsigned last_pte, i;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100238
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700239 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100240
Daniel Vetter7bddb012012-02-09 17:15:47 +0100241 while (num_entries) {
242 last_pte = first_pte + num_entries;
243 if (last_pte > I915_PPGTT_PT_ENTRIES)
244 last_pte = I915_PPGTT_PT_ENTRIES;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100245
Daniel Vettera15326a2013-03-19 23:48:39 +0100246 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
Daniel Vetter7bddb012012-02-09 17:15:47 +0100247
248 for (i = first_pte; i < last_pte; i++)
249 pt_vaddr[i] = scratch_pte;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100250
251 kunmap_atomic(pt_vaddr);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100252
Daniel Vetter7bddb012012-02-09 17:15:47 +0100253 num_entries -= last_pte - first_pte;
254 first_pte = 0;
Daniel Vettera15326a2013-03-19 23:48:39 +0100255 act_pt++;
Daniel Vetter7bddb012012-02-09 17:15:47 +0100256 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100257}
258
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700259static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
Daniel Vetterdef886c2013-01-24 14:44:56 -0800260 struct sg_table *pages,
261 unsigned first_entry,
262 enum i915_cache_level cache_level)
263{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700264 struct i915_hw_ppgtt *ppgtt =
265 container_of(vm, struct i915_hw_ppgtt, base);
Ben Widawskye7c2b582013-04-08 18:43:48 -0700266 gen6_gtt_pte_t *pt_vaddr;
Daniel Vettera15326a2013-03-19 23:48:39 +0100267 unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
Imre Deak6e995e22013-02-18 19:28:04 +0200268 unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
269 struct sg_page_iter sg_iter;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800270
Daniel Vettera15326a2013-03-19 23:48:39 +0100271 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
Imre Deak6e995e22013-02-18 19:28:04 +0200272 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
273 dma_addr_t page_addr;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800274
Imre Deak2db76d72013-03-26 15:14:18 +0200275 page_addr = sg_page_iter_dma_address(&sg_iter);
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700276 pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level);
Imre Deak6e995e22013-02-18 19:28:04 +0200277 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
278 kunmap_atomic(pt_vaddr);
Daniel Vettera15326a2013-03-19 23:48:39 +0100279 act_pt++;
280 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
Imre Deak6e995e22013-02-18 19:28:04 +0200281 act_pte = 0;
Daniel Vetterdef886c2013-01-24 14:44:56 -0800282
Daniel Vetterdef886c2013-01-24 14:44:56 -0800283 }
Daniel Vetterdef886c2013-01-24 14:44:56 -0800284 }
Imre Deak6e995e22013-02-18 19:28:04 +0200285 kunmap_atomic(pt_vaddr);
Daniel Vetterdef886c2013-01-24 14:44:56 -0800286}
287
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700288static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100289{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700290 struct i915_hw_ppgtt *ppgtt =
291 container_of(vm, struct i915_hw_ppgtt, base);
Daniel Vetter3440d262013-01-24 13:49:56 -0800292 int i;
293
Ben Widawsky93bd8642013-07-16 16:50:06 -0700294 drm_mm_takedown(&ppgtt->base.mm);
295
Daniel Vetter3440d262013-01-24 13:49:56 -0800296 if (ppgtt->pt_dma_addr) {
297 for (i = 0; i < ppgtt->num_pd_entries; i++)
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700298 pci_unmap_page(ppgtt->base.dev->pdev,
Daniel Vetter3440d262013-01-24 13:49:56 -0800299 ppgtt->pt_dma_addr[i],
300 4096, PCI_DMA_BIDIRECTIONAL);
301 }
302
303 kfree(ppgtt->pt_dma_addr);
304 for (i = 0; i < ppgtt->num_pd_entries; i++)
305 __free_page(ppgtt->pt_pages[i]);
306 kfree(ppgtt->pt_pages);
307 kfree(ppgtt);
308}
309
310static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
311{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700312 struct drm_device *dev = ppgtt->base.dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100313 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100314 unsigned first_pd_entry_in_global_pt;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100315 int i;
316 int ret = -ENOMEM;
317
318 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
319 * entries. For aliasing ppgtt support we just steal them at the end for
320 * now. */
Daniel Vettere1b73cb2013-05-21 09:52:16 +0200321 first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100322
Chris Wilson08c45262013-07-30 19:04:37 +0100323 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
Ben Widawsky6670a5a2013-06-27 16:30:04 -0700324 ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
Ben Widawsky61973492013-04-08 18:43:54 -0700325 ppgtt->enable = gen6_ppgtt_enable;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700326 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
327 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
328 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
329 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100330 ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
331 GFP_KERNEL);
332 if (!ppgtt->pt_pages)
Daniel Vetter3440d262013-01-24 13:49:56 -0800333 return -ENOMEM;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100334
335 for (i = 0; i < ppgtt->num_pd_entries; i++) {
336 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
337 if (!ppgtt->pt_pages[i])
338 goto err_pt_alloc;
339 }
340
Ben Widawsky8d2e6302013-01-18 12:30:33 -0800341 ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
342 GFP_KERNEL);
343 if (!ppgtt->pt_dma_addr)
344 goto err_pt_alloc;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100345
Ben Widawsky8d2e6302013-01-18 12:30:33 -0800346 for (i = 0; i < ppgtt->num_pd_entries; i++) {
347 dma_addr_t pt_addr;
Daniel Vetter211c5682012-04-10 17:29:17 +0200348
Ben Widawsky8d2e6302013-01-18 12:30:33 -0800349 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
350 PCI_DMA_BIDIRECTIONAL);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100351
Ben Widawsky8d2e6302013-01-18 12:30:33 -0800352 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
353 ret = -EIO;
354 goto err_pd_pin;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100355
Daniel Vetter211c5682012-04-10 17:29:17 +0200356 }
Ben Widawsky8d2e6302013-01-18 12:30:33 -0800357 ppgtt->pt_dma_addr[i] = pt_addr;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100358 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100359
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700360 ppgtt->base.clear_range(&ppgtt->base, 0,
361 ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100362
Ben Widawskye7c2b582013-04-08 18:43:48 -0700363 ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100364
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100365 return 0;
366
367err_pd_pin:
368 if (ppgtt->pt_dma_addr) {
369 for (i--; i >= 0; i--)
370 pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
371 4096, PCI_DMA_BIDIRECTIONAL);
372 }
373err_pt_alloc:
374 kfree(ppgtt->pt_dma_addr);
375 for (i = 0; i < ppgtt->num_pd_entries; i++) {
376 if (ppgtt->pt_pages[i])
377 __free_page(ppgtt->pt_pages[i]);
378 }
379 kfree(ppgtt->pt_pages);
Daniel Vetter3440d262013-01-24 13:49:56 -0800380
381 return ret;
382}
383
384static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
385{
386 struct drm_i915_private *dev_priv = dev->dev_private;
387 struct i915_hw_ppgtt *ppgtt;
388 int ret;
389
390 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
391 if (!ppgtt)
392 return -ENOMEM;
393
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700394 ppgtt->base.dev = dev;
Daniel Vetter3440d262013-01-24 13:49:56 -0800395
Ben Widawsky3ed124b2013-04-08 18:43:53 -0700396 if (INTEL_INFO(dev)->gen < 8)
397 ret = gen6_ppgtt_init(ppgtt);
398 else
399 BUG();
400
Daniel Vetter3440d262013-01-24 13:49:56 -0800401 if (ret)
402 kfree(ppgtt);
Ben Widawsky93bd8642013-07-16 16:50:06 -0700403 else {
Daniel Vetter3440d262013-01-24 13:49:56 -0800404 dev_priv->mm.aliasing_ppgtt = ppgtt;
Ben Widawsky93bd8642013-07-16 16:50:06 -0700405 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
406 ppgtt->base.total);
407 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100408
409 return ret;
410}
411
412void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100416
417 if (!ppgtt)
418 return;
419
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700420 ppgtt->base.cleanup(&ppgtt->base);
Ben Widawsky5963cf02013-04-08 18:43:55 -0700421 dev_priv->mm.aliasing_ppgtt = NULL;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100422}
423
Daniel Vetter7bddb012012-02-09 17:15:47 +0100424void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
425 struct drm_i915_gem_object *obj,
426 enum i915_cache_level cache_level)
427{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700428 ppgtt->base.insert_entries(&ppgtt->base, obj->pages,
429 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
430 cache_level);
Daniel Vetter7bddb012012-02-09 17:15:47 +0100431}
432
433void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
434 struct drm_i915_gem_object *obj)
435{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700436 ppgtt->base.clear_range(&ppgtt->base,
437 i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
438 obj->base.size >> PAGE_SHIFT);
Daniel Vetter7bddb012012-02-09 17:15:47 +0100439}
440
Ben Widawskya81cc002013-01-18 12:30:31 -0800441extern int intel_iommu_gfx_mapped;
442/* Certain Gen5 chipsets require require idling the GPU before
443 * unmapping anything from the GTT when VT-d is enabled.
444 */
445static inline bool needs_idle_maps(struct drm_device *dev)
446{
447#ifdef CONFIG_INTEL_IOMMU
448 /* Query intel_iommu to see if we need the workaround. Presumably that
449 * was loaded first.
450 */
451 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
452 return true;
453#endif
454 return false;
455}
456
Ben Widawsky5c042282011-10-17 15:51:55 -0700457static bool do_idling(struct drm_i915_private *dev_priv)
458{
459 bool ret = dev_priv->mm.interruptible;
460
Ben Widawskya81cc002013-01-18 12:30:31 -0800461 if (unlikely(dev_priv->gtt.do_idle_maps)) {
Ben Widawsky5c042282011-10-17 15:51:55 -0700462 dev_priv->mm.interruptible = false;
Ben Widawskyb2da9fe2012-04-26 16:02:58 -0700463 if (i915_gpu_idle(dev_priv->dev)) {
Ben Widawsky5c042282011-10-17 15:51:55 -0700464 DRM_ERROR("Couldn't idle GPU\n");
465 /* Wait a bit, in hopes it avoids the hang */
466 udelay(10);
467 }
468 }
469
470 return ret;
471}
472
473static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
474{
Ben Widawskya81cc002013-01-18 12:30:31 -0800475 if (unlikely(dev_priv->gtt.do_idle_maps))
Ben Widawsky5c042282011-10-17 15:51:55 -0700476 dev_priv->mm.interruptible = interruptible;
477}
478
Daniel Vetter76aaf222010-11-05 22:23:30 +0100479void i915_gem_restore_gtt_mappings(struct drm_device *dev)
480{
481 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +0000482 struct drm_i915_gem_object *obj;
Daniel Vetter76aaf222010-11-05 22:23:30 +0100483
Chris Wilsonbee4a182011-01-21 10:54:32 +0000484 /* First fill our portion of the GTT with scratch pages */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700485 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
486 dev_priv->gtt.base.start / PAGE_SIZE,
487 dev_priv->gtt.base.total / PAGE_SIZE);
Chris Wilsonbee4a182011-01-21 10:54:32 +0000488
Ben Widawsky35c20a62013-05-31 11:28:48 -0700489 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilsona8e93122010-12-08 14:28:54 +0000490 i915_gem_clflush_object(obj);
Daniel Vetter74163902012-02-15 23:50:21 +0100491 i915_gem_gtt_bind_object(obj, obj->cache_level);
Daniel Vetter76aaf222010-11-05 22:23:30 +0100492 }
493
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800494 i915_gem_chipset_flush(dev);
Daniel Vetter76aaf222010-11-05 22:23:30 +0100495}
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100496
Daniel Vetter74163902012-02-15 23:50:21 +0100497int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100498{
Chris Wilson9da3da62012-06-01 15:20:22 +0100499 if (obj->has_dma_mapping)
Daniel Vetter74163902012-02-15 23:50:21 +0100500 return 0;
Chris Wilson9da3da62012-06-01 15:20:22 +0100501
502 if (!dma_map_sg(&obj->base.dev->pdev->dev,
503 obj->pages->sgl, obj->pages->nents,
504 PCI_DMA_BIDIRECTIONAL))
505 return -ENOSPC;
506
507 return 0;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100508}
509
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800510/*
511 * Binds an object into the global gtt with the specified cache level. The object
512 * will be accessible to the GPU via commands whose operands reference offsets
513 * within the global GTT as well as accessible by the GPU through the GMADR
514 * mapped BAR (dev_priv->mm.gtt->gtt).
515 */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700516static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800517 struct sg_table *st,
518 unsigned int first_entry,
519 enum i915_cache_level level)
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800520{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700521 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawskye7c2b582013-04-08 18:43:48 -0700522 gen6_gtt_pte_t __iomem *gtt_entries =
523 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Imre Deak6e995e22013-02-18 19:28:04 +0200524 int i = 0;
525 struct sg_page_iter sg_iter;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800526 dma_addr_t addr;
527
Imre Deak6e995e22013-02-18 19:28:04 +0200528 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
Imre Deak2db76d72013-03-26 15:14:18 +0200529 addr = sg_page_iter_dma_address(&sg_iter);
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700530 iowrite32(vm->pte_encode(addr, level), &gtt_entries[i]);
Imre Deak6e995e22013-02-18 19:28:04 +0200531 i++;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800532 }
533
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800534 /* XXX: This serves as a posting read to make sure that the PTE has
535 * actually been updated. There is some concern that even though
536 * registers and PTEs are within the same BAR that they are potentially
537 * of NUMA access patterns. Therefore, even with the way we assume
538 * hardware should work, we must keep this posting read for paranoia.
539 */
540 if (i != 0)
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700541 WARN_ON(readl(&gtt_entries[i-1]) !=
542 vm->pte_encode(addr, level));
Ben Widawsky0f9b91c2012-11-04 09:21:30 -0800543
544 /* This next bit makes the above posting read even more important. We
545 * want to flush the TLBs only after we're certain all the PTE updates
546 * have finished.
547 */
548 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
549 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800550}
551
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700552static void gen6_ggtt_clear_range(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800553 unsigned int first_entry,
554 unsigned int num_entries)
555{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700556 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawskye7c2b582013-04-08 18:43:48 -0700557 gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
558 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawskya54c0c22013-01-24 14:45:00 -0800559 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800560 int i;
561
562 if (WARN(num_entries > max_entries,
563 "First entry = %d; Num entries = %d (max=%d)\n",
564 first_entry, num_entries, max_entries))
565 num_entries = max_entries;
566
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700567 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800568 for (i = 0; i < num_entries; i++)
569 iowrite32(scratch_pte, &gtt_base[i]);
570 readl(gtt_base);
571}
572
573
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700574static void i915_ggtt_insert_entries(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800575 struct sg_table *st,
576 unsigned int pg_start,
577 enum i915_cache_level cache_level)
578{
579 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
580 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
581
582 intel_gtt_insert_sg_entries(st, pg_start, flags);
583
584}
585
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700586static void i915_ggtt_clear_range(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800587 unsigned int first_entry,
588 unsigned int num_entries)
589{
590 intel_gtt_clear_range(first_entry, num_entries);
591}
592
593
Daniel Vetter74163902012-02-15 23:50:21 +0100594void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
595 enum i915_cache_level cache_level)
Chris Wilsond5bd1442011-04-14 06:48:26 +0100596{
597 struct drm_device *dev = obj->base.dev;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800598 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700599 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800600
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700601 dev_priv->gtt.base.insert_entries(&dev_priv->gtt.base, obj->pages,
602 entry,
603 cache_level);
Chris Wilsond5bd1442011-04-14 06:48:26 +0100604
Daniel Vetter74898d72012-02-15 23:50:22 +0100605 obj->has_global_gtt_mapping = 1;
Chris Wilsond5bd1442011-04-14 06:48:26 +0100606}
607
Chris Wilson05394f32010-11-08 19:18:58 +0000608void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100609{
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800610 struct drm_device *dev = obj->base.dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700612 const unsigned long entry = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800613
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700614 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
615 entry,
616 obj->base.size >> PAGE_SHIFT);
Daniel Vetter74898d72012-02-15 23:50:22 +0100617
618 obj->has_global_gtt_mapping = 0;
Daniel Vetter74163902012-02-15 23:50:21 +0100619}
620
621void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
622{
Ben Widawsky5c042282011-10-17 15:51:55 -0700623 struct drm_device *dev = obj->base.dev;
624 struct drm_i915_private *dev_priv = dev->dev_private;
625 bool interruptible;
626
627 interruptible = do_idling(dev_priv);
628
Chris Wilson9da3da62012-06-01 15:20:22 +0100629 if (!obj->has_dma_mapping)
630 dma_unmap_sg(&dev->pdev->dev,
631 obj->pages->sgl, obj->pages->nents,
632 PCI_DMA_BIDIRECTIONAL);
Ben Widawsky5c042282011-10-17 15:51:55 -0700633
634 undo_idling(dev_priv, interruptible);
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +0100635}
Daniel Vetter644ec022012-03-26 09:45:40 +0200636
Chris Wilson42d6ab42012-07-26 11:49:32 +0100637static void i915_gtt_color_adjust(struct drm_mm_node *node,
638 unsigned long color,
639 unsigned long *start,
640 unsigned long *end)
641{
642 if (node->color != color)
643 *start += 4096;
644
645 if (!list_empty(&node->node_list)) {
646 node = list_entry(node->node_list.next,
647 struct drm_mm_node,
648 node_list);
649 if (node->allocated && node->color != color)
650 *end -= 4096;
651 }
652}
Ben Widawskyd7e50082012-12-18 10:31:25 -0800653void i915_gem_setup_global_gtt(struct drm_device *dev,
654 unsigned long start,
655 unsigned long mappable_end,
656 unsigned long end)
Daniel Vetter644ec022012-03-26 09:45:40 +0200657{
Ben Widawskye78891c2013-01-25 16:41:04 -0800658 /* Let GEM Manage all of the aperture.
659 *
660 * However, leave one page at the end still bound to the scratch page.
661 * There are a number of places where the hardware apparently prefetches
662 * past the end of the object, and we've seen multiple hangs with the
663 * GPU head pointer stuck in a batchbuffer bound at the last page of the
664 * aperture. One page should be enough to keep any prefetching inside
665 * of the aperture.
666 */
Ben Widawsky40d749802013-07-31 16:59:59 -0700667 struct drm_i915_private *dev_priv = dev->dev_private;
668 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
Chris Wilsoned2f3452012-11-15 11:32:19 +0000669 struct drm_mm_node *entry;
670 struct drm_i915_gem_object *obj;
671 unsigned long hole_start, hole_end;
Daniel Vetter644ec022012-03-26 09:45:40 +0200672
Ben Widawsky35451cb2013-01-17 12:45:13 -0800673 BUG_ON(mappable_end > end);
674
Chris Wilsoned2f3452012-11-15 11:32:19 +0000675 /* Subtract the guard page ... */
Ben Widawsky40d749802013-07-31 16:59:59 -0700676 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
Chris Wilson42d6ab42012-07-26 11:49:32 +0100677 if (!HAS_LLC(dev))
Ben Widawsky93bd8642013-07-16 16:50:06 -0700678 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
Daniel Vetter644ec022012-03-26 09:45:40 +0200679
Chris Wilsoned2f3452012-11-15 11:32:19 +0000680 /* Mark any preallocated objects as occupied */
Ben Widawsky35c20a62013-05-31 11:28:48 -0700681 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawsky40d749802013-07-31 16:59:59 -0700682 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
Ben Widawskyb3a070c2013-07-05 14:41:02 -0700683 int ret;
Ben Widawskyedd41a82013-07-05 14:41:05 -0700684 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
Ben Widawskyc6cfb322013-07-05 14:41:06 -0700685 i915_gem_obj_ggtt_offset(obj), obj->base.size);
Chris Wilsoned2f3452012-11-15 11:32:19 +0000686
Ben Widawskyc6cfb322013-07-05 14:41:06 -0700687 WARN_ON(i915_gem_obj_ggtt_bound(obj));
Ben Widawsky40d749802013-07-31 16:59:59 -0700688 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
Ben Widawskyc6cfb322013-07-05 14:41:06 -0700689 if (ret)
Ben Widawskyb3a070c2013-07-05 14:41:02 -0700690 DRM_DEBUG_KMS("Reservation failed\n");
Chris Wilsoned2f3452012-11-15 11:32:19 +0000691 obj->has_global_gtt_mapping = 1;
Ben Widawsky2f633152013-07-17 12:19:03 -0700692 list_add(&vma->vma_link, &obj->vma_list);
Chris Wilsoned2f3452012-11-15 11:32:19 +0000693 }
694
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700695 dev_priv->gtt.base.start = start;
696 dev_priv->gtt.base.total = end - start;
Daniel Vetter644ec022012-03-26 09:45:40 +0200697
Chris Wilsoned2f3452012-11-15 11:32:19 +0000698 /* Clear any non-preallocated blocks */
Ben Widawsky40d749802013-07-31 16:59:59 -0700699 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700700 const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
Chris Wilsoned2f3452012-11-15 11:32:19 +0000701 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
702 hole_start, hole_end);
Ben Widawsky40d749802013-07-31 16:59:59 -0700703 ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
Chris Wilsoned2f3452012-11-15 11:32:19 +0000704 }
705
706 /* And finally clear the reserved guard page */
Ben Widawsky40d749802013-07-31 16:59:59 -0700707 ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1);
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800708}
709
Ben Widawskyd7e50082012-12-18 10:31:25 -0800710static bool
711intel_enable_ppgtt(struct drm_device *dev)
712{
713 if (i915_enable_ppgtt >= 0)
714 return i915_enable_ppgtt;
715
716#ifdef CONFIG_INTEL_IOMMU
717 /* Disable ppgtt on SNB if VT-d is on. */
718 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
719 return false;
720#endif
721
722 return true;
723}
724
725void i915_gem_init_global_gtt(struct drm_device *dev)
726{
727 struct drm_i915_private *dev_priv = dev->dev_private;
728 unsigned long gtt_size, mappable_size;
Ben Widawskyd7e50082012-12-18 10:31:25 -0800729
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700730 gtt_size = dev_priv->gtt.base.total;
Ben Widawsky93d18792013-01-17 12:45:17 -0800731 mappable_size = dev_priv->gtt.mappable_end;
Ben Widawskyd7e50082012-12-18 10:31:25 -0800732
733 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
Ben Widawskye78891c2013-01-25 16:41:04 -0800734 int ret;
Ben Widawsky3eb1c002013-04-08 18:43:52 -0700735
736 if (INTEL_INFO(dev)->gen <= 7) {
737 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
738 * aperture accordingly when using aliasing ppgtt. */
Ben Widawsky6670a5a2013-06-27 16:30:04 -0700739 gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
Ben Widawsky3eb1c002013-04-08 18:43:52 -0700740 }
Ben Widawskyd7e50082012-12-18 10:31:25 -0800741
742 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
743
744 ret = i915_gem_init_aliasing_ppgtt(dev);
Ben Widawskye78891c2013-01-25 16:41:04 -0800745 if (!ret)
Ben Widawskyd7e50082012-12-18 10:31:25 -0800746 return;
Ben Widawskye78891c2013-01-25 16:41:04 -0800747
748 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
Ben Widawsky93bd8642013-07-16 16:50:06 -0700749 drm_mm_takedown(&dev_priv->gtt.base.mm);
Ben Widawsky6670a5a2013-06-27 16:30:04 -0700750 gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE;
Ben Widawskyd7e50082012-12-18 10:31:25 -0800751 }
Ben Widawskye78891c2013-01-25 16:41:04 -0800752 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800753}
754
755static int setup_scratch_page(struct drm_device *dev)
756{
757 struct drm_i915_private *dev_priv = dev->dev_private;
758 struct page *page;
759 dma_addr_t dma_addr;
760
761 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
762 if (page == NULL)
763 return -ENOMEM;
764 get_page(page);
765 set_pages_uc(page, 1);
766
767#ifdef CONFIG_INTEL_IOMMU
768 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
769 PCI_DMA_BIDIRECTIONAL);
770 if (pci_dma_mapping_error(dev->pdev, dma_addr))
771 return -EINVAL;
772#else
773 dma_addr = page_to_phys(page);
774#endif
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700775 dev_priv->gtt.base.scratch.page = page;
776 dev_priv->gtt.base.scratch.addr = dma_addr;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800777
778 return 0;
779}
780
781static void teardown_scratch_page(struct drm_device *dev)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700784 struct page *page = dev_priv->gtt.base.scratch.page;
785
786 set_pages_wb(page, 1);
787 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800788 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700789 put_page(page);
790 __free_page(page);
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800791}
792
793static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
794{
795 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
796 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
797 return snb_gmch_ctl << 20;
798}
799
Ben Widawskybaa09f52013-01-24 13:49:57 -0800800static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800801{
802 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
803 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
804 return snb_gmch_ctl << 25; /* 32 MB units */
805}
806
Ben Widawskybaa09f52013-01-24 13:49:57 -0800807static int gen6_gmch_probe(struct drm_device *dev,
808 size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -0800809 size_t *stolen,
810 phys_addr_t *mappable_base,
811 unsigned long *mappable_end)
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 phys_addr_t gtt_bus_addr;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800815 unsigned int gtt_size;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800816 u16 snb_gmch_ctl;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800817 int ret;
818
Ben Widawsky41907dd2013-02-08 11:32:47 -0800819 *mappable_base = pci_resource_start(dev->pdev, 2);
820 *mappable_end = pci_resource_len(dev->pdev, 2);
821
Ben Widawskybaa09f52013-01-24 13:49:57 -0800822 /* 64/512MB is the current min/max we actually know of, but this is just
823 * a coarse sanity check.
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800824 */
Ben Widawsky41907dd2013-02-08 11:32:47 -0800825 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
Ben Widawskybaa09f52013-01-24 13:49:57 -0800826 DRM_ERROR("Unknown GMADR size (%lx)\n",
827 dev_priv->gtt.mappable_end);
828 return -ENXIO;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800829 }
830
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800831 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
832 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
Ben Widawskybaa09f52013-01-24 13:49:57 -0800833 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
834 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
835
Ben Widawskyc4ae25e2013-05-01 11:00:34 -0700836 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
Ben Widawskye7c2b582013-04-08 18:43:48 -0700837 *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800838
Ben Widawskya93e4162013-04-08 18:43:47 -0700839 /* For Modern GENs the PTEs and register space are split in the BAR */
840 gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
841 (pci_resource_len(dev->pdev, 0) / 2);
842
Ben Widawskybaa09f52013-01-24 13:49:57 -0800843 dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
844 if (!dev_priv->gtt.gsm) {
845 DRM_ERROR("Failed to map the gtt page table\n");
846 return -ENOMEM;
847 }
848
849 ret = setup_scratch_page(dev);
850 if (ret)
851 DRM_ERROR("Scratch setup failed\n");
852
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700853 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
854 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800855
856 return ret;
857}
858
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700859static void gen6_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -0800860{
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700861
862 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
863 iounmap(gtt->gsm);
864 teardown_scratch_page(vm->dev);
Ben Widawskybaa09f52013-01-24 13:49:57 -0800865}
866
867static int i915_gmch_probe(struct drm_device *dev,
868 size_t *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -0800869 size_t *stolen,
870 phys_addr_t *mappable_base,
871 unsigned long *mappable_end)
Ben Widawskybaa09f52013-01-24 13:49:57 -0800872{
873 struct drm_i915_private *dev_priv = dev->dev_private;
874 int ret;
875
Ben Widawskybaa09f52013-01-24 13:49:57 -0800876 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
877 if (!ret) {
878 DRM_ERROR("failed to set up gmch\n");
879 return -EIO;
880 }
881
Ben Widawsky41907dd2013-02-08 11:32:47 -0800882 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -0800883
884 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700885 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
886 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800887
888 return 0;
889}
890
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700891static void i915_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -0800892{
893 intel_gmch_remove();
894}
895
896int i915_gem_gtt_init(struct drm_device *dev)
897{
898 struct drm_i915_private *dev_priv = dev->dev_private;
899 struct i915_gtt *gtt = &dev_priv->gtt;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800900 int ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800901
Ben Widawskybaa09f52013-01-24 13:49:57 -0800902 if (INTEL_INFO(dev)->gen <= 5) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700903 gtt->gtt_probe = i915_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700904 gtt->base.cleanup = i915_gmch_remove;
Ben Widawskybaa09f52013-01-24 13:49:57 -0800905 } else {
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700906 gtt->gtt_probe = gen6_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700907 gtt->base.cleanup = gen6_gmch_remove;
Ben Widawsky4d15c142013-07-04 11:02:06 -0700908 if (IS_HASWELL(dev) && dev_priv->ellc_size)
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700909 gtt->base.pte_encode = iris_pte_encode;
Ben Widawsky4d15c142013-07-04 11:02:06 -0700910 else if (IS_HASWELL(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700911 gtt->base.pte_encode = hsw_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700912 else if (IS_VALLEYVIEW(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700913 gtt->base.pte_encode = byt_pte_encode;
Chris Wilson350ec882013-08-06 13:17:02 +0100914 else if (INTEL_INFO(dev)->gen >= 7)
915 gtt->base.pte_encode = ivb_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700916 else
Chris Wilson350ec882013-08-06 13:17:02 +0100917 gtt->base.pte_encode = snb_pte_encode;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800918 }
919
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700920 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700921 &gtt->mappable_base, &gtt->mappable_end);
Ben Widawskya54c0c22013-01-24 14:45:00 -0800922 if (ret)
Ben Widawskybaa09f52013-01-24 13:49:57 -0800923 return ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800924
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700925 gtt->base.dev = dev;
926
Ben Widawskybaa09f52013-01-24 13:49:57 -0800927 /* GMADR is the PCI mmio aperture into the global GTT. */
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700928 DRM_INFO("Memory usable by graphics device = %zdM\n",
929 gtt->base.total >> 20);
Ben Widawskyb2f21b42013-06-27 16:30:20 -0700930 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
931 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -0800932
Ben Widawskye76e9ae2012-11-04 09:21:27 -0800933 return 0;
Daniel Vetter644ec022012-03-26 09:45:40 +0200934}