Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "drm_crtc_helper.h" |
| 28 | #include "radeon_drm.h" |
| 29 | #include "radeon.h" |
| 30 | #include "atom.h" |
| 31 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 32 | static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) |
| 33 | { |
| 34 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 35 | struct drm_encoder_helper_funcs *encoder_funcs; |
| 36 | |
| 37 | encoder_funcs = encoder->helper_private; |
| 38 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); |
| 39 | radeon_encoder->active_device = 0; |
| 40 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 41 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 42 | static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) |
| 43 | { |
| 44 | struct drm_device *dev = encoder->dev; |
| 45 | struct radeon_device *rdev = dev->dev_private; |
| 46 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 47 | uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; |
| 48 | int panel_pwr_delay = 2000; |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 49 | bool is_mac = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 50 | DRM_DEBUG("\n"); |
| 51 | |
| 52 | if (radeon_encoder->enc_priv) { |
| 53 | if (rdev->is_atom_bios) { |
| 54 | struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; |
| 55 | panel_pwr_delay = lvds->panel_pwr_delay; |
| 56 | } else { |
| 57 | struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; |
| 58 | panel_pwr_delay = lvds->panel_pwr_delay; |
| 59 | } |
| 60 | } |
| 61 | |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 62 | /* macs (and possibly some x86 oem systems?) wire up LVDS strangely |
| 63 | * Taken from radeonfb. |
| 64 | */ |
| 65 | if ((rdev->mode_info.connector_table == CT_IBOOK) || |
| 66 | (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || |
| 67 | (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || |
| 68 | (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) |
| 69 | is_mac = true; |
| 70 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | switch (mode) { |
| 72 | case DRM_MODE_DPMS_ON: |
| 73 | disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); |
| 74 | disp_pwr_man |= RADEON_AUTO_PWRUP_EN; |
| 75 | WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); |
| 76 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 77 | lvds_pll_cntl |= RADEON_LVDS_PLL_EN; |
| 78 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
| 79 | udelay(1000); |
| 80 | |
| 81 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 82 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; |
| 83 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
| 84 | |
| 85 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 86 | lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 87 | if (is_mac) |
| 88 | lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); |
| 90 | udelay(panel_pwr_delay * 1000); |
| 91 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 92 | break; |
| 93 | case DRM_MODE_DPMS_STANDBY: |
| 94 | case DRM_MODE_DPMS_SUSPEND: |
| 95 | case DRM_MODE_DPMS_OFF: |
| 96 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 97 | WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); |
| 98 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 99 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
Alex Deucher | 3890ddf | 2010-01-12 11:16:57 -0500 | [diff] [blame] | 100 | if (is_mac) { |
| 101 | lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; |
| 102 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 103 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); |
| 104 | } else { |
| 105 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 106 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); |
| 107 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | udelay(panel_pwr_delay * 1000); |
| 109 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 110 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
| 111 | break; |
| 112 | } |
| 113 | |
| 114 | if (rdev->is_atom_bios) |
| 115 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 116 | else |
| 117 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 118 | |
| 119 | /* adjust pm to dpms change */ |
| 120 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) |
| 124 | { |
| 125 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 126 | |
| 127 | if (rdev->is_atom_bios) |
| 128 | radeon_atom_output_lock(encoder, true); |
| 129 | else |
| 130 | radeon_combios_output_lock(encoder, true); |
| 131 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 132 | } |
| 133 | |
| 134 | static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) |
| 135 | { |
| 136 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 137 | |
| 138 | radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); |
| 139 | if (rdev->is_atom_bios) |
| 140 | radeon_atom_output_lock(encoder, false); |
| 141 | else |
| 142 | radeon_combios_output_lock(encoder, false); |
| 143 | } |
| 144 | |
| 145 | static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, |
| 146 | struct drm_display_mode *mode, |
| 147 | struct drm_display_mode *adjusted_mode) |
| 148 | { |
| 149 | struct drm_device *dev = encoder->dev; |
| 150 | struct radeon_device *rdev = dev->dev_private; |
| 151 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 152 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 153 | uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; |
| 154 | |
| 155 | DRM_DEBUG("\n"); |
| 156 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); |
| 158 | lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; |
| 159 | |
| 160 | lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); |
Alex Deucher | 32f48ff | 2009-11-30 01:54:16 -0500 | [diff] [blame] | 161 | if (rdev->is_atom_bios) { |
| 162 | /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl |
| 163 | * need to call that on resume to set up the reg properly. |
| 164 | */ |
| 165 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 166 | atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); |
| 167 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
| 168 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; |
| 170 | if (lvds) { |
| 171 | DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); |
| 172 | lvds_gen_cntl = lvds->lvds_gen_cntl; |
| 173 | lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
| 174 | (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
| 175 | lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | |
| 176 | (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); |
| 177 | } else |
| 178 | lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); |
Alex Deucher | 32f48ff | 2009-11-30 01:54:16 -0500 | [diff] [blame] | 179 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 180 | lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; |
| 181 | lvds_gen_cntl &= ~(RADEON_LVDS_ON | |
| 182 | RADEON_LVDS_BLON | |
| 183 | RADEON_LVDS_EN | |
| 184 | RADEON_LVDS_RST_FM); |
| 185 | |
| 186 | if (ASIC_IS_R300(rdev)) |
| 187 | lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); |
| 188 | |
| 189 | if (radeon_crtc->crtc_id == 0) { |
| 190 | if (ASIC_IS_R300(rdev)) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 191 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 192 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; |
| 193 | } else |
| 194 | lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; |
| 195 | } else { |
| 196 | if (ASIC_IS_R300(rdev)) |
| 197 | lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; |
| 198 | else |
| 199 | lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; |
| 200 | } |
| 201 | |
| 202 | WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); |
| 203 | WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); |
| 204 | WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); |
| 205 | |
| 206 | if (rdev->family == CHIP_RV410) |
| 207 | WREG32(RADEON_CLOCK_CNTL_INDEX, 0); |
| 208 | |
| 209 | if (rdev->is_atom_bios) |
| 210 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 211 | else |
| 212 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 213 | } |
| 214 | |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 215 | static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, |
| 216 | struct drm_display_mode *mode, |
| 217 | struct drm_display_mode *adjusted_mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 218 | { |
| 219 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 220 | struct drm_device *dev = encoder->dev; |
| 221 | struct radeon_device *rdev = dev->dev_private; |
| 222 | |
| 223 | /* adjust pm to upcoming mode change */ |
| 224 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 225 | |
Alex Deucher | 8c2a6d7 | 2009-10-14 02:00:42 -0400 | [diff] [blame] | 226 | /* set the active encoder to connector routing */ |
| 227 | radeon_encoder_set_active_device(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 228 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
| 229 | |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 230 | /* get the native mode for LVDS */ |
Alex Deucher | 3515387 | 2010-04-30 12:00:44 -0400 | [diff] [blame^] | 231 | if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) |
| 232 | radeon_panel_mode_fixup(encoder, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 233 | |
| 234 | return true; |
| 235 | } |
| 236 | |
| 237 | static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { |
| 238 | .dpms = radeon_legacy_lvds_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 239 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 240 | .prepare = radeon_legacy_lvds_prepare, |
| 241 | .mode_set = radeon_legacy_lvds_mode_set, |
| 242 | .commit = radeon_legacy_lvds_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 243 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 244 | }; |
| 245 | |
| 246 | |
| 247 | static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { |
| 248 | .destroy = radeon_enc_destroy, |
| 249 | }; |
| 250 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) |
| 252 | { |
| 253 | struct drm_device *dev = encoder->dev; |
| 254 | struct radeon_device *rdev = dev->dev_private; |
| 255 | uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| 256 | uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 257 | uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 258 | |
| 259 | DRM_DEBUG("\n"); |
| 260 | |
| 261 | switch (mode) { |
| 262 | case DRM_MODE_DPMS_ON: |
| 263 | crtc_ext_cntl |= RADEON_CRTC_CRT_ON; |
| 264 | dac_cntl &= ~RADEON_DAC_PDWN; |
| 265 | dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | |
| 266 | RADEON_DAC_PDWN_G | |
| 267 | RADEON_DAC_PDWN_B); |
| 268 | break; |
| 269 | case DRM_MODE_DPMS_STANDBY: |
| 270 | case DRM_MODE_DPMS_SUSPEND: |
| 271 | case DRM_MODE_DPMS_OFF: |
| 272 | crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; |
| 273 | dac_cntl |= RADEON_DAC_PDWN; |
| 274 | dac_macro_cntl |= (RADEON_DAC_PDWN_R | |
| 275 | RADEON_DAC_PDWN_G | |
| 276 | RADEON_DAC_PDWN_B); |
| 277 | break; |
| 278 | } |
| 279 | |
| 280 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| 281 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 282 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 283 | |
| 284 | if (rdev->is_atom_bios) |
| 285 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 286 | else |
| 287 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 288 | |
| 289 | /* adjust pm to dpms change */ |
| 290 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) |
| 294 | { |
| 295 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 296 | |
| 297 | if (rdev->is_atom_bios) |
| 298 | radeon_atom_output_lock(encoder, true); |
| 299 | else |
| 300 | radeon_combios_output_lock(encoder, true); |
| 301 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 302 | } |
| 303 | |
| 304 | static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) |
| 305 | { |
| 306 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 307 | |
| 308 | radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
| 309 | |
| 310 | if (rdev->is_atom_bios) |
| 311 | radeon_atom_output_lock(encoder, false); |
| 312 | else |
| 313 | radeon_combios_output_lock(encoder, false); |
| 314 | } |
| 315 | |
| 316 | static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, |
| 317 | struct drm_display_mode *mode, |
| 318 | struct drm_display_mode *adjusted_mode) |
| 319 | { |
| 320 | struct drm_device *dev = encoder->dev; |
| 321 | struct radeon_device *rdev = dev->dev_private; |
| 322 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 323 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 324 | uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; |
| 325 | |
| 326 | DRM_DEBUG("\n"); |
| 327 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 328 | if (radeon_crtc->crtc_id == 0) { |
| 329 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
| 330 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
| 331 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
| 332 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 333 | } else { |
| 334 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); |
| 335 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 336 | } |
| 337 | } else { |
| 338 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { |
| 339 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & |
| 340 | ~(RADEON_DISP_DAC_SOURCE_MASK); |
| 341 | disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; |
| 342 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 343 | } else { |
| 344 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; |
| 345 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | dac_cntl = (RADEON_DAC_MASK_ALL | |
| 350 | RADEON_DAC_VGA_ADR_EN | |
| 351 | /* TODO 6-bits */ |
| 352 | RADEON_DAC_8BIT_EN); |
| 353 | |
| 354 | WREG32_P(RADEON_DAC_CNTL, |
| 355 | dac_cntl, |
| 356 | RADEON_DAC_RANGE_CNTL | |
| 357 | RADEON_DAC_BLANKING); |
| 358 | |
| 359 | if (radeon_encoder->enc_priv) { |
| 360 | struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; |
| 361 | dac_macro_cntl = p_dac->ps2_pdac_adj; |
| 362 | } else |
| 363 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 364 | dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; |
| 365 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 366 | |
| 367 | if (rdev->is_atom_bios) |
| 368 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 369 | else |
| 370 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 371 | } |
| 372 | |
| 373 | static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, |
| 374 | struct drm_connector *connector) |
| 375 | { |
| 376 | struct drm_device *dev = encoder->dev; |
| 377 | struct radeon_device *rdev = dev->dev_private; |
| 378 | uint32_t vclk_ecp_cntl, crtc_ext_cntl; |
| 379 | uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; |
| 380 | enum drm_connector_status found = connector_status_disconnected; |
| 381 | bool color = true; |
| 382 | |
| 383 | /* save the regs we need */ |
| 384 | vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| 385 | crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| 386 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 387 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 388 | dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); |
| 389 | |
| 390 | tmp = vclk_ecp_cntl & |
| 391 | ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| 392 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| 393 | |
| 394 | tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; |
| 395 | WREG32(RADEON_CRTC_EXT_CNTL, tmp); |
| 396 | |
| 397 | tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | |
| 398 | RADEON_DAC_FORCE_DATA_EN; |
| 399 | |
| 400 | if (color) |
| 401 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
| 402 | else |
| 403 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
| 404 | |
| 405 | if (ASIC_IS_R300(rdev)) |
| 406 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 407 | else |
| 408 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 409 | |
| 410 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
| 411 | |
| 412 | tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); |
| 413 | tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; |
| 414 | WREG32(RADEON_DAC_CNTL, tmp); |
| 415 | |
| 416 | tmp &= ~(RADEON_DAC_PDWN_R | |
| 417 | RADEON_DAC_PDWN_G | |
| 418 | RADEON_DAC_PDWN_B); |
| 419 | |
| 420 | WREG32(RADEON_DAC_MACRO_CNTL, tmp); |
| 421 | |
| 422 | udelay(2000); |
| 423 | |
| 424 | if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) |
| 425 | found = connector_status_connected; |
| 426 | |
| 427 | /* restore the regs we used */ |
| 428 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 429 | WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); |
| 430 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 431 | WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| 432 | WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); |
| 433 | |
| 434 | return found; |
| 435 | } |
| 436 | |
| 437 | static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { |
| 438 | .dpms = radeon_legacy_primary_dac_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 439 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 440 | .prepare = radeon_legacy_primary_dac_prepare, |
| 441 | .mode_set = radeon_legacy_primary_dac_mode_set, |
| 442 | .commit = radeon_legacy_primary_dac_commit, |
| 443 | .detect = radeon_legacy_primary_dac_detect, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 444 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 445 | }; |
| 446 | |
| 447 | |
| 448 | static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { |
| 449 | .destroy = radeon_enc_destroy, |
| 450 | }; |
| 451 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 452 | static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) |
| 453 | { |
| 454 | struct drm_device *dev = encoder->dev; |
| 455 | struct radeon_device *rdev = dev->dev_private; |
| 456 | uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); |
| 457 | DRM_DEBUG("\n"); |
| 458 | |
| 459 | switch (mode) { |
| 460 | case DRM_MODE_DPMS_ON: |
| 461 | fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 462 | break; |
| 463 | case DRM_MODE_DPMS_STANDBY: |
| 464 | case DRM_MODE_DPMS_SUSPEND: |
| 465 | case DRM_MODE_DPMS_OFF: |
| 466 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 467 | break; |
| 468 | } |
| 469 | |
| 470 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
| 471 | |
| 472 | if (rdev->is_atom_bios) |
| 473 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 474 | else |
| 475 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 476 | |
| 477 | /* adjust pm to dpms change */ |
| 478 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) |
| 482 | { |
| 483 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 484 | |
| 485 | if (rdev->is_atom_bios) |
| 486 | radeon_atom_output_lock(encoder, true); |
| 487 | else |
| 488 | radeon_combios_output_lock(encoder, true); |
| 489 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 490 | } |
| 491 | |
| 492 | static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) |
| 493 | { |
| 494 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 495 | |
| 496 | radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); |
| 497 | |
| 498 | if (rdev->is_atom_bios) |
| 499 | radeon_atom_output_lock(encoder, true); |
| 500 | else |
| 501 | radeon_combios_output_lock(encoder, true); |
| 502 | } |
| 503 | |
| 504 | static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, |
| 505 | struct drm_display_mode *mode, |
| 506 | struct drm_display_mode *adjusted_mode) |
| 507 | { |
| 508 | struct drm_device *dev = encoder->dev; |
| 509 | struct radeon_device *rdev = dev->dev_private; |
| 510 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 511 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 512 | uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; |
| 513 | int i; |
| 514 | |
| 515 | DRM_DEBUG("\n"); |
| 516 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 517 | tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); |
| 518 | tmp &= 0xfffff; |
| 519 | if (rdev->family == CHIP_RV280) { |
| 520 | /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ |
| 521 | tmp ^= (1 << 22); |
| 522 | tmds_pll_cntl ^= (1 << 22); |
| 523 | } |
| 524 | |
| 525 | if (radeon_encoder->enc_priv) { |
| 526 | struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; |
| 527 | |
| 528 | for (i = 0; i < 4; i++) { |
| 529 | if (tmds->tmds_pll[i].freq == 0) |
| 530 | break; |
| 531 | if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { |
| 532 | tmp = tmds->tmds_pll[i].value ; |
| 533 | break; |
| 534 | } |
| 535 | } |
| 536 | } |
| 537 | |
| 538 | if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { |
| 539 | if (tmp & 0xfff00000) |
| 540 | tmds_pll_cntl = tmp; |
| 541 | else { |
| 542 | tmds_pll_cntl &= 0xfff00000; |
| 543 | tmds_pll_cntl |= tmp; |
| 544 | } |
| 545 | } else |
| 546 | tmds_pll_cntl = tmp; |
| 547 | |
| 548 | tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & |
| 549 | ~(RADEON_TMDS_TRANSMITTER_PLLRST); |
| 550 | |
| 551 | if (rdev->family == CHIP_R200 || |
| 552 | rdev->family == CHIP_R100 || |
| 553 | ASIC_IS_R300(rdev)) |
| 554 | tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); |
| 555 | else /* RV chips got this bit reversed */ |
| 556 | tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; |
| 557 | |
| 558 | fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | |
| 559 | (RADEON_FP_CRTC_DONT_SHADOW_VPAR | |
| 560 | RADEON_FP_CRTC_DONT_SHADOW_HEND)); |
| 561 | |
| 562 | fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); |
| 563 | |
Alex Deucher | 1b4d7d7 | 2009-10-15 01:33:35 -0400 | [diff] [blame] | 564 | fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | |
| 565 | RADEON_FP_DFP_SYNC_SEL | |
| 566 | RADEON_FP_CRT_SYNC_SEL | |
| 567 | RADEON_FP_CRTC_LOCK_8DOT | |
| 568 | RADEON_FP_USE_SHADOW_EN | |
| 569 | RADEON_FP_CRTC_USE_SHADOW_VEND | |
| 570 | RADEON_FP_CRT_SYNC_ALT); |
| 571 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 572 | if (1) /* FIXME rgbBits == 8 */ |
| 573 | fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ |
| 574 | else |
| 575 | fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ |
| 576 | |
| 577 | if (radeon_crtc->crtc_id == 0) { |
| 578 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
| 579 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 580 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 581 | fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; |
| 582 | else |
| 583 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; |
| 584 | } else |
Alex Deucher | 1b4d7d7 | 2009-10-15 01:33:35 -0400 | [diff] [blame] | 585 | fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 586 | } else { |
| 587 | if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { |
| 588 | fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; |
| 589 | fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; |
| 590 | } else |
| 591 | fp_gen_cntl |= RADEON_FP_SEL_CRTC2; |
| 592 | } |
| 593 | |
| 594 | WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); |
| 595 | WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); |
| 596 | WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); |
| 597 | |
| 598 | if (rdev->is_atom_bios) |
| 599 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 600 | else |
| 601 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 602 | } |
| 603 | |
| 604 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { |
| 605 | .dpms = radeon_legacy_tmds_int_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 606 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 607 | .prepare = radeon_legacy_tmds_int_prepare, |
| 608 | .mode_set = radeon_legacy_tmds_int_mode_set, |
| 609 | .commit = radeon_legacy_tmds_int_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 610 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 611 | }; |
| 612 | |
| 613 | |
| 614 | static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { |
| 615 | .destroy = radeon_enc_destroy, |
| 616 | }; |
| 617 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 618 | static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) |
| 619 | { |
| 620 | struct drm_device *dev = encoder->dev; |
| 621 | struct radeon_device *rdev = dev->dev_private; |
| 622 | uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 623 | DRM_DEBUG("\n"); |
| 624 | |
| 625 | switch (mode) { |
| 626 | case DRM_MODE_DPMS_ON: |
| 627 | fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; |
| 628 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 629 | break; |
| 630 | case DRM_MODE_DPMS_STANDBY: |
| 631 | case DRM_MODE_DPMS_SUSPEND: |
| 632 | case DRM_MODE_DPMS_OFF: |
| 633 | fp2_gen_cntl |= RADEON_FP2_BLANK_EN; |
| 634 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 635 | break; |
| 636 | } |
| 637 | |
| 638 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 639 | |
| 640 | if (rdev->is_atom_bios) |
| 641 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 642 | else |
| 643 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 644 | |
| 645 | /* adjust pm to dpms change */ |
| 646 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 647 | } |
| 648 | |
| 649 | static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) |
| 650 | { |
| 651 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 652 | |
| 653 | if (rdev->is_atom_bios) |
| 654 | radeon_atom_output_lock(encoder, true); |
| 655 | else |
| 656 | radeon_combios_output_lock(encoder, true); |
| 657 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 658 | } |
| 659 | |
| 660 | static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) |
| 661 | { |
| 662 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 663 | radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); |
| 664 | |
| 665 | if (rdev->is_atom_bios) |
| 666 | radeon_atom_output_lock(encoder, false); |
| 667 | else |
| 668 | radeon_combios_output_lock(encoder, false); |
| 669 | } |
| 670 | |
| 671 | static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, |
| 672 | struct drm_display_mode *mode, |
| 673 | struct drm_display_mode *adjusted_mode) |
| 674 | { |
| 675 | struct drm_device *dev = encoder->dev; |
| 676 | struct radeon_device *rdev = dev->dev_private; |
| 677 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 678 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 679 | uint32_t fp2_gen_cntl; |
| 680 | |
| 681 | DRM_DEBUG("\n"); |
| 682 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 683 | if (rdev->is_atom_bios) { |
| 684 | radeon_encoder->pixel_clock = adjusted_mode->clock; |
| 685 | atombios_external_tmds_setup(encoder, ATOM_ENABLE); |
| 686 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 687 | } else { |
| 688 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 689 | |
| 690 | if (1) /* FIXME rgbBits == 8 */ |
| 691 | fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ |
| 692 | else |
| 693 | fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ |
| 694 | |
| 695 | fp2_gen_cntl &= ~(RADEON_FP2_ON | |
| 696 | RADEON_FP2_DVO_EN | |
| 697 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 698 | |
| 699 | /* XXX: these are oem specific */ |
| 700 | if (ASIC_IS_R300(rdev)) { |
| 701 | if ((dev->pdev->device == 0x4850) && |
| 702 | (dev->pdev->subsystem_vendor == 0x1028) && |
| 703 | (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ |
| 704 | fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; |
| 705 | else |
| 706 | fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; |
| 707 | |
| 708 | /*if (mode->clock > 165000) |
| 709 | fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ |
| 710 | } |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 711 | if (!radeon_combios_external_tmds_setup(encoder)) |
| 712 | radeon_external_tmds_setup(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 713 | } |
| 714 | |
| 715 | if (radeon_crtc->crtc_id == 0) { |
| 716 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
| 717 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 718 | if (radeon_encoder->rmx_type != RMX_OFF) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 719 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; |
| 720 | else |
| 721 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; |
| 722 | } else |
| 723 | fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; |
| 724 | } else { |
| 725 | if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { |
| 726 | fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; |
| 727 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
| 728 | } else |
| 729 | fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; |
| 730 | } |
| 731 | |
| 732 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 733 | |
| 734 | if (rdev->is_atom_bios) |
| 735 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 736 | else |
| 737 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 738 | } |
| 739 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 740 | static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) |
| 741 | { |
| 742 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 743 | struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; |
| 744 | if (tmds) { |
| 745 | if (tmds->i2c_bus) |
| 746 | radeon_i2c_destroy(tmds->i2c_bus); |
| 747 | } |
| 748 | kfree(radeon_encoder->enc_priv); |
| 749 | drm_encoder_cleanup(encoder); |
| 750 | kfree(radeon_encoder); |
| 751 | } |
| 752 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 753 | static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { |
| 754 | .dpms = radeon_legacy_tmds_ext_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 755 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 756 | .prepare = radeon_legacy_tmds_ext_prepare, |
| 757 | .mode_set = radeon_legacy_tmds_ext_mode_set, |
| 758 | .commit = radeon_legacy_tmds_ext_commit, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 759 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 760 | }; |
| 761 | |
| 762 | |
| 763 | static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 764 | .destroy = radeon_ext_tmds_enc_destroy, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 765 | }; |
| 766 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 767 | static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) |
| 768 | { |
| 769 | struct drm_device *dev = encoder->dev; |
| 770 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 771 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 772 | uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 773 | uint32_t tv_master_cntl = 0; |
| 774 | bool is_tv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 775 | DRM_DEBUG("\n"); |
| 776 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 777 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
| 778 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 779 | if (rdev->family == CHIP_R200) |
| 780 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| 781 | else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 782 | if (is_tv) |
| 783 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
| 784 | else |
| 785 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 786 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 787 | } |
| 788 | |
| 789 | switch (mode) { |
| 790 | case DRM_MODE_DPMS_ON: |
| 791 | if (rdev->family == CHIP_R200) { |
| 792 | fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 793 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 794 | if (is_tv) |
| 795 | tv_master_cntl |= RADEON_TV_ON; |
| 796 | else |
| 797 | crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; |
| 798 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 799 | if (rdev->family == CHIP_R420 || |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 800 | rdev->family == CHIP_R423 || |
| 801 | rdev->family == CHIP_RV410) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 802 | tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 803 | R420_TV_DAC_GDACPD | |
| 804 | R420_TV_DAC_BDACPD | |
| 805 | RADEON_TV_DAC_BGSLEEP); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 806 | else |
| 807 | tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 808 | RADEON_TV_DAC_GDACPD | |
| 809 | RADEON_TV_DAC_BDACPD | |
| 810 | RADEON_TV_DAC_BGSLEEP); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 811 | } |
| 812 | break; |
| 813 | case DRM_MODE_DPMS_STANDBY: |
| 814 | case DRM_MODE_DPMS_SUSPEND: |
| 815 | case DRM_MODE_DPMS_OFF: |
| 816 | if (rdev->family == CHIP_R200) |
| 817 | fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); |
| 818 | else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 819 | if (is_tv) |
| 820 | tv_master_cntl &= ~RADEON_TV_ON; |
| 821 | else |
| 822 | crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; |
| 823 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 824 | if (rdev->family == CHIP_R420 || |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 825 | rdev->family == CHIP_R423 || |
| 826 | rdev->family == CHIP_RV410) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 827 | tv_dac_cntl |= (R420_TV_DAC_RDACPD | |
| 828 | R420_TV_DAC_GDACPD | |
| 829 | R420_TV_DAC_BDACPD | |
| 830 | RADEON_TV_DAC_BGSLEEP); |
| 831 | else |
| 832 | tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | |
| 833 | RADEON_TV_DAC_GDACPD | |
| 834 | RADEON_TV_DAC_BDACPD | |
| 835 | RADEON_TV_DAC_BGSLEEP); |
| 836 | } |
| 837 | break; |
| 838 | } |
| 839 | |
| 840 | if (rdev->family == CHIP_R200) { |
| 841 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 842 | } else { |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 843 | if (is_tv) |
| 844 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
| 845 | else |
| 846 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 847 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 848 | } |
| 849 | |
| 850 | if (rdev->is_atom_bios) |
| 851 | radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
| 852 | else |
| 853 | radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 854 | |
| 855 | /* adjust pm to dpms change */ |
| 856 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 857 | } |
| 858 | |
| 859 | static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) |
| 860 | { |
| 861 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 862 | |
| 863 | if (rdev->is_atom_bios) |
| 864 | radeon_atom_output_lock(encoder, true); |
| 865 | else |
| 866 | radeon_combios_output_lock(encoder, true); |
| 867 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 868 | } |
| 869 | |
| 870 | static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) |
| 871 | { |
| 872 | struct radeon_device *rdev = encoder->dev->dev_private; |
| 873 | |
| 874 | radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
| 875 | |
| 876 | if (rdev->is_atom_bios) |
| 877 | radeon_atom_output_lock(encoder, true); |
| 878 | else |
| 879 | radeon_combios_output_lock(encoder, true); |
| 880 | } |
| 881 | |
| 882 | static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, |
| 883 | struct drm_display_mode *mode, |
| 884 | struct drm_display_mode *adjusted_mode) |
| 885 | { |
| 886 | struct drm_device *dev = encoder->dev; |
| 887 | struct radeon_device *rdev = dev->dev_private; |
| 888 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
| 889 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 890 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 891 | uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 892 | uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; |
| 893 | bool is_tv = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 894 | |
| 895 | DRM_DEBUG("\n"); |
| 896 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 897 | is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; |
| 898 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 899 | if (rdev->family != CHIP_R200) { |
| 900 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 901 | if (rdev->family == CHIP_R420 || |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 902 | rdev->family == CHIP_R423 || |
| 903 | rdev->family == CHIP_RV410) { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 904 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 905 | RADEON_TV_DAC_BGADJ_MASK | |
| 906 | R420_TV_DAC_DACADJ_MASK | |
| 907 | R420_TV_DAC_RDACPD | |
| 908 | R420_TV_DAC_GDACPD | |
| 909 | R420_TV_DAC_BDACPD | |
| 910 | R420_TV_DAC_TVENABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 911 | } else { |
| 912 | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 913 | RADEON_TV_DAC_BGADJ_MASK | |
| 914 | RADEON_TV_DAC_DACADJ_MASK | |
| 915 | RADEON_TV_DAC_RDACPD | |
| 916 | RADEON_TV_DAC_GDACPD | |
| 917 | RADEON_TV_DAC_BDACPD); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 918 | } |
| 919 | |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 920 | tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; |
| 921 | |
| 922 | if (is_tv) { |
| 923 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 924 | tv_dac->tv_std == TV_STD_NTSC_J || |
| 925 | tv_dac->tv_std == TV_STD_PAL_M || |
| 926 | tv_dac->tv_std == TV_STD_PAL_60) |
| 927 | tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; |
| 928 | else |
| 929 | tv_dac_cntl |= tv_dac->pal_tvdac_adj; |
| 930 | |
| 931 | if (tv_dac->tv_std == TV_STD_NTSC || |
| 932 | tv_dac->tv_std == TV_STD_NTSC_J) |
| 933 | tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; |
| 934 | else |
| 935 | tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 936 | } else |
Alex Deucher | 7741618 | 2010-04-06 00:05:46 -0400 | [diff] [blame] | 937 | tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | |
| 938 | tv_dac->ps2_tvdac_adj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 939 | |
| 940 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 941 | } |
| 942 | |
| 943 | if (ASIC_IS_R300(rdev)) { |
| 944 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; |
| 945 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 946 | } |
| 947 | |
| 948 | if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) |
| 949 | disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 950 | else |
| 951 | disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); |
| 952 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 953 | if (rdev->family == CHIP_R200) |
| 954 | fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 955 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 956 | if (is_tv) { |
| 957 | uint32_t dac_cntl; |
| 958 | |
| 959 | dac_cntl = RREG32(RADEON_DAC_CNTL); |
| 960 | dac_cntl &= ~RADEON_DAC_TVO_EN; |
| 961 | WREG32(RADEON_DAC_CNTL, dac_cntl); |
| 962 | |
| 963 | if (ASIC_IS_R300(rdev)) |
| 964 | gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; |
| 965 | |
| 966 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; |
| 967 | if (radeon_crtc->crtc_id == 0) { |
| 968 | if (ASIC_IS_R300(rdev)) { |
| 969 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 970 | disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | |
| 971 | RADEON_DISP_TV_SOURCE_CRTC); |
| 972 | } |
| 973 | if (rdev->family >= CHIP_R200) { |
| 974 | disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; |
| 975 | } else { |
| 976 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 977 | } |
| 978 | } else { |
| 979 | if (ASIC_IS_R300(rdev)) { |
| 980 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 981 | disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; |
| 982 | } |
| 983 | if (rdev->family >= CHIP_R200) { |
| 984 | disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; |
| 985 | } else { |
| 986 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
| 987 | } |
| 988 | } |
| 989 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 990 | } else { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 991 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 992 | dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; |
| 993 | |
| 994 | if (radeon_crtc->crtc_id == 0) { |
| 995 | if (ASIC_IS_R300(rdev)) { |
| 996 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 997 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; |
| 998 | } else if (rdev->family == CHIP_R200) { |
| 999 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
| 1000 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 1001 | } else |
| 1002 | disp_hw_debug |= RADEON_CRT2_DISP1_SEL; |
| 1003 | } else { |
| 1004 | if (ASIC_IS_R300(rdev)) { |
| 1005 | disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1006 | disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1007 | } else if (rdev->family == CHIP_R200) { |
| 1008 | fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | |
| 1009 | RADEON_FP2_DVO_RATE_SEL_SDR); |
| 1010 | fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; |
| 1011 | } else |
| 1012 | disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; |
| 1013 | } |
| 1014 | WREG32(RADEON_DAC_CNTL2, dac2_cntl); |
| 1015 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1016 | |
| 1017 | if (ASIC_IS_R300(rdev)) { |
| 1018 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1019 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 1020 | } |
| 1021 | |
| 1022 | if (rdev->family >= CHIP_R200) |
| 1023 | WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1024 | else |
| 1025 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 1026 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1027 | if (rdev->family == CHIP_R200) |
| 1028 | WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| 1029 | |
| 1030 | if (is_tv) |
| 1031 | radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); |
| 1032 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1033 | if (rdev->is_atom_bios) |
| 1034 | radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 1035 | else |
| 1036 | radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); |
| 1037 | |
| 1038 | } |
| 1039 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1040 | static bool r300_legacy_tv_detect(struct drm_encoder *encoder, |
| 1041 | struct drm_connector *connector) |
| 1042 | { |
| 1043 | struct drm_device *dev = encoder->dev; |
| 1044 | struct radeon_device *rdev = dev->dev_private; |
| 1045 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
| 1046 | uint32_t disp_output_cntl, gpiopad_a, tmp; |
| 1047 | bool found = false; |
| 1048 | |
| 1049 | /* save regs needed */ |
| 1050 | gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
| 1051 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1052 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 1053 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 1054 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1055 | disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); |
| 1056 | |
| 1057 | WREG32_P(RADEON_GPIOPAD_A, 0, ~1); |
| 1058 | |
| 1059 | WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); |
| 1060 | |
| 1061 | WREG32(RADEON_CRTC2_GEN_CNTL, |
| 1062 | RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); |
| 1063 | |
| 1064 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1065 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1066 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
| 1067 | |
| 1068 | WREG32(RADEON_DAC_EXT_CNTL, |
| 1069 | RADEON_DAC2_FORCE_BLANK_OFF_EN | |
| 1070 | RADEON_DAC2_FORCE_DATA_EN | |
| 1071 | RADEON_DAC_FORCE_DATA_SEL_RGB | |
| 1072 | (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); |
| 1073 | |
| 1074 | WREG32(RADEON_TV_DAC_CNTL, |
| 1075 | RADEON_TV_DAC_STD_NTSC | |
| 1076 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
| 1077 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
| 1078 | |
| 1079 | RREG32(RADEON_TV_DAC_CNTL); |
| 1080 | mdelay(4); |
| 1081 | |
| 1082 | WREG32(RADEON_TV_DAC_CNTL, |
| 1083 | RADEON_TV_DAC_NBLANK | |
| 1084 | RADEON_TV_DAC_NHOLD | |
| 1085 | RADEON_TV_MONITOR_DETECT_EN | |
| 1086 | RADEON_TV_DAC_STD_NTSC | |
| 1087 | (8 << RADEON_TV_DAC_BGADJ_SHIFT) | |
| 1088 | (6 << RADEON_TV_DAC_DACADJ_SHIFT)); |
| 1089 | |
| 1090 | RREG32(RADEON_TV_DAC_CNTL); |
| 1091 | mdelay(6); |
| 1092 | |
| 1093 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
| 1094 | if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { |
| 1095 | found = true; |
| 1096 | DRM_DEBUG("S-video TV connection detected\n"); |
| 1097 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
| 1098 | found = true; |
| 1099 | DRM_DEBUG("Composite TV connection detected\n"); |
| 1100 | } |
| 1101 | |
| 1102 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1103 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 1104 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 1105 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 1106 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1107 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
| 1108 | return found; |
| 1109 | } |
| 1110 | |
| 1111 | static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, |
| 1112 | struct drm_connector *connector) |
| 1113 | { |
| 1114 | struct drm_device *dev = encoder->dev; |
| 1115 | struct radeon_device *rdev = dev->dev_private; |
| 1116 | uint32_t tv_dac_cntl, dac_cntl2; |
| 1117 | uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; |
| 1118 | bool found = false; |
| 1119 | |
| 1120 | if (ASIC_IS_R300(rdev)) |
| 1121 | return r300_legacy_tv_detect(encoder, connector); |
| 1122 | |
| 1123 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1124 | tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); |
| 1125 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1126 | config_cntl = RREG32(RADEON_CONFIG_CNTL); |
| 1127 | tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); |
| 1128 | |
| 1129 | tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; |
| 1130 | WREG32(RADEON_DAC_CNTL2, tmp); |
| 1131 | |
| 1132 | tmp = tv_master_cntl | RADEON_TV_ON; |
| 1133 | tmp &= ~(RADEON_TV_ASYNC_RST | |
| 1134 | RADEON_RESTART_PHASE_FIX | |
| 1135 | RADEON_CRT_FIFO_CE_EN | |
| 1136 | RADEON_TV_FIFO_CE_EN | |
| 1137 | RADEON_RE_SYNC_NOW_SEL_MASK); |
| 1138 | tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; |
| 1139 | WREG32(RADEON_TV_MASTER_CNTL, tmp); |
| 1140 | |
| 1141 | tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | |
| 1142 | RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | |
| 1143 | (8 << RADEON_TV_DAC_BGADJ_SHIFT); |
| 1144 | |
| 1145 | if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) |
| 1146 | tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); |
| 1147 | else |
| 1148 | tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); |
| 1149 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
| 1150 | |
| 1151 | tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | |
| 1152 | RADEON_RED_MX_FORCE_DAC_DATA | |
| 1153 | RADEON_GRN_MX_FORCE_DAC_DATA | |
| 1154 | RADEON_BLU_MX_FORCE_DAC_DATA | |
| 1155 | (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); |
| 1156 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); |
| 1157 | |
| 1158 | mdelay(3); |
| 1159 | tmp = RREG32(RADEON_TV_DAC_CNTL); |
| 1160 | if (tmp & RADEON_TV_DAC_GDACDET) { |
| 1161 | found = true; |
| 1162 | DRM_DEBUG("S-video TV connection detected\n"); |
| 1163 | } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { |
| 1164 | found = true; |
| 1165 | DRM_DEBUG("Composite TV connection detected\n"); |
| 1166 | } |
| 1167 | |
| 1168 | WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); |
| 1169 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1170 | WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); |
| 1171 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1172 | return found; |
| 1173 | } |
| 1174 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1175 | static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, |
| 1176 | struct drm_connector *connector) |
| 1177 | { |
| 1178 | struct drm_device *dev = encoder->dev; |
| 1179 | struct radeon_device *rdev = dev->dev_private; |
| 1180 | uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; |
| 1181 | uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp; |
| 1182 | enum drm_connector_status found = connector_status_disconnected; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1183 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1184 | struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1185 | bool color = true; |
| 1186 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1187 | if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || |
| 1188 | connector->connector_type == DRM_MODE_CONNECTOR_Composite || |
| 1189 | connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { |
| 1190 | bool tv_detect; |
| 1191 | |
| 1192 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) |
| 1193 | return connector_status_disconnected; |
| 1194 | |
| 1195 | tv_detect = radeon_legacy_tv_detect(encoder, connector); |
| 1196 | if (tv_detect && tv_dac) |
| 1197 | found = connector_status_connected; |
| 1198 | return found; |
| 1199 | } |
| 1200 | |
| 1201 | /* don't probe if the encoder is being used for something else not CRT related */ |
| 1202 | if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { |
| 1203 | DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); |
| 1204 | return connector_status_disconnected; |
| 1205 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1206 | |
| 1207 | /* save the regs we need */ |
| 1208 | pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| 1209 | gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0; |
| 1210 | disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0; |
| 1211 | disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG); |
| 1212 | crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| 1213 | tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); |
| 1214 | dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); |
| 1215 | dac_cntl2 = RREG32(RADEON_DAC_CNTL2); |
| 1216 | |
| 1217 | tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb |
| 1218 | | RADEON_PIX2CLK_DAC_ALWAYS_ONb); |
| 1219 | WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| 1220 | |
| 1221 | if (ASIC_IS_R300(rdev)) |
| 1222 | WREG32_P(RADEON_GPIOPAD_A, 1, ~1); |
| 1223 | |
| 1224 | tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; |
| 1225 | tmp |= RADEON_CRTC2_CRT2_ON | |
| 1226 | (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); |
| 1227 | |
| 1228 | WREG32(RADEON_CRTC2_GEN_CNTL, tmp); |
| 1229 | |
| 1230 | if (ASIC_IS_R300(rdev)) { |
| 1231 | tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; |
| 1232 | tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; |
| 1233 | WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); |
| 1234 | } else { |
| 1235 | tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; |
| 1236 | WREG32(RADEON_DISP_HW_DEBUG, tmp); |
| 1237 | } |
| 1238 | |
| 1239 | tmp = RADEON_TV_DAC_NBLANK | |
| 1240 | RADEON_TV_DAC_NHOLD | |
| 1241 | RADEON_TV_MONITOR_DETECT_EN | |
| 1242 | RADEON_TV_DAC_STD_PS2; |
| 1243 | |
| 1244 | WREG32(RADEON_TV_DAC_CNTL, tmp); |
| 1245 | |
| 1246 | tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | |
| 1247 | RADEON_DAC2_FORCE_DATA_EN; |
| 1248 | |
| 1249 | if (color) |
| 1250 | tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; |
| 1251 | else |
| 1252 | tmp |= RADEON_DAC_FORCE_DATA_SEL_G; |
| 1253 | |
| 1254 | if (ASIC_IS_R300(rdev)) |
| 1255 | tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 1256 | else |
| 1257 | tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); |
| 1258 | |
| 1259 | WREG32(RADEON_DAC_EXT_CNTL, tmp); |
| 1260 | |
| 1261 | tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; |
| 1262 | WREG32(RADEON_DAC_CNTL2, tmp); |
| 1263 | |
| 1264 | udelay(10000); |
| 1265 | |
| 1266 | if (ASIC_IS_R300(rdev)) { |
| 1267 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) |
| 1268 | found = connector_status_connected; |
| 1269 | } else { |
| 1270 | if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) |
| 1271 | found = connector_status_connected; |
| 1272 | } |
| 1273 | |
| 1274 | /* restore regs we used */ |
| 1275 | WREG32(RADEON_DAC_CNTL2, dac_cntl2); |
| 1276 | WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); |
| 1277 | WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); |
| 1278 | WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| 1279 | |
| 1280 | if (ASIC_IS_R300(rdev)) { |
| 1281 | WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); |
| 1282 | WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); |
| 1283 | } else { |
| 1284 | WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); |
| 1285 | } |
| 1286 | WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); |
| 1287 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1288 | return found; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1289 | |
| 1290 | } |
| 1291 | |
| 1292 | static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { |
| 1293 | .dpms = radeon_legacy_tv_dac_dpms, |
Alex Deucher | 80297e8 | 2009-11-12 14:55:14 -0500 | [diff] [blame] | 1294 | .mode_fixup = radeon_legacy_mode_fixup, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1295 | .prepare = radeon_legacy_tv_dac_prepare, |
| 1296 | .mode_set = radeon_legacy_tv_dac_mode_set, |
| 1297 | .commit = radeon_legacy_tv_dac_commit, |
| 1298 | .detect = radeon_legacy_tv_dac_detect, |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 1299 | .disable = radeon_legacy_encoder_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1300 | }; |
| 1301 | |
| 1302 | |
| 1303 | static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { |
| 1304 | .destroy = radeon_enc_destroy, |
| 1305 | }; |
| 1306 | |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1307 | |
| 1308 | static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) |
| 1309 | { |
| 1310 | struct drm_device *dev = encoder->base.dev; |
| 1311 | struct radeon_device *rdev = dev->dev_private; |
| 1312 | struct radeon_encoder_int_tmds *tmds = NULL; |
| 1313 | bool ret; |
| 1314 | |
| 1315 | tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
| 1316 | |
| 1317 | if (!tmds) |
| 1318 | return NULL; |
| 1319 | |
| 1320 | if (rdev->is_atom_bios) |
| 1321 | ret = radeon_atombios_get_tmds_info(encoder, tmds); |
| 1322 | else |
| 1323 | ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); |
| 1324 | |
| 1325 | if (ret == false) |
| 1326 | radeon_legacy_get_tmds_info_from_table(encoder, tmds); |
| 1327 | |
| 1328 | return tmds; |
| 1329 | } |
| 1330 | |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1331 | static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) |
| 1332 | { |
| 1333 | struct drm_device *dev = encoder->base.dev; |
| 1334 | struct radeon_device *rdev = dev->dev_private; |
| 1335 | struct radeon_encoder_ext_tmds *tmds = NULL; |
| 1336 | bool ret; |
| 1337 | |
| 1338 | if (rdev->is_atom_bios) |
| 1339 | return NULL; |
| 1340 | |
| 1341 | tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); |
| 1342 | |
| 1343 | if (!tmds) |
| 1344 | return NULL; |
| 1345 | |
| 1346 | ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); |
| 1347 | |
| 1348 | if (ret == false) |
| 1349 | radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); |
| 1350 | |
| 1351 | return tmds; |
| 1352 | } |
| 1353 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1354 | void |
| 1355 | radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device) |
| 1356 | { |
| 1357 | struct radeon_device *rdev = dev->dev_private; |
| 1358 | struct drm_encoder *encoder; |
| 1359 | struct radeon_encoder *radeon_encoder; |
| 1360 | |
| 1361 | /* see if we already added it */ |
| 1362 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1363 | radeon_encoder = to_radeon_encoder(encoder); |
| 1364 | if (radeon_encoder->encoder_id == encoder_id) { |
| 1365 | radeon_encoder->devices |= supported_device; |
| 1366 | return; |
| 1367 | } |
| 1368 | |
| 1369 | } |
| 1370 | |
| 1371 | /* add a new one */ |
| 1372 | radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); |
| 1373 | if (!radeon_encoder) |
| 1374 | return; |
| 1375 | |
| 1376 | encoder = &radeon_encoder->base; |
Dave Airlie | dfee561 | 2009-10-02 09:19:09 +1000 | [diff] [blame] | 1377 | if (rdev->flags & RADEON_SINGLE_CRTC) |
| 1378 | encoder->possible_crtcs = 0x1; |
| 1379 | else |
| 1380 | encoder->possible_crtcs = 0x3; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1381 | |
| 1382 | radeon_encoder->enc_priv = NULL; |
| 1383 | |
| 1384 | radeon_encoder->encoder_id = encoder_id; |
| 1385 | radeon_encoder->devices = supported_device; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1386 | radeon_encoder->rmx_type = RMX_OFF; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1387 | |
| 1388 | switch (radeon_encoder->encoder_id) { |
| 1389 | case ENCODER_OBJECT_ID_INTERNAL_LVDS: |
Dave Airlie | 80e6914 | 2009-08-17 10:22:37 +1000 | [diff] [blame] | 1390 | encoder->possible_crtcs = 0x1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1391 | drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); |
| 1392 | drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); |
| 1393 | if (rdev->is_atom_bios) |
| 1394 | radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); |
| 1395 | else |
| 1396 | radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); |
| 1397 | radeon_encoder->rmx_type = RMX_FULL; |
| 1398 | break; |
| 1399 | case ENCODER_OBJECT_ID_INTERNAL_TMDS1: |
| 1400 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1401 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); |
Dave Airlie | 445282d | 2009-09-09 17:40:54 +1000 | [diff] [blame] | 1402 | radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1403 | break; |
| 1404 | case ENCODER_OBJECT_ID_INTERNAL_DAC1: |
| 1405 | drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC); |
| 1406 | drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1407 | if (rdev->is_atom_bios) |
| 1408 | radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); |
| 1409 | else |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1410 | radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); |
| 1411 | break; |
| 1412 | case ENCODER_OBJECT_ID_INTERNAL_DAC2: |
| 1413 | drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC); |
| 1414 | drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); |
Alex Deucher | 6fe7ac3 | 2009-06-12 17:26:08 +0000 | [diff] [blame] | 1415 | if (rdev->is_atom_bios) |
| 1416 | radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); |
| 1417 | else |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1418 | radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); |
| 1419 | break; |
| 1420 | case ENCODER_OBJECT_ID_INTERNAL_DVO1: |
| 1421 | drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS); |
| 1422 | drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); |
| 1423 | if (!rdev->is_atom_bios) |
Alex Deucher | fcec570 | 2009-11-10 21:25:07 -0500 | [diff] [blame] | 1424 | radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1425 | break; |
| 1426 | } |
| 1427 | } |