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gerrit-public.fairphone.software / kernel / msm-4.9 / 35c319b47884e49d9d0a84779097916ccb173947 / . / drivers / scsi / mpt3sas / mpi / mpi2.h
blob: c2d127c7d4e2986a9aa1c9341ab4ac9d44c28e86 [file] [log] [blame]
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]1/*
Sreekanth Reddya4ffce02014-09-12 15:35:29 +0530[diff] [blame]2 * Copyright (c) 2000-2014 LSI Corporation.
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Sreekanth Reddy35c319b2015-06-30 12:24:55 +0530[diff] [blame^]11 * mpi2.h Version: 02.00.34
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]85 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
88 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
Sreekanth Reddy861ff732014-09-12 15:35:25 +0530[diff] [blame]89 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
90 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddya94bea32015-06-30 12:24:51 +0530[diff] [blame]91 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
92 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
Sreekanth Reddy35c319b2015-06-30 12:24:55 +0530[diff] [blame^]93 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]94 * --------------------------------------------------------------------------
95 */
96
97#ifndef MPI2_H
98#define MPI2_H
99
100/*****************************************************************************
101*
102* MPI Version Definitions
103*
104*****************************************************************************/
105
106#define MPI2_VERSION_MAJOR_MASK (0xFF00)
107#define MPI2_VERSION_MAJOR_SHIFT (8)
108#define MPI2_VERSION_MINOR_MASK (0x00FF)
109#define MPI2_VERSION_MINOR_SHIFT (0)
110
111/*major version for all MPI v2.x */
112#define MPI2_VERSION_MAJOR (0x02)
113
114/*minor version for MPI v2.0 compatible products */
115#define MPI2_VERSION_MINOR (0x00)
116#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
117 MPI2_VERSION_MINOR)
118#define MPI2_VERSION_02_00 (0x0200)
119
120/*minor version for MPI v2.5 compatible products */
121#define MPI25_VERSION_MINOR (0x05)
122#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
123 MPI25_VERSION_MINOR)
124#define MPI2_VERSION_02_05 (0x0205)
125
126/*Unit and Dev versioning for this MPI header set */
Sreekanth Reddy35c319b2015-06-30 12:24:55 +0530[diff] [blame^]127#define MPI2_HEADER_VERSION_UNIT (0x22)
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]128#define MPI2_HEADER_VERSION_DEV (0x00)
129#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
130#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
131#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
132#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
133#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
134 MPI2_HEADER_VERSION_DEV)
135
136/*****************************************************************************
137*
138* IOC State Definitions
139*
140*****************************************************************************/
141
142#define MPI2_IOC_STATE_RESET (0x00000000)
143#define MPI2_IOC_STATE_READY (0x10000000)
144#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
145#define MPI2_IOC_STATE_FAULT (0x40000000)
146
147#define MPI2_IOC_STATE_MASK (0xF0000000)
148#define MPI2_IOC_STATE_SHIFT (28)
149
150/*Fault state range for prodcut specific codes */
151#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
152#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
153
154/*****************************************************************************
155*
156* System Interface Register Definitions
157*
158*****************************************************************************/
159
160typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
161 U32 Doorbell; /*0x00 */
162 U32 WriteSequence; /*0x04 */
163 U32 HostDiagnostic; /*0x08 */
164 U32 Reserved1; /*0x0C */
165 U32 DiagRWData; /*0x10 */
166 U32 DiagRWAddressLow; /*0x14 */
167 U32 DiagRWAddressHigh; /*0x18 */
168 U32 Reserved2[5]; /*0x1C */
169 U32 HostInterruptStatus; /*0x30 */
170 U32 HostInterruptMask; /*0x34 */
171 U32 DCRData; /*0x38 */
172 U32 DCRAddress; /*0x3C */
173 U32 Reserved3[2]; /*0x40 */
174 U32 ReplyFreeHostIndex; /*0x48 */
175 U32 Reserved4[8]; /*0x4C */
176 U32 ReplyPostHostIndex; /*0x6C */
177 U32 Reserved5; /*0x70 */
178 U32 HCBSize; /*0x74 */
179 U32 HCBAddressLow; /*0x78 */
180 U32 HCBAddressHigh; /*0x7C */
181 U32 Reserved6[16]; /*0x80 */
182 U32 RequestDescriptorPostLow; /*0xC0 */
183 U32 RequestDescriptorPostHigh; /*0xC4 */
184 U32 Reserved7[14]; /*0xC8 */
185} MPI2_SYSTEM_INTERFACE_REGS,
186 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
187 Mpi2SystemInterfaceRegs_t,
188 *pMpi2SystemInterfaceRegs_t;
189
190/*
191 *Defines for working with the Doorbell register.
192 */
193#define MPI2_DOORBELL_OFFSET (0x00000000)
194
195/*IOC --> System values */
196#define MPI2_DOORBELL_USED (0x08000000)
197#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
198#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
199#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
200#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
201
202/*System --> IOC values */
203#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
204#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
205#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
206#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
207
208/*
209 *Defines for the WriteSequence register
210 */
211#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
212#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
213#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
214#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
215#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
216#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
217#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
218#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
219#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
220
221/*
222 *Defines for the HostDiagnostic register
223 */
224#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
225
226#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
227#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
228#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
229
230#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
231#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
232#define MPI2_DIAG_HCB_MODE (0x00000100)
233#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
234#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
235#define MPI2_DIAG_RESET_HISTORY (0x00000020)
236#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
237#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
238#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
239
240/*
241 *Offsets for DiagRWData and address
242 */
243#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
244#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
245#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
246
247/*
248 *Defines for the HostInterruptStatus register
249 */
250#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
251#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
252#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
253#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
254#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
255#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
256#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
257
258/*
259 *Defines for the HostInterruptMask register
260 */
261#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
262#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
263#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
264#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
265#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
266#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
267
268/*
269 *Offsets for DCRData and address
270 */
271#define MPI2_DCR_DATA_OFFSET (0x00000038)
272#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
273
274/*
275 *Offset for the Reply Free Queue
276 */
277#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
278
279/*
280 *Defines for the Reply Descriptor Post Queue
281 */
282#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
283#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
284#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
285#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Sreekanth Reddy17263e72013-06-29 03:54:07 +0530[diff] [blame]286#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
287
Sreekanth Reddyf92363d2012-11-30 07:44:21 +0530[diff] [blame]288
289/*
290 *Defines for the HCBSize and address
291 */
292#define MPI2_HCB_SIZE_OFFSET (0x00000074)
293#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
294#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
295
296#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
297#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
298
299/*
300 *Offsets for the Request Queue
301 */
302#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
303#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
304
305/*Hard Reset delay timings */
306#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
307#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
308#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
309
310/*****************************************************************************
311*
312* Message Descriptors
313*
314*****************************************************************************/
315
316/*Request Descriptors */
317
318/*Default Request Descriptor */
319typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
320 U8 RequestFlags; /*0x00 */
321 U8 MSIxIndex; /*0x01 */
322 U16 SMID; /*0x02 */
323 U16 LMID; /*0x04 */
324 U16 DescriptorTypeDependent; /*0x06 */
325} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
326 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
327 Mpi2DefaultRequestDescriptor_t,
328 *pMpi2DefaultRequestDescriptor_t;
329
330/*defines for the RequestFlags field */
331#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
332#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
333#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
334#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
335#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
336#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
337#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
338
339#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
340
341/*High Priority Request Descriptor */
342typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
343 U8 RequestFlags; /*0x00 */
344 U8 MSIxIndex; /*0x01 */
345 U16 SMID; /*0x02 */
346 U16 LMID; /*0x04 */
347 U16 Reserved1; /*0x06 */
348} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
349 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
350 Mpi2HighPriorityRequestDescriptor_t,
351 *pMpi2HighPriorityRequestDescriptor_t;
352
353/*SCSI IO Request Descriptor */
354typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
355 U8 RequestFlags; /*0x00 */
356 U8 MSIxIndex; /*0x01 */
357 U16 SMID; /*0x02 */
358 U16 LMID; /*0x04 */
359 U16 DevHandle; /*0x06 */
360} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
361 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
362 Mpi2SCSIIORequestDescriptor_t,
363 *pMpi2SCSIIORequestDescriptor_t;
364
365/*SCSI Target Request Descriptor */
366typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
367 U8 RequestFlags; /*0x00 */
368 U8 MSIxIndex; /*0x01 */
369 U16 SMID; /*0x02 */
370 U16 LMID; /*0x04 */
371 U16 IoIndex; /*0x06 */
372} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
373 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
374 Mpi2SCSITargetRequestDescriptor_t,
375 *pMpi2SCSITargetRequestDescriptor_t;
376
377/*RAID Accelerator Request Descriptor */
378typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
379 U8 RequestFlags; /*0x00 */
380 U8 MSIxIndex; /*0x01 */
381 U16 SMID; /*0x02 */
382 U16 LMID; /*0x04 */
383 U16 Reserved; /*0x06 */
384} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
385 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
386 Mpi2RAIDAcceleratorRequestDescriptor_t,
387 *pMpi2RAIDAcceleratorRequestDescriptor_t;
388
389/*Fast Path SCSI IO Request Descriptor */
390typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
391 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
392 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
393 Mpi25FastPathSCSIIORequestDescriptor_t,
394 *pMpi25FastPathSCSIIORequestDescriptor_t;
395
396/*union of Request Descriptors */
397typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
398 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
399 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
400 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
401 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
402 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
403 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
404 U64 Words;
405} MPI2_REQUEST_DESCRIPTOR_UNION,
406 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
407 Mpi2RequestDescriptorUnion_t,
408 *pMpi2RequestDescriptorUnion_t;
409
410/*Reply Descriptors */
411
412/*Default Reply Descriptor */
413typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
414 U8 ReplyFlags; /*0x00 */
415 U8 MSIxIndex; /*0x01 */
416 U16 DescriptorTypeDependent1; /*0x02 */
417 U32 DescriptorTypeDependent2; /*0x04 */
418} MPI2_DEFAULT_REPLY_DESCRIPTOR,
419 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
420 Mpi2DefaultReplyDescriptor_t,
421 *pMpi2DefaultReplyDescriptor_t;
422
423/*defines for the ReplyFlags field */
424#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
425#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
426#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
427#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
428#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
429#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
430#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
431#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
432
433/*values for marking a reply descriptor as unused */
434#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
435#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
436
437/*Address Reply Descriptor */
438typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
439 U8 ReplyFlags; /*0x00 */
440 U8 MSIxIndex; /*0x01 */
441 U16 SMID; /*0x02 */
442 U32 ReplyFrameAddress; /*0x04 */
443} MPI2_ADDRESS_REPLY_DESCRIPTOR,
444 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
445 Mpi2AddressReplyDescriptor_t,
446 *pMpi2AddressReplyDescriptor_t;
447
448#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
449
450/*SCSI IO Success Reply Descriptor */
451typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
452 U8 ReplyFlags; /*0x00 */
453 U8 MSIxIndex; /*0x01 */
454 U16 SMID; /*0x02 */
455 U16 TaskTag; /*0x04 */
456 U16 Reserved1; /*0x06 */
457} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
458 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
459 Mpi2SCSIIOSuccessReplyDescriptor_t,
460 *pMpi2SCSIIOSuccessReplyDescriptor_t;
461
462/*TargetAssist Success Reply Descriptor */
463typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
464 U8 ReplyFlags; /*0x00 */
465 U8 MSIxIndex; /*0x01 */
466 U16 SMID; /*0x02 */
467 U8 SequenceNumber; /*0x04 */
468 U8 Reserved1; /*0x05 */
469 U16 IoIndex; /*0x06 */
470} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
471 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
472 Mpi2TargetAssistSuccessReplyDescriptor_t,
473 *pMpi2TargetAssistSuccessReplyDescriptor_t;
474
475/*Target Command Buffer Reply Descriptor */
476typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
477 U8 ReplyFlags; /*0x00 */
478 U8 MSIxIndex; /*0x01 */
479 U8 VP_ID; /*0x02 */
480 U8 Flags; /*0x03 */
481 U16 InitiatorDevHandle; /*0x04 */
482 U16 IoIndex; /*0x06 */
483} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
484 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
485 Mpi2TargetCommandBufferReplyDescriptor_t,
486 *pMpi2TargetCommandBufferReplyDescriptor_t;
487
488/*defines for Flags field */
489#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
490
491/*RAID Accelerator Success Reply Descriptor */
492typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
493 U8 ReplyFlags; /*0x00 */
494 U8 MSIxIndex; /*0x01 */
495 U16 SMID; /*0x02 */
496 U32 Reserved; /*0x04 */
497} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
498 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
499 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
500 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
501
502/*Fast Path SCSI IO Success Reply Descriptor */
503typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
504 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
505 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
506 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
507 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
508
509/*union of Reply Descriptors */
510typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
511 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
512 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
513 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
514 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
515 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
516 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
517 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
518 U64 Words;
519} MPI2_REPLY_DESCRIPTORS_UNION,
520 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
521 Mpi2ReplyDescriptorsUnion_t,
522 *pMpi2ReplyDescriptorsUnion_t;
523
524/*****************************************************************************
525*
526* Message Functions
527*
528*****************************************************************************/
529
530#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
531#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
532#define MPI2_FUNCTION_IOC_INIT (0x02)
533#define MPI2_FUNCTION_IOC_FACTS (0x03)
534#define MPI2_FUNCTION_CONFIG (0x04)
535#define MPI2_FUNCTION_PORT_FACTS (0x05)
536#define MPI2_FUNCTION_PORT_ENABLE (0x06)
537#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
538#define MPI2_FUNCTION_EVENT_ACK (0x08)
539#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
540#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
541#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
542#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
543#define MPI2_FUNCTION_FW_UPLOAD (0x12)
544#define MPI2_FUNCTION_RAID_ACTION (0x15)
545#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
546#define MPI2_FUNCTION_TOOLBOX (0x17)
547#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
548#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
549#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
550#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
551#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
552#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
553#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
554#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
555#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
556#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
557#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
558#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
559#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
560#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
561
562/*Doorbell functions */
563#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
564#define MPI2_FUNCTION_HANDSHAKE (0x42)
565
566/*****************************************************************************
567*
568* IOC Status Values
569*
570*****************************************************************************/
571
572/*mask for IOCStatus status value */
573#define MPI2_IOCSTATUS_MASK (0x7FFF)
574
575/****************************************************************************
576* Common IOCStatus values for all replies
577****************************************************************************/
578
579#define MPI2_IOCSTATUS_SUCCESS (0x0000)
580#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
581#define MPI2_IOCSTATUS_BUSY (0x0002)
582#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
583#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
584#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
585#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
586#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
587#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
588#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
589
590/****************************************************************************
591* Config IOCStatus values
592****************************************************************************/
593
594#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
595#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
596#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
597#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
598#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
599#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
600
601/****************************************************************************
602* SCSI IO Reply
603****************************************************************************/
604
605#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
606#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
607#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
608#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
609#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
610#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
611#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
612#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
613#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
614#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
615#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
616#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
617
618/****************************************************************************
619* For use by SCSI Initiator and SCSI Target end-to-end data protection
620****************************************************************************/
621
622#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
623#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
624#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
625
626/****************************************************************************
627* SCSI Target values
628****************************************************************************/
629
630#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
631#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
632#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
633#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
634#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
635#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
636#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
637#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
638#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
639#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
640
641/****************************************************************************
642* Serial Attached SCSI values
643****************************************************************************/
644
645#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
646#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
647
648/****************************************************************************
649* Diagnostic Buffer Post / Diagnostic Release values
650****************************************************************************/
651
652#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
653
654/****************************************************************************
655* RAID Accelerator values
656****************************************************************************/
657
658#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
659
660/****************************************************************************
661* IOCStatus flag to indicate that log info is available
662****************************************************************************/
663
664#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
665
666/****************************************************************************
667* IOCLogInfo Types
668****************************************************************************/
669
670#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
671#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
672#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
673#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
674#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
675#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
676#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
677#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
678
679/*****************************************************************************
680*
681* Standard Message Structures
682*
683*****************************************************************************/
684
685/****************************************************************************
686*Request Message Header for all request messages
687****************************************************************************/
688
689typedef struct _MPI2_REQUEST_HEADER {
690 U16 FunctionDependent1; /*0x00 */
691 U8 ChainOffset; /*0x02 */
692 U8 Function; /*0x03 */
693 U16 FunctionDependent2; /*0x04 */
694 U8 FunctionDependent3; /*0x06 */
695 U8 MsgFlags; /*0x07 */
696 U8 VP_ID; /*0x08 */
697 U8 VF_ID; /*0x09 */
698 U16 Reserved1; /*0x0A */
699} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
700 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
701
702/****************************************************************************
703* Default Reply
704****************************************************************************/
705
706typedef struct _MPI2_DEFAULT_REPLY {
707 U16 FunctionDependent1; /*0x00 */
708 U8 MsgLength; /*0x02 */
709 U8 Function; /*0x03 */
710 U16 FunctionDependent2; /*0x04 */
711 U8 FunctionDependent3; /*0x06 */
712 U8 MsgFlags; /*0x07 */
713 U8 VP_ID; /*0x08 */
714 U8 VF_ID; /*0x09 */
715 U16 Reserved1; /*0x0A */
716 U16 FunctionDependent5; /*0x0C */
717 U16 IOCStatus; /*0x0E */
718 U32 IOCLogInfo; /*0x10 */
719} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
720 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
721
722/*common version structure/union used in messages and configuration pages */
723
724typedef struct _MPI2_VERSION_STRUCT {
725 U8 Dev; /*0x00 */
726 U8 Unit; /*0x01 */
727 U8 Minor; /*0x02 */
728 U8 Major; /*0x03 */
729} MPI2_VERSION_STRUCT;
730
731typedef union _MPI2_VERSION_UNION {
732 MPI2_VERSION_STRUCT Struct;
733 U32 Word;
734} MPI2_VERSION_UNION;
735
736/*LUN field defines, common to many structures */
737#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
738#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
739#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
740#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
741#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
742#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
743
744/*****************************************************************************
745*
746* Fusion-MPT MPI Scatter Gather Elements
747*
748*****************************************************************************/
749
750/****************************************************************************
751* MPI Simple Element structures
752****************************************************************************/
753
754typedef struct _MPI2_SGE_SIMPLE32 {
755 U32 FlagsLength;
756 U32 Address;
757} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
758 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
759
760typedef struct _MPI2_SGE_SIMPLE64 {
761 U32 FlagsLength;
762 U64 Address;
763} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
764 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
765
766typedef struct _MPI2_SGE_SIMPLE_UNION {
767 U32 FlagsLength;
768 union {
769 U32 Address32;
770 U64 Address64;
771 } u;
772} MPI2_SGE_SIMPLE_UNION,
773 *PTR_MPI2_SGE_SIMPLE_UNION,
774 Mpi2SGESimpleUnion_t,
775 *pMpi2SGESimpleUnion_t;
776
777/****************************************************************************
778* MPI Chain Element structures - for MPI v2.0 products only
779****************************************************************************/
780
781typedef struct _MPI2_SGE_CHAIN32 {
782 U16 Length;
783 U8 NextChainOffset;
784 U8 Flags;
785 U32 Address;
786} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
787 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
788
789typedef struct _MPI2_SGE_CHAIN64 {
790 U16 Length;
791 U8 NextChainOffset;
792 U8 Flags;
793 U64 Address;
794} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
795 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
796
797typedef struct _MPI2_SGE_CHAIN_UNION {
798 U16 Length;
799 U8 NextChainOffset;
800 U8 Flags;
801 union {
802 U32 Address32;
803 U64 Address64;
804 } u;
805} MPI2_SGE_CHAIN_UNION,
806 *PTR_MPI2_SGE_CHAIN_UNION,
807 Mpi2SGEChainUnion_t,
808 *pMpi2SGEChainUnion_t;
809
810/****************************************************************************
811* MPI Transaction Context Element structures - for MPI v2.0 products only
812****************************************************************************/
813
814typedef struct _MPI2_SGE_TRANSACTION32 {
815 U8 Reserved;
816 U8 ContextSize;
817 U8 DetailsLength;
818 U8 Flags;
819 U32 TransactionContext[1];
820 U32 TransactionDetails[1];
821} MPI2_SGE_TRANSACTION32,
822 *PTR_MPI2_SGE_TRANSACTION32,
823 Mpi2SGETransaction32_t,
824 *pMpi2SGETransaction32_t;
825
826typedef struct _MPI2_SGE_TRANSACTION64 {
827 U8 Reserved;
828 U8 ContextSize;
829 U8 DetailsLength;
830 U8 Flags;
831 U32 TransactionContext[2];
832 U32 TransactionDetails[1];
833} MPI2_SGE_TRANSACTION64,
834 *PTR_MPI2_SGE_TRANSACTION64,
835 Mpi2SGETransaction64_t,
836 *pMpi2SGETransaction64_t;
837
838typedef struct _MPI2_SGE_TRANSACTION96 {
839 U8 Reserved;
840 U8 ContextSize;
841 U8 DetailsLength;
842 U8 Flags;
843 U32 TransactionContext[3];
844 U32 TransactionDetails[1];
845} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
846 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
847
848typedef struct _MPI2_SGE_TRANSACTION128 {
849 U8 Reserved;
850 U8 ContextSize;
851 U8 DetailsLength;
852 U8 Flags;
853 U32 TransactionContext[4];
854 U32 TransactionDetails[1];
855} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
856 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
857
858typedef struct _MPI2_SGE_TRANSACTION_UNION {
859 U8 Reserved;
860 U8 ContextSize;
861 U8 DetailsLength;
862 U8 Flags;
863 union {
864 U32 TransactionContext32[1];
865 U32 TransactionContext64[2];
866 U32 TransactionContext96[3];
867 U32 TransactionContext128[4];
868 } u;
869 U32 TransactionDetails[1];
870} MPI2_SGE_TRANSACTION_UNION,
871 *PTR_MPI2_SGE_TRANSACTION_UNION,
872 Mpi2SGETransactionUnion_t,
873 *pMpi2SGETransactionUnion_t;
874
875/****************************************************************************
876* MPI SGE union for IO SGL's - for MPI v2.0 products only
877****************************************************************************/
878
879typedef struct _MPI2_MPI_SGE_IO_UNION {
880 union {
881 MPI2_SGE_SIMPLE_UNION Simple;
882 MPI2_SGE_CHAIN_UNION Chain;
883 } u;
884} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
885 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
886
887/****************************************************************************
888* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
889****************************************************************************/
890
891typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
892 union {
893 MPI2_SGE_SIMPLE_UNION Simple;
894 MPI2_SGE_TRANSACTION_UNION Transaction;
895 } u;
896} MPI2_SGE_TRANS_SIMPLE_UNION,
897 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
898 Mpi2SGETransSimpleUnion_t,
899 *pMpi2SGETransSimpleUnion_t;
900
901/****************************************************************************
902* All MPI SGE types union
903****************************************************************************/
904
905typedef struct _MPI2_MPI_SGE_UNION {
906 union {
907 MPI2_SGE_SIMPLE_UNION Simple;
908 MPI2_SGE_CHAIN_UNION Chain;
909 MPI2_SGE_TRANSACTION_UNION Transaction;
910 } u;
911} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
912 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
913
914/****************************************************************************
915* MPI SGE field definition and masks
916****************************************************************************/
917
918/*Flags field bit definitions */
919
920#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
921#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
922#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
923#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
924#define MPI2_SGE_FLAGS_DIRECTION (0x04)
925#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
926#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
927
928#define MPI2_SGE_FLAGS_SHIFT (24)
929
930#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
931#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
932
933/*Element Type */
934
935#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
936#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
937#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
938#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
939
940/*Address location */
941
942#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
943
944/*Direction */
945
946#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
947#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
948
949#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
950#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
951
952/*Address Size */
953
954#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
955#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
956
957/*Context Size */
958
959#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
960#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
961#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
962#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
963
964#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
965#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
966
967/****************************************************************************
968* MPI SGE operation Macros
969****************************************************************************/
970
971/*SIMPLE FlagsLength manipulations... */
972#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
973#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
974 MPI2_SGE_FLAGS_SHIFT)
975#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
976#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
977
978#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
979 MPI2_SGE_LENGTH(l))
980
981#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
982#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
983#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
984 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
985
986/*CAUTION - The following are READ-MODIFY-WRITE! */
987#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
988 MPI2_SGE_SET_FLAGS(f))
989#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
990 MPI2_SGE_LENGTH(l))
991
992#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
993 MPI2_SGE_CHAIN_OFFSET_SHIFT)
994
995/*****************************************************************************
996*
997* Fusion-MPT IEEE Scatter Gather Elements
998*
999*****************************************************************************/
1000
1001/****************************************************************************
1002* IEEE Simple Element structures
1003****************************************************************************/
1004
1005/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1006typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
1007 U32 Address;
1008 U32 FlagsLength;
1009} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
1010 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1011
1012typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1013 U64 Address;
1014 U32 Length;
1015 U16 Reserved1;
1016 U8 Reserved2;
1017 U8 Flags;
1018} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1019 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1020
1021typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1022 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1023 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1024} MPI2_IEEE_SGE_SIMPLE_UNION,
1025 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1026 Mpi2IeeeSgeSimpleUnion_t,
1027 *pMpi2IeeeSgeSimpleUnion_t;
1028
1029/****************************************************************************
1030* IEEE Chain Element structures
1031****************************************************************************/
1032
1033/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1034typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1035
1036/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1037typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1038
1039typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1040 MPI2_IEEE_SGE_CHAIN32 Chain32;
1041 MPI2_IEEE_SGE_CHAIN64 Chain64;
1042} MPI2_IEEE_SGE_CHAIN_UNION,
1043 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1044 Mpi2IeeeSgeChainUnion_t,
1045 *pMpi2IeeeSgeChainUnion_t;
1046
1047/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1048typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1049 U64 Address;
1050 U32 Length;
1051 U16 Reserved1;
1052 U8 NextChainOffset;
1053 U8 Flags;
1054} MPI25_IEEE_SGE_CHAIN64,
1055 *PTR_MPI25_IEEE_SGE_CHAIN64,
1056 Mpi25IeeeSgeChain64_t,
1057 *pMpi25IeeeSgeChain64_t;
1058
1059/****************************************************************************
1060* All IEEE SGE types union
1061****************************************************************************/
1062
1063/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1064typedef struct _MPI2_IEEE_SGE_UNION {
1065 union {
1066 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1067 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1068 } u;
1069} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1070 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1071
1072/****************************************************************************
1073* IEEE SGE union for IO SGL's
1074****************************************************************************/
1075
1076typedef union _MPI25_SGE_IO_UNION {
1077 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1078 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1079} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1080 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1081
1082/****************************************************************************
1083* IEEE SGE field definitions and masks
1084****************************************************************************/
1085
1086/*Flags field bit definitions */
1087
1088#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1089#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1090
1091#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1092
1093#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1094
1095/*Element Type */
1096
1097#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1098#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1099
1100/*Data Location Address Space */
1101
1102#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1103#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1104#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1105#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1106#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1107#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1108#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1109 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1110
1111/****************************************************************************
1112* IEEE SGE operation Macros
1113****************************************************************************/
1114
1115/*SIMPLE FlagsLength manipulations... */
1116#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1117#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1118 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1119#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1120
1121#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1122 MPI2_IEEE32_SGE_LENGTH(l))
1123
1124#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1125 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1126#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1127 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1128#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1129 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1130
1131/*CAUTION - The following are READ-MODIFY-WRITE! */
1132#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1133 MPI2_IEEE32_SGE_SET_FLAGS(f))
1134#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1135 MPI2_IEEE32_SGE_LENGTH(l))
1136
1137/*****************************************************************************
1138*
1139* Fusion-MPT MPI/IEEE Scatter Gather Unions
1140*
1141*****************************************************************************/
1142
1143typedef union _MPI2_SIMPLE_SGE_UNION {
1144 MPI2_SGE_SIMPLE_UNION MpiSimple;
1145 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1146} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1147 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1148
1149typedef union _MPI2_SGE_IO_UNION {
1150 MPI2_SGE_SIMPLE_UNION MpiSimple;
1151 MPI2_SGE_CHAIN_UNION MpiChain;
1152 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1153 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1154} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1155 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1156
1157/****************************************************************************
1158*
1159* Values for SGLFlags field, used in many request messages with an SGL
1160*
1161****************************************************************************/
1162
1163/*values for MPI SGL Data Location Address Space subfield */
1164#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1165#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1166#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1167#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1168#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1169/*values for SGL Type subfield */
1170#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1171#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1172#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1173#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1174
1175#endif