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gerrit-public.fairphone.software / kernel / msm-4.9 / 36356bcc4d6a4208f9b6088e1df9781351c6d7bf / . / arch / arm / boot / dts / am33xx.dtsi
blob: acd37057bca94377e5f092a754ee9cece5dede8a [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
Geert Uytterhoeven5c5be9d2014-03-28 11:11:37 +0100[diff] [blame]75 * The soc node represents the soc top level view. It is used for IPs
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
Roger Quadros63728d52014-09-09 16:28:01 +0300[diff] [blame]86 am33xx_control_module: control_module@4a002000 {
87 compatible = "syscon";
88 reg = <0x44e10000 0x7fc>;
89 };
90
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]91 am33xx_pinmux: pinmux@44e10800 {
92 compatible = "pinctrl-single";
93 reg = <0x44e10800 0x0238>;
94 #address-cells = <1>;
95 #size-cells = <0>;
96 pinctrl-single,register-width = <32>;
97 pinctrl-single,function-mask = <0x7f>;
98 };
99
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]100 /*
101 * XXX: Use a flat representation of the AM33XX interconnect.
Geert Uytterhoevenb7ab5242014-03-28 11:11:39 +0100[diff] [blame]102 * The real AM33XX interconnect network is quite complex. Since
103 * it will not bring real advantage to represent that in DT
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]104 * for the moment, just use a fake OCP bus entry to represent
105 * the whole bus hierarchy.
106 */
107 ocp {
108 compatible = "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112 ti,hwmods = "l3_main";
113
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]114 prcm: prcm@44e00000 {
115 compatible = "ti,am3-prcm";
116 reg = <0x44e00000 0x4000>;
117
118 prcm_clocks: clocks {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 };
122
123 prcm_clockdomains: clockdomains {
124 };
125 };
126
127 scrm: scrm@44e10000 {
128 compatible = "ti,am3-scrm";
129 reg = <0x44e10000 0x2000>;
130
131 scrm_clocks: clocks {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 };
135
136 scrm_clockdomains: clockdomains {
137 };
138 };
139
Markus Pargmannc9aaf872014-09-29 08:53:18 +0200[diff] [blame]140 cm: syscon@44e10000 {
141 compatible = "ti,am33xx-controlmodule", "syscon";
142 reg = <0x44e10000 0x800>;
143 };
144
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]145 intc: interrupt-controller@48200000 {
Felipe Balbicab82b72014-09-08 17:54:48 -0700[diff] [blame]146 compatible = "ti,am33xx-intc";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]147 interrupt-controller;
148 #interrupt-cells = <1>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]149 reg = <0x48200000 0x1000>;
150 };
151
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]152 edma: edma@49000000 {
153 compatible = "ti,edma3";
154 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
155 reg = <0x49000000 0x10000>,
Thomas Gleixnercf7eb972014-04-13 20:44:46 +0200[diff] [blame]156 <0x44e10f90 0x40>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]157 interrupts = <12 13 14>;
158 #dma-cells = <1>;
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]159 };
160
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]161 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 compatible = "ti,omap4-gpio";
163 ti,hwmods = "gpio1";
164 gpio-controller;
165 #gpio-cells = <2>;
166 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]167 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]168 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]170 };
171
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]172 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]173 compatible = "ti,omap4-gpio";
174 ti,hwmods = "gpio2";
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]178 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]180 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]181 };
182
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]183 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]184 compatible = "ti,omap4-gpio";
185 ti,hwmods = "gpio3";
186 gpio-controller;
187 #gpio-cells = <2>;
188 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]189 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]190 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]191 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]192 };
193
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]194 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]195 compatible = "ti,omap4-gpio";
196 ti,hwmods = "gpio4";
197 gpio-controller;
198 #gpio-cells = <2>;
199 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]200 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]201 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]202 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]203 };
204
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]205 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]206 compatible = "ti,omap3-uart";
207 ti,hwmods = "uart1";
208 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]210 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]211 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]212 dmas = <&edma 26>, <&edma 27>;
213 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]214 };
215
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]216 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]217 compatible = "ti,omap3-uart";
218 ti,hwmods = "uart2";
219 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]220 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]221 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]222 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]223 dmas = <&edma 28>, <&edma 29>;
224 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]225 };
226
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]227 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]228 compatible = "ti,omap3-uart";
229 ti,hwmods = "uart3";
230 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]231 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]232 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]233 status = "disabled";
Sebastian Andrzej Siewior13fd3d52014-09-29 20:06:46 +0200[diff] [blame]234 dmas = <&edma 30>, <&edma 31>;
235 dma-names = "tx", "rx";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]236 };
237
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]238 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]239 compatible = "ti,omap3-uart";
240 ti,hwmods = "uart4";
241 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]242 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]243 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]244 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]245 };
246
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]247 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 compatible = "ti,omap3-uart";
249 ti,hwmods = "uart5";
250 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]251 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]252 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]253 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]254 };
255
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]256 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]257 compatible = "ti,omap3-uart";
258 ti,hwmods = "uart6";
259 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]260 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]261 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]262 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]263 };
264
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]265 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]266 compatible = "ti,omap4-i2c";
267 #address-cells = <1>;
268 #size-cells = <0>;
269 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]270 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]271 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]272 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]273 };
274
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]275 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]276 compatible = "ti,omap4-i2c";
277 #address-cells = <1>;
278 #size-cells = <0>;
279 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]280 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]281 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]282 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]283 };
284
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]285 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]286 compatible = "ti,omap4-i2c";
287 #address-cells = <1>;
288 #size-cells = <0>;
289 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]290 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]291 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]292 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]293 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]294
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]295 mmc1: mmc@48060000 {
296 compatible = "ti,omap4-hsmmc";
297 ti,hwmods = "mmc1";
298 ti,dual-volt;
299 ti,needs-special-reset;
300 ti,needs-special-hs-handling;
301 dmas = <&edma 24
302 &edma 25>;
303 dma-names = "tx", "rx";
304 interrupts = <64>;
305 interrupt-parent = <&intc>;
306 reg = <0x48060000 0x1000>;
307 status = "disabled";
308 };
309
310 mmc2: mmc@481d8000 {
311 compatible = "ti,omap4-hsmmc";
312 ti,hwmods = "mmc2";
313 ti,needs-special-reset;
314 dmas = <&edma 2
315 &edma 3>;
316 dma-names = "tx", "rx";
317 interrupts = <28>;
318 interrupt-parent = <&intc>;
319 reg = <0x481d8000 0x1000>;
320 status = "disabled";
321 };
322
323 mmc3: mmc@47810000 {
324 compatible = "ti,omap4-hsmmc";
325 ti,hwmods = "mmc3";
326 ti,needs-special-reset;
327 interrupts = <29>;
328 interrupt-parent = <&intc>;
329 reg = <0x47810000 0x1000>;
330 status = "disabled";
331 };
332
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]333 hwspinlock: spinlock@480ca000 {
334 compatible = "ti,omap4-hwspinlock";
335 reg = <0x480ca000 0x1000>;
336 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]337 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]338 };
339
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]340 wdt2: wdt@44e35000 {
341 compatible = "ti,omap3-wdt";
342 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]343 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]344 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]345 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]346
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]347 dcan0: can@481cc000 {
348 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]349 ti,hwmods = "d_can0";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]350 reg = <0x481cc000 0x2000>;
351 clocks = <&dcan0_fck>;
352 clock-names = "fck";
353 syscon-raminit = <&am33xx_control_module 0x644 0>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]354 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]355 status = "disabled";
356 };
357
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]358 dcan1: can@481d0000 {
359 compatible = "ti,am3352-d_can";
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]360 ti,hwmods = "d_can1";
Roger Quadrose23aabc2014-09-09 16:15:35 +0300[diff] [blame]361 reg = <0x481d0000 0x2000>;
362 clocks = <&dcan1_fck>;
363 clock-names = "fck";
364 syscon-raminit = <&am33xx_control_module 0x644 1>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]365 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]366 status = "disabled";
367 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]368
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]369 mailbox: mailbox@480C8000 {
370 compatible = "ti,omap4-mailbox";
371 reg = <0x480C8000 0x200>;
372 interrupts = <77>;
373 ti,hwmods = "mailbox";
Suman Anna24df0452014-11-03 17:07:35 -0600[diff] [blame]374 #mbox-cells = <1>;
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]375 ti,mbox-num-users = <4>;
376 ti,mbox-num-fifos = <8>;
Suman Annad27704d2014-09-10 14:27:23 -0500[diff] [blame]377 mbox_wkupm3: wkup_m3 {
378 ti,mbox-tx = <0 0 0>;
379 ti,mbox-rx = <0 0 3>;
380 };
Suman Anna40242302014-07-11 16:44:36 -0500[diff] [blame]381 };
382
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]383 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]384 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]385 reg = <0x44e31000 0x400>;
386 interrupts = <67>;
387 ti,hwmods = "timer1";
388 ti,timer-alwon;
389 };
390
391 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]392 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]393 reg = <0x48040000 0x400>;
394 interrupts = <68>;
395 ti,hwmods = "timer2";
396 };
397
398 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]399 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]400 reg = <0x48042000 0x400>;
401 interrupts = <69>;
402 ti,hwmods = "timer3";
403 };
404
405 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]406 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]407 reg = <0x48044000 0x400>;
408 interrupts = <92>;
409 ti,hwmods = "timer4";
410 ti,timer-pwm;
411 };
412
413 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]414 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]415 reg = <0x48046000 0x400>;
416 interrupts = <93>;
417 ti,hwmods = "timer5";
418 ti,timer-pwm;
419 };
420
421 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]422 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]423 reg = <0x48048000 0x400>;
424 interrupts = <94>;
425 ti,hwmods = "timer6";
426 ti,timer-pwm;
427 };
428
429 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]430 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]431 reg = <0x4804a000 0x400>;
432 interrupts = <95>;
433 ti,hwmods = "timer7";
434 ti,timer-pwm;
435 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]436
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]437 rtc: rtc@44e3e000 {
Johan Hovold6ac7b4a2014-12-10 15:53:25 -0800[diff] [blame]438 compatible = "ti,am3352-rtc", "ti,da830-rtc";
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]439 reg = <0x44e3e000 0x1000>;
440 interrupts = <75
441 76>;
442 ti,hwmods = "rtc";
443 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]444
445 spi0: spi@48030000 {
446 compatible = "ti,omap4-mcspi";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]450 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]451 ti,spi-num-cs = <2>;
452 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]453 dmas = <&edma 16
454 &edma 17
455 &edma 18
456 &edma 19>;
457 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]458 status = "disabled";
459 };
460
461 spi1: spi@481a0000 {
462 compatible = "ti,omap4-mcspi";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]466 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]467 ti,spi-num-cs = <2>;
468 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]469 dmas = <&edma 42
470 &edma 43
471 &edma 44
472 &edma 45>;
473 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]474 status = "disabled";
475 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]476
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]477 usb: usb@47400000 {
478 compatible = "ti,am33xx-usb";
479 reg = <0x47400000 0x1000>;
480 ranges;
481 #address-cells = <1>;
482 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]483 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]484 status = "disabled";
485
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]486 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]487 compatible = "ti,am335x-usb-ctrl-module";
488 reg = <0x44e10620 0x10
489 0x44e10648 0x4>;
490 reg-names = "phy_ctrl", "wakeup";
491 status = "disabled";
492 };
493
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]494 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]495 compatible = "ti,am335x-usb-phy";
496 reg = <0x47401300 0x100>;
497 reg-names = "phy";
498 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]499 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]500 };
501
502 usb0: usb@47401000 {
503 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]504 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]505 reg = <0x47401400 0x400
506 0x47401000 0x200>;
507 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]508
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]509 interrupts = <18>;
510 interrupt-names = "mc";
511 dr_mode = "otg";
512 mentor,multipoint = <1>;
513 mentor,num-eps = <16>;
514 mentor,ram-bits = <12>;
515 mentor,power = <500>;
516 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]517
518 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
519 &cppi41dma 2 0 &cppi41dma 3 0
520 &cppi41dma 4 0 &cppi41dma 5 0
521 &cppi41dma 6 0 &cppi41dma 7 0
522 &cppi41dma 8 0 &cppi41dma 9 0
523 &cppi41dma 10 0 &cppi41dma 11 0
524 &cppi41dma 12 0 &cppi41dma 13 0
525 &cppi41dma 14 0 &cppi41dma 0 1
526 &cppi41dma 1 1 &cppi41dma 2 1
527 &cppi41dma 3 1 &cppi41dma 4 1
528 &cppi41dma 5 1 &cppi41dma 6 1
529 &cppi41dma 7 1 &cppi41dma 8 1
530 &cppi41dma 9 1 &cppi41dma 10 1
531 &cppi41dma 11 1 &cppi41dma 12 1
532 &cppi41dma 13 1 &cppi41dma 14 1>;
533 dma-names =
534 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
535 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
536 "rx14", "rx15",
537 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
538 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
539 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]540 };
541
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]542 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]543 compatible = "ti,am335x-usb-phy";
544 reg = <0x47401b00 0x100>;
545 reg-names = "phy";
546 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]547 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]548 };
549
550 usb1: usb@47401800 {
551 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]552 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]553 reg = <0x47401c00 0x400
554 0x47401800 0x200>;
555 reg-names = "mc", "control";
556 interrupts = <19>;
557 interrupt-names = "mc";
558 dr_mode = "otg";
559 mentor,multipoint = <1>;
560 mentor,num-eps = <16>;
561 mentor,ram-bits = <12>;
562 mentor,power = <500>;
563 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]564
565 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
566 &cppi41dma 17 0 &cppi41dma 18 0
567 &cppi41dma 19 0 &cppi41dma 20 0
568 &cppi41dma 21 0 &cppi41dma 22 0
569 &cppi41dma 23 0 &cppi41dma 24 0
570 &cppi41dma 25 0 &cppi41dma 26 0
571 &cppi41dma 27 0 &cppi41dma 28 0
572 &cppi41dma 29 0 &cppi41dma 15 1
573 &cppi41dma 16 1 &cppi41dma 17 1
574 &cppi41dma 18 1 &cppi41dma 19 1
575 &cppi41dma 20 1 &cppi41dma 21 1
576 &cppi41dma 22 1 &cppi41dma 23 1
577 &cppi41dma 24 1 &cppi41dma 25 1
578 &cppi41dma 26 1 &cppi41dma 27 1
579 &cppi41dma 28 1 &cppi41dma 29 1>;
580 dma-names =
581 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
582 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
583 "rx14", "rx15",
584 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
585 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
586 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]587 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]588
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]589 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]590 compatible = "ti,am3359-cppi41";
591 reg = <0x47400000 0x1000
592 0x47402000 0x1000
593 0x47403000 0x1000
594 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]595 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]596 interrupts = <17>;
597 interrupt-names = "glue";
598 #dma-cells = <2>;
599 #dma-channels = <30>;
600 #dma-requests = <256>;
601 status = "disabled";
602 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]603 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]604
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]605 epwmss0: epwmss@48300000 {
606 compatible = "ti,am33xx-pwmss";
607 reg = <0x48300000 0x10>;
608 ti,hwmods = "epwmss0";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 status = "disabled";
612 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
613 0x48300180 0x48300180 0x80 /* EQEP */
614 0x48300200 0x48300200 0x80>; /* EHRPWM */
615
616 ecap0: ecap@48300100 {
617 compatible = "ti,am33xx-ecap";
618 #pwm-cells = <3>;
619 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]620 interrupts = <31>;
621 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]622 ti,hwmods = "ecap0";
623 status = "disabled";
624 };
625
626 ehrpwm0: ehrpwm@48300200 {
627 compatible = "ti,am33xx-ehrpwm";
628 #pwm-cells = <3>;
629 reg = <0x48300200 0x80>;
630 ti,hwmods = "ehrpwm0";
631 status = "disabled";
632 };
633 };
634
635 epwmss1: epwmss@48302000 {
636 compatible = "ti,am33xx-pwmss";
637 reg = <0x48302000 0x10>;
638 ti,hwmods = "epwmss1";
639 #address-cells = <1>;
640 #size-cells = <1>;
641 status = "disabled";
642 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
643 0x48302180 0x48302180 0x80 /* EQEP */
644 0x48302200 0x48302200 0x80>; /* EHRPWM */
645
646 ecap1: ecap@48302100 {
647 compatible = "ti,am33xx-ecap";
648 #pwm-cells = <3>;
649 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]650 interrupts = <47>;
651 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]652 ti,hwmods = "ecap1";
653 status = "disabled";
654 };
655
656 ehrpwm1: ehrpwm@48302200 {
657 compatible = "ti,am33xx-ehrpwm";
658 #pwm-cells = <3>;
659 reg = <0x48302200 0x80>;
660 ti,hwmods = "ehrpwm1";
661 status = "disabled";
662 };
663 };
664
665 epwmss2: epwmss@48304000 {
666 compatible = "ti,am33xx-pwmss";
667 reg = <0x48304000 0x10>;
668 ti,hwmods = "epwmss2";
669 #address-cells = <1>;
670 #size-cells = <1>;
671 status = "disabled";
672 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
673 0x48304180 0x48304180 0x80 /* EQEP */
674 0x48304200 0x48304200 0x80>; /* EHRPWM */
675
676 ecap2: ecap@48304100 {
677 compatible = "ti,am33xx-ecap";
678 #pwm-cells = <3>;
679 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]680 interrupts = <61>;
681 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]682 ti,hwmods = "ecap2";
683 status = "disabled";
684 };
685
686 ehrpwm2: ehrpwm@48304200 {
687 compatible = "ti,am33xx-ehrpwm";
688 #pwm-cells = <3>;
689 reg = <0x48304200 0x80>;
690 ti,hwmods = "ehrpwm2";
691 status = "disabled";
692 };
693 };
694
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]695 mac: ethernet@4a100000 {
696 compatible = "ti,cpsw";
697 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame]698 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
699 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]700 cpdma_channels = <8>;
701 ale_entries = <1024>;
702 bd_ram_size = <0x2000>;
703 no_bd_ram = <0>;
704 rx_descs = <64>;
705 mac_control = <0x20>;
706 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]707 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]708 cpts_clock_mult = <0x80000000>;
709 cpts_clock_shift = <29>;
710 reg = <0x4a100000 0x800
711 0x4a101200 0x100>;
712 #address-cells = <1>;
713 #size-cells = <1>;
714 interrupt-parent = <&intc>;
715 /*
716 * c0_rx_thresh_pend
717 * c0_rx_pend
718 * c0_tx_pend
719 * c0_misc_pend
720 */
721 interrupts = <40 41 42 43>;
722 ranges;
Markus Pargmannfa5f4ad2014-09-29 08:53:19 +0200[diff] [blame]723 syscon = <&cm>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]724 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]725
726 davinci_mdio: mdio@4a101000 {
727 compatible = "ti,davinci_mdio";
728 #address-cells = <1>;
729 #size-cells = <0>;
730 ti,hwmods = "davinci_mdio";
731 bus_freq = <1000000>;
732 reg = <0x4a101000 0x100>;
Johan Hovold16c75a12014-05-08 10:57:36 +0200[diff] [blame]733 status = "disabled";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]734 };
735
736 cpsw_emac0: slave@4a100200 {
737 /* Filled in by U-Boot */
738 mac-address = [ 00 00 00 00 00 00 ];
739 };
740
741 cpsw_emac1: slave@4a100300 {
742 /* Filled in by U-Boot */
743 mac-address = [ 00 00 00 00 00 00 ];
744 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]745
746 phy_sel: cpsw-phy-sel@44e10650 {
747 compatible = "ti,am3352-cpsw-phy-sel";
748 reg= <0x44e10650 0x4>;
749 reg-names = "gmii-sel";
750 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]751 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]752
753 ocmcram: ocmcram@40300000 {
Rajendra Nayak8b9a2812014-09-10 11:04:03 -0500[diff] [blame]754 compatible = "mmio-sram";
755 reg = <0x40300000 0x10000>; /* 64k */
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]756 };
757
758 wkup_m3: wkup_m3@44d00000 {
759 compatible = "ti,am3353-wkup-m3";
760 reg = <0x44d00000 0x4000 /* M3 UMEM */
761 0x44d80000 0x2000>; /* M3 DMEM */
762 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]763 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]764 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]765
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]766 elm: elm@48080000 {
767 compatible = "ti,am3352-elm";
768 reg = <0x48080000 0x2000>;
769 interrupts = <4>;
770 ti,hwmods = "elm";
771 status = "disabled";
772 };
773
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]774 lcdc: lcdc@4830e000 {
775 compatible = "ti,am33xx-tilcdc";
776 reg = <0x4830e000 0x1000>;
777 interrupt-parent = <&intc>;
778 interrupts = <36>;
779 ti,hwmods = "lcdc";
780 status = "disabled";
781 };
782
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]783 tscadc: tscadc@44e0d000 {
784 compatible = "ti,am3359-tscadc";
785 reg = <0x44e0d000 0x1000>;
786 interrupt-parent = <&intc>;
787 interrupts = <16>;
788 ti,hwmods = "adc_tsc";
789 status = "disabled";
790
791 tsc {
792 compatible = "ti,am3359-tsc";
793 };
794 am335x_adc: adc {
795 #io-channel-cells = <1>;
796 compatible = "ti,am3359-adc";
797 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]798 };
799
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]800 gpmc: gpmc@50000000 {
801 compatible = "ti,am3352-gpmc";
802 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]803 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]804 reg = <0x50000000 0x2000>;
805 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]806 gpmc,num-cs = <7>;
807 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]808 #address-cells = <2>;
809 #size-cells = <1>;
810 status = "disabled";
811 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]812
813 sham: sham@53100000 {
814 compatible = "ti,omap4-sham";
815 ti,hwmods = "sham";
816 reg = <0x53100000 0x200>;
817 interrupts = <109>;
818 dmas = <&edma 36>;
819 dma-names = "rx";
820 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]821
822 aes: aes@53500000 {
823 compatible = "ti,omap4-aes";
824 ti,hwmods = "aes";
825 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]826 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]827 dmas = <&edma 6>,
828 <&edma 5>;
829 dma-names = "tx", "rx";
830 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]831
832 mcasp0: mcasp@48038000 {
833 compatible = "ti,am33xx-mcasp-audio";
834 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]835 reg = <0x48038000 0x2000>,
836 <0x46000000 0x400000>;
837 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]838 interrupts = <80>, <81>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]839 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]840 status = "disabled";
841 dmas = <&edma 8>,
842 <&edma 9>;
843 dma-names = "tx", "rx";
844 };
845
846 mcasp1: mcasp@4803C000 {
847 compatible = "ti,am33xx-mcasp-audio";
848 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]849 reg = <0x4803C000 0x2000>,
850 <0x46400000 0x400000>;
851 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]852 interrupts = <82>, <83>;
Geert Uytterhoevenae107d02014-04-22 20:40:25 +0200[diff] [blame]853 interrupt-names = "tx", "rx";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]854 status = "disabled";
855 dmas = <&edma 10>,
856 <&edma 11>;
857 dma-names = "tx", "rx";
858 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]859
860 rng: rng@48310000 {
861 compatible = "ti,omap4-rng";
862 ti,hwmods = "rng";
863 reg = <0x48310000 0x2000>;
864 interrupts = <111>;
865 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]866 };
867};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]868
869/include/ "am33xx-clocks.dtsi"