blob: b26f7e3172790c14d60469944e607c092c0595f2 [file] [log] [blame]
David Howells61730c52012-10-09 09:47:14 +01001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _UAPI_ASM_PTRACE_H
10#define _UAPI_ASM_PTRACE_H
11
12/* 0 - 31 are integer registers, 32 - 63 are fp registers. */
13#define FPR_BASE 32
14#define PC 64
15#define CAUSE 65
16#define BADVADDR 66
17#define MMHI 67
18#define MMLO 68
19#define FPC_CSR 69
20#define FPC_EIR 70
21#define DSP_BASE 71 /* 3 more hi / lo register pairs */
22#define DSP_CONTROL 77
23#define ACX 78
24
David Daney8f657932013-05-22 22:35:56 +000025#ifndef __KERNEL__
David Howells61730c52012-10-09 09:47:14 +010026/*
27 * This struct defines the way the registers are stored on the stack during a
28 * system call/exception. As usual the registers k0/k1 aren't being saved.
29 */
30struct pt_regs {
David Howells61730c52012-10-09 09:47:14 +010031 /* Saved main processor registers. */
32 unsigned long regs[32];
33
34 /* Saved special registers. */
35 unsigned long cp0_status;
36 unsigned long hi;
37 unsigned long lo;
David Howells61730c52012-10-09 09:47:14 +010038 unsigned long cp0_badvaddr;
39 unsigned long cp0_cause;
40 unsigned long cp0_epc;
David Howells61730c52012-10-09 09:47:14 +010041} __attribute__ ((aligned (8)));
David Daney8f657932013-05-22 22:35:56 +000042#endif /* __KERNEL__ */
David Howells61730c52012-10-09 09:47:14 +010043
44/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
45#define PTRACE_GETREGS 12
46#define PTRACE_SETREGS 13
47#define PTRACE_GETFPREGS 14
48#define PTRACE_SETFPREGS 15
49/* #define PTRACE_GETFPXREGS 18 */
50/* #define PTRACE_SETFPXREGS 19 */
51
52#define PTRACE_OLDSETOPTIONS 21
53
54#define PTRACE_GET_THREAD_AREA 25
55#define PTRACE_SET_THREAD_AREA 26
56
Ralf Baechle70342282013-01-22 12:59:30 +010057/* Calls to trace a 64bit program from a 32bit program. */
David Howells61730c52012-10-09 09:47:14 +010058#define PTRACE_PEEKTEXT_3264 0xc0
59#define PTRACE_PEEKDATA_3264 0xc1
60#define PTRACE_POKETEXT_3264 0xc2
61#define PTRACE_POKEDATA_3264 0xc3
62#define PTRACE_GET_THREAD_AREA_3264 0xc4
63
Ralf Baechle70342282013-01-22 12:59:30 +010064/* Read and write watchpoint registers. */
David Howells61730c52012-10-09 09:47:14 +010065enum pt_watch_style {
66 pt_watch_style_mips32,
67 pt_watch_style_mips64
68};
69struct mips32_watch_regs {
70 unsigned int watchlo[8];
71 /* Lower 16 bits of watchhi. */
72 unsigned short watchhi[8];
73 /* Valid mask and I R W bits.
74 * bit 0 -- 1 if W bit is usable.
75 * bit 1 -- 1 if R bit is usable.
76 * bit 2 -- 1 if I bit is usable.
77 * bits 3 - 11 -- Valid watchhi mask bits.
78 */
79 unsigned short watch_masks[8];
80 /* The number of valid watch register pairs. */
81 unsigned int num_valid;
82} __attribute__((aligned(8)));
83
84struct mips64_watch_regs {
85 unsigned long long watchlo[8];
86 unsigned short watchhi[8];
87 unsigned short watch_masks[8];
88 unsigned int num_valid;
89} __attribute__((aligned(8)));
90
91struct pt_watch_regs {
92 enum pt_watch_style style;
93 union {
94 struct mips32_watch_regs mips32;
95 struct mips64_watch_regs mips64;
96 };
97};
98
99#define PTRACE_GET_WATCH_REGS 0xd0
100#define PTRACE_SET_WATCH_REGS 0xd1
101
102
103#endif /* _UAPI_ASM_PTRACE_H */