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Magnus Damm9570ef22009-05-01 06:51:00 +00001/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090032#include <linux/sh_timer.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Magnus Damm9570ef22009-05-01 06:51:00 +000034
35struct sh_tmu_priv {
36 void __iomem *mapbase;
37 struct clk *clk;
38 struct irqaction irqaction;
39 struct platform_device *pdev;
40 unsigned long rate;
41 unsigned long periodic;
42 struct clock_event_device ced;
43 struct clocksource cs;
44};
45
46static DEFINE_SPINLOCK(sh_tmu_lock);
47
48#define TSTR -1 /* shared register */
49#define TCOR 0 /* channel register */
50#define TCNT 1 /* channel register */
51#define TCR 2 /* channel register */
52
53static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
54{
Paul Mundt46a12f72009-05-03 17:57:17 +090055 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000056 void __iomem *base = p->mapbase;
57 unsigned long offs;
58
59 if (reg_nr == TSTR)
60 return ioread8(base - cfg->channel_offset);
61
62 offs = reg_nr << 2;
63
64 if (reg_nr == TCR)
65 return ioread16(base + offs);
66 else
67 return ioread32(base + offs);
68}
69
70static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
71 unsigned long value)
72{
Paul Mundt46a12f72009-05-03 17:57:17 +090073 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000074 void __iomem *base = p->mapbase;
75 unsigned long offs;
76
77 if (reg_nr == TSTR) {
78 iowrite8(value, base - cfg->channel_offset);
79 return;
80 }
81
82 offs = reg_nr << 2;
83
84 if (reg_nr == TCR)
85 iowrite16(value, base + offs);
86 else
87 iowrite32(value, base + offs);
88}
89
90static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
91{
Paul Mundt46a12f72009-05-03 17:57:17 +090092 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +000093 unsigned long flags, value;
94
95 /* start stop register shared by multiple timer channels */
96 spin_lock_irqsave(&sh_tmu_lock, flags);
97 value = sh_tmu_read(p, TSTR);
98
99 if (start)
100 value |= 1 << cfg->timer_bit;
101 else
102 value &= ~(1 << cfg->timer_bit);
103
104 sh_tmu_write(p, TSTR, value);
105 spin_unlock_irqrestore(&sh_tmu_lock, flags);
106}
107
108static int sh_tmu_enable(struct sh_tmu_priv *p)
109{
Magnus Damm9570ef22009-05-01 06:51:00 +0000110 int ret;
111
Paul Mundtd4905ce2011-05-31 15:23:20 +0900112 /* enable clock */
Magnus Damm9570ef22009-05-01 06:51:00 +0000113 ret = clk_enable(p->clk);
114 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900115 dev_err(&p->pdev->dev, "cannot enable clock\n");
Magnus Damm9570ef22009-05-01 06:51:00 +0000116 return ret;
117 }
118
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p, 0);
121
122 /* maximum timeout */
123 sh_tmu_write(p, TCOR, 0xffffffff);
124 sh_tmu_write(p, TCNT, 0xffffffff);
125
126 /* configure channel to parent clock / 4, irq off */
127 p->rate = clk_get_rate(p->clk) / 4;
128 sh_tmu_write(p, TCR, 0x0000);
129
130 /* enable channel */
131 sh_tmu_start_stop_ch(p, 1);
132
133 return 0;
134}
135
136static void sh_tmu_disable(struct sh_tmu_priv *p)
137{
138 /* disable channel */
139 sh_tmu_start_stop_ch(p, 0);
140
Magnus Dammbe890a12009-06-17 05:04:04 +0000141 /* disable interrupts in TMU block */
142 sh_tmu_write(p, TCR, 0x0000);
143
Paul Mundtd4905ce2011-05-31 15:23:20 +0900144 /* stop clock */
Magnus Damm9570ef22009-05-01 06:51:00 +0000145 clk_disable(p->clk);
146}
147
148static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
149 int periodic)
150{
151 /* stop timer */
152 sh_tmu_start_stop_ch(p, 0);
153
154 /* acknowledge interrupt */
155 sh_tmu_read(p, TCR);
156
157 /* enable interrupt */
158 sh_tmu_write(p, TCR, 0x0020);
159
160 /* reload delta value in case of periodic timer */
161 if (periodic)
162 sh_tmu_write(p, TCOR, delta);
163 else
Shin-ichiro KAWASAKI6f4b67b2009-06-21 10:56:22 +0000164 sh_tmu_write(p, TCOR, 0xffffffff);
Magnus Damm9570ef22009-05-01 06:51:00 +0000165
166 sh_tmu_write(p, TCNT, delta);
167
168 /* start timer */
169 sh_tmu_start_stop_ch(p, 1);
170}
171
172static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
173{
174 struct sh_tmu_priv *p = dev_id;
175
176 /* disable or acknowledge interrupt */
177 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
178 sh_tmu_write(p, TCR, 0x0000);
179 else
180 sh_tmu_write(p, TCR, 0x0020);
181
182 /* notify clockevent layer */
183 p->ced.event_handler(&p->ced);
184 return IRQ_HANDLED;
185}
186
187static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
188{
189 return container_of(cs, struct sh_tmu_priv, cs);
190}
191
192static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
193{
194 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
195
196 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
197}
198
199static int sh_tmu_clocksource_enable(struct clocksource *cs)
200{
201 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
Magnus Damm0aeac452011-04-25 22:38:37 +0900202 int ret;
Magnus Damm9570ef22009-05-01 06:51:00 +0000203
Magnus Damm0aeac452011-04-25 22:38:37 +0900204 ret = sh_tmu_enable(p);
205 if (!ret)
206 __clocksource_updatefreq_hz(cs, p->rate);
207 return ret;
Magnus Damm9570ef22009-05-01 06:51:00 +0000208}
209
210static void sh_tmu_clocksource_disable(struct clocksource *cs)
211{
212 sh_tmu_disable(cs_to_sh_tmu(cs));
213}
214
215static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
216 char *name, unsigned long rating)
217{
218 struct clocksource *cs = &p->cs;
219
220 cs->name = name;
221 cs->rating = rating;
222 cs->read = sh_tmu_clocksource_read;
223 cs->enable = sh_tmu_clocksource_enable;
224 cs->disable = sh_tmu_clocksource_disable;
225 cs->mask = CLOCKSOURCE_MASK(32);
226 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
Aurelien Jarno66f49122010-05-31 21:45:48 +0000227
Paul Mundt214a6072010-03-10 16:26:25 +0900228 dev_info(&p->pdev->dev, "used as clock source\n");
Magnus Damm0aeac452011-04-25 22:38:37 +0900229
230 /* Register with dummy 1 Hz value, gets updated in ->enable() */
231 clocksource_register_hz(cs, 1);
Magnus Damm9570ef22009-05-01 06:51:00 +0000232 return 0;
233}
234
235static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
236{
237 return container_of(ced, struct sh_tmu_priv, ced);
238}
239
240static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
241{
242 struct clock_event_device *ced = &p->ced;
243
244 sh_tmu_enable(p);
245
246 /* TODO: calculate good shift from rate and counter bit width */
247
248 ced->shift = 32;
249 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
250 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
251 ced->min_delta_ns = 5000;
252
253 if (periodic) {
254 p->periodic = (p->rate + HZ/2) / HZ;
255 sh_tmu_set_next(p, p->periodic, 1);
256 }
257}
258
259static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
260 struct clock_event_device *ced)
261{
262 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
263 int disabled = 0;
264
265 /* deal with old setting first */
266 switch (ced->mode) {
267 case CLOCK_EVT_MODE_PERIODIC:
268 case CLOCK_EVT_MODE_ONESHOT:
269 sh_tmu_disable(p);
270 disabled = 1;
271 break;
272 default:
273 break;
274 }
275
276 switch (mode) {
277 case CLOCK_EVT_MODE_PERIODIC:
Paul Mundt214a6072010-03-10 16:26:25 +0900278 dev_info(&p->pdev->dev, "used for periodic clock events\n");
Magnus Damm9570ef22009-05-01 06:51:00 +0000279 sh_tmu_clock_event_start(p, 1);
280 break;
281 case CLOCK_EVT_MODE_ONESHOT:
Paul Mundt214a6072010-03-10 16:26:25 +0900282 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
Magnus Damm9570ef22009-05-01 06:51:00 +0000283 sh_tmu_clock_event_start(p, 0);
284 break;
285 case CLOCK_EVT_MODE_UNUSED:
286 if (!disabled)
287 sh_tmu_disable(p);
288 break;
289 case CLOCK_EVT_MODE_SHUTDOWN:
290 default:
291 break;
292 }
293}
294
295static int sh_tmu_clock_event_next(unsigned long delta,
296 struct clock_event_device *ced)
297{
298 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
299
300 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
301
302 /* program new delta value */
303 sh_tmu_set_next(p, delta, 0);
304 return 0;
305}
306
307static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
308 char *name, unsigned long rating)
309{
310 struct clock_event_device *ced = &p->ced;
311 int ret;
312
313 memset(ced, 0, sizeof(*ced));
314
315 ced->name = name;
316 ced->features = CLOCK_EVT_FEAT_PERIODIC;
317 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
318 ced->rating = rating;
319 ced->cpumask = cpumask_of(0);
320 ced->set_next_event = sh_tmu_clock_event_next;
321 ced->set_mode = sh_tmu_clock_event_mode;
322
Paul Mundt214a6072010-03-10 16:26:25 +0900323 dev_info(&p->pdev->dev, "used for clock events\n");
Paul Mundtda64c2a2010-02-25 16:37:46 +0900324 clockevents_register_device(ced);
325
Magnus Damm9570ef22009-05-01 06:51:00 +0000326 ret = setup_irq(p->irqaction.irq, &p->irqaction);
327 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900328 dev_err(&p->pdev->dev, "failed to request irq %d\n",
329 p->irqaction.irq);
Magnus Damm9570ef22009-05-01 06:51:00 +0000330 return;
331 }
Magnus Damm9570ef22009-05-01 06:51:00 +0000332}
333
334static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
335 unsigned long clockevent_rating,
336 unsigned long clocksource_rating)
337{
338 if (clockevent_rating)
339 sh_tmu_register_clockevent(p, name, clockevent_rating);
340 else if (clocksource_rating)
341 sh_tmu_register_clocksource(p, name, clocksource_rating);
342
343 return 0;
344}
345
346static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
347{
Paul Mundt46a12f72009-05-03 17:57:17 +0900348 struct sh_timer_config *cfg = pdev->dev.platform_data;
Magnus Damm9570ef22009-05-01 06:51:00 +0000349 struct resource *res;
350 int irq, ret;
351 ret = -ENXIO;
352
353 memset(p, 0, sizeof(*p));
354 p->pdev = pdev;
355
356 if (!cfg) {
357 dev_err(&p->pdev->dev, "missing platform data\n");
358 goto err0;
359 }
360
361 platform_set_drvdata(pdev, p);
362
363 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
364 if (!res) {
365 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
366 goto err0;
367 }
368
369 irq = platform_get_irq(p->pdev, 0);
370 if (irq < 0) {
371 dev_err(&p->pdev->dev, "failed to get irq\n");
372 goto err0;
373 }
374
375 /* map memory, let mapbase point to our channel */
376 p->mapbase = ioremap_nocache(res->start, resource_size(res));
377 if (p->mapbase == NULL) {
Paul Mundt214a6072010-03-10 16:26:25 +0900378 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
Magnus Damm9570ef22009-05-01 06:51:00 +0000379 goto err0;
380 }
381
382 /* setup data for setup_irq() (too early for request_irq()) */
Paul Mundt214a6072010-03-10 16:26:25 +0900383 p->irqaction.name = dev_name(&p->pdev->dev);
Magnus Damm9570ef22009-05-01 06:51:00 +0000384 p->irqaction.handler = sh_tmu_interrupt;
385 p->irqaction.dev_id = p;
386 p->irqaction.irq = irq;
Paul Mundtfecf0662010-04-15 11:59:28 +0900387 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
388 IRQF_IRQPOLL | IRQF_NOBALANCING;
Magnus Damm9570ef22009-05-01 06:51:00 +0000389
390 /* get hold of clock */
Paul Mundtc2a25e82010-03-29 16:55:43 +0900391 p->clk = clk_get(&p->pdev->dev, "tmu_fck");
Magnus Damm9570ef22009-05-01 06:51:00 +0000392 if (IS_ERR(p->clk)) {
Magnus Damm03ff8582010-10-13 07:36:38 +0000393 dev_err(&p->pdev->dev, "cannot get clock\n");
394 ret = PTR_ERR(p->clk);
395 goto err1;
Magnus Damm9570ef22009-05-01 06:51:00 +0000396 }
397
Paul Mundt214a6072010-03-10 16:26:25 +0900398 return sh_tmu_register(p, (char *)dev_name(&p->pdev->dev),
Magnus Damm9570ef22009-05-01 06:51:00 +0000399 cfg->clockevent_rating,
400 cfg->clocksource_rating);
401 err1:
402 iounmap(p->mapbase);
403 err0:
404 return ret;
405}
406
407static int __devinit sh_tmu_probe(struct platform_device *pdev)
408{
409 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
Magnus Damm9570ef22009-05-01 06:51:00 +0000410 int ret;
411
412 if (p) {
Paul Mundt214a6072010-03-10 16:26:25 +0900413 dev_info(&pdev->dev, "kept as earlytimer\n");
Magnus Damm9570ef22009-05-01 06:51:00 +0000414 return 0;
415 }
416
417 p = kmalloc(sizeof(*p), GFP_KERNEL);
418 if (p == NULL) {
419 dev_err(&pdev->dev, "failed to allocate driver data\n");
420 return -ENOMEM;
421 }
422
423 ret = sh_tmu_setup(p, pdev);
424 if (ret) {
425 kfree(p);
426 platform_set_drvdata(pdev, NULL);
427 }
Magnus Damm9570ef22009-05-01 06:51:00 +0000428 return ret;
429}
430
431static int __devexit sh_tmu_remove(struct platform_device *pdev)
432{
433 return -EBUSY; /* cannot unregister clockevent and clocksource */
434}
435
436static struct platform_driver sh_tmu_device_driver = {
437 .probe = sh_tmu_probe,
438 .remove = __devexit_p(sh_tmu_remove),
439 .driver = {
440 .name = "sh_tmu",
441 }
442};
443
444static int __init sh_tmu_init(void)
445{
446 return platform_driver_register(&sh_tmu_device_driver);
447}
448
449static void __exit sh_tmu_exit(void)
450{
451 platform_driver_unregister(&sh_tmu_device_driver);
452}
453
454early_platform_init("earlytimer", &sh_tmu_device_driver);
455module_init(sh_tmu_init);
456module_exit(sh_tmu_exit);
457
458MODULE_AUTHOR("Magnus Damm");
459MODULE_DESCRIPTION("SuperH TMU Timer Driver");
460MODULE_LICENSE("GPL v2");