Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 38451998fb8a5f9c933b2c462a790d5633605ac8 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob: 94d3d845d36ef057a75d67874d84583cdbce462d [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
45static int rtl8xxxu_debug;
46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57
58module_param_named(debug, rtl8xxxu_debug, int, 0600);
59MODULE_PARM_DESC(debug, "Set debug mask");
60module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
61MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
62
63#define USB_VENDOR_ID_REALTEK 0x0bda
64/* Minimum IEEE80211_MAX_FRAME_LEN */
65#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
66#define RTL8XXXU_RX_URBS 32
67#define RTL8XXXU_RX_URB_PENDING_WATER 8
68#define RTL8XXXU_TX_URBS 64
69#define RTL8XXXU_TX_URB_LOW_WATER 25
70#define RTL8XXXU_TX_URB_HIGH_WATER 32
71
72static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
73 struct rtl8xxxu_rx_urb *rx_urb);
74
75static struct ieee80211_rate rtl8xxxu_rates[] = {
76 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
77 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
78 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
79 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
80 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
81 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
82 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
83 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
84 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
85 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
86 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
87 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
88};
89
90static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
91 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
92 .hw_value = 1, .max_power = 30 },
93 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
94 .hw_value = 2, .max_power = 30 },
95 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
96 .hw_value = 3, .max_power = 30 },
97 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
98 .hw_value = 4, .max_power = 30 },
99 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
100 .hw_value = 5, .max_power = 30 },
101 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
102 .hw_value = 6, .max_power = 30 },
103 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
104 .hw_value = 7, .max_power = 30 },
105 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
106 .hw_value = 8, .max_power = 30 },
107 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
108 .hw_value = 9, .max_power = 30 },
109 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
110 .hw_value = 10, .max_power = 30 },
111 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
112 .hw_value = 11, .max_power = 30 },
113 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
114 .hw_value = 12, .max_power = 30 },
115 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
116 .hw_value = 13, .max_power = 30 },
117 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
118 .hw_value = 14, .max_power = 30 }
119};
120
121static struct ieee80211_supported_band rtl8xxxu_supported_band = {
122 .channels = rtl8xxxu_channels_2g,
123 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
124 .bitrates = rtl8xxxu_rates,
125 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
126};
127
128static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
129 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
130 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
131 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
132 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
133 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
134 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
135 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
136 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
137 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
138 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
139 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
140 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
141 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
142 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
143 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
144 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
145 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
146 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
147 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
148 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
149 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
150 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
151};
152
153static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
154 {0x800, 0x80040000}, {0x804, 0x00000003},
155 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
156 {0x810, 0x10001331}, {0x814, 0x020c3d10},
157 {0x818, 0x02200385}, {0x81c, 0x00000000},
158 {0x820, 0x01000100}, {0x824, 0x00390004},
159 {0x828, 0x00000000}, {0x82c, 0x00000000},
160 {0x830, 0x00000000}, {0x834, 0x00000000},
161 {0x838, 0x00000000}, {0x83c, 0x00000000},
162 {0x840, 0x00010000}, {0x844, 0x00000000},
163 {0x848, 0x00000000}, {0x84c, 0x00000000},
164 {0x850, 0x00000000}, {0x854, 0x00000000},
165 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
166 {0x860, 0x66f60110}, {0x864, 0x061f0130},
167 {0x868, 0x00000000}, {0x86c, 0x32323200},
168 {0x870, 0x07000760}, {0x874, 0x22004000},
169 {0x878, 0x00000808}, {0x87c, 0x00000000},
170 {0x880, 0xc0083070}, {0x884, 0x000004d5},
171 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
172 {0x890, 0x00000800}, {0x894, 0xfffffffe},
173 {0x898, 0x40302010}, {0x89c, 0x00706050},
174 {0x900, 0x00000000}, {0x904, 0x00000023},
175 {0x908, 0x00000000}, {0x90c, 0x81121111},
176 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
177 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
178 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
179 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
180 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
181 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
182 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
183 {0xa78, 0x00000900},
184 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
185 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
186 {0xc10, 0x08800000}, {0xc14, 0x40000100},
187 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
188 {0xc20, 0x00000000}, {0xc24, 0x00000000},
189 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
190 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
191 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
192 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
193 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
194 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
195 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
196 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
197 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
198 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
199 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
200 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
201 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
202 {0xc90, 0x00121820}, {0xc94, 0x00000000},
203 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
204 {0xca0, 0x00000000}, {0xca4, 0x00000080},
205 {0xca8, 0x00000000}, {0xcac, 0x00000000},
206 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
207 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
208 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
209 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
210 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
211 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
212 {0xce0, 0x00222222}, {0xce4, 0x00000000},
213 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
214 {0xd00, 0x00080740}, {0xd04, 0x00020401},
215 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
216 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
217 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
218 {0xd30, 0x00000000}, {0xd34, 0x80608000},
219 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
220 {0xd40, 0x00000000}, {0xd44, 0x00000000},
221 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
222 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
223 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
224 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
225 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
226 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
227 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
228 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
229 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
230 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
231 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
232 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
233 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
234 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
235 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
236 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
237 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
238 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
239 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
240 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
241 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
242 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
243 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
244 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
245 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
246 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
247 {0xf00, 0x00000300},
248 {0xffff, 0xffffffff},
249};
250
251static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
252 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
253 {0x800, 0x80040002}, {0x804, 0x00000003},
254 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
255 {0x810, 0x10000330}, {0x814, 0x020c3d10},
256 {0x818, 0x02200385}, {0x81c, 0x00000000},
257 {0x820, 0x01000100}, {0x824, 0x00390004},
258 {0x828, 0x01000100}, {0x82c, 0x00390004},
259 {0x830, 0x27272727}, {0x834, 0x27272727},
260 {0x838, 0x27272727}, {0x83c, 0x27272727},
261 {0x840, 0x00010000}, {0x844, 0x00010000},
262 {0x848, 0x27272727}, {0x84c, 0x27272727},
263 {0x850, 0x00000000}, {0x854, 0x00000000},
264 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
265 {0x860, 0x66e60230}, {0x864, 0x061f0130},
266 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
267 {0x870, 0x07000700}, {0x874, 0x22184000},
268 {0x878, 0x08080808}, {0x87c, 0x00000000},
269 {0x880, 0xc0083070}, {0x884, 0x000004d5},
270 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
271 {0x890, 0x00000800}, {0x894, 0xfffffffe},
272 {0x898, 0x40302010}, {0x89c, 0x00706050},
273 {0x900, 0x00000000}, {0x904, 0x00000023},
274 {0x908, 0x00000000}, {0x90c, 0x81121313},
275 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
276 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
277 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
278 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
279 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
280 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
281 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
282 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
283 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
284 {0xc10, 0x08800000}, {0xc14, 0x40000100},
285 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
286 {0xc20, 0x00000000}, {0xc24, 0x00000000},
287 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
288 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
289 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
290 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
291 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
292 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
293 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
294 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
295 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
296 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
297 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
298 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
299 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
300 {0xc90, 0x00121820}, {0xc94, 0x00000000},
301 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
302 {0xca0, 0x00000000}, {0xca4, 0x00000080},
303 {0xca8, 0x00000000}, {0xcac, 0x00000000},
304 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
305 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
306 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
307 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
308 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
309 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
310 {0xce0, 0x00222222}, {0xce4, 0x00000000},
311 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
312 {0xd00, 0x00080740}, {0xd04, 0x00020403},
313 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
314 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
315 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
316 {0xd30, 0x00000000}, {0xd34, 0x80608000},
317 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
318 {0xd40, 0x00000000}, {0xd44, 0x00000000},
319 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
320 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
321 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
322 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
323 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
324 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
325 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
326 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
327 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
328 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
329 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
330 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
331 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
332 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
333 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
334 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
335 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
336 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
337 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
338 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
339 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
340 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
341 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
342 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
343 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
344 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
345 {0xf00, 0x00000300},
346 {0xffff, 0xffffffff},
347};
348
349static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
350 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
351 {0x040, 0x000c0004}, {0x800, 0x80040000},
352 {0x804, 0x00000001}, {0x808, 0x0000fc00},
353 {0x80c, 0x0000000a}, {0x810, 0x10005388},
354 {0x814, 0x020c3d10}, {0x818, 0x02200385},
355 {0x81c, 0x00000000}, {0x820, 0x01000100},
356 {0x824, 0x00390204}, {0x828, 0x00000000},
357 {0x82c, 0x00000000}, {0x830, 0x00000000},
358 {0x834, 0x00000000}, {0x838, 0x00000000},
359 {0x83c, 0x00000000}, {0x840, 0x00010000},
360 {0x844, 0x00000000}, {0x848, 0x00000000},
361 {0x84c, 0x00000000}, {0x850, 0x00000000},
362 {0x854, 0x00000000}, {0x858, 0x569a569a},
363 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
364 {0x864, 0x061f0130}, {0x868, 0x00000000},
365 {0x86c, 0x20202000}, {0x870, 0x03000300},
366 {0x874, 0x22004000}, {0x878, 0x00000808},
367 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
368 {0x884, 0x000004d5}, {0x888, 0x00000000},
369 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
370 {0x894, 0xfffffffe}, {0x898, 0x40302010},
371 {0x89c, 0x00706050}, {0x900, 0x00000000},
372 {0x904, 0x00000023}, {0x908, 0x00000000},
373 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
374 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
375 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
376 {0xa14, 0x11144028}, {0xa18, 0x00881117},
377 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
378 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
379 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
380 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
381 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
382 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
383 {0xc14, 0x40000100}, {0xc18, 0x08800000},
384 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
385 {0xc24, 0x00000000}, {0xc28, 0x00000000},
386 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
387 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
388 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
389 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
390 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
391 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
392 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
393 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
394 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
395 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
396 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
397 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
398 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
399 {0xc94, 0x00000000}, {0xc98, 0x00121820},
400 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
401 {0xca4, 0x00000080}, {0xca8, 0x00000000},
402 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
403 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
404 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
405 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
406 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
407 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
408 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
409 {0xce4, 0x00000000}, {0xce8, 0x37644302},
410 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
411 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
412 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
413 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
414 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
415 {0xd34, 0x80608000}, {0xd38, 0x00000000},
416 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
417 {0xd44, 0x00000000}, {0xd48, 0x00000000},
418 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
419 {0xd54, 0x00000000}, {0xd58, 0x00000000},
420 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
421 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
422 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
423 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
424 {0xe00, 0x24242424}, {0xe04, 0x24242424},
425 {0xe08, 0x03902024}, {0xe10, 0x24242424},
426 {0xe14, 0x24242424}, {0xe18, 0x24242424},
427 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
428 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
429 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
430 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
431 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
432 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
433 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
434 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
435 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
436 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
437 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
438 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
439 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
440 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
441 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
442 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
443 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
444 {0xf00, 0x00000300},
445 {0xffff, 0xffffffff},
446};
447
448static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
449 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
450 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
451 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
452 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
453 {0xc78, 0x78080001}, {0xc78, 0x77090001},
454 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
455 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
456 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
457 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
458 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
459 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
460 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
461 {0xc78, 0x68180001}, {0xc78, 0x67190001},
462 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
463 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
464 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
465 {0xc78, 0x60200001}, {0xc78, 0x49210001},
466 {0xc78, 0x48220001}, {0xc78, 0x47230001},
467 {0xc78, 0x46240001}, {0xc78, 0x45250001},
468 {0xc78, 0x44260001}, {0xc78, 0x43270001},
469 {0xc78, 0x42280001}, {0xc78, 0x41290001},
470 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
471 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
472 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
473 {0xc78, 0x21300001}, {0xc78, 0x20310001},
474 {0xc78, 0x06320001}, {0xc78, 0x05330001},
475 {0xc78, 0x04340001}, {0xc78, 0x03350001},
476 {0xc78, 0x02360001}, {0xc78, 0x01370001},
477 {0xc78, 0x00380001}, {0xc78, 0x00390001},
478 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
479 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
480 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
481 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
482 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
483 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
484 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
485 {0xc78, 0x78480001}, {0xc78, 0x77490001},
486 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
487 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
488 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
489 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
490 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
491 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
492 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
493 {0xc78, 0x68580001}, {0xc78, 0x67590001},
494 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
495 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
496 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
497 {0xc78, 0x60600001}, {0xc78, 0x49610001},
498 {0xc78, 0x48620001}, {0xc78, 0x47630001},
499 {0xc78, 0x46640001}, {0xc78, 0x45650001},
500 {0xc78, 0x44660001}, {0xc78, 0x43670001},
501 {0xc78, 0x42680001}, {0xc78, 0x41690001},
502 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
503 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
504 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
505 {0xc78, 0x21700001}, {0xc78, 0x20710001},
506 {0xc78, 0x06720001}, {0xc78, 0x05730001},
507 {0xc78, 0x04740001}, {0xc78, 0x03750001},
508 {0xc78, 0x02760001}, {0xc78, 0x01770001},
509 {0xc78, 0x00780001}, {0xc78, 0x00790001},
510 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
511 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
512 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
513 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
514 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
515 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
516 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
517 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
518 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
519 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
520 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
521 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
522 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
523 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
524 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
525 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
526 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
527 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
528 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
529 {0xffff, 0xffffffff}
530};
531
532static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
533 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
534 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
535 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
536 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
537 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
538 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
539 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
540 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
541 {0xc78, 0x73100001}, {0xc78, 0x72110001},
542 {0xc78, 0x71120001}, {0xc78, 0x70130001},
543 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
544 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
545 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
546 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
547 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
548 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
549 {0xc78, 0x63200001}, {0xc78, 0x62210001},
550 {0xc78, 0x61220001}, {0xc78, 0x60230001},
551 {0xc78, 0x46240001}, {0xc78, 0x45250001},
552 {0xc78, 0x44260001}, {0xc78, 0x43270001},
553 {0xc78, 0x42280001}, {0xc78, 0x41290001},
554 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
555 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
556 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
557 {0xc78, 0x21300001}, {0xc78, 0x20310001},
558 {0xc78, 0x06320001}, {0xc78, 0x05330001},
559 {0xc78, 0x04340001}, {0xc78, 0x03350001},
560 {0xc78, 0x02360001}, {0xc78, 0x01370001},
561 {0xc78, 0x00380001}, {0xc78, 0x00390001},
562 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
563 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
564 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
565 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
566 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
567 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
568 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
569 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
570 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
571 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
572 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
573 {0xc78, 0x73500001}, {0xc78, 0x72510001},
574 {0xc78, 0x71520001}, {0xc78, 0x70530001},
575 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
576 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
577 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
578 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
579 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
580 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
581 {0xc78, 0x63600001}, {0xc78, 0x62610001},
582 {0xc78, 0x61620001}, {0xc78, 0x60630001},
583 {0xc78, 0x46640001}, {0xc78, 0x45650001},
584 {0xc78, 0x44660001}, {0xc78, 0x43670001},
585 {0xc78, 0x42680001}, {0xc78, 0x41690001},
586 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
587 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
588 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
589 {0xc78, 0x21700001}, {0xc78, 0x20710001},
590 {0xc78, 0x06720001}, {0xc78, 0x05730001},
591 {0xc78, 0x04740001}, {0xc78, 0x03750001},
592 {0xc78, 0x02760001}, {0xc78, 0x01770001},
593 {0xc78, 0x00780001}, {0xc78, 0x00790001},
594 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
595 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
596 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
597 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
598 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
599 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
600 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
601 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
602 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
603 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
604 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
605 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
606 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
607 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
608 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
609 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
610 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
611 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
612 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
613 {0xffff, 0xffffffff}
614};
615
616static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
617 {0x00, 0x00030159}, {0x01, 0x00031284},
618 {0x02, 0x00098000}, {0x03, 0x00039c63},
619 {0x04, 0x000210e7}, {0x09, 0x0002044f},
620 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
621 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
622 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
623 {0x19, 0x00000000}, {0x1a, 0x00030355},
624 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
625 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
626 {0x1f, 0x00000000}, {0x20, 0x0000b614},
627 {0x21, 0x0006c000}, {0x22, 0x00000000},
628 {0x23, 0x00001558}, {0x24, 0x00000060},
629 {0x25, 0x00000483}, {0x26, 0x0004f000},
630 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
631 {0x29, 0x00004783}, {0x2a, 0x00000001},
632 {0x2b, 0x00021334}, {0x2a, 0x00000000},
633 {0x2b, 0x00000054}, {0x2a, 0x00000001},
634 {0x2b, 0x00000808}, {0x2b, 0x00053333},
635 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
636 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
637 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
638 {0x2b, 0x00000808}, {0x2b, 0x00063333},
639 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
640 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
641 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
642 {0x2b, 0x00000808}, {0x2b, 0x00073333},
643 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
644 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
645 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
646 {0x2b, 0x00000709}, {0x2b, 0x00063333},
647 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
648 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
649 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
650 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
651 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
652 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
653 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
654 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
655 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
656 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
657 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
658 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
659 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
660 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
661 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
662 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
663 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
664 {0x10, 0x0002000f}, {0x11, 0x000203f9},
665 {0x10, 0x0003000f}, {0x11, 0x000ff500},
666 {0x10, 0x00000000}, {0x11, 0x00000000},
667 {0x10, 0x0008000f}, {0x11, 0x0003f100},
668 {0x10, 0x0009000f}, {0x11, 0x00023100},
669 {0x12, 0x00032000}, {0x12, 0x00071000},
670 {0x12, 0x000b0000}, {0x12, 0x000fc000},
671 {0x13, 0x000287b3}, {0x13, 0x000244b7},
672 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
673 {0x13, 0x00018493}, {0x13, 0x0001429b},
674 {0x13, 0x00010299}, {0x13, 0x0000c29c},
675 {0x13, 0x000081a0}, {0x13, 0x000040ac},
676 {0x13, 0x00000020}, {0x14, 0x0001944c},
677 {0x14, 0x00059444}, {0x14, 0x0009944c},
678 {0x14, 0x000d9444}, {0x15, 0x0000f474},
679 {0x15, 0x0004f477}, {0x15, 0x0008f455},
680 {0x15, 0x000cf455}, {0x16, 0x00000339},
681 {0x16, 0x00040339}, {0x16, 0x00080339},
682 {0x16, 0x000c0366}, {0x00, 0x00010159},
683 {0x18, 0x0000f401}, {0xfe, 0x00000000},
684 {0xfe, 0x00000000}, {0x1f, 0x00000003},
685 {0xfe, 0x00000000}, {0xfe, 0x00000000},
686 {0x1e, 0x00000247}, {0x1f, 0x00000000},
687 {0x00, 0x00030159},
688 {0xff, 0xffffffff}
689};
690
691static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
692 {0x00, 0x00030159}, {0x01, 0x00031284},
693 {0x02, 0x00098000}, {0x03, 0x00018c63},
694 {0x04, 0x000210e7}, {0x09, 0x0002044f},
695 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
696 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
697 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
698 {0x19, 0x00000000}, {0x1a, 0x00010255},
699 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
700 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
701 {0x1f, 0x00080001}, {0x20, 0x0000b614},
702 {0x21, 0x0006c000}, {0x22, 0x00000000},
703 {0x23, 0x00001558}, {0x24, 0x00000060},
704 {0x25, 0x00000483}, {0x26, 0x0004f000},
705 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
706 {0x29, 0x00004783}, {0x2a, 0x00000001},
707 {0x2b, 0x00021334}, {0x2a, 0x00000000},
708 {0x2b, 0x00000054}, {0x2a, 0x00000001},
709 {0x2b, 0x00000808}, {0x2b, 0x00053333},
710 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
711 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
712 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
713 {0x2b, 0x00000808}, {0x2b, 0x00063333},
714 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
715 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
716 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
717 {0x2b, 0x00000808}, {0x2b, 0x00073333},
718 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
719 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
720 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
721 {0x2b, 0x00000709}, {0x2b, 0x00063333},
722 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
723 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
724 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
725 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
726 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
727 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
728 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
729 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
730 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
731 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
732 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
733 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
734 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
735 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
736 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
737 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
738 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
739 {0x10, 0x0002000f}, {0x11, 0x000203f9},
740 {0x10, 0x0003000f}, {0x11, 0x000ff500},
741 {0x10, 0x00000000}, {0x11, 0x00000000},
742 {0x10, 0x0008000f}, {0x11, 0x0003f100},
743 {0x10, 0x0009000f}, {0x11, 0x00023100},
744 {0x12, 0x00032000}, {0x12, 0x00071000},
745 {0x12, 0x000b0000}, {0x12, 0x000fc000},
746 {0x13, 0x000287b3}, {0x13, 0x000244b7},
747 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
748 {0x13, 0x00018493}, {0x13, 0x0001429b},
749 {0x13, 0x00010299}, {0x13, 0x0000c29c},
750 {0x13, 0x000081a0}, {0x13, 0x000040ac},
751 {0x13, 0x00000020}, {0x14, 0x0001944c},
752 {0x14, 0x00059444}, {0x14, 0x0009944c},
753 {0x14, 0x000d9444}, {0x15, 0x0000f424},
754 {0x15, 0x0004f424}, {0x15, 0x0008f424},
755 {0x15, 0x000cf424}, {0x16, 0x000e0330},
756 {0x16, 0x000a0330}, {0x16, 0x00060330},
757 {0x16, 0x00020330}, {0x00, 0x00010159},
758 {0x18, 0x0000f401}, {0xfe, 0x00000000},
759 {0xfe, 0x00000000}, {0x1f, 0x00080003},
760 {0xfe, 0x00000000}, {0xfe, 0x00000000},
761 {0x1e, 0x00044457}, {0x1f, 0x00080000},
762 {0x00, 0x00030159},
763 {0xff, 0xffffffff}
764};
765
766static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
767 {0x00, 0x00030159}, {0x01, 0x00031284},
768 {0x02, 0x00098000}, {0x03, 0x00018c63},
769 {0x04, 0x000210e7}, {0x09, 0x0002044f},
770 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
771 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
772 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
773 {0x12, 0x00032000}, {0x12, 0x00071000},
774 {0x12, 0x000b0000}, {0x12, 0x000fc000},
775 {0x13, 0x000287af}, {0x13, 0x000244b7},
776 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
777 {0x13, 0x00018493}, {0x13, 0x00014297},
778 {0x13, 0x00010295}, {0x13, 0x0000c298},
779 {0x13, 0x0000819c}, {0x13, 0x000040a8},
780 {0x13, 0x0000001c}, {0x14, 0x0001944c},
781 {0x14, 0x00059444}, {0x14, 0x0009944c},
782 {0x14, 0x000d9444}, {0x15, 0x0000f424},
783 {0x15, 0x0004f424}, {0x15, 0x0008f424},
784 {0x15, 0x000cf424}, {0x16, 0x000e0330},
785 {0x16, 0x000a0330}, {0x16, 0x00060330},
786 {0x16, 0x00020330},
787 {0xff, 0xffffffff}
788};
789
790static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
791 {0x00, 0x00030159}, {0x01, 0x00031284},
792 {0x02, 0x00098000}, {0x03, 0x00018c63},
793 {0x04, 0x000210e7}, {0x09, 0x0002044f},
794 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
795 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
796 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
797 {0x19, 0x00000000}, {0x1a, 0x00010255},
798 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
799 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
800 {0x1f, 0x00080001}, {0x20, 0x0000b614},
801 {0x21, 0x0006c000}, {0x22, 0x00000000},
802 {0x23, 0x00001558}, {0x24, 0x00000060},
803 {0x25, 0x00000483}, {0x26, 0x0004f000},
804 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
805 {0x29, 0x00004783}, {0x2a, 0x00000001},
806 {0x2b, 0x00021334}, {0x2a, 0x00000000},
807 {0x2b, 0x00000054}, {0x2a, 0x00000001},
808 {0x2b, 0x00000808}, {0x2b, 0x00053333},
809 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
810 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
811 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
812 {0x2b, 0x00000808}, {0x2b, 0x00063333},
813 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
814 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
815 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
816 {0x2b, 0x00000808}, {0x2b, 0x00073333},
817 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
818 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
819 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
820 {0x2b, 0x00000709}, {0x2b, 0x00063333},
821 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
822 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
823 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
824 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
825 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
826 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
827 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
828 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
829 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
830 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
831 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
832 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
833 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
834 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
835 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
836 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
837 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
838 {0x10, 0x0002000f}, {0x11, 0x000203f9},
839 {0x10, 0x0003000f}, {0x11, 0x000ff500},
840 {0x10, 0x00000000}, {0x11, 0x00000000},
841 {0x10, 0x0008000f}, {0x11, 0x0003f100},
842 {0x10, 0x0009000f}, {0x11, 0x00023100},
843 {0x12, 0x00032000}, {0x12, 0x00071000},
844 {0x12, 0x000b0000}, {0x12, 0x000fc000},
845 {0x13, 0x000287b3}, {0x13, 0x000244b7},
846 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
847 {0x13, 0x00018493}, {0x13, 0x0001429b},
848 {0x13, 0x00010299}, {0x13, 0x0000c29c},
849 {0x13, 0x000081a0}, {0x13, 0x000040ac},
850 {0x13, 0x00000020}, {0x14, 0x0001944c},
851 {0x14, 0x00059444}, {0x14, 0x0009944c},
852 {0x14, 0x000d9444}, {0x15, 0x0000f405},
853 {0x15, 0x0004f405}, {0x15, 0x0008f405},
854 {0x15, 0x000cf405}, {0x16, 0x000e0330},
855 {0x16, 0x000a0330}, {0x16, 0x00060330},
856 {0x16, 0x00020330}, {0x00, 0x00010159},
857 {0x18, 0x0000f401}, {0xfe, 0x00000000},
858 {0xfe, 0x00000000}, {0x1f, 0x00080003},
859 {0xfe, 0x00000000}, {0xfe, 0x00000000},
860 {0x1e, 0x00044457}, {0x1f, 0x00080000},
861 {0x00, 0x00030159},
862 {0xff, 0xffffffff}
863};
864
865static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
866 {0x00, 0x00030159}, {0x01, 0x00031284},
867 {0x02, 0x00098000}, {0x03, 0x00018c63},
868 {0x04, 0x000210e7}, {0x09, 0x0002044f},
869 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
870 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
871 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
872 {0x19, 0x00000000}, {0x1a, 0x00000255},
873 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
874 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
875 {0x1f, 0x00080001}, {0x20, 0x0000b614},
876 {0x21, 0x0006c000}, {0x22, 0x0000083c},
877 {0x23, 0x00001558}, {0x24, 0x00000060},
878 {0x25, 0x00000483}, {0x26, 0x0004f000},
879 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
880 {0x29, 0x00004783}, {0x2a, 0x00000001},
881 {0x2b, 0x00021334}, {0x2a, 0x00000000},
882 {0x2b, 0x00000054}, {0x2a, 0x00000001},
883 {0x2b, 0x00000808}, {0x2b, 0x00053333},
884 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
885 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
886 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
887 {0x2b, 0x00000808}, {0x2b, 0x00063333},
888 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
889 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
890 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
891 {0x2b, 0x00000808}, {0x2b, 0x00073333},
892 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
893 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
894 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
895 {0x2b, 0x00000709}, {0x2b, 0x00063333},
896 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
897 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
898 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
899 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
900 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
901 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
902 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
903 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
904 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
905 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
906 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
907 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
908 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
909 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
910 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
911 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
912 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
913 {0x10, 0x0002000f}, {0x11, 0x000203f9},
914 {0x10, 0x0003000f}, {0x11, 0x000ff500},
915 {0x10, 0x00000000}, {0x11, 0x00000000},
916 {0x10, 0x0008000f}, {0x11, 0x0003f100},
917 {0x10, 0x0009000f}, {0x11, 0x00023100},
918 {0x12, 0x000d8000}, {0x12, 0x00090000},
919 {0x12, 0x00051000}, {0x12, 0x00012000},
920 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
921 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
922 {0x13, 0x000183a4}, {0x13, 0x00014398},
923 {0x13, 0x000101a4}, {0x13, 0x0000c198},
924 {0x13, 0x000080a4}, {0x13, 0x00004098},
925 {0x13, 0x00000000}, {0x14, 0x0001944c},
926 {0x14, 0x00059444}, {0x14, 0x0009944c},
927 {0x14, 0x000d9444}, {0x15, 0x0000f405},
928 {0x15, 0x0004f405}, {0x15, 0x0008f405},
929 {0x15, 0x000cf405}, {0x16, 0x000e0330},
930 {0x16, 0x000a0330}, {0x16, 0x00060330},
931 {0x16, 0x00020330}, {0x00, 0x00010159},
932 {0x18, 0x0000f401}, {0xfe, 0x00000000},
933 {0xfe, 0x00000000}, {0x1f, 0x00080003},
934 {0xfe, 0x00000000}, {0xfe, 0x00000000},
935 {0x1e, 0x00044457}, {0x1f, 0x00080000},
936 {0x00, 0x00030159},
937 {0xff, 0xffffffff}
938};
939
940static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
941 { /* RF_A */
942 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
943 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
944 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
945 .hspiread = REG_HSPI_XA_READBACK,
946 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
947 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
948 },
949 { /* RF_B */
950 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
951 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
952 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
953 .hspiread = REG_HSPI_XB_READBACK,
954 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
955 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
956 },
957};
958
959static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
960 REG_OFDM0_XA_RX_IQ_IMBALANCE,
961 REG_OFDM0_XB_RX_IQ_IMBALANCE,
962 REG_OFDM0_ENERGY_CCA_THRES,
963 REG_OFDM0_AGCR_SSI_TABLE,
964 REG_OFDM0_XA_TX_IQ_IMBALANCE,
965 REG_OFDM0_XB_TX_IQ_IMBALANCE,
966 REG_OFDM0_XC_TX_AFE,
967 REG_OFDM0_XD_TX_AFE,
968 REG_OFDM0_RX_IQ_EXT_ANTA
969};
970
971static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
972{
973 struct usb_device *udev = priv->udev;
974 int len;
975 u8 data;
976
977 mutex_lock(&priv->usb_buf_mutex);
978 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
979 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
980 addr, 0, &priv->usb_buf.val8, sizeof(u8),
981 RTW_USB_CONTROL_MSG_TIMEOUT);
982 data = priv->usb_buf.val8;
983 mutex_unlock(&priv->usb_buf_mutex);
984
985 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
986 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
987 __func__, addr, data, len);
988 return data;
989}
990
991static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
992{
993 struct usb_device *udev = priv->udev;
994 int len;
995 u16 data;
996
997 mutex_lock(&priv->usb_buf_mutex);
998 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
999 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001 RTW_USB_CONTROL_MSG_TIMEOUT);
1002 data = le16_to_cpu(priv->usb_buf.val16);
1003 mutex_unlock(&priv->usb_buf_mutex);
1004
1005 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1007 __func__, addr, data, len);
1008 return data;
1009}
1010
1011static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012{
1013 struct usb_device *udev = priv->udev;
1014 int len;
1015 u32 data;
1016
1017 mutex_lock(&priv->usb_buf_mutex);
1018 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021 RTW_USB_CONTROL_MSG_TIMEOUT);
1022 data = le32_to_cpu(priv->usb_buf.val32);
1023 mutex_unlock(&priv->usb_buf_mutex);
1024
1025 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1027 __func__, addr, data, len);
1028 return data;
1029}
1030
1031static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032{
1033 struct usb_device *udev = priv->udev;
1034 int ret;
1035
1036 mutex_lock(&priv->usb_buf_mutex);
1037 priv->usb_buf.val8 = val;
1038 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041 RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043 mutex_unlock(&priv->usb_buf_mutex);
1044
1045 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047 __func__, addr, val);
1048 return ret;
1049}
1050
1051static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052{
1053 struct usb_device *udev = priv->udev;
1054 int ret;
1055
1056 mutex_lock(&priv->usb_buf_mutex);
1057 priv->usb_buf.val16 = cpu_to_le16(val);
1058 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061 RTW_USB_CONTROL_MSG_TIMEOUT);
1062 mutex_unlock(&priv->usb_buf_mutex);
1063
1064 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066 __func__, addr, val);
1067 return ret;
1068}
1069
1070static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071{
1072 struct usb_device *udev = priv->udev;
1073 int ret;
1074
1075 mutex_lock(&priv->usb_buf_mutex);
1076 priv->usb_buf.val32 = cpu_to_le32(val);
1077 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080 RTW_USB_CONTROL_MSG_TIMEOUT);
1081 mutex_unlock(&priv->usb_buf_mutex);
1082
1083 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085 __func__, addr, val);
1086 return ret;
1087}
1088
1089static int
1090rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091{
1092 struct usb_device *udev = priv->udev;
1093 int blocksize = priv->fops->writeN_block_size;
1094 int ret, i, count, remainder;
1095
1096 count = len / blocksize;
1097 remainder = len % blocksize;
1098
1099 for (i = 0; i < count; i++) {
1100 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102 addr, 0, buf, blocksize,
1103 RTW_USB_CONTROL_MSG_TIMEOUT);
1104 if (ret != blocksize)
1105 goto write_error;
1106
1107 addr += blocksize;
1108 buf += blocksize;
1109 }
1110
1111 if (remainder) {
1112 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114 addr, 0, buf, remainder,
1115 RTW_USB_CONTROL_MSG_TIMEOUT);
1116 if (ret != remainder)
1117 goto write_error;
1118 }
1119
1120 return len;
1121
1122write_error:
1123 dev_info(&udev->dev,
1124 "%s: Failed to write block at addr: %04x size: %04x\n",
1125 __func__, addr, blocksize);
1126 return -EAGAIN;
1127}
1128
1129static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130 enum rtl8xxxu_rfpath path, u8 reg)
1131{
1132 u32 hssia, val32, retval;
1133
1134 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135 if (path != RF_A)
1136 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137 else
1138 val32 = hssia;
1139
1140 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146 udelay(10);
1147
1148 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149 udelay(100);
1150
1151 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153 udelay(10);
1154
1155 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156 if (val32 & FPGA0_HSSI_PARM1_PI)
1157 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158 else
1159 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161 retval &= 0xfffff;
1162
1163 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165 __func__, reg, retval);
1166 return retval;
1167}
1168
1169static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171{
1172 int ret, retval;
1173 u32 dataaddr;
1174
1175 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177 __func__, reg, data);
1178
1179 data &= FPGA0_LSSI_PARM_DATA_MASK;
1180 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182 /* Use XB for path B */
1183 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184 if (ret != sizeof(dataaddr))
1185 retval = -EIO;
1186 else
1187 retval = 0;
1188
1189 udelay(1);
1190
1191 return retval;
1192}
1193
1194static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195{
1196 struct device *dev = &priv->udev->dev;
1197 int mbox_nr, retry, retval = 0;
1198 int mbox_reg, mbox_ext_reg;
1199 u8 val8;
1200
1201 mutex_lock(&priv->h2c_mutex);
1202
1203 mbox_nr = priv->next_mbox;
1204 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207 /*
1208 * MBOX ready?
1209 */
1210 retry = 100;
1211 do {
1212 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213 if (!(val8 & BIT(mbox_nr)))
1214 break;
1215 } while (retry--);
1216
1217 if (!retry) {
1218 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219 retval = -EBUSY;
1220 goto error;
1221 }
1222
1223 /*
1224 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225 */
1226 if (h2c->cmd.cmd & H2C_EXT) {
1227 rtl8xxxu_write16(priv, mbox_ext_reg,
1228 le16_to_cpu(h2c->raw.ext));
1229 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230 dev_info(dev, "H2C_EXT %04x\n",
1231 le16_to_cpu(h2c->raw.ext));
1232 }
1233 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239error:
1240 mutex_unlock(&priv->h2c_mutex);
1241 return retval;
1242}
1243
1244static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245{
1246 u8 val8;
1247 u32 val32;
1248
1249 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250 val8 |= BIT(0) | BIT(3);
1251 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254 val32 &= ~(BIT(4) | BIT(5));
1255 val32 |= BIT(3);
1256 if (priv->rf_paths == 2) {
1257 val32 &= ~(BIT(20) | BIT(21));
1258 val32 |= BIT(19);
1259 }
1260 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263 val32 &= ~OFDM_RF_PATH_TX_MASK;
1264 if (priv->tx_paths == 2)
1265 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267 val32 |= OFDM_RF_PATH_TX_B;
1268 else
1269 val32 |= OFDM_RF_PATH_TX_A;
1270 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273 val32 &= ~FPGA_RF_MODE_JAPAN;
1274 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276 if (priv->rf_paths == 2)
1277 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278 else
1279 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282 if (priv->rf_paths == 2)
1283 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286}
1287
1288static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289{
1290 u8 sps0;
1291 u32 val32;
1292
1293 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297 /* RF RX code for preamble power saving */
1298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300 if (priv->rf_paths == 2)
1301 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304 /* Disable TX for four paths */
1305 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306 val32 &= ~OFDM_RF_PATH_TX_MASK;
1307 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309 /* Enable power saving */
1310 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311 val32 |= FPGA_RF_MODE_JAPAN;
1312 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314 /* AFE control register to power down bits [30:22] */
1315 if (priv->rf_paths == 2)
1316 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317 else
1318 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320 /* Power down RF module */
1321 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322 if (priv->rf_paths == 2)
1323 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325 sps0 &= ~(BIT(0) | BIT(3));
1326 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327}
1328
1329
1330static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331{
1332 u8 val8;
1333
1334 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335 val8 &= ~BIT(6);
1336 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340 val8 &= ~BIT(0);
1341 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342}
1343
1344
1345/*
1346 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347 * supports the 2.4GHz band, so channels 1 - 14:
1348 * group 0: channels 1 - 3
1349 * group 1: channels 4 - 9
1350 * group 2: channels 10 - 14
1351 *
1352 * Note: We index from 0 in the code
1353 */
1354static int rtl8723a_channel_to_group(int channel)
1355{
1356 int group;
1357
1358 if (channel < 4)
1359 group = 0;
1360 else if (channel < 10)
1361 group = 1;
1362 else
1363 group = 2;
1364
1365 return group;
1366}
1367
1368static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369{
1370 struct rtl8xxxu_priv *priv = hw->priv;
1371 u32 val32, rsr;
1372 u8 val8, opmode;
1373 bool ht = true;
1374 int sec_ch_above, channel;
1375 int i;
1376
1377 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379 channel = hw->conf.chandef.chan->hw_value;
1380
1381 switch (hw->conf.chandef.width) {
1382 case NL80211_CHAN_WIDTH_20_NOHT:
1383 ht = false;
1384 case NL80211_CHAN_WIDTH_20:
1385 opmode |= BW_OPMODE_20MHZ;
1386 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389 val32 &= ~FPGA_RF_MODE;
1390 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393 val32 &= ~FPGA_RF_MODE;
1394 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397 val32 |= FPGA0_ANALOG2_20MHZ;
1398 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399 break;
1400 case NL80211_CHAN_WIDTH_40:
1401 if (hw->conf.chandef.center_freq1 >
1402 hw->conf.chandef.chan->center_freq) {
1403 sec_ch_above = 1;
1404 channel += 2;
1405 } else {
1406 sec_ch_above = 0;
1407 channel -= 2;
1408 }
1409
1410 opmode &= ~BW_OPMODE_20MHZ;
1411 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413 if (sec_ch_above)
1414 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415 else
1416 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420 val32 |= FPGA_RF_MODE;
1421 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424 val32 |= FPGA_RF_MODE;
1425 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427 /*
1428 * Set Control channel to upper or lower. These settings
1429 * are required only for 40MHz
1430 */
1431 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432 val32 &= ~CCK0_SIDEBAND;
1433 if (!sec_ch_above)
1434 val32 |= CCK0_SIDEBAND;
1435 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439 if (sec_ch_above)
1440 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441 else
1442 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451 if (sec_ch_above)
1452 val32 |= FPGA0_PS_UPPER_CHANNEL;
1453 else
1454 val32 |= FPGA0_PS_LOWER_CHANNEL;
1455 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456 break;
1457
1458 default:
1459 break;
1460 }
1461
1462 for (i = RF_A; i < priv->rf_paths; i++) {
1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464 val32 &= ~MODE_AG_CHANNEL_MASK;
1465 val32 |= channel;
1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467 }
1468
1469 if (ht)
1470 val8 = 0x0e;
1471 else
1472 val8 = 0x0a;
1473
1474 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480 for (i = RF_A; i < priv->rf_paths; i++) {
1481 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484 else
1485 val32 |= MODE_AG_CHANNEL_20MHZ;
1486 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487 }
1488}
1489
1490static void
1491rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492{
1493 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496 u8 val8;
1497 int group, i;
1498
1499 group = rtl8723a_channel_to_group(channel);
1500
1501 cck[0] = priv->cck_tx_power_index_A[group];
1502 cck[1] = priv->cck_tx_power_index_B[group];
1503
1504 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510 mcsbase[0] = ofdm[0];
1511 mcsbase[1] = ofdm[1];
1512 if (!ht40) {
1513 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515 }
1516
1517 if (priv->tx_paths > 1) {
1518 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1520 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1522 }
1523
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525 dev_info(&priv->udev->dev,
1526 "%s: Setting TX power CCK A: %02x, "
1527 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531 if (cck[i] > RF6052_MAX_TX_PWR)
1532 cck[i] = RF6052_MAX_TX_PWR;
1533 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534 ofdm[i] = RF6052_MAX_TX_PWR;
1535 }
1536
1537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538 val32 &= 0xffff00ff;
1539 val32 |= (cck[0] << 8);
1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543 val32 &= 0xff;
1544 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548 val32 &= 0xffffff00;
1549 val32 |= cck[1];
1550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553 val32 &= 0xff;
1554 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568 mcsbase[0] << 16 | mcsbase[0] << 24;
1569 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582 for (i = 0; i < 3; i++) {
1583 if (i != 2)
1584 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585 else
1586 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588 }
1589 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590 for (i = 0; i < 3; i++) {
1591 if (i != 2)
1592 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593 else
1594 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596 }
1597}
1598
1599static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600 enum nl80211_iftype linktype)
1601{
1602 u16 val8;
1603
1604 val8 = rtl8xxxu_read16(priv, REG_MSR);
1605 val8 &= ~MSR_LINKTYPE_MASK;
1606
1607 switch (linktype) {
1608 case NL80211_IFTYPE_UNSPECIFIED:
1609 val8 |= MSR_LINKTYPE_NONE;
1610 break;
1611 case NL80211_IFTYPE_ADHOC:
1612 val8 |= MSR_LINKTYPE_ADHOC;
1613 break;
1614 case NL80211_IFTYPE_STATION:
1615 val8 |= MSR_LINKTYPE_STATION;
1616 break;
1617 case NL80211_IFTYPE_AP:
1618 val8 |= MSR_LINKTYPE_AP;
1619 break;
1620 default:
1621 goto out;
1622 }
1623
1624 rtl8xxxu_write8(priv, REG_MSR, val8);
1625out:
1626 return;
1627}
1628
1629static void
1630rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631{
1632 u16 val16;
1633
1634 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635 RETRY_LIMIT_SHORT_MASK) |
1636 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637 RETRY_LIMIT_LONG_MASK);
1638
1639 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640}
1641
1642static void
1643rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644{
1645 u16 val16;
1646
1647 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651}
1652
1653static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654{
1655 struct device *dev = &priv->udev->dev;
1656 char *cut;
1657
1658 switch (priv->chip_cut) {
1659 case 0:
1660 cut = "A";
1661 break;
1662 case 1:
1663 cut = "B";
1664 break;
1665 default:
1666 cut = "unknown";
1667 }
1668
1669 dev_info(dev,
1670 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671 priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674 priv->hi_pa);
1675
1676 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677}
1678
1679static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680{
1681 struct device *dev = &priv->udev->dev;
1682 u32 val32, bonding;
1683 u16 val16;
1684
1685 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687 SYS_CFG_CHIP_VERSION_SHIFT;
1688 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689 dev_info(dev, "Unsupported test chip\n");
1690 return -ENOTSUPP;
1691 }
1692
1693 if (val32 & SYS_CFG_BT_FUNC) {
1694 sprintf(priv->chip_name, "8723AU");
1695 priv->rf_paths = 1;
1696 priv->rx_paths = 1;
1697 priv->tx_paths = 1;
1698 priv->rtlchip = 0x8723a;
1699
1700 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701 if (val32 & MULTI_WIFI_FUNC_EN)
1702 priv->has_wifi = 1;
1703 if (val32 & MULTI_BT_FUNC_EN)
1704 priv->has_bluetooth = 1;
1705 if (val32 & MULTI_GPS_FUNC_EN)
1706 priv->has_gps = 1;
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame^]1707 priv->is_multi_func = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1708 } else if (val32 & SYS_CFG_TYPE_ID) {
1709 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1710 bonding &= HPON_FSM_BONDING_MASK;
1711 if (bonding == HPON_FSM_BONDING_1T2R) {
1712 sprintf(priv->chip_name, "8191CU");
1713 priv->rf_paths = 2;
1714 priv->rx_paths = 2;
1715 priv->tx_paths = 1;
1716 priv->rtlchip = 0x8191c;
1717 } else {
1718 sprintf(priv->chip_name, "8192CU");
1719 priv->rf_paths = 2;
1720 priv->rx_paths = 2;
1721 priv->tx_paths = 2;
1722 priv->rtlchip = 0x8192c;
1723 }
1724 priv->has_wifi = 1;
1725 } else {
1726 sprintf(priv->chip_name, "8188CU");
1727 priv->rf_paths = 1;
1728 priv->rx_paths = 1;
1729 priv->tx_paths = 1;
1730 priv->rtlchip = 0x8188c;
1731 priv->has_wifi = 1;
1732 }
1733
1734 if (val32 & SYS_CFG_VENDOR_ID)
1735 priv->vendor_umc = 1;
1736
1737 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1738 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1739
1740 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1741 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1742 priv->ep_tx_high_queue = 1;
1743 priv->ep_tx_count++;
1744 }
1745
1746 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1747 priv->ep_tx_normal_queue = 1;
1748 priv->ep_tx_count++;
1749 }
1750
1751 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1752 priv->ep_tx_low_queue = 1;
1753 priv->ep_tx_count++;
1754 }
1755
1756 /*
1757 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1758 */
1759 if (!priv->ep_tx_count) {
1760 switch (priv->nr_out_eps) {
1761 case 3:
1762 priv->ep_tx_low_queue = 1;
1763 priv->ep_tx_count++;
1764 case 2:
1765 priv->ep_tx_normal_queue = 1;
1766 priv->ep_tx_count++;
1767 case 1:
1768 priv->ep_tx_high_queue = 1;
1769 priv->ep_tx_count++;
1770 break;
1771 default:
1772 dev_info(dev, "Unsupported USB TX end-points\n");
1773 return -ENOTSUPP;
1774 }
1775 }
1776
1777 return 0;
1778}
1779
1780static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1781{
1782 if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1783 return -EINVAL;
1784
1785 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1786
1787 memcpy(priv->cck_tx_power_index_A,
1788 priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1789 sizeof(priv->cck_tx_power_index_A));
1790 memcpy(priv->cck_tx_power_index_B,
1791 priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1792 sizeof(priv->cck_tx_power_index_B));
1793
1794 memcpy(priv->ht40_1s_tx_power_index_A,
1795 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1796 sizeof(priv->ht40_1s_tx_power_index_A));
1797 memcpy(priv->ht40_1s_tx_power_index_B,
1798 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1799 sizeof(priv->ht40_1s_tx_power_index_B));
1800
1801 memcpy(priv->ht20_tx_power_index_diff,
1802 priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1803 sizeof(priv->ht20_tx_power_index_diff));
1804 memcpy(priv->ofdm_tx_power_index_diff,
1805 priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1806 sizeof(priv->ofdm_tx_power_index_diff));
1807
1808 memcpy(priv->ht40_max_power_offset,
1809 priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1810 sizeof(priv->ht40_max_power_offset));
1811 memcpy(priv->ht20_max_power_offset,
1812 priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1813 sizeof(priv->ht20_max_power_offset));
1814
1815 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1816 priv->efuse_wifi.efuse8723.vendor_name);
1817 dev_info(&priv->udev->dev, "Product: %.41s\n",
1818 priv->efuse_wifi.efuse8723.device_name);
1819 return 0;
1820}
1821
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1822#ifdef CONFIG_RTL8XXXU_UNTESTED
1823
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1824static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1825{
1826 int i;
1827
1828 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1829 return -EINVAL;
1830
1831 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1832
1833 memcpy(priv->cck_tx_power_index_A,
1834 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1835 sizeof(priv->cck_tx_power_index_A));
1836 memcpy(priv->cck_tx_power_index_B,
1837 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1838 sizeof(priv->cck_tx_power_index_B));
1839
1840 memcpy(priv->ht40_1s_tx_power_index_A,
1841 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1842 sizeof(priv->ht40_1s_tx_power_index_A));
1843 memcpy(priv->ht40_1s_tx_power_index_B,
1844 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1845 sizeof(priv->ht40_1s_tx_power_index_B));
1846 memcpy(priv->ht40_2s_tx_power_index_diff,
1847 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1848 sizeof(priv->ht40_2s_tx_power_index_diff));
1849
1850 memcpy(priv->ht20_tx_power_index_diff,
1851 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1852 sizeof(priv->ht20_tx_power_index_diff));
1853 memcpy(priv->ofdm_tx_power_index_diff,
1854 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1855 sizeof(priv->ofdm_tx_power_index_diff));
1856
1857 memcpy(priv->ht40_max_power_offset,
1858 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1859 sizeof(priv->ht40_max_power_offset));
1860 memcpy(priv->ht20_max_power_offset,
1861 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1862 sizeof(priv->ht20_max_power_offset));
1863
1864 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1865 priv->efuse_wifi.efuse8192.vendor_name);
1866 dev_info(&priv->udev->dev, "Product: %.20s\n",
1867 priv->efuse_wifi.efuse8192.device_name);
1868
1869 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1870 sprintf(priv->chip_name, "8188RU");
1871 priv->hi_pa = 1;
1872 }
1873
1874 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1875 unsigned char *raw = priv->efuse_wifi.raw;
1876
1877 dev_info(&priv->udev->dev,
1878 "%s: dumping efuse (0x%02zx bytes):\n",
1879 __func__, sizeof(struct rtl8192cu_efuse));
1880 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1881 dev_info(&priv->udev->dev, "%02x: "
1882 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1883 raw[i], raw[i + 1], raw[i + 2],
1884 raw[i + 3], raw[i + 4], raw[i + 5],
1885 raw[i + 6], raw[i + 7]);
1886 }
1887 }
1888 return 0;
1889}
1890
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1891#endif
1892
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1893static int
1894rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1895{
1896 int i;
1897 u8 val8;
1898 u32 val32;
1899
1900 /* Write Address */
1901 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1902 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1903 val8 &= 0xfc;
1904 val8 |= (offset >> 8) & 0x03;
1905 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1906
1907 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1908 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1909
1910 /* Poll for data read */
1911 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1912 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1913 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1914 if (val32 & BIT(31))
1915 break;
1916 }
1917
1918 if (i == RTL8XXXU_MAX_REG_POLL)
1919 return -EIO;
1920
1921 udelay(50);
1922 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1923
1924 *data = val32 & 0xff;
1925 return 0;
1926}
1927
1928static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1929{
1930 struct device *dev = &priv->udev->dev;
1931 int i, ret = 0;
1932 u8 val8, word_mask, header, extheader;
1933 u16 val16, efuse_addr, offset;
1934 u32 val32;
1935
1936 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1937 if (val16 & EEPROM_ENABLE)
1938 priv->has_eeprom = 1;
1939 if (val16 & EEPROM_BOOT)
1940 priv->boot_eeprom = 1;
1941
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame^]1942 if (priv->is_multi_func) {
1943 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1944 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1945 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1946 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1947
1948 dev_dbg(dev, "Booting from %s\n",
1949 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1950
1951 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1952
1953 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1954 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1955 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1956 val16 |= SYS_ISO_PWC_EV12V;
1957 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1958 }
1959 /* Reset: 0x0000[28], default valid */
1960 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1961 if (!(val16 & SYS_FUNC_ELDR)) {
1962 val16 |= SYS_FUNC_ELDR;
1963 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1964 }
1965
1966 /*
1967 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1968 */
1969 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1970 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1971 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1972 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1973 }
1974
1975 /* Default value is 0xff */
1976 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1977
1978 efuse_addr = 0;
1979 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1980 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1981 if (ret || header == 0xff)
1982 goto exit;
1983
1984 if ((header & 0x1f) == 0x0f) { /* extended header */
1985 offset = (header & 0xe0) >> 5;
1986
1987 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1988 &extheader);
1989 if (ret)
1990 goto exit;
1991 /* All words disabled */
1992 if ((extheader & 0x0f) == 0x0f)
1993 continue;
1994
1995 offset |= ((extheader & 0xf0) >> 1);
1996 word_mask = extheader & 0x0f;
1997 } else {
1998 offset = (header >> 4) & 0x0f;
1999 word_mask = header & 0x0f;
2000 }
2001
2002 if (offset < EFUSE_MAX_SECTION_8723A) {
2003 u16 map_addr;
2004 /* Get word enable value from PG header */
2005
2006 /* We have 8 bits to indicate validity */
2007 map_addr = offset * 8;
2008 if (map_addr >= EFUSE_MAP_LEN_8723A) {
2009 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2010 "efuse corrupt!\n",
2011 __func__, map_addr);
2012 ret = -EINVAL;
2013 goto exit;
2014 }
2015 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2016 /* Check word enable condition in the section */
2017 if (!(word_mask & BIT(i))) {
2018 ret = rtl8xxxu_read_efuse8(priv,
2019 efuse_addr++,
2020 &val8);
2021 if (ret)
2022 goto exit;
2023 priv->efuse_wifi.raw[map_addr++] = val8;
2024
2025 ret = rtl8xxxu_read_efuse8(priv,
2026 efuse_addr++,
2027 &val8);
2028 if (ret)
2029 goto exit;
2030 priv->efuse_wifi.raw[map_addr++] = val8;
2031 } else
2032 map_addr += 2;
2033 }
2034 } else {
2035 dev_warn(dev,
2036 "%s: Illegal offset (%04x), efuse corrupt!\n",
2037 __func__, offset);
2038 ret = -EINVAL;
2039 goto exit;
2040 }
2041 }
2042
2043exit:
2044 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2045
2046 return ret;
2047}
2048
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2049static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2050{
2051 u8 val8;
2052 u16 sys_func;
2053
2054 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2055 val8 &= ~BIT(3);
2056 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2057 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2058 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2059 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2060 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
2061 val8 |= BIT(3);
2062 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2063 sys_func |= SYS_FUNC_CPU_ENABLE;
2064 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2065}
2066
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2067static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2068{
2069 struct device *dev = &priv->udev->dev;
2070 int ret = 0, i;
2071 u32 val32;
2072
2073 /* Poll checksum report */
2074 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2075 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2076 if (val32 & MCU_FW_DL_CSUM_REPORT)
2077 break;
2078 }
2079
2080 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2081 dev_warn(dev, "Firmware checksum poll timed out\n");
2082 ret = -EAGAIN;
2083 goto exit;
2084 }
2085
2086 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2087 val32 |= MCU_FW_DL_READY;
2088 val32 &= ~MCU_WINT_INIT_READY;
2089 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2090
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2091 /*
2092 * Reset the 8051 in order for the firmware to start running,
2093 * otherwise it won't come up on the 8192eu
2094 */
2095 rtl8xxxu_reset_8051(priv);
2096
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2097 /* Wait for firmware to become ready */
2098 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2099 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2100 if (val32 & MCU_WINT_INIT_READY)
2101 break;
2102
2103 udelay(100);
2104 }
2105
2106 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2107 dev_warn(dev, "Firmware failed to start\n");
2108 ret = -EAGAIN;
2109 goto exit;
2110 }
2111
2112exit:
2113 return ret;
2114}
2115
2116static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2117{
2118 int pages, remainder, i, ret;
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2119 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2120 u16 val16;
2121 u32 val32;
2122 u8 *fwptr;
2123
2124 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2125 val8 |= 4;
2126 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2127
2128 /* 8051 enable */
2129 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame]2130 val16 |= SYS_FUNC_CPU_ENABLE;
2131 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2132
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2133 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2134 if (val8 & MCU_FW_RAM_SEL) {
2135 pr_info("do the RAM reset\n");
2136 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2137 rtl8xxxu_reset_8051(priv);
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2138 }
2139
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2140 /* MCU firmware download enable */
2141 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2142 val8 |= MCU_FW_DL_ENABLE;
2143 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2144
2145 /* 8051 reset */
2146 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2147 val32 &= ~BIT(19);
2148 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2149
2150 /* Reset firmware download checksum */
2151 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2152 val8 |= MCU_FW_DL_CSUM_REPORT;
2153 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2154
2155 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2156 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2157
2158 fwptr = priv->fw_data->data;
2159
2160 for (i = 0; i < pages; i++) {
2161 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2162 val8 |= i;
2163 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2164
2165 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2166 fwptr, RTL_FW_PAGE_SIZE);
2167 if (ret != RTL_FW_PAGE_SIZE) {
2168 ret = -EAGAIN;
2169 goto fw_abort;
2170 }
2171
2172 fwptr += RTL_FW_PAGE_SIZE;
2173 }
2174
2175 if (remainder) {
2176 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2177 val8 |= i;
2178 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2179 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2180 fwptr, remainder);
2181 if (ret != remainder) {
2182 ret = -EAGAIN;
2183 goto fw_abort;
2184 }
2185 }
2186
2187 ret = 0;
2188fw_abort:
2189 /* MCU firmware download disable */
2190 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2191 val16 &= ~MCU_FW_DL_ENABLE;
2192 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2193
2194 return ret;
2195}
2196
2197static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2198{
2199 struct device *dev = &priv->udev->dev;
2200 const struct firmware *fw;
2201 int ret = 0;
2202 u16 signature;
2203
2204 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2205 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2206 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2207 ret = -EAGAIN;
2208 goto exit;
2209 }
2210 if (!fw) {
2211 dev_warn(dev, "Firmware data not available\n");
2212 ret = -EINVAL;
2213 goto exit;
2214 }
2215
2216 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
Tobias Klauser98e27cb2016-02-03 13:39:43 -0500[diff] [blame]2217 if (!priv->fw_data) {
2218 ret = -ENOMEM;
2219 goto exit;
2220 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2221 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2222
2223 signature = le16_to_cpu(priv->fw_data->signature);
2224 switch (signature & 0xfff0) {
2225 case 0x92c0:
2226 case 0x88c0:
2227 case 0x2300:
2228 break;
2229 default:
2230 ret = -EINVAL;
2231 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2232 __func__, signature);
2233 }
2234
2235 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2236 le16_to_cpu(priv->fw_data->major_version),
2237 priv->fw_data->minor_version, signature);
2238
2239exit:
2240 release_firmware(fw);
2241 return ret;
2242}
2243
2244static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2245{
2246 char *fw_name;
2247 int ret;
2248
2249 switch (priv->chip_cut) {
2250 case 0:
2251 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2252 break;
2253 case 1:
2254 if (priv->enable_bluetooth)
2255 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2256 else
2257 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2258
2259 break;
2260 default:
2261 return -EINVAL;
2262 }
2263
2264 ret = rtl8xxxu_load_firmware(priv, fw_name);
2265 return ret;
2266}
2267
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2268#ifdef CONFIG_RTL8XXXU_UNTESTED
2269
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2270static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2271{
2272 char *fw_name;
2273 int ret;
2274
2275 if (!priv->vendor_umc)
2276 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2277 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2278 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2279 else
2280 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2281
2282 ret = rtl8xxxu_load_firmware(priv, fw_name);
2283
2284 return ret;
2285}
2286
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2287#endif
2288
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2289static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2290{
2291 u16 val16;
2292 int i = 100;
2293
2294 /* Inform 8051 to perform reset */
2295 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2296
2297 for (i = 100; i > 0; i--) {
2298 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2299
2300 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2301 dev_dbg(&priv->udev->dev,
2302 "%s: Firmware self reset success!\n", __func__);
2303 break;
2304 }
2305 udelay(50);
2306 }
2307
2308 if (!i) {
2309 /* Force firmware reset */
2310 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2311 val16 &= ~SYS_FUNC_CPU_ENABLE;
2312 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2313 }
2314}
2315
2316static int
2317rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2318{
2319 int i, ret;
2320 u16 reg;
2321 u8 val;
2322
2323 for (i = 0; ; i++) {
2324 reg = array[i].reg;
2325 val = array[i].val;
2326
2327 if (reg == 0xffff && val == 0xff)
2328 break;
2329
2330 ret = rtl8xxxu_write8(priv, reg, val);
2331 if (ret != 1) {
2332 dev_warn(&priv->udev->dev,
2333 "Failed to initialize MAC\n");
2334 return -EAGAIN;
2335 }
2336 }
2337
2338 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2339
2340 return 0;
2341}
2342
2343static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2344 struct rtl8xxxu_reg32val *array)
2345{
2346 int i, ret;
2347 u16 reg;
2348 u32 val;
2349
2350 for (i = 0; ; i++) {
2351 reg = array[i].reg;
2352 val = array[i].val;
2353
2354 if (reg == 0xffff && val == 0xffffffff)
2355 break;
2356
2357 ret = rtl8xxxu_write32(priv, reg, val);
2358 if (ret != sizeof(val)) {
2359 dev_warn(&priv->udev->dev,
2360 "Failed to initialize PHY\n");
2361 return -EAGAIN;
2362 }
2363 udelay(1);
2364 }
2365
2366 return 0;
2367}
2368
2369/*
2370 * Most of this is black magic retrieved from the old rtl8723au driver
2371 */
2372static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2373{
2374 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2375 u32 val32;
2376
2377 /*
2378 * Todo: The vendor driver maintains a table of PHY register
2379 * addresses, which is initialized here. Do we need this?
2380 */
2381
2382 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2383 udelay(2);
2384 val8 |= AFE_PLL_320_ENABLE;
2385 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2386 udelay(2);
2387
2388 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2389 udelay(2);
2390
2391 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2392 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2393 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2394
2395 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2396 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2397 val32 &= ~AFE_XTAL_RF_GATE;
2398 if (priv->has_bluetooth)
2399 val32 &= ~AFE_XTAL_BT_GATE;
2400 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2401
2402 /* 6. 0x1f[7:0] = 0x07 */
2403 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2404 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2405
2406 if (priv->hi_pa)
2407 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2408 else if (priv->tx_paths == 2)
2409 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2410 else
2411 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2412
2413
2414 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2415 priv->vendor_umc && priv->chip_cut == 1)
2416 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2417
2418 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2419 /*
2420 * For 1T2R boards, patch the registers.
2421 *
2422 * It looks like 8191/2 1T2R boards use path B for TX
2423 */
2424 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2425 val32 &= ~(BIT(0) | BIT(1));
2426 val32 |= BIT(1);
2427 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2428
2429 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2430 val32 &= ~0x300033;
2431 val32 |= 0x200022;
2432 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2433
2434 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2435 val32 &= 0xff000000;
2436 val32 |= 0x45000000;
2437 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2438
2439 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2440 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2441 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2442 OFDM_RF_PATH_TX_B);
2443 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2444
2445 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2446 val32 &= ~(BIT(4) | BIT(5));
2447 val32 |= BIT(4);
2448 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2449
2450 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2451 val32 &= ~(BIT(27) | BIT(26));
2452 val32 |= BIT(27);
2453 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2454
2455 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2456 val32 &= ~(BIT(27) | BIT(26));
2457 val32 |= BIT(27);
2458 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2459
2460 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2461 val32 &= ~(BIT(27) | BIT(26));
2462 val32 |= BIT(27);
2463 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2464
2465 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2466 val32 &= ~(BIT(27) | BIT(26));
2467 val32 |= BIT(27);
2468 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2469
2470 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2471 val32 &= ~(BIT(27) | BIT(26));
2472 val32 |= BIT(27);
2473 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2474 }
2475
2476 if (priv->hi_pa)
2477 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2478 else
2479 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2480
2481 if (priv->rtlchip == 0x8723a &&
2482 priv->efuse_wifi.efuse8723.version >= 0x01) {
2483 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2484
2485 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2486 val32 &= 0xff000fff;
2487 val32 |= ((val8 | (val8 << 6)) << 12);
2488
2489 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2490 }
2491
2492 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2493 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2494 ldohci12 = 0x57;
2495 lpldo = 1;
2496 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2497
2498 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2499
2500 return 0;
2501}
2502
2503static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2504 struct rtl8xxxu_rfregval *array,
2505 enum rtl8xxxu_rfpath path)
2506{
2507 int i, ret;
2508 u8 reg;
2509 u32 val;
2510
2511 for (i = 0; ; i++) {
2512 reg = array[i].reg;
2513 val = array[i].val;
2514
2515 if (reg == 0xff && val == 0xffffffff)
2516 break;
2517
2518 switch (reg) {
2519 case 0xfe:
2520 msleep(50);
2521 continue;
2522 case 0xfd:
2523 mdelay(5);
2524 continue;
2525 case 0xfc:
2526 mdelay(1);
2527 continue;
2528 case 0xfb:
2529 udelay(50);
2530 continue;
2531 case 0xfa:
2532 udelay(5);
2533 continue;
2534 case 0xf9:
2535 udelay(1);
2536 continue;
2537 }
2538
2539 reg &= 0x3f;
2540
2541 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2542 if (ret) {
2543 dev_warn(&priv->udev->dev,
2544 "Failed to initialize RF\n");
2545 return -EAGAIN;
2546 }
2547 udelay(1);
2548 }
2549
2550 return 0;
2551}
2552
2553static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2554 struct rtl8xxxu_rfregval *table,
2555 enum rtl8xxxu_rfpath path)
2556{
2557 u32 val32;
2558 u16 val16, rfsi_rfenv;
2559 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2560
2561 switch (path) {
2562 case RF_A:
2563 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2564 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2565 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2566 break;
2567 case RF_B:
2568 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2569 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2570 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2571 break;
2572 default:
2573 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2574 __func__, path + 'A');
2575 return -EINVAL;
2576 }
2577 /* For path B, use XB */
2578 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2579 rfsi_rfenv &= FPGA0_RF_RFENV;
2580
2581 /*
2582 * These two we might be able to optimize into one
2583 */
2584 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2585 val32 |= BIT(20); /* 0x10 << 16 */
2586 rtl8xxxu_write32(priv, reg_int_oe, val32);
2587 udelay(1);
2588
2589 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2590 val32 |= BIT(4);
2591 rtl8xxxu_write32(priv, reg_int_oe, val32);
2592 udelay(1);
2593
2594 /*
2595 * These two we might be able to optimize into one
2596 */
2597 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2598 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2599 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2600 udelay(1);
2601
2602 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2603 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2604 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2605 udelay(1);
2606
2607 rtl8xxxu_init_rf_regs(priv, table, path);
2608
2609 /* For path B, use XB */
2610 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2611 val16 &= ~FPGA0_RF_RFENV;
2612 val16 |= rfsi_rfenv;
2613 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2614
2615 return 0;
2616}
2617
2618static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2619{
2620 int ret = -EBUSY;
2621 int count = 0;
2622 u32 value;
2623
2624 value = LLT_OP_WRITE | address << 8 | data;
2625
2626 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2627
2628 do {
2629 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2630 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2631 ret = 0;
2632 break;
2633 }
2634 } while (count++ < 20);
2635
2636 return ret;
2637}
2638
2639static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2640{
2641 int ret;
2642 int i;
2643
2644 for (i = 0; i < last_tx_page; i++) {
2645 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2646 if (ret)
2647 goto exit;
2648 }
2649
2650 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2651 if (ret)
2652 goto exit;
2653
2654 /* Mark remaining pages as a ring buffer */
2655 for (i = last_tx_page + 1; i < 0xff; i++) {
2656 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2657 if (ret)
2658 goto exit;
2659 }
2660
2661 /* Let last entry point to the start entry of ring buffer */
2662 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2663 if (ret)
2664 goto exit;
2665
2666exit:
2667 return ret;
2668}
2669
2670static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2671{
2672 u16 val16, hi, lo;
2673 u16 hiq, mgq, bkq, beq, viq, voq;
2674 int hip, mgp, bkp, bep, vip, vop;
2675 int ret = 0;
2676
2677 switch (priv->ep_tx_count) {
2678 case 1:
2679 if (priv->ep_tx_high_queue) {
2680 hi = TRXDMA_QUEUE_HIGH;
2681 } else if (priv->ep_tx_low_queue) {
2682 hi = TRXDMA_QUEUE_LOW;
2683 } else if (priv->ep_tx_normal_queue) {
2684 hi = TRXDMA_QUEUE_NORMAL;
2685 } else {
2686 hi = 0;
2687 ret = -EINVAL;
2688 }
2689
2690 hiq = hi;
2691 mgq = hi;
2692 bkq = hi;
2693 beq = hi;
2694 viq = hi;
2695 voq = hi;
2696
2697 hip = 0;
2698 mgp = 0;
2699 bkp = 0;
2700 bep = 0;
2701 vip = 0;
2702 vop = 0;
2703 break;
2704 case 2:
2705 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2706 hi = TRXDMA_QUEUE_HIGH;
2707 lo = TRXDMA_QUEUE_LOW;
2708 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2709 hi = TRXDMA_QUEUE_NORMAL;
2710 lo = TRXDMA_QUEUE_LOW;
2711 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2712 hi = TRXDMA_QUEUE_HIGH;
2713 lo = TRXDMA_QUEUE_NORMAL;
2714 } else {
2715 ret = -EINVAL;
2716 hi = 0;
2717 lo = 0;
2718 }
2719
2720 hiq = hi;
2721 mgq = hi;
2722 bkq = lo;
2723 beq = lo;
2724 viq = hi;
2725 voq = hi;
2726
2727 hip = 0;
2728 mgp = 0;
2729 bkp = 1;
2730 bep = 1;
2731 vip = 0;
2732 vop = 0;
2733 break;
2734 case 3:
2735 beq = TRXDMA_QUEUE_LOW;
2736 bkq = TRXDMA_QUEUE_LOW;
2737 viq = TRXDMA_QUEUE_NORMAL;
2738 voq = TRXDMA_QUEUE_HIGH;
2739 mgq = TRXDMA_QUEUE_HIGH;
2740 hiq = TRXDMA_QUEUE_HIGH;
2741
2742 hip = hiq ^ 3;
2743 mgp = mgq ^ 3;
2744 bkp = bkq ^ 3;
2745 bep = beq ^ 3;
2746 vip = viq ^ 3;
2747 vop = viq ^ 3;
2748 break;
2749 default:
2750 ret = -EINVAL;
2751 }
2752
2753 /*
2754 * None of the vendor drivers are configuring the beacon
2755 * queue here .... why?
2756 */
2757 if (!ret) {
2758 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2759 val16 &= 0x7;
2760 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2761 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2762 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2763 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2764 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2765 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2766 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2767
2768 priv->pipe_out[TXDESC_QUEUE_VO] =
2769 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2770 priv->pipe_out[TXDESC_QUEUE_VI] =
2771 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2772 priv->pipe_out[TXDESC_QUEUE_BE] =
2773 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2774 priv->pipe_out[TXDESC_QUEUE_BK] =
2775 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2776 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2777 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2778 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2779 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2780 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2781 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2782 priv->pipe_out[TXDESC_QUEUE_CMD] =
2783 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2784 }
2785
2786 return ret;
2787}
2788
2789static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2790 bool iqk_ok, int result[][8],
2791 int candidate, bool tx_only)
2792{
2793 u32 oldval, x, tx0_a, reg;
2794 int y, tx0_c;
2795 u32 val32;
2796
2797 if (!iqk_ok)
2798 return;
2799
2800 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2801 oldval = val32 >> 22;
2802
2803 x = result[candidate][0];
2804 if ((x & 0x00000200) != 0)
2805 x = x | 0xfffffc00;
2806 tx0_a = (x * oldval) >> 8;
2807
2808 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2809 val32 &= ~0x3ff;
2810 val32 |= tx0_a;
2811 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2812
2813 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2814 val32 &= ~BIT(31);
2815 if ((x * oldval >> 7) & 0x1)
2816 val32 |= BIT(31);
2817 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2818
2819 y = result[candidate][1];
2820 if ((y & 0x00000200) != 0)
2821 y = y | 0xfffffc00;
2822 tx0_c = (y * oldval) >> 8;
2823
2824 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2825 val32 &= ~0xf0000000;
2826 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2827 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2828
2829 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2830 val32 &= ~0x003f0000;
2831 val32 |= ((tx0_c & 0x3f) << 16);
2832 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2833
2834 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2835 val32 &= ~BIT(29);
2836 if ((y * oldval >> 7) & 0x1)
2837 val32 |= BIT(29);
2838 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2839
2840 if (tx_only) {
2841 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2842 return;
2843 }
2844
2845 reg = result[candidate][2];
2846
2847 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2848 val32 &= ~0x3ff;
2849 val32 |= (reg & 0x3ff);
2850 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2851
2852 reg = result[candidate][3] & 0x3F;
2853
2854 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2855 val32 &= ~0xfc00;
2856 val32 |= ((reg << 10) & 0xfc00);
2857 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2858
2859 reg = (result[candidate][3] >> 6) & 0xF;
2860
2861 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2862 val32 &= ~0xf0000000;
2863 val32 |= (reg << 28);
2864 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2865}
2866
2867static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2868 bool iqk_ok, int result[][8],
2869 int candidate, bool tx_only)
2870{
2871 u32 oldval, x, tx1_a, reg;
2872 int y, tx1_c;
2873 u32 val32;
2874
2875 if (!iqk_ok)
2876 return;
2877
2878 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2879 oldval = val32 >> 22;
2880
2881 x = result[candidate][4];
2882 if ((x & 0x00000200) != 0)
2883 x = x | 0xfffffc00;
2884 tx1_a = (x * oldval) >> 8;
2885
2886 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2887 val32 &= ~0x3ff;
2888 val32 |= tx1_a;
2889 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2890
2891 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2892 val32 &= ~BIT(27);
2893 if ((x * oldval >> 7) & 0x1)
2894 val32 |= BIT(27);
2895 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2896
2897 y = result[candidate][5];
2898 if ((y & 0x00000200) != 0)
2899 y = y | 0xfffffc00;
2900 tx1_c = (y * oldval) >> 8;
2901
2902 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2903 val32 &= ~0xf0000000;
2904 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2905 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2906
2907 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2908 val32 &= ~0x003f0000;
2909 val32 |= ((tx1_c & 0x3f) << 16);
2910 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2911
2912 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2913 val32 &= ~BIT(25);
2914 if ((y * oldval >> 7) & 0x1)
2915 val32 |= BIT(25);
2916 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2917
2918 if (tx_only) {
2919 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2920 return;
2921 }
2922
2923 reg = result[candidate][6];
2924
2925 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2926 val32 &= ~0x3ff;
2927 val32 |= (reg & 0x3ff);
2928 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2929
2930 reg = result[candidate][7] & 0x3f;
2931
2932 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2933 val32 &= ~0xfc00;
2934 val32 |= ((reg << 10) & 0xfc00);
2935 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2936
2937 reg = (result[candidate][7] >> 6) & 0xf;
2938
2939 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2940 val32 &= ~0x0000f000;
2941 val32 |= (reg << 12);
2942 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2943}
2944
2945#define MAX_TOLERANCE 5
2946
2947static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2948 int result[][8], int c1, int c2)
2949{
2950 u32 i, j, diff, simubitmap, bound = 0;
2951 int candidate[2] = {-1, -1}; /* for path A and path B */
2952 bool retval = true;
2953
2954 if (priv->tx_paths > 1)
2955 bound = 8;
2956 else
2957 bound = 4;
2958
2959 simubitmap = 0;
2960
2961 for (i = 0; i < bound; i++) {
2962 diff = (result[c1][i] > result[c2][i]) ?
2963 (result[c1][i] - result[c2][i]) :
2964 (result[c2][i] - result[c1][i]);
2965 if (diff > MAX_TOLERANCE) {
2966 if ((i == 2 || i == 6) && !simubitmap) {
2967 if (result[c1][i] + result[c1][i + 1] == 0)
2968 candidate[(i / 4)] = c2;
2969 else if (result[c2][i] + result[c2][i + 1] == 0)
2970 candidate[(i / 4)] = c1;
2971 else
2972 simubitmap = simubitmap | (1 << i);
2973 } else {
2974 simubitmap = simubitmap | (1 << i);
2975 }
2976 }
2977 }
2978
2979 if (simubitmap == 0) {
2980 for (i = 0; i < (bound / 4); i++) {
2981 if (candidate[i] >= 0) {
2982 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2983 result[3][j] = result[candidate[i]][j];
2984 retval = false;
2985 }
2986 }
2987 return retval;
2988 } else if (!(simubitmap & 0x0f)) {
2989 /* path A OK */
2990 for (i = 0; i < 4; i++)
2991 result[3][i] = result[c1][i];
2992 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2993 /* path B OK */
2994 for (i = 4; i < 8; i++)
2995 result[3][i] = result[c1][i];
2996 }
2997
2998 return false;
2999}
3000
3001static void
3002rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3003{
3004 int i;
3005
3006 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3007 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3008
3009 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3010}
3011
3012static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3013 const u32 *reg, u32 *backup)
3014{
3015 int i;
3016
3017 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3018 rtl8xxxu_write8(priv, reg[i], backup[i]);
3019
3020 rtl8xxxu_write32(priv, reg[i], backup[i]);
3021}
3022
3023static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3024 u32 *backup, int count)
3025{
3026 int i;
3027
3028 for (i = 0; i < count; i++)
3029 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3030}
3031
3032static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3033 u32 *backup, int count)
3034{
3035 int i;
3036
3037 for (i = 0; i < count; i++)
3038 rtl8xxxu_write32(priv, regs[i], backup[i]);
3039}
3040
3041
3042static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3043 bool path_a_on)
3044{
3045 u32 path_on;
3046 int i;
3047
3048 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3049 if (priv->tx_paths == 1) {
3050 path_on = 0x0bdb25a0;
3051 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3052 } else {
3053 rtl8xxxu_write32(priv, regs[0], path_on);
3054 }
3055
3056 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3057 rtl8xxxu_write32(priv, regs[i], path_on);
3058}
3059
3060static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3061 const u32 *regs, u32 *backup)
3062{
3063 int i = 0;
3064
3065 rtl8xxxu_write8(priv, regs[i], 0x3f);
3066
3067 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3068 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3069
3070 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3071}
3072
3073static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3074{
3075 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3076 int result = 0;
3077
3078 /* path-A IQK setting */
3079 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3080 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3081 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3082
3083 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3084 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3085 0x28160502;
3086 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3087
3088 /* path-B IQK setting */
3089 if (priv->rf_paths > 1) {
3090 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3091 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3092 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3093 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3094 }
3095
3096 /* LO calibration setting */
3097 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3098
3099 /* One shot, path A LOK & IQK */
3100 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3101 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3102
3103 mdelay(1);
3104
3105 /* Check failed */
3106 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3107 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3108 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3109 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3110
3111 if (!(reg_eac & BIT(28)) &&
3112 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3113 ((reg_e9c & 0x03ff0000) != 0x00420000))
3114 result |= 0x01;
3115 else /* If TX not OK, ignore RX */
3116 goto out;
3117
3118 /* If TX is OK, check whether RX is OK */
3119 if (!(reg_eac & BIT(27)) &&
3120 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3121 ((reg_eac & 0x03ff0000) != 0x00360000))
3122 result |= 0x02;
3123 else
3124 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3125 __func__);
3126out:
3127 return result;
3128}
3129
3130static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3131{
3132 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3133 int result = 0;
3134
3135 /* One shot, path B LOK & IQK */
3136 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3137 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3138
3139 mdelay(1);
3140
3141 /* Check failed */
3142 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3143 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3144 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3145 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3146 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3147
3148 if (!(reg_eac & BIT(31)) &&
3149 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3150 ((reg_ebc & 0x03ff0000) != 0x00420000))
3151 result |= 0x01;
3152 else
3153 goto out;
3154
3155 if (!(reg_eac & BIT(30)) &&
3156 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3157 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3158 result |= 0x02;
3159 else
3160 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3161 __func__);
3162out:
3163 return result;
3164}
3165
3166static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3167 int result[][8], int t)
3168{
3169 struct device *dev = &priv->udev->dev;
3170 u32 i, val32;
3171 int path_a_ok, path_b_ok;
3172 int retry = 2;
3173 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3174 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3175 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3176 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3177 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3178 REG_TX_TO_TX, REG_RX_CCK,
3179 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3180 REG_RX_TO_RX, REG_STANDBY,
3181 REG_SLEEP, REG_PMPD_ANAEN
3182 };
3183 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3184 REG_TXPAUSE, REG_BEACON_CTRL,
3185 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3186 };
3187 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3188 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3189 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3190 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3191 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3192 };
3193
3194 /*
3195 * Note: IQ calibration must be performed after loading
3196 * PHY_REG.txt , and radio_a, radio_b.txt
3197 */
3198
3199 if (t == 0) {
3200 /* Save ADDA parameters, turn Path A ADDA on */
3201 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3202 RTL8XXXU_ADDA_REGS);
3203 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3204 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3205 priv->bb_backup, RTL8XXXU_BB_REGS);
3206 }
3207
3208 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3209
3210 if (t == 0) {
3211 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3212 if (val32 & FPGA0_HSSI_PARM1_PI)
3213 priv->pi_enabled = 1;
3214 }
3215
3216 if (!priv->pi_enabled) {
3217 /* Switch BB to PI mode to do IQ Calibration. */
3218 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3219 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3220 }
3221
3222 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3223 val32 &= ~FPGA_RF_MODE_CCK;
3224 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3225
3226 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3227 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3228 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3229
3230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3231 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3232 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3233
3234 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3235 val32 &= ~BIT(10);
3236 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3237 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3238 val32 &= ~BIT(10);
3239 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3240
3241 if (priv->tx_paths > 1) {
3242 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3243 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3244 }
3245
3246 /* MAC settings */
3247 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3248
3249 /* Page B init */
3250 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3251
3252 if (priv->tx_paths > 1)
3253 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3254
3255 /* IQ calibration setting */
3256 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3257 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3258 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3259
3260 for (i = 0; i < retry; i++) {
3261 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3262 if (path_a_ok == 0x03) {
3263 val32 = rtl8xxxu_read32(priv,
3264 REG_TX_POWER_BEFORE_IQK_A);
3265 result[t][0] = (val32 >> 16) & 0x3ff;
3266 val32 = rtl8xxxu_read32(priv,
3267 REG_TX_POWER_AFTER_IQK_A);
3268 result[t][1] = (val32 >> 16) & 0x3ff;
3269 val32 = rtl8xxxu_read32(priv,
3270 REG_RX_POWER_BEFORE_IQK_A_2);
3271 result[t][2] = (val32 >> 16) & 0x3ff;
3272 val32 = rtl8xxxu_read32(priv,
3273 REG_RX_POWER_AFTER_IQK_A_2);
3274 result[t][3] = (val32 >> 16) & 0x3ff;
3275 break;
3276 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3277 /* TX IQK OK */
3278 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3279 __func__);
3280
3281 val32 = rtl8xxxu_read32(priv,
3282 REG_TX_POWER_BEFORE_IQK_A);
3283 result[t][0] = (val32 >> 16) & 0x3ff;
3284 val32 = rtl8xxxu_read32(priv,
3285 REG_TX_POWER_AFTER_IQK_A);
3286 result[t][1] = (val32 >> 16) & 0x3ff;
3287 }
3288 }
3289
3290 if (!path_a_ok)
3291 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3292
3293 if (priv->tx_paths > 1) {
3294 /*
3295 * Path A into standby
3296 */
3297 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3298 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3299 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3300
3301 /* Turn Path B ADDA on */
3302 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3303
3304 for (i = 0; i < retry; i++) {
3305 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3306 if (path_b_ok == 0x03) {
3307 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3308 result[t][4] = (val32 >> 16) & 0x3ff;
3309 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3310 result[t][5] = (val32 >> 16) & 0x3ff;
3311 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3312 result[t][6] = (val32 >> 16) & 0x3ff;
3313 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3314 result[t][7] = (val32 >> 16) & 0x3ff;
3315 break;
3316 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3317 /* TX IQK OK */
3318 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3319 result[t][4] = (val32 >> 16) & 0x3ff;
3320 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3321 result[t][5] = (val32 >> 16) & 0x3ff;
3322 }
3323 }
3324
3325 if (!path_b_ok)
3326 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3327 }
3328
3329 /* Back to BB mode, load original value */
3330 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3331
3332 if (t) {
3333 if (!priv->pi_enabled) {
3334 /*
3335 * Switch back BB to SI mode after finishing
3336 * IQ Calibration
3337 */
3338 val32 = 0x01000000;
3339 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3340 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3341 }
3342
3343 /* Reload ADDA power saving parameters */
3344 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3345 RTL8XXXU_ADDA_REGS);
3346
3347 /* Reload MAC parameters */
3348 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3349
3350 /* Reload BB parameters */
3351 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3352 priv->bb_backup, RTL8XXXU_BB_REGS);
3353
3354 /* Restore RX initial gain */
3355 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3356
3357 if (priv->tx_paths > 1) {
3358 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3359 0x00032ed3);
3360 }
3361
3362 /* Load 0xe30 IQC default value */
3363 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3364 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3365 }
3366}
3367
3368static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3369{
3370 struct device *dev = &priv->udev->dev;
3371 int result[4][8]; /* last is final result */
3372 int i, candidate;
3373 bool path_a_ok, path_b_ok;
3374 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3375 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3376 s32 reg_tmp = 0;
3377 bool simu;
3378
3379 memset(result, 0, sizeof(result));
3380 candidate = -1;
3381
3382 path_a_ok = false;
3383 path_b_ok = false;
3384
3385 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3386
3387 for (i = 0; i < 3; i++) {
3388 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3389
3390 if (i == 1) {
3391 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3392 if (simu) {
3393 candidate = 0;
3394 break;
3395 }
3396 }
3397
3398 if (i == 2) {
3399 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3400 if (simu) {
3401 candidate = 0;
3402 break;
3403 }
3404
3405 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3406 if (simu) {
3407 candidate = 1;
3408 } else {
3409 for (i = 0; i < 8; i++)
3410 reg_tmp += result[3][i];
3411
3412 if (reg_tmp)
3413 candidate = 3;
3414 else
3415 candidate = -1;
3416 }
3417 }
3418 }
3419
3420 for (i = 0; i < 4; i++) {
3421 reg_e94 = result[i][0];
3422 reg_e9c = result[i][1];
3423 reg_ea4 = result[i][2];
3424 reg_eac = result[i][3];
3425 reg_eb4 = result[i][4];
3426 reg_ebc = result[i][5];
3427 reg_ec4 = result[i][6];
3428 reg_ecc = result[i][7];
3429 }
3430
3431 if (candidate >= 0) {
3432 reg_e94 = result[candidate][0];
3433 priv->rege94 = reg_e94;
3434 reg_e9c = result[candidate][1];
3435 priv->rege9c = reg_e9c;
3436 reg_ea4 = result[candidate][2];
3437 reg_eac = result[candidate][3];
3438 reg_eb4 = result[candidate][4];
3439 priv->regeb4 = reg_eb4;
3440 reg_ebc = result[candidate][5];
3441 priv->regebc = reg_ebc;
3442 reg_ec4 = result[candidate][6];
3443 reg_ecc = result[candidate][7];
3444 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3445 dev_dbg(dev,
3446 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3447 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3448 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3449 path_a_ok = true;
3450 path_b_ok = true;
3451 } else {
3452 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3453 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3454 }
3455
3456 if (reg_e94 && candidate >= 0)
3457 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3458 candidate, (reg_ea4 == 0));
3459
3460 if (priv->tx_paths > 1 && reg_eb4)
3461 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3462 candidate, (reg_ec4 == 0));
3463
3464 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3465 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3466}
3467
3468static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3469{
3470 u32 val32;
3471 u32 rf_amode, rf_bmode = 0, lstf;
3472
3473 /* Check continuous TX and Packet TX */
3474 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3475
3476 if (lstf & OFDM_LSTF_MASK) {
3477 /* Disable all continuous TX */
3478 val32 = lstf & ~OFDM_LSTF_MASK;
3479 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3480
3481 /* Read original RF mode Path A */
3482 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3483
3484 /* Set RF mode to standby Path A */
3485 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3486 (rf_amode & 0x8ffff) | 0x10000);
3487
3488 /* Path-B */
3489 if (priv->tx_paths > 1) {
3490 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3491 RF6052_REG_AC);
3492
3493 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3494 (rf_bmode & 0x8ffff) | 0x10000);
3495 }
3496 } else {
3497 /* Deal with Packet TX case */
3498 /* block all queues */
3499 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3500 }
3501
3502 /* Start LC calibration */
3503 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3504 val32 |= 0x08000;
3505 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3506
3507 msleep(100);
3508
3509 /* Restore original parameters */
3510 if (lstf & OFDM_LSTF_MASK) {
3511 /* Path-A */
3512 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3513 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3514
3515 /* Path-B */
3516 if (priv->tx_paths > 1)
3517 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3518 rf_bmode);
3519 } else /* Deal with Packet TX case */
3520 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3521}
3522
3523static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3524{
3525 int i;
3526 u16 reg;
3527
3528 reg = REG_MACID;
3529
3530 for (i = 0; i < ETH_ALEN; i++)
3531 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3532
3533 return 0;
3534}
3535
3536static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3537{
3538 int i;
3539 u16 reg;
3540
3541 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3542
3543 reg = REG_BSSID;
3544
3545 for (i = 0; i < ETH_ALEN; i++)
3546 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3547
3548 return 0;
3549}
3550
3551static void
3552rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3553{
3554 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3555 u8 max_agg = 0xf;
3556 int i;
3557
3558 ampdu_factor = 1 << (ampdu_factor + 2);
3559 if (ampdu_factor > max_agg)
3560 ampdu_factor = max_agg;
3561
3562 for (i = 0; i < 4; i++) {
3563 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3564 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3565
3566 if ((vals[i] & 0x0f) > ampdu_factor)
3567 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3568
3569 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3570 }
3571}
3572
3573static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3574{
3575 u8 val8;
3576
3577 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3578 val8 &= 0xf8;
3579 val8 |= density;
3580 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3581}
3582
3583static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3584{
3585 u8 val8;
3586 int count, ret;
3587
3588 /* Start of rtl8723AU_card_enable_flow */
3589 /* Act to Cardemu sequence*/
3590 /* Turn off RF */
3591 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3592
3593 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3594 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3595 val8 &= ~LEDCFG2_DPDT_SELECT;
3596 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3597
3598 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3599 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3600 val8 |= BIT(1);
3601 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3602
3603 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3604 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3605 if ((val8 & BIT(1)) == 0)
3606 break;
3607 udelay(10);
3608 }
3609
3610 if (!count) {
3611 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3612 __func__);
3613 ret = -EBUSY;
3614 goto exit;
3615 }
3616
3617 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3618 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3619 val8 |= SYS_ISO_ANALOG_IPS;
3620 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3621
3622 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3623 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3624 val8 &= ~LDOA15_ENABLE;
3625 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3626
3627exit:
3628 return ret;
3629}
3630
3631static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3632{
3633 u8 val8;
3634 u8 val32;
3635 int count, ret;
3636
3637 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3638
3639 /*
3640 * Poll - wait for RX packet to complete
3641 */
3642 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3643 val32 = rtl8xxxu_read32(priv, 0x5f8);
3644 if (!val32)
3645 break;
3646 udelay(10);
3647 }
3648
3649 if (!count) {
3650 dev_warn(&priv->udev->dev,
3651 "%s: RX poll timed out (0x05f8)\n", __func__);
3652 ret = -EBUSY;
3653 goto exit;
3654 }
3655
3656 /* Disable CCK and OFDM, clock gated */
3657 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3658 val8 &= ~SYS_FUNC_BBRSTB;
3659 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3660
3661 udelay(2);
3662
3663 /* Reset baseband */
3664 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3665 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3666 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3667
3668 /* Reset MAC TRX */
3669 val8 = rtl8xxxu_read8(priv, REG_CR);
3670 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3671 rtl8xxxu_write8(priv, REG_CR, val8);
3672
3673 /* Reset MAC TRX */
3674 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3675 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3676 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3677
3678 /* Respond TX OK to scheduler */
3679 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3680 val8 |= DUAL_TSF_TX_OK;
3681 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3682
3683exit:
3684 return ret;
3685}
3686
3687static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3688{
3689 u8 val8;
3690
3691 /* Clear suspend enable and power down enable*/
3692 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3693 val8 &= ~(BIT(3) | BIT(7));
3694 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3695
3696 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3697 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3698 val8 &= ~BIT(0);
3699 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3700
3701 /* 0x04[12:11] = 11 enable WL suspend*/
3702 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3703 val8 &= ~(BIT(3) | BIT(4));
3704 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3705}
3706
3707static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3708{
3709 u8 val8;
3710 u32 val32;
3711 int count, ret = 0;
3712
3713 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3714 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3715 val8 |= LDOA15_ENABLE;
3716 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3717
3718 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3719 val8 = rtl8xxxu_read8(priv, 0x0067);
3720 val8 &= ~BIT(4);
3721 rtl8xxxu_write8(priv, 0x0067, val8);
3722
3723 mdelay(1);
3724
3725 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3726 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3727 val8 &= ~SYS_ISO_ANALOG_IPS;
3728 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3729
3730 /* disable SW LPS 0x04[10]= 0 */
3731 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3732 val8 &= ~BIT(2);
3733 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3734
3735 /* wait till 0x04[17] = 1 power ready*/
3736 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3737 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3738 if (val32 & BIT(17))
3739 break;
3740
3741 udelay(10);
3742 }
3743
3744 if (!count) {
3745 ret = -EBUSY;
3746 goto exit;
3747 }
3748
3749 /* We should be able to optimize the following three entries into one */
3750
3751 /* release WLON reset 0x04[16]= 1*/
3752 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3753 val8 |= BIT(0);
3754 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3755
3756 /* disable HWPDN 0x04[15]= 0*/
3757 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3758 val8 &= ~BIT(7);
3759 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3760
3761 /* disable WL suspend*/
3762 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3763 val8 &= ~(BIT(3) | BIT(4));
3764 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3765
3766 /* set, then poll until 0 */
3767 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3768 val32 |= APS_FSMCO_MAC_ENABLE;
3769 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3770
3771 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3772 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3773 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3774 ret = 0;
3775 break;
3776 }
3777 udelay(10);
3778 }
3779
3780 if (!count) {
3781 ret = -EBUSY;
3782 goto exit;
3783 }
3784
3785 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3786 /*
3787 * Note: Vendor driver actually clears this bit, despite the
3788 * documentation claims it's being set!
3789 */
3790 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3791 val8 |= LEDCFG2_DPDT_SELECT;
3792 val8 &= ~LEDCFG2_DPDT_SELECT;
3793 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3794
3795exit:
3796 return ret;
3797}
3798
3799static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3800{
3801 u8 val8;
3802
3803 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3804 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3805
3806 /* 0x04[12:11] = 01 enable WL suspend */
3807 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3808 val8 &= ~BIT(4);
3809 val8 |= BIT(3);
3810 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3811
3812 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3813 val8 |= BIT(7);
3814 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3815
3816 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3817 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3818 val8 |= BIT(0);
3819 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3820
3821 return 0;
3822}
3823
3824static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3825{
3826 u8 val8;
3827 u16 val16;
3828 u32 val32;
3829 int ret;
3830
3831 /*
3832 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3833 */
3834 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3835
3836 rtl8xxxu_disabled_to_emu(priv);
3837
3838 ret = rtl8xxxu_emu_to_active(priv);
3839 if (ret)
3840 goto exit;
3841
3842 /*
3843 * 0x0004[19] = 1, reset 8051
3844 */
3845 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3846 val8 |= BIT(3);
3847 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3848
3849 /*
3850 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3851 * Set CR bit10 to enable 32k calibration.
3852 */
3853 val16 = rtl8xxxu_read16(priv, REG_CR);
3854 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3855 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3856 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3857 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3858 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3859 rtl8xxxu_write16(priv, REG_CR, val16);
3860
3861 /* For EFuse PG */
3862 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3863 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3864 val32 |= (0x06 << 28);
3865 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3866exit:
3867 return ret;
3868}
3869
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3870#ifdef CONFIG_RTL8XXXU_UNTESTED
3871
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3872static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3873{
3874 u8 val8;
3875 u16 val16;
3876 u32 val32;
3877 int i;
3878
3879 for (i = 100; i; i--) {
3880 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3881 if (val8 & APS_FSMCO_PFM_ALDN)
3882 break;
3883 }
3884
3885 if (!i) {
3886 pr_info("%s: Poll failed\n", __func__);
3887 return -ENODEV;
3888 }
3889
3890 /*
3891 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3892 */
3893 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3894 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3895 udelay(100);
3896
3897 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3898 if (!(val8 & LDOV12D_ENABLE)) {
3899 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3900 val8 |= LDOV12D_ENABLE;
3901 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3902
3903 udelay(100);
3904
3905 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3906 val8 &= ~SYS_ISO_MD2PP;
3907 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3908 }
3909
3910 /*
3911 * Auto enable WLAN
3912 */
3913 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3914 val16 |= APS_FSMCO_MAC_ENABLE;
3915 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3916
3917 for (i = 1000; i; i--) {
3918 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3919 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3920 break;
3921 }
3922 if (!i) {
3923 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3924 return -EBUSY;
3925 }
3926
3927 /*
3928 * Enable radio, GPIO, LED
3929 */
3930 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3931 APS_FSMCO_PFM_ALDN;
3932 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3933
3934 /*
3935 * Release RF digital isolation
3936 */
3937 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3938 val16 &= ~SYS_ISO_DIOR;
3939 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3940
3941 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3942 val8 &= ~APSD_CTRL_OFF;
3943 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3944 for (i = 200; i; i--) {
3945 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3946 if (!(val8 & APSD_CTRL_OFF_STATUS))
3947 break;
3948 }
3949
3950 if (!i) {
3951 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3952 return -EBUSY;
3953 }
3954
3955 /*
3956 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3957 */
3958 val16 = rtl8xxxu_read16(priv, REG_CR);
3959 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3960 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3961 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3962 rtl8xxxu_write16(priv, REG_CR, val16);
3963
3964 /*
3965 * Workaround for 8188RU LNA power leakage problem.
3966 */
3967 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3968 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3969 val32 &= ~BIT(1);
3970 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3971 }
3972 return 0;
3973}
3974
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3975#endif
3976
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3977static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3978{
3979 u8 val8;
3980 u16 val16;
3981 u32 val32;
3982
3983 /*
3984 * Workaround for 8188RU LNA power leakage problem.
3985 */
3986 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3987 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3988 val32 |= BIT(1);
3989 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3990 }
3991
3992 rtl8xxxu_active_to_lps(priv);
3993
3994 /* Turn off RF */
3995 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3996
3997 /* Reset Firmware if running in RAM */
3998 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3999 rtl8xxxu_firmware_self_reset(priv);
4000
4001 /* Reset MCU */
4002 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4003 val16 &= ~SYS_FUNC_CPU_ENABLE;
4004 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4005
4006 /* Reset MCU ready status */
4007 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4008
4009 rtl8xxxu_active_to_emu(priv);
4010 rtl8xxxu_emu_to_disabled(priv);
4011
4012 /* Reset MCU IO Wrapper */
4013 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4014 val8 &= ~BIT(0);
4015 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4016
4017 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4018 val8 |= BIT(0);
4019 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4020
4021 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4022 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4023}
4024
4025static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4026{
4027 if (!priv->has_bluetooth)
4028 return;
4029}
4030
4031static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4032{
4033 struct rtl8xxxu_priv *priv = hw->priv;
4034 struct device *dev = &priv->udev->dev;
4035 struct rtl8xxxu_rfregval *rftable;
4036 bool macpower;
4037 int ret;
4038 u8 val8;
4039 u16 val16;
4040 u32 val32;
4041
4042 /* Check if MAC is already powered on */
4043 val8 = rtl8xxxu_read8(priv, REG_CR);
4044
4045 /*
4046 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4047 * initialized. First MAC returns 0xea, second MAC returns 0x00
4048 */
4049 if (val8 == 0xea)
4050 macpower = false;
4051 else
4052 macpower = true;
4053
4054 ret = priv->fops->power_on(priv);
4055 if (ret < 0) {
4056 dev_warn(dev, "%s: Failed power on\n", __func__);
4057 goto exit;
4058 }
4059
4060 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4061 if (!macpower) {
4062 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4063 if (ret) {
4064 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4065 goto exit;
4066 }
4067 }
4068
4069 ret = rtl8xxxu_download_firmware(priv);
4070 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4071 if (ret)
4072 goto exit;
4073 ret = rtl8xxxu_start_firmware(priv);
4074 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4075 if (ret)
4076 goto exit;
4077
4078 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4079 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4080 if (ret)
4081 goto exit;
4082
4083 ret = rtl8xxxu_init_phy_bb(priv);
4084 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4085 if (ret)
4086 goto exit;
4087
4088 switch(priv->rtlchip) {
4089 case 0x8723a:
4090 rftable = rtl8723au_radioa_1t_init_table;
4091 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4092 break;
4093 case 0x8188c:
4094 if (priv->hi_pa)
4095 rftable = rtl8188ru_radioa_1t_highpa_table;
4096 else
4097 rftable = rtl8192cu_radioa_1t_init_table;
4098 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4099 break;
4100 case 0x8191c:
4101 rftable = rtl8192cu_radioa_1t_init_table;
4102 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4103 break;
4104 case 0x8192c:
4105 rftable = rtl8192cu_radioa_2t_init_table;
4106 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4107 if (ret)
4108 break;
4109 rftable = rtl8192cu_radiob_2t_init_table;
4110 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4111 break;
4112 default:
4113 ret = -EINVAL;
4114 }
4115
4116 if (ret)
4117 goto exit;
4118
4119 /* Reduce 80M spur */
4120 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4121 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4122 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4123 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4124
4125 /* RFSW Control - clear bit 14 ?? */
4126 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4127 /* 0x07000760 */
4128 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4129 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4130 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4131 FPGA0_RF_BD_CTRL_SHIFT);
4132 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4133 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4134 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4135
4136 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4137 RF6052_REG_MODE_AG);
4138
4139 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4140 if (!macpower) {
4141 if (priv->ep_tx_normal_queue)
4142 val8 = TX_PAGE_NUM_NORM_PQ;
4143 else
4144 val8 = 0;
4145
4146 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4147
4148 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4149
4150 if (priv->ep_tx_high_queue)
4151 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4152 if (priv->ep_tx_low_queue)
4153 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4154
4155 rtl8xxxu_write32(priv, REG_RQPN, val32);
4156
4157 /*
4158 * Set TX buffer boundary
4159 */
4160 val8 = TX_TOTAL_PAGE_NUM + 1;
4161 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4162 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4163 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4164 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4165 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4166 }
4167
4168 ret = rtl8xxxu_init_queue_priority(priv);
4169 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4170 if (ret)
4171 goto exit;
4172
4173 /*
4174 * Set RX page boundary
4175 */
4176 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4177 /*
4178 * Transfer page size is always 128
4179 */
4180 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4181 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4182 rtl8xxxu_write8(priv, REG_PBP, val8);
4183
4184 /*
4185 * Unit in 8 bytes, not obvious what it is used for
4186 */
4187 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4188
4189 /*
4190 * Enable all interrupts - not obvious USB needs to do this
4191 */
4192 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4193 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4194
4195 rtl8xxxu_set_mac(priv);
4196 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4197
4198 /*
4199 * Configure initial WMAC settings
4200 */
4201 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4202 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4203 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4204 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4205 rtl8xxxu_write32(priv, REG_RCR, val32);
4206
4207 /*
4208 * Accept all multicast
4209 */
4210 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4211 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4212
4213 /*
4214 * Init adaptive controls
4215 */
4216 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4217 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4218 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4219 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4220
4221 /* CCK = 0x0a, OFDM = 0x10 */
4222 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4223 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4224 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4225
4226 /*
4227 * Init EDCA
4228 */
4229 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4230
4231 /* Set CCK SIFS */
4232 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4233
4234 /* Set OFDM SIFS */
4235 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4236
4237 /* TXOP */
4238 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4239 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4240 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4241 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4242
4243 /* Set data auto rate fallback retry count */
4244 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4245 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4246 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4247 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4248
4249 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4250 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4251 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4252
4253 /* Set ACK timeout */
4254 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4255
4256 /*
4257 * Initialize beacon parameters
4258 */
4259 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4260 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4261 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4262 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4263 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4264 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4265
4266 /*
4267 * Enable CCK and OFDM block
4268 */
4269 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4270 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4271 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4272
4273 /*
4274 * Invalidate all CAM entries - bit 30 is undocumented
4275 */
4276 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4277
4278 /*
4279 * Start out with default power levels for channel 6, 20MHz
4280 */
4281 rtl8723a_set_tx_power(priv, 1, false);
4282
4283 /* Let the 8051 take control of antenna setting */
4284 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4285 val8 |= LEDCFG2_DPDT_SELECT;
4286 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4287
4288 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4289
4290 /* Disable BAR - not sure if this has any effect on USB */
4291 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4292
4293 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4294
Jes Sorensene5c447c2016-02-03 13:39:48 -0500[diff] [blame]4295 rtl8723a_phy_iq_calibrate(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4296
4297 /*
4298 * This should enable thermal meter
4299 */
4300 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4301
4302 rtl8723a_phy_lc_calibrate(priv);
4303
4304 /* fix USB interface interference issue */
4305 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4306 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4307 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4308 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4309
4310 /* Solve too many protocol error on USB bus */
4311 /* Can't do this for 8188/8192 UMC A cut parts */
4312 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4313 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4314 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4315
4316 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4317 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4318 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4319
4320 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4321 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4322 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4323
4324 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4325 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4326 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4327
4328 /* Init BT hw config. */
4329 rtl8xxxu_init_bt(priv);
4330
4331 /*
4332 * Not sure if we really need to save these parameters, but the
4333 * vendor driver does
4334 */
4335 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4336 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4337 priv->path_a_hi_power = 1;
4338
4339 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4340 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4341
4342 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4343 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4344
4345 /* Set NAV_UPPER to 30000us */
4346 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4347 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4348
4349 /*
4350 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4351 * but we need to fin root cause.
4352 */
4353 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4354 if ((val32 & 0xff000000) != 0x83000000) {
4355 val32 |= FPGA_RF_MODE_CCK;
4356 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4357 }
4358
4359 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4360 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4361 /* ack for xmit mgmt frames. */
4362 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4363
4364exit:
4365 return ret;
4366}
4367
4368static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4369{
4370 struct rtl8xxxu_priv *priv = hw->priv;
4371
4372 rtl8xxxu_power_off(priv);
4373}
4374
4375static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4376 struct ieee80211_key_conf *key, const u8 *mac)
4377{
4378 u32 cmd, val32, addr, ctrl;
4379 int j, i, tmp_debug;
4380
4381 tmp_debug = rtl8xxxu_debug;
4382 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4383 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4384
4385 /*
4386 * This is a bit of a hack - the lower bits of the cipher
4387 * suite selector happens to match the cipher index in the CAM
4388 */
4389 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4390 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4391
4392 for (j = 5; j >= 0; j--) {
4393 switch (j) {
4394 case 0:
4395 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4396 break;
4397 case 1:
4398 val32 = mac[2] | (mac[3] << 8) |
4399 (mac[4] << 16) | (mac[5] << 24);
4400 break;
4401 default:
4402 i = (j - 2) << 2;
4403 val32 = key->key[i] | (key->key[i + 1] << 8) |
4404 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4405 break;
4406 }
4407
4408 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4409 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4410 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4411 udelay(100);
4412 }
4413
4414 rtl8xxxu_debug = tmp_debug;
4415}
4416
4417static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4418 struct ieee80211_vif *vif, const u8* mac)
4419{
4420 struct rtl8xxxu_priv *priv = hw->priv;
4421 u8 val8;
4422
4423 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4424 val8 |= BEACON_DISABLE_TSF_UPDATE;
4425 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4426}
4427
4428static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4429 struct ieee80211_vif *vif)
4430{
4431 struct rtl8xxxu_priv *priv = hw->priv;
4432 u8 val8;
4433
4434 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4435 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4436 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4437}
4438
4439static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4440 u32 ramask, int sgi)
4441{
4442 struct h2c_cmd h2c;
4443
4444 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4445 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4446 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4447
4448 h2c.ramask.arg = 0x80;
4449 if (sgi)
4450 h2c.ramask.arg |= 0x20;
4451
4452 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4453 ramask, h2c.ramask.arg);
4454 rtl8723a_h2c_cmd(priv, &h2c);
4455}
4456
4457static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4458{
4459 u32 val32;
4460 u8 rate_idx = 0;
4461
4462 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4463
4464 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4465 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4466 val32 |= rate_cfg;
4467 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4468
4469 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4470
4471 while (rate_cfg) {
4472 rate_cfg = (rate_cfg >> 1);
4473 rate_idx++;
4474 }
4475 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4476}
4477
4478static void
4479rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4480 struct ieee80211_bss_conf *bss_conf, u32 changed)
4481{
4482 struct rtl8xxxu_priv *priv = hw->priv;
4483 struct device *dev = &priv->udev->dev;
4484 struct ieee80211_sta *sta;
4485 u32 val32;
4486 u8 val8;
4487
4488 if (changed & BSS_CHANGED_ASSOC) {
4489 struct h2c_cmd h2c;
4490
4491 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4492
4493 memset(&h2c, 0, sizeof(struct h2c_cmd));
4494 rtl8xxxu_set_linktype(priv, vif->type);
4495
4496 if (bss_conf->assoc) {
4497 u32 ramask;
4498 int sgi = 0;
4499
4500 rcu_read_lock();
4501 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4502 if (!sta) {
4503 dev_info(dev, "%s: ASSOC no sta found\n",
4504 __func__);
4505 rcu_read_unlock();
4506 goto error;
4507 }
4508
4509 if (sta->ht_cap.ht_supported)
4510 dev_info(dev, "%s: HT supported\n", __func__);
4511 if (sta->vht_cap.vht_supported)
4512 dev_info(dev, "%s: VHT supported\n", __func__);
4513
4514 /* TODO: Set bits 28-31 for rate adaptive id */
4515 ramask = (sta->supp_rates[0] & 0xfff) |
4516 sta->ht_cap.mcs.rx_mask[0] << 12 |
4517 sta->ht_cap.mcs.rx_mask[1] << 20;
4518 if (sta->ht_cap.cap &
4519 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4520 sgi = 1;
4521 rcu_read_unlock();
4522
4523 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4524
4525 val32 = rtl8xxxu_read32(priv, REG_RCR);
4526 val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4527 rtl8xxxu_write32(priv, REG_RCR, val32);
4528
4529 /* Enable RX of data frames */
4530 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4531
4532 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4533
4534 rtl8723a_stop_tx_beacon(priv);
4535
4536 /* joinbss sequence */
4537 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4538 0xc000 | bss_conf->aid);
4539
4540 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4541 } else {
4542 val32 = rtl8xxxu_read32(priv, REG_RCR);
4543 val32 &= ~(RCR_CHECK_BSSID_MATCH |
4544 RCR_CHECK_BSSID_BEACON);
4545 rtl8xxxu_write32(priv, REG_RCR, val32);
4546
4547 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4548 val8 |= BEACON_DISABLE_TSF_UPDATE;
4549 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4550
4551 /* Disable RX of data frames */
4552 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4553 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4554 }
4555 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4556 rtl8723a_h2c_cmd(priv, &h2c);
4557 }
4558
4559 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4560 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4561 bss_conf->use_short_preamble);
4562 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4563 if (bss_conf->use_short_preamble)
4564 val32 |= RSR_ACK_SHORT_PREAMBLE;
4565 else
4566 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4567 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4568 }
4569
4570 if (changed & BSS_CHANGED_ERP_SLOT) {
4571 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4572 bss_conf->use_short_slot);
4573
4574 if (bss_conf->use_short_slot)
4575 val8 = 9;
4576 else
4577 val8 = 20;
4578 rtl8xxxu_write8(priv, REG_SLOT, val8);
4579 }
4580
4581 if (changed & BSS_CHANGED_BSSID) {
4582 dev_dbg(dev, "Changed BSSID!\n");
4583 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4584 }
4585
4586 if (changed & BSS_CHANGED_BASIC_RATES) {
4587 dev_dbg(dev, "Changed BASIC_RATES!\n");
4588 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4589 }
4590error:
4591 return;
4592}
4593
4594static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4595{
4596 u32 rtlqueue;
4597
4598 switch (queue) {
4599 case IEEE80211_AC_VO:
4600 rtlqueue = TXDESC_QUEUE_VO;
4601 break;
4602 case IEEE80211_AC_VI:
4603 rtlqueue = TXDESC_QUEUE_VI;
4604 break;
4605 case IEEE80211_AC_BE:
4606 rtlqueue = TXDESC_QUEUE_BE;
4607 break;
4608 case IEEE80211_AC_BK:
4609 rtlqueue = TXDESC_QUEUE_BK;
4610 break;
4611 default:
4612 rtlqueue = TXDESC_QUEUE_BE;
4613 }
4614
4615 return rtlqueue;
4616}
4617
4618static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4619{
4620 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4621 u32 queue;
4622
4623 if (ieee80211_is_mgmt(hdr->frame_control))
4624 queue = TXDESC_QUEUE_MGNT;
4625 else
4626 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4627
4628 return queue;
4629}
4630
4631static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4632{
4633 __le16 *ptr = (__le16 *)tx_desc;
4634 u16 csum = 0;
4635 int i;
4636
4637 /*
4638 * Clear csum field before calculation, as the csum field is
4639 * in the middle of the struct.
4640 */
4641 tx_desc->csum = cpu_to_le16(0);
4642
4643 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4644 csum = csum ^ le16_to_cpu(ptr[i]);
4645
4646 tx_desc->csum |= cpu_to_le16(csum);
4647}
4648
4649static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4650{
4651 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4652 unsigned long flags;
4653
4654 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4655 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4656 list_del(&tx_urb->list);
4657 priv->tx_urb_free_count--;
4658 usb_free_urb(&tx_urb->urb);
4659 }
4660 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4661}
4662
4663static struct rtl8xxxu_tx_urb *
4664rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4665{
4666 struct rtl8xxxu_tx_urb *tx_urb;
4667 unsigned long flags;
4668
4669 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4670 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4671 struct rtl8xxxu_tx_urb, list);
4672 if (tx_urb) {
4673 list_del(&tx_urb->list);
4674 priv->tx_urb_free_count--;
4675 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4676 !priv->tx_stopped) {
4677 priv->tx_stopped = true;
4678 ieee80211_stop_queues(priv->hw);
4679 }
4680 }
4681
4682 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4683
4684 return tx_urb;
4685}
4686
4687static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4688 struct rtl8xxxu_tx_urb *tx_urb)
4689{
4690 unsigned long flags;
4691
4692 INIT_LIST_HEAD(&tx_urb->list);
4693
4694 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4695
4696 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4697 priv->tx_urb_free_count++;
4698 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4699 priv->tx_stopped) {
4700 priv->tx_stopped = false;
4701 ieee80211_wake_queues(priv->hw);
4702 }
4703
4704 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4705}
4706
4707static void rtl8xxxu_tx_complete(struct urb *urb)
4708{
4709 struct sk_buff *skb = (struct sk_buff *)urb->context;
4710 struct ieee80211_tx_info *tx_info;
4711 struct ieee80211_hw *hw;
4712 struct rtl8xxxu_tx_urb *tx_urb =
4713 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4714
4715 tx_info = IEEE80211_SKB_CB(skb);
4716 hw = tx_info->rate_driver_data[0];
4717
4718 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4719
4720 ieee80211_tx_info_clear_status(tx_info);
4721 tx_info->status.rates[0].idx = -1;
4722 tx_info->status.rates[0].count = 0;
4723
4724 if (!urb->status)
4725 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4726
4727 ieee80211_tx_status_irqsafe(hw, skb);
4728
4729 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4730}
4731
4732static void rtl8xxxu_dump_action(struct device *dev,
4733 struct ieee80211_hdr *hdr)
4734{
4735 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4736 u16 cap, timeout;
4737
4738 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4739 return;
4740
4741 switch (mgmt->u.action.u.addba_resp.action_code) {
4742 case WLAN_ACTION_ADDBA_RESP:
4743 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4744 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4745 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4746 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4747 "status %02x\n",
4748 timeout,
4749 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4750 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4751 (cap >> 1) & 0x1,
4752 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4753 break;
4754 case WLAN_ACTION_ADDBA_REQ:
4755 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4756 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4757 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4758 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4759 timeout,
4760 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4761 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4762 (cap >> 1) & 0x1);
4763 break;
4764 default:
4765 dev_info(dev, "action frame %02x\n",
4766 mgmt->u.action.u.addba_resp.action_code);
4767 break;
4768 }
4769}
4770
4771static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4772 struct ieee80211_tx_control *control,
4773 struct sk_buff *skb)
4774{
4775 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4776 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4777 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4778 struct rtl8xxxu_priv *priv = hw->priv;
4779 struct rtl8xxxu_tx_desc *tx_desc;
4780 struct rtl8xxxu_tx_urb *tx_urb;
4781 struct ieee80211_sta *sta = NULL;
4782 struct ieee80211_vif *vif = tx_info->control.vif;
4783 struct device *dev = &priv->udev->dev;
4784 u32 queue, rate;
4785 u16 pktlen = skb->len;
4786 u16 seq_number;
4787 u16 rate_flag = tx_info->control.rates[0].flags;
4788 int ret;
4789
4790 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4791 dev_warn(dev,
4792 "%s: Not enough headroom (%i) for tx descriptor\n",
4793 __func__, skb_headroom(skb));
4794 goto error;
4795 }
4796
4797 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4798 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4799 __func__, skb->len);
4800 goto error;
4801 }
4802
4803 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4804 if (!tx_urb) {
4805 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4806 goto error;
4807 }
4808
4809 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4810 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4811 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4812
4813 if (ieee80211_is_action(hdr->frame_control))
4814 rtl8xxxu_dump_action(dev, hdr);
4815
4816 tx_info->rate_driver_data[0] = hw;
4817
4818 if (control && control->sta)
4819 sta = control->sta;
4820
4821 tx_desc = (struct rtl8xxxu_tx_desc *)
4822 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4823
4824 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4825 tx_desc->pkt_size = cpu_to_le16(pktlen);
4826 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4827
4828 tx_desc->txdw0 =
4829 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4830 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4831 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4832 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4833
4834 queue = rtl8xxxu_queue_select(hw, skb);
4835 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4836
4837 if (tx_info->control.hw_key) {
4838 switch (tx_info->control.hw_key->cipher) {
4839 case WLAN_CIPHER_SUITE_WEP40:
4840 case WLAN_CIPHER_SUITE_WEP104:
4841 case WLAN_CIPHER_SUITE_TKIP:
4842 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4843 break;
4844 case WLAN_CIPHER_SUITE_CCMP:
4845 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4846 break;
4847 default:
4848 break;
4849 }
4850 }
4851
4852 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4853 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4854
4855 if (rate_flag & IEEE80211_TX_RC_MCS)
4856 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4857 else
4858 rate = tx_rate->hw_value;
4859 tx_desc->txdw5 = cpu_to_le32(rate);
4860
4861 if (ieee80211_is_data(hdr->frame_control))
4862 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4863
4864 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4865 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4866 if (sta->ht_cap.ht_supported) {
4867 u32 ampdu, val32;
4868
4869 ampdu = (u32)sta->ht_cap.ampdu_density;
4870 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4871 tx_desc->txdw2 |= cpu_to_le32(val32);
4872 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4873 } else
4874 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4875 } else
4876 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4877
4878 if (ieee80211_is_data_qos(hdr->frame_control))
4879 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4880 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4881 (sta && vif && vif->bss_conf.use_short_preamble))
4882 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4883 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4884 (ieee80211_is_data_qos(hdr->frame_control) &&
4885 sta && sta->ht_cap.cap &
4886 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4887 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4888 }
4889 if (ieee80211_is_mgmt(hdr->frame_control)) {
4890 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4891 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4892 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4893 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4894 }
4895
4896 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4897 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4898 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4899 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4900 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4901 }
4902
4903 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4904
4905 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4906 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4907
4908 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4909 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4910 if (ret) {
4911 usb_unanchor_urb(&tx_urb->urb);
4912 rtl8xxxu_free_tx_urb(priv, tx_urb);
4913 goto error;
4914 }
4915 return;
4916error:
4917 dev_kfree_skb(skb);
4918}
4919
4920static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4921 struct ieee80211_rx_status *rx_status,
4922 struct rtl8xxxu_rx_desc *rx_desc,
4923 struct rtl8723au_phy_stats *phy_stats)
4924{
4925 if (phy_stats->sgi_en)
4926 rx_status->flag |= RX_FLAG_SHORT_GI;
4927
4928 if (rx_desc->rxmcs < DESC_RATE_6M) {
4929 /*
4930 * Handle PHY stats for CCK rates
4931 */
4932 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4933
4934 switch (cck_agc_rpt & 0xc0) {
4935 case 0xc0:
4936 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4937 break;
4938 case 0x80:
4939 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4940 break;
4941 case 0x40:
4942 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4943 break;
4944 case 0x00:
4945 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4946 break;
4947 }
4948 } else {
4949 rx_status->signal =
4950 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4951 }
4952}
4953
4954static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4955{
4956 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4957 unsigned long flags;
4958
4959 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4960
4961 list_for_each_entry_safe(rx_urb, tmp,
4962 &priv->rx_urb_pending_list, list) {
4963 list_del(&rx_urb->list);
4964 priv->rx_urb_pending_count--;
4965 usb_free_urb(&rx_urb->urb);
4966 }
4967
4968 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4969}
4970
4971static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4972 struct rtl8xxxu_rx_urb *rx_urb)
4973{
4974 struct sk_buff *skb;
4975 unsigned long flags;
4976 int pending = 0;
4977
4978 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4979
4980 if (!priv->shutdown) {
4981 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4982 priv->rx_urb_pending_count++;
4983 pending = priv->rx_urb_pending_count;
4984 } else {
4985 skb = (struct sk_buff *)rx_urb->urb.context;
4986 dev_kfree_skb(skb);
4987 usb_free_urb(&rx_urb->urb);
4988 }
4989
4990 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4991
4992 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4993 schedule_work(&priv->rx_urb_wq);
4994}
4995
4996static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4997{
4998 struct rtl8xxxu_priv *priv;
4999 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5000 struct list_head local;
5001 struct sk_buff *skb;
5002 unsigned long flags;
5003 int ret;
5004
5005 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5006 INIT_LIST_HEAD(&local);
5007
5008 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5009
5010 list_splice_init(&priv->rx_urb_pending_list, &local);
5011 priv->rx_urb_pending_count = 0;
5012
5013 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5014
5015 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5016 list_del_init(&rx_urb->list);
5017 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5018 /*
5019 * If out of memory or temporary error, put it back on the
5020 * queue and try again. Otherwise the device is dead/gone
5021 * and we should drop it.
5022 */
5023 switch (ret) {
5024 case 0:
5025 break;
5026 case -ENOMEM:
5027 case -EAGAIN:
5028 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5029 break;
5030 default:
5031 pr_info("failed to requeue urb %i\n", ret);
5032 skb = (struct sk_buff *)rx_urb->urb.context;
5033 dev_kfree_skb(skb);
5034 usb_free_urb(&rx_urb->urb);
5035 }
5036 }
5037}
5038
5039static void rtl8xxxu_rx_complete(struct urb *urb)
5040{
5041 struct rtl8xxxu_rx_urb *rx_urb =
5042 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5043 struct ieee80211_hw *hw = rx_urb->hw;
5044 struct rtl8xxxu_priv *priv = hw->priv;
5045 struct sk_buff *skb = (struct sk_buff *)urb->context;
5046 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5047 struct rtl8723au_phy_stats *phy_stats;
5048 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5049 struct ieee80211_mgmt *mgmt;
5050 struct device *dev = &priv->udev->dev;
5051 __le32 *_rx_desc_le = (__le32 *)skb->data;
5052 u32 *_rx_desc = (u32 *)skb->data;
5053 int cnt, len, drvinfo_sz, desc_shift, i;
5054
5055 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5056 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5057
5058 cnt = rx_desc->frag;
5059 len = rx_desc->pktlen;
5060 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5061 desc_shift = rx_desc->shift;
5062 skb_put(skb, urb->actual_length);
5063
5064 if (urb->status == 0) {
5065 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5066 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5067
5068 skb_pull(skb, drvinfo_sz + desc_shift);
5069
5070 mgmt = (struct ieee80211_mgmt *)skb->data;
5071
5072 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5073
5074 if (rx_desc->phy_stats)
5075 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5076 rx_desc, phy_stats);
5077
5078 rx_status->freq = hw->conf.chandef.chan->center_freq;
5079 rx_status->band = hw->conf.chandef.chan->band;
5080
5081 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5082 rx_status->flag |= RX_FLAG_MACTIME_START;
5083
5084 if (!rx_desc->swdec)
5085 rx_status->flag |= RX_FLAG_DECRYPTED;
5086 if (rx_desc->crc32)
5087 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5088 if (rx_desc->bw)
5089 rx_status->flag |= RX_FLAG_40MHZ;
5090
5091 if (rx_desc->rxht) {
5092 rx_status->flag |= RX_FLAG_HT;
5093 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5094 } else {
5095 rx_status->rate_idx = rx_desc->rxmcs;
5096 }
5097
5098 ieee80211_rx_irqsafe(hw, skb);
5099 skb = NULL;
5100 rx_urb->urb.context = NULL;
5101 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5102 } else {
5103 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5104 goto cleanup;
5105 }
5106 return;
5107
5108cleanup:
5109 usb_free_urb(urb);
5110 dev_kfree_skb(skb);
5111 return;
5112}
5113
5114static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5115 struct rtl8xxxu_rx_urb *rx_urb)
5116{
5117 struct sk_buff *skb;
5118 int skb_size;
5119 int ret;
5120
5121 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5122 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5123 if (!skb)
5124 return -ENOMEM;
5125
5126 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5127 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5128 skb_size, rtl8xxxu_rx_complete, skb);
5129 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5130 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5131 if (ret)
5132 usb_unanchor_urb(&rx_urb->urb);
5133 return ret;
5134}
5135
5136static void rtl8xxxu_int_complete(struct urb *urb)
5137{
5138 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5139 struct device *dev = &priv->udev->dev;
5140 int ret;
5141
5142 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5143 if (urb->status == 0) {
5144 usb_anchor_urb(urb, &priv->int_anchor);
5145 ret = usb_submit_urb(urb, GFP_ATOMIC);
5146 if (ret)
5147 usb_unanchor_urb(urb);
5148 } else {
5149 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5150 }
5151}
5152
5153
5154static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5155{
5156 struct rtl8xxxu_priv *priv = hw->priv;
5157 struct urb *urb;
5158 u32 val32;
5159 int ret;
5160
5161 urb = usb_alloc_urb(0, GFP_KERNEL);
5162 if (!urb)
5163 return -ENOMEM;
5164
5165 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5166 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5167 rtl8xxxu_int_complete, priv, 1);
5168 usb_anchor_urb(urb, &priv->int_anchor);
5169 ret = usb_submit_urb(urb, GFP_KERNEL);
5170 if (ret) {
5171 usb_unanchor_urb(urb);
5172 goto error;
5173 }
5174
5175 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5176 val32 |= USB_HIMR_CPWM;
5177 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5178
5179error:
5180 return ret;
5181}
5182
5183static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5184 struct ieee80211_vif *vif)
5185{
5186 struct rtl8xxxu_priv *priv = hw->priv;
5187 int ret;
5188 u8 val8;
5189
5190 switch (vif->type) {
5191 case NL80211_IFTYPE_STATION:
5192 rtl8723a_stop_tx_beacon(priv);
5193
5194 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5195 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5196 BEACON_DISABLE_TSF_UPDATE;
5197 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5198 ret = 0;
5199 break;
5200 default:
5201 ret = -EOPNOTSUPP;
5202 }
5203
5204 rtl8xxxu_set_linktype(priv, vif->type);
5205
5206 return ret;
5207}
5208
5209static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5210 struct ieee80211_vif *vif)
5211{
5212 struct rtl8xxxu_priv *priv = hw->priv;
5213
5214 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5215}
5216
5217static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5218{
5219 struct rtl8xxxu_priv *priv = hw->priv;
5220 struct device *dev = &priv->udev->dev;
5221 u16 val16;
5222 int ret = 0, channel;
5223 bool ht40;
5224
5225 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5226 dev_info(dev,
5227 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5228 __func__, hw->conf.chandef.chan->hw_value,
5229 changed, hw->conf.chandef.width);
5230
5231 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5232 val16 = ((hw->conf.long_frame_max_tx_count <<
5233 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5234 ((hw->conf.short_frame_max_tx_count <<
5235 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5236 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5237 }
5238
5239 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5240 switch (hw->conf.chandef.width) {
5241 case NL80211_CHAN_WIDTH_20_NOHT:
5242 case NL80211_CHAN_WIDTH_20:
5243 ht40 = false;
5244 break;
5245 case NL80211_CHAN_WIDTH_40:
5246 ht40 = true;
5247 break;
5248 default:
5249 ret = -ENOTSUPP;
5250 goto exit;
5251 }
5252
5253 channel = hw->conf.chandef.chan->hw_value;
5254
5255 rtl8723a_set_tx_power(priv, channel, ht40);
5256
5257 rtl8723au_config_channel(hw);
5258 }
5259
5260exit:
5261 return ret;
5262}
5263
5264static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5265 struct ieee80211_vif *vif, u16 queue,
5266 const struct ieee80211_tx_queue_params *param)
5267{
5268 struct rtl8xxxu_priv *priv = hw->priv;
5269 struct device *dev = &priv->udev->dev;
5270 u32 val32;
5271 u8 aifs, acm_ctrl, acm_bit;
5272
5273 aifs = param->aifs;
5274
5275 val32 = aifs |
5276 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5277 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5278 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5279
5280 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5281 dev_dbg(dev,
5282 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5283 __func__, queue, val32, param->acm, acm_ctrl);
5284
5285 switch (queue) {
5286 case IEEE80211_AC_VO:
5287 acm_bit = ACM_HW_CTRL_VO;
5288 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5289 break;
5290 case IEEE80211_AC_VI:
5291 acm_bit = ACM_HW_CTRL_VI;
5292 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5293 break;
5294 case IEEE80211_AC_BE:
5295 acm_bit = ACM_HW_CTRL_BE;
5296 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5297 break;
5298 case IEEE80211_AC_BK:
5299 acm_bit = ACM_HW_CTRL_BK;
5300 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5301 break;
5302 default:
5303 acm_bit = 0;
5304 break;
5305 }
5306
5307 if (param->acm)
5308 acm_ctrl |= acm_bit;
5309 else
5310 acm_ctrl &= ~acm_bit;
5311 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5312
5313 return 0;
5314}
5315
5316static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5317 unsigned int changed_flags,
5318 unsigned int *total_flags, u64 multicast)
5319{
5320 struct rtl8xxxu_priv *priv = hw->priv;
5321
5322 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5323 __func__, changed_flags, *total_flags);
5324
5325 *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5326}
5327
5328static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5329{
5330 if (rts > 2347)
5331 return -EINVAL;
5332
5333 return 0;
5334}
5335
5336static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5337 struct ieee80211_vif *vif,
5338 struct ieee80211_sta *sta,
5339 struct ieee80211_key_conf *key)
5340{
5341 struct rtl8xxxu_priv *priv = hw->priv;
5342 struct device *dev = &priv->udev->dev;
5343 u8 mac_addr[ETH_ALEN];
5344 u8 val8;
5345 u16 val16;
5346 u32 val32;
5347 int retval = -EOPNOTSUPP;
5348
5349 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5350 __func__, cmd, key->cipher, key->keyidx);
5351
5352 if (vif->type != NL80211_IFTYPE_STATION)
5353 return -EOPNOTSUPP;
5354
5355 if (key->keyidx > 3)
5356 return -EOPNOTSUPP;
5357
5358 switch (key->cipher) {
5359 case WLAN_CIPHER_SUITE_WEP40:
5360 case WLAN_CIPHER_SUITE_WEP104:
5361
5362 break;
5363 case WLAN_CIPHER_SUITE_CCMP:
5364 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5365 break;
5366 case WLAN_CIPHER_SUITE_TKIP:
5367 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5368 default:
5369 return -EOPNOTSUPP;
5370 }
5371
5372 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5373 dev_dbg(dev, "%s: pairwise key\n", __func__);
5374 ether_addr_copy(mac_addr, sta->addr);
5375 } else {
5376 dev_dbg(dev, "%s: group key\n", __func__);
5377 eth_broadcast_addr(mac_addr);
5378 }
5379
5380 val16 = rtl8xxxu_read16(priv, REG_CR);
5381 val16 |= CR_SECURITY_ENABLE;
5382 rtl8xxxu_write16(priv, REG_CR, val16);
5383
5384 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5385 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5386 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5387 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5388
5389 switch (cmd) {
5390 case SET_KEY:
5391 key->hw_key_idx = key->keyidx;
5392 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5393 rtl8xxxu_cam_write(priv, key, mac_addr);
5394 retval = 0;
5395 break;
5396 case DISABLE_KEY:
5397 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5398 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5399 key->keyidx << CAM_CMD_KEY_SHIFT;
5400 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5401 retval = 0;
5402 break;
5403 default:
5404 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5405 }
5406
5407 return retval;
5408}
5409
5410static int
5411rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5412 enum ieee80211_ampdu_mlme_action action,
5413 struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5414 bool amsdu)
5415{
5416 struct rtl8xxxu_priv *priv = hw->priv;
5417 struct device *dev = &priv->udev->dev;
5418 u8 ampdu_factor, ampdu_density;
5419
5420 switch (action) {
5421 case IEEE80211_AMPDU_TX_START:
5422 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5423 ampdu_factor = sta->ht_cap.ampdu_factor;
5424 ampdu_density = sta->ht_cap.ampdu_density;
5425 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5426 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5427 dev_dbg(dev,
5428 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5429 ampdu_factor, ampdu_density);
5430 break;
5431 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5432 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5433 rtl8xxxu_set_ampdu_factor(priv, 0);
5434 rtl8xxxu_set_ampdu_min_space(priv, 0);
5435 break;
5436 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5437 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5438 __func__);
5439 rtl8xxxu_set_ampdu_factor(priv, 0);
5440 rtl8xxxu_set_ampdu_min_space(priv, 0);
5441 break;
5442 case IEEE80211_AMPDU_RX_START:
5443 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5444 break;
5445 case IEEE80211_AMPDU_RX_STOP:
5446 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5447 break;
5448 default:
5449 break;
5450 }
5451 return 0;
5452}
5453
5454static int rtl8xxxu_start(struct ieee80211_hw *hw)
5455{
5456 struct rtl8xxxu_priv *priv = hw->priv;
5457 struct rtl8xxxu_rx_urb *rx_urb;
5458 struct rtl8xxxu_tx_urb *tx_urb;
5459 unsigned long flags;
5460 int ret, i;
5461
5462 ret = 0;
5463
5464 init_usb_anchor(&priv->rx_anchor);
5465 init_usb_anchor(&priv->tx_anchor);
5466 init_usb_anchor(&priv->int_anchor);
5467
5468 rtl8723a_enable_rf(priv);
5469 ret = rtl8xxxu_submit_int_urb(hw);
5470 if (ret)
5471 goto exit;
5472
5473 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5474 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5475 if (!tx_urb) {
5476 if (!i)
5477 ret = -ENOMEM;
5478
5479 goto error_out;
5480 }
5481 usb_init_urb(&tx_urb->urb);
5482 INIT_LIST_HEAD(&tx_urb->list);
5483 tx_urb->hw = hw;
5484 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5485 priv->tx_urb_free_count++;
5486 }
5487
5488 priv->tx_stopped = false;
5489
5490 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5491 priv->shutdown = false;
5492 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5493
5494 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5495 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5496 if (!rx_urb) {
5497 if (!i)
5498 ret = -ENOMEM;
5499
5500 goto error_out;
5501 }
5502 usb_init_urb(&rx_urb->urb);
5503 INIT_LIST_HEAD(&rx_urb->list);
5504 rx_urb->hw = hw;
5505
5506 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5507 }
5508exit:
5509 /*
5510 * Disable all data frames
5511 */
5512 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5513 /*
5514 * Accept all mgmt frames
5515 */
5516 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5517
5518 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5519
5520 return ret;
5521
5522error_out:
5523 rtl8xxxu_free_tx_resources(priv);
5524 /*
5525 * Disable all data and mgmt frames
5526 */
5527 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5528 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5529
5530 return ret;
5531}
5532
5533static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5534{
5535 struct rtl8xxxu_priv *priv = hw->priv;
5536 unsigned long flags;
5537
5538 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5539
5540 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5541 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5542
5543 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5544 priv->shutdown = true;
5545 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5546
5547 usb_kill_anchored_urbs(&priv->rx_anchor);
5548 usb_kill_anchored_urbs(&priv->tx_anchor);
5549 usb_kill_anchored_urbs(&priv->int_anchor);
5550
5551 rtl8723a_disable_rf(priv);
5552
5553 /*
5554 * Disable interrupts
5555 */
5556 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5557
5558 rtl8xxxu_free_rx_resources(priv);
5559 rtl8xxxu_free_tx_resources(priv);
5560}
5561
5562static const struct ieee80211_ops rtl8xxxu_ops = {
5563 .tx = rtl8xxxu_tx,
5564 .add_interface = rtl8xxxu_add_interface,
5565 .remove_interface = rtl8xxxu_remove_interface,
5566 .config = rtl8xxxu_config,
5567 .conf_tx = rtl8xxxu_conf_tx,
5568 .bss_info_changed = rtl8xxxu_bss_info_changed,
5569 .configure_filter = rtl8xxxu_configure_filter,
5570 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5571 .start = rtl8xxxu_start,
5572 .stop = rtl8xxxu_stop,
5573 .sw_scan_start = rtl8xxxu_sw_scan_start,
5574 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5575 .set_key = rtl8xxxu_set_key,
5576 .ampdu_action = rtl8xxxu_ampdu_action,
5577};
5578
5579static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5580 struct usb_interface *interface)
5581{
5582 struct usb_interface_descriptor *interface_desc;
5583 struct usb_host_interface *host_interface;
5584 struct usb_endpoint_descriptor *endpoint;
5585 struct device *dev = &priv->udev->dev;
5586 int i, j = 0, endpoints;
5587 u8 dir, xtype, num;
5588 int ret = 0;
5589
5590 host_interface = &interface->altsetting[0];
5591 interface_desc = &host_interface->desc;
5592 endpoints = interface_desc->bNumEndpoints;
5593
5594 for (i = 0; i < endpoints; i++) {
5595 endpoint = &host_interface->endpoint[i].desc;
5596
5597 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5598 num = usb_endpoint_num(endpoint);
5599 xtype = usb_endpoint_type(endpoint);
5600 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5601 dev_dbg(dev,
5602 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5603 __func__, dir, num, xtype);
5604 if (usb_endpoint_dir_in(endpoint) &&
5605 usb_endpoint_xfer_bulk(endpoint)) {
5606 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5607 dev_dbg(dev, "%s: in endpoint num %i\n",
5608 __func__, num);
5609
5610 if (priv->pipe_in) {
5611 dev_warn(dev,
5612 "%s: Too many IN pipes\n", __func__);
5613 ret = -EINVAL;
5614 goto exit;
5615 }
5616
5617 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5618 }
5619
5620 if (usb_endpoint_dir_in(endpoint) &&
5621 usb_endpoint_xfer_int(endpoint)) {
5622 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5623 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5624 __func__, num);
5625
5626 if (priv->pipe_interrupt) {
5627 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5628 __func__);
5629 ret = -EINVAL;
5630 goto exit;
5631 }
5632
5633 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5634 }
5635
5636 if (usb_endpoint_dir_out(endpoint) &&
5637 usb_endpoint_xfer_bulk(endpoint)) {
5638 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5639 dev_dbg(dev, "%s: out endpoint num %i\n",
5640 __func__, num);
5641 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5642 dev_warn(dev,
5643 "%s: Too many OUT pipes\n", __func__);
5644 ret = -EINVAL;
5645 goto exit;
5646 }
5647 priv->out_ep[j++] = num;
5648 }
5649 }
5650exit:
5651 priv->nr_out_eps = j;
5652 return ret;
5653}
5654
5655static int rtl8xxxu_probe(struct usb_interface *interface,
5656 const struct usb_device_id *id)
5657{
5658 struct rtl8xxxu_priv *priv;
5659 struct ieee80211_hw *hw;
5660 struct usb_device *udev;
5661 struct ieee80211_supported_band *sband;
5662 int ret = 0;
5663 int untested = 1;
5664
5665 udev = usb_get_dev(interface_to_usbdev(interface));
5666
5667 switch (id->idVendor) {
5668 case USB_VENDOR_ID_REALTEK:
5669 switch(id->idProduct) {
5670 case 0x1724:
5671 case 0x8176:
5672 case 0x8178:
5673 case 0x817f:
5674 untested = 0;
5675 break;
5676 }
5677 break;
5678 case 0x7392:
5679 if (id->idProduct == 0x7811)
5680 untested = 0;
5681 break;
5682 default:
5683 break;
5684 }
5685
5686 if (untested) {
5687 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5688 dev_info(&udev->dev,
5689 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5690 id->idVendor, id->idProduct);
5691 dev_info(&udev->dev,
5692 "Please report results to Jes.Sorensen@gmail.com\n");
5693 }
5694
5695 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5696 if (!hw) {
5697 ret = -ENOMEM;
5698 goto exit;
5699 }
5700
5701 priv = hw->priv;
5702 priv->hw = hw;
5703 priv->udev = udev;
5704 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5705 mutex_init(&priv->usb_buf_mutex);
5706 mutex_init(&priv->h2c_mutex);
5707 INIT_LIST_HEAD(&priv->tx_urb_free_list);
5708 spin_lock_init(&priv->tx_urb_lock);
5709 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5710 spin_lock_init(&priv->rx_urb_lock);
5711 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5712
5713 usb_set_intfdata(interface, hw);
5714
5715 ret = rtl8xxxu_parse_usb(priv, interface);
5716 if (ret)
5717 goto exit;
5718
5719 ret = rtl8xxxu_identify_chip(priv);
5720 if (ret) {
5721 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5722 goto exit;
5723 }
5724
5725 ret = rtl8xxxu_read_efuse(priv);
5726 if (ret) {
5727 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5728 goto exit;
5729 }
5730
5731 ret = priv->fops->parse_efuse(priv);
5732 if (ret) {
5733 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5734 goto exit;
5735 }
5736
5737 rtl8xxxu_print_chipinfo(priv);
5738
5739 ret = priv->fops->load_firmware(priv);
5740 if (ret) {
5741 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5742 goto exit;
5743 }
5744
5745 ret = rtl8xxxu_init_device(hw);
5746
5747 hw->wiphy->max_scan_ssids = 1;
5748 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5749 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5750 hw->queues = 4;
5751
5752 sband = &rtl8xxxu_supported_band;
5753 sband->ht_cap.ht_supported = true;
5754 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5755 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5756 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5757 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5758 sband->ht_cap.mcs.rx_mask[0] = 0xff;
5759 sband->ht_cap.mcs.rx_mask[4] = 0x01;
5760 if (priv->rf_paths > 1) {
5761 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5762 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5763 }
5764 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5765 /*
5766 * Some APs will negotiate HT20_40 in a noisy environment leading
5767 * to miserable performance. Rather than defaulting to this, only
5768 * enable it if explicitly requested at module load time.
5769 */
5770 if (rtl8xxxu_ht40_2g) {
5771 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5772 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5773 }
5774 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5775
5776 hw->wiphy->rts_threshold = 2347;
5777
5778 SET_IEEE80211_DEV(priv->hw, &interface->dev);
5779 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5780
5781 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5782 ieee80211_hw_set(hw, SIGNAL_DBM);
5783 /*
5784 * The firmware handles rate control
5785 */
5786 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5787 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5788
5789 ret = ieee80211_register_hw(priv->hw);
5790 if (ret) {
5791 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5792 __func__, ret);
5793 goto exit;
5794 }
5795
5796exit:
5797 if (ret < 0)
5798 usb_put_dev(udev);
5799 return ret;
5800}
5801
5802static void rtl8xxxu_disconnect(struct usb_interface *interface)
5803{
5804 struct rtl8xxxu_priv *priv;
5805 struct ieee80211_hw *hw;
5806
5807 hw = usb_get_intfdata(interface);
5808 priv = hw->priv;
5809
5810 rtl8xxxu_disable_device(hw);
5811 usb_set_intfdata(interface, NULL);
5812
5813 dev_info(&priv->udev->dev, "disconnecting\n");
5814
5815 ieee80211_unregister_hw(hw);
5816
5817 kfree(priv->fw_data);
5818 mutex_destroy(&priv->usb_buf_mutex);
5819 mutex_destroy(&priv->h2c_mutex);
5820
5821 usb_put_dev(priv->udev);
5822 ieee80211_free_hw(hw);
5823}
5824
5825static struct rtl8xxxu_fileops rtl8723au_fops = {
5826 .parse_efuse = rtl8723au_parse_efuse,
5827 .load_firmware = rtl8723au_load_firmware,
5828 .power_on = rtl8723au_power_on,
5829 .writeN_block_size = 1024,
5830};
5831
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5832#ifdef CONFIG_RTL8XXXU_UNTESTED
5833
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5834static struct rtl8xxxu_fileops rtl8192cu_fops = {
5835 .parse_efuse = rtl8192cu_parse_efuse,
5836 .load_firmware = rtl8192cu_load_firmware,
5837 .power_on = rtl8192cu_power_on,
5838 .writeN_block_size = 128,
5839};
5840
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5841#endif
5842
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5843static struct usb_device_id dev_table[] = {
5844{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5845 .driver_info = (unsigned long)&rtl8723au_fops},
5846{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5847 .driver_info = (unsigned long)&rtl8723au_fops},
5848{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5849 .driver_info = (unsigned long)&rtl8723au_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]5850#ifdef CONFIG_RTL8XXXU_UNTESTED
5851/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5852{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5853 .driver_info = (unsigned long)&rtl8192cu_fops},
5854{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5855 .driver_info = (unsigned long)&rtl8192cu_fops},
5856{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5857 .driver_info = (unsigned long)&rtl8192cu_fops},
5858/* Tested by Larry Finger */
5859{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5860 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5861/* Currently untested 8188 series devices */
5862{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5863 .driver_info = (unsigned long)&rtl8192cu_fops},
5864{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5865 .driver_info = (unsigned long)&rtl8192cu_fops},
5866{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5867 .driver_info = (unsigned long)&rtl8192cu_fops},
5868{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5869 .driver_info = (unsigned long)&rtl8192cu_fops},
5870{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5871 .driver_info = (unsigned long)&rtl8192cu_fops},
5872{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5873 .driver_info = (unsigned long)&rtl8192cu_fops},
5874{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5875 .driver_info = (unsigned long)&rtl8192cu_fops},
5876{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5877 .driver_info = (unsigned long)&rtl8192cu_fops},
5878{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5879 .driver_info = (unsigned long)&rtl8192cu_fops},
5880{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5881 .driver_info = (unsigned long)&rtl8192cu_fops},
5882{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5883 .driver_info = (unsigned long)&rtl8192cu_fops},
5884{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5885 .driver_info = (unsigned long)&rtl8192cu_fops},
5886{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5887 .driver_info = (unsigned long)&rtl8192cu_fops},
5888{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5889 .driver_info = (unsigned long)&rtl8192cu_fops},
5890{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5891 .driver_info = (unsigned long)&rtl8192cu_fops},
5892{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5893 .driver_info = (unsigned long)&rtl8192cu_fops},
5894{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5895 .driver_info = (unsigned long)&rtl8192cu_fops},
5896{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5897 .driver_info = (unsigned long)&rtl8192cu_fops},
5898{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5899 .driver_info = (unsigned long)&rtl8192cu_fops},
5900{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5901 .driver_info = (unsigned long)&rtl8192cu_fops},
5902{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5903 .driver_info = (unsigned long)&rtl8192cu_fops},
5904{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5905 .driver_info = (unsigned long)&rtl8192cu_fops},
5906{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5907 .driver_info = (unsigned long)&rtl8192cu_fops},
5908{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5909 .driver_info = (unsigned long)&rtl8192cu_fops},
5910{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5911 .driver_info = (unsigned long)&rtl8192cu_fops},
5912{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5913 .driver_info = (unsigned long)&rtl8192cu_fops},
5914{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5915 .driver_info = (unsigned long)&rtl8192cu_fops},
5916{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5917 .driver_info = (unsigned long)&rtl8192cu_fops},
5918{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5919 .driver_info = (unsigned long)&rtl8192cu_fops},
5920{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5921 .driver_info = (unsigned long)&rtl8192cu_fops},
5922{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5923 .driver_info = (unsigned long)&rtl8192cu_fops},
5924{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5925 .driver_info = (unsigned long)&rtl8192cu_fops},
5926{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5927 .driver_info = (unsigned long)&rtl8192cu_fops},
5928{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5929 .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5930{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5931 .driver_info = (unsigned long)&rtl8192cu_fops},
5932{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5933 .driver_info = (unsigned long)&rtl8192cu_fops},
5934{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5935 .driver_info = (unsigned long)&rtl8192cu_fops},
5936{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5937 .driver_info = (unsigned long)&rtl8192cu_fops},
5938{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5939 .driver_info = (unsigned long)&rtl8192cu_fops},
5940{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5941 .driver_info = (unsigned long)&rtl8192cu_fops},
5942{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5943 .driver_info = (unsigned long)&rtl8192cu_fops},
5944/* Currently untested 8192 series devices */
5945{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5946 .driver_info = (unsigned long)&rtl8192cu_fops},
5947{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5948 .driver_info = (unsigned long)&rtl8192cu_fops},
5949{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5950 .driver_info = (unsigned long)&rtl8192cu_fops},
5951{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5952 .driver_info = (unsigned long)&rtl8192cu_fops},
5953{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5954 .driver_info = (unsigned long)&rtl8192cu_fops},
5955{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5956 .driver_info = (unsigned long)&rtl8192cu_fops},
5957{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5958 .driver_info = (unsigned long)&rtl8192cu_fops},
5959{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5960 .driver_info = (unsigned long)&rtl8192cu_fops},
5961{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5962 .driver_info = (unsigned long)&rtl8192cu_fops},
5963{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5964 .driver_info = (unsigned long)&rtl8192cu_fops},
5965{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5966 .driver_info = (unsigned long)&rtl8192cu_fops},
5967{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5968 .driver_info = (unsigned long)&rtl8192cu_fops},
5969{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5970 .driver_info = (unsigned long)&rtl8192cu_fops},
5971{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5972 .driver_info = (unsigned long)&rtl8192cu_fops},
5973{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5974 .driver_info = (unsigned long)&rtl8192cu_fops},
5975{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5976 .driver_info = (unsigned long)&rtl8192cu_fops},
5977{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5978 .driver_info = (unsigned long)&rtl8192cu_fops},
5979{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5980 .driver_info = (unsigned long)&rtl8192cu_fops},
5981{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5982 .driver_info = (unsigned long)&rtl8192cu_fops},
5983{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5984 .driver_info = (unsigned long)&rtl8192cu_fops},
5985{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5986 .driver_info = (unsigned long)&rtl8192cu_fops},
5987{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5988 .driver_info = (unsigned long)&rtl8192cu_fops},
5989{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5990 .driver_info = (unsigned long)&rtl8192cu_fops},
5991{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5992 .driver_info = (unsigned long)&rtl8192cu_fops},
5993{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
5994 .driver_info = (unsigned long)&rtl8192cu_fops},
5995#endif
5996{ }
5997};
5998
5999static struct usb_driver rtl8xxxu_driver = {
6000 .name = DRIVER_NAME,
6001 .probe = rtl8xxxu_probe,
6002 .disconnect = rtl8xxxu_disconnect,
6003 .id_table = dev_table,
6004 .disable_hub_initiated_lpm = 1,
6005};
6006
6007static int __init rtl8xxxu_module_init(void)
6008{
6009 int res;
6010
6011 res = usb_register(&rtl8xxxu_driver);
6012 if (res < 0)
6013 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6014
6015 return res;
6016}
6017
6018static void __exit rtl8xxxu_module_exit(void)
6019{
6020 usb_deregister(&rtl8xxxu_driver);
6021}
6022
6023
6024MODULE_DEVICE_TABLE(usb, dev_table);
6025
6026module_init(rtl8xxxu_module_init);
6027module_exit(rtl8xxxu_module_exit);