Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
| 25 | #include <subdev/device.h> |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 26 | #include <subdev/bios.h> |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 27 | #include <subdev/gpio.h> |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 28 | #include <subdev/i2c.h> |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 29 | #include <subdev/clock.h> |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 30 | #include <subdev/devinit.h> |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 31 | #include <subdev/mc.h> |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 32 | #include <subdev/timer.h> |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 33 | #include <subdev/fb.h> |
| 34 | #include <subdev/ltcg.h> |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 35 | #include <subdev/instmem.h> |
| 36 | #include <subdev/vm.h> |
| 37 | #include <subdev/bar.h> |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 38 | |
| 39 | int |
| 40 | nvc0_identify(struct nouveau_device *device) |
| 41 | { |
| 42 | switch (device->chipset) { |
| 43 | case 0xc0: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 44 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 45 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 46 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 47 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 48 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 49 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 50 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 51 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 52 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 53 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 54 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 55 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 56 | break; |
| 57 | case 0xc4: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 58 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 59 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 60 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 61 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 62 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 63 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 64 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 65 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 66 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 67 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 68 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 69 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 70 | break; |
| 71 | case 0xc3: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 72 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 73 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 74 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 75 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 76 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 77 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 78 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 79 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 80 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 81 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 82 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 83 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 84 | break; |
| 85 | case 0xce: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 86 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 87 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 88 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 89 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 90 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 91 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 92 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 93 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 94 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 95 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 96 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 97 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 98 | break; |
| 99 | case 0xcf: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 100 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 101 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 102 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 103 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 104 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 105 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 106 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 107 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 108 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 109 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 110 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 111 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 112 | break; |
| 113 | case 0xc1: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 114 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 115 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 116 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 117 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 118 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 119 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 120 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 121 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 122 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 123 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 124 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 125 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 126 | break; |
| 127 | case 0xc8: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 128 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 129 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 130 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 131 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 132 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 133 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 134 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 135 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 136 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 137 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 138 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 139 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 140 | break; |
| 141 | case 0xd9: |
Ben Skeggs | 70c0f26 | 2012-07-10 10:49:22 +1000 | [diff] [blame] | 142 | device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; |
Ben Skeggs | e0996ae | 2012-07-10 12:20:17 +1000 | [diff] [blame] | 143 | device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass; |
Ben Skeggs | 4196faa | 2012-07-10 14:36:38 +1000 | [diff] [blame] | 144 | device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass; |
Ben Skeggs | 8aceb7d | 2012-07-10 16:45:24 +1000 | [diff] [blame] | 145 | device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 146 | device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass; |
Ben Skeggs | 7d9115d | 2012-07-11 15:58:56 +1000 | [diff] [blame] | 147 | device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass; |
Ben Skeggs | 5a5c743 | 2012-07-11 16:08:25 +1000 | [diff] [blame] | 148 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
Ben Skeggs | 861d210 | 2012-07-11 19:05:01 +1000 | [diff] [blame] | 149 | device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass; |
| 150 | device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass; |
Ben Skeggs | 3863c9b | 2012-07-14 19:09:17 +1000 | [diff] [blame^] | 151 | device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass; |
| 152 | device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; |
| 153 | device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; |
Ben Skeggs | 9274f4a | 2012-07-06 07:36:43 +1000 | [diff] [blame] | 154 | break; |
| 155 | default: |
| 156 | nv_fatal(device, "unknown Fermi chipset\n"); |
| 157 | return -EINVAL; |
| 158 | } |
| 159 | |
| 160 | return 0; |
| 161 | } |