Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips |
| 3 | * |
| 4 | * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is automatically generated from the AM33XX hardware databases. |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation version 2. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Tony Lindgren | 3a8761c | 2012-10-08 09:11:22 -0700 | [diff] [blame] | 17 | #include <linux/i2c-omap.h> |
| 18 | |
Tony Lindgren | 2a296c8 | 2012-10-02 17:41:35 -0700 | [diff] [blame] | 19 | #include "omap_hwmod.h" |
Tony Lindgren | 11964f5 | 2012-09-12 21:29:07 -0700 | [diff] [blame] | 20 | #include <linux/platform_data/gpio-omap.h> |
Kevin Hilman | aa817b2 | 2012-09-20 09:38:14 -0700 | [diff] [blame] | 21 | #include <linux/platform_data/spi-omap2-mcspi.h> |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 22 | |
| 23 | #include "omap_hwmod_common_data.h" |
| 24 | |
| 25 | #include "control.h" |
| 26 | #include "cm33xx.h" |
| 27 | #include "prm33xx.h" |
| 28 | #include "prm-regbits-33xx.h" |
Tony Lindgren | 3a8761c | 2012-10-08 09:11:22 -0700 | [diff] [blame] | 29 | #include "i2c.h" |
Tony Lindgren | 68f39e7 | 2012-10-15 12:09:43 -0700 | [diff] [blame] | 30 | #include "mmc.h" |
Vaibhav Hiremath | 05cf03b | 2013-03-31 20:22:21 -0600 | [diff] [blame] | 31 | #include "wd_timer.h" |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 32 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 33 | /* |
| 34 | * IP blocks |
| 35 | */ |
| 36 | |
| 37 | /* |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 38 | * 'emif' class |
| 39 | * instance(s): emif |
| 40 | */ |
| 41 | static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = { |
| 42 | .rev_offs = 0x0000, |
| 43 | }; |
| 44 | |
| 45 | static struct omap_hwmod_class am33xx_emif_hwmod_class = { |
| 46 | .name = "emif", |
| 47 | .sysc = &am33xx_emif_sysc, |
| 48 | }; |
| 49 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 50 | /* emif */ |
| 51 | static struct omap_hwmod am33xx_emif_hwmod = { |
| 52 | .name = "emif", |
| 53 | .class = &am33xx_emif_hwmod_class, |
| 54 | .clkdm_name = "l3_clkdm", |
| 55 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 56 | .main_clk = "dpll_ddr_m2_div2_ck", |
| 57 | .prcm = { |
| 58 | .omap4 = { |
| 59 | .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET, |
| 60 | .modulemode = MODULEMODE_SWCTRL, |
| 61 | }, |
| 62 | }, |
| 63 | }; |
| 64 | |
| 65 | /* |
| 66 | * 'l3' class |
| 67 | * instance(s): l3_main, l3_s, l3_instr |
| 68 | */ |
| 69 | static struct omap_hwmod_class am33xx_l3_hwmod_class = { |
| 70 | .name = "l3", |
| 71 | }; |
| 72 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 73 | static struct omap_hwmod am33xx_l3_main_hwmod = { |
| 74 | .name = "l3_main", |
| 75 | .class = &am33xx_l3_hwmod_class, |
| 76 | .clkdm_name = "l3_clkdm", |
| 77 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 78 | .main_clk = "l3_gclk", |
| 79 | .prcm = { |
| 80 | .omap4 = { |
| 81 | .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET, |
| 82 | .modulemode = MODULEMODE_SWCTRL, |
| 83 | }, |
| 84 | }, |
| 85 | }; |
| 86 | |
| 87 | /* l3_s */ |
| 88 | static struct omap_hwmod am33xx_l3_s_hwmod = { |
| 89 | .name = "l3_s", |
| 90 | .class = &am33xx_l3_hwmod_class, |
| 91 | .clkdm_name = "l3s_clkdm", |
| 92 | }; |
| 93 | |
| 94 | /* l3_instr */ |
| 95 | static struct omap_hwmod am33xx_l3_instr_hwmod = { |
| 96 | .name = "l3_instr", |
| 97 | .class = &am33xx_l3_hwmod_class, |
| 98 | .clkdm_name = "l3_clkdm", |
| 99 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 100 | .main_clk = "l3_gclk", |
| 101 | .prcm = { |
| 102 | .omap4 = { |
| 103 | .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET, |
| 104 | .modulemode = MODULEMODE_SWCTRL, |
| 105 | }, |
| 106 | }, |
| 107 | }; |
| 108 | |
| 109 | /* |
| 110 | * 'l4' class |
| 111 | * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw |
| 112 | */ |
| 113 | static struct omap_hwmod_class am33xx_l4_hwmod_class = { |
| 114 | .name = "l4", |
| 115 | }; |
| 116 | |
| 117 | /* l4_ls */ |
| 118 | static struct omap_hwmod am33xx_l4_ls_hwmod = { |
| 119 | .name = "l4_ls", |
| 120 | .class = &am33xx_l4_hwmod_class, |
| 121 | .clkdm_name = "l4ls_clkdm", |
| 122 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 123 | .main_clk = "l4ls_gclk", |
| 124 | .prcm = { |
| 125 | .omap4 = { |
| 126 | .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET, |
| 127 | .modulemode = MODULEMODE_SWCTRL, |
| 128 | }, |
| 129 | }, |
| 130 | }; |
| 131 | |
| 132 | /* l4_hs */ |
| 133 | static struct omap_hwmod am33xx_l4_hs_hwmod = { |
| 134 | .name = "l4_hs", |
| 135 | .class = &am33xx_l4_hwmod_class, |
| 136 | .clkdm_name = "l4hs_clkdm", |
| 137 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 138 | .main_clk = "l4hs_gclk", |
| 139 | .prcm = { |
| 140 | .omap4 = { |
| 141 | .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET, |
| 142 | .modulemode = MODULEMODE_SWCTRL, |
| 143 | }, |
| 144 | }, |
| 145 | }; |
| 146 | |
| 147 | |
| 148 | /* l4_wkup */ |
| 149 | static struct omap_hwmod am33xx_l4_wkup_hwmod = { |
| 150 | .name = "l4_wkup", |
| 151 | .class = &am33xx_l4_hwmod_class, |
| 152 | .clkdm_name = "l4_wkup_clkdm", |
| 153 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 154 | .prcm = { |
| 155 | .omap4 = { |
| 156 | .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, |
| 157 | .modulemode = MODULEMODE_SWCTRL, |
| 158 | }, |
| 159 | }, |
| 160 | }; |
| 161 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 162 | /* |
| 163 | * 'mpu' class |
| 164 | */ |
| 165 | static struct omap_hwmod_class am33xx_mpu_hwmod_class = { |
| 166 | .name = "mpu", |
| 167 | }; |
| 168 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 169 | static struct omap_hwmod am33xx_mpu_hwmod = { |
| 170 | .name = "mpu", |
| 171 | .class = &am33xx_mpu_hwmod_class, |
| 172 | .clkdm_name = "mpu_clkdm", |
| 173 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 174 | .main_clk = "dpll_mpu_m2_ck", |
| 175 | .prcm = { |
| 176 | .omap4 = { |
| 177 | .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET, |
| 178 | .modulemode = MODULEMODE_SWCTRL, |
| 179 | }, |
| 180 | }, |
| 181 | }; |
| 182 | |
| 183 | /* |
| 184 | * 'wakeup m3' class |
| 185 | * Wakeup controller sub-system under wakeup domain |
| 186 | */ |
| 187 | static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { |
| 188 | .name = "wkup_m3", |
| 189 | }; |
| 190 | |
| 191 | static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = { |
| 192 | { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, |
| 193 | }; |
| 194 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 195 | /* wkup_m3 */ |
| 196 | static struct omap_hwmod am33xx_wkup_m3_hwmod = { |
| 197 | .name = "wkup_m3", |
| 198 | .class = &am33xx_wkup_m3_hwmod_class, |
| 199 | .clkdm_name = "l4_wkup_aon_clkdm", |
Hebbar Gururaja | 092bda6 | 2013-02-08 08:21:10 -0700 | [diff] [blame] | 200 | /* Keep hardreset asserted */ |
| 201 | .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 202 | .main_clk = "dpll_core_m4_div2_ck", |
| 203 | .prcm = { |
| 204 | .omap4 = { |
| 205 | .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, |
| 206 | .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, |
Vaibhav Bedia | 3077fe6 | 2013-01-29 16:45:05 +0530 | [diff] [blame] | 207 | .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 208 | .modulemode = MODULEMODE_SWCTRL, |
| 209 | }, |
| 210 | }, |
| 211 | .rst_lines = am33xx_wkup_m3_resets, |
| 212 | .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets), |
| 213 | }; |
| 214 | |
| 215 | /* |
| 216 | * 'pru-icss' class |
| 217 | * Programmable Real-Time Unit and Industrial Communication Subsystem |
| 218 | */ |
| 219 | static struct omap_hwmod_class am33xx_pruss_hwmod_class = { |
| 220 | .name = "pruss", |
| 221 | }; |
| 222 | |
| 223 | static struct omap_hwmod_rst_info am33xx_pruss_resets[] = { |
| 224 | { .name = "pruss", .rst_shift = 1 }, |
| 225 | }; |
| 226 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 227 | /* pru-icss */ |
| 228 | /* Pseudo hwmod for reset control purpose only */ |
| 229 | static struct omap_hwmod am33xx_pruss_hwmod = { |
| 230 | .name = "pruss", |
| 231 | .class = &am33xx_pruss_hwmod_class, |
| 232 | .clkdm_name = "pruss_ocp_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 233 | .main_clk = "pruss_ocp_gclk", |
| 234 | .prcm = { |
| 235 | .omap4 = { |
| 236 | .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET, |
| 237 | .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET, |
| 238 | .modulemode = MODULEMODE_SWCTRL, |
| 239 | }, |
| 240 | }, |
| 241 | .rst_lines = am33xx_pruss_resets, |
| 242 | .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets), |
| 243 | }; |
| 244 | |
| 245 | /* gfx */ |
| 246 | /* Pseudo hwmod for reset control purpose only */ |
| 247 | static struct omap_hwmod_class am33xx_gfx_hwmod_class = { |
| 248 | .name = "gfx", |
| 249 | }; |
| 250 | |
| 251 | static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { |
Vaibhav Hiremath | 27c7004 | 2013-05-05 00:18:04 +0530 | [diff] [blame] | 252 | { .name = "gfx", .rst_shift = 0, .st_shift = 0}, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 253 | }; |
| 254 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 255 | static struct omap_hwmod am33xx_gfx_hwmod = { |
| 256 | .name = "gfx", |
| 257 | .class = &am33xx_gfx_hwmod_class, |
| 258 | .clkdm_name = "gfx_l3_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 259 | .main_clk = "gfx_fck_div_ck", |
| 260 | .prcm = { |
| 261 | .omap4 = { |
| 262 | .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET, |
| 263 | .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET, |
Vaibhav Hiremath | 27c7004 | 2013-05-05 00:18:04 +0530 | [diff] [blame] | 264 | .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 265 | .modulemode = MODULEMODE_SWCTRL, |
| 266 | }, |
| 267 | }, |
| 268 | .rst_lines = am33xx_gfx_resets, |
| 269 | .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), |
| 270 | }; |
| 271 | |
| 272 | /* |
| 273 | * 'prcm' class |
| 274 | * power and reset manager (whole prcm infrastructure) |
| 275 | */ |
| 276 | static struct omap_hwmod_class am33xx_prcm_hwmod_class = { |
| 277 | .name = "prcm", |
| 278 | }; |
| 279 | |
| 280 | /* prcm */ |
| 281 | static struct omap_hwmod am33xx_prcm_hwmod = { |
| 282 | .name = "prcm", |
| 283 | .class = &am33xx_prcm_hwmod_class, |
| 284 | .clkdm_name = "l4_wkup_clkdm", |
| 285 | }; |
| 286 | |
| 287 | /* |
| 288 | * 'adc/tsc' class |
| 289 | * TouchScreen Controller (Anolog-To-Digital Converter) |
| 290 | */ |
| 291 | static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { |
| 292 | .rev_offs = 0x00, |
| 293 | .sysc_offs = 0x10, |
| 294 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
| 295 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 296 | SIDLE_SMART_WKUP), |
| 297 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 298 | }; |
| 299 | |
| 300 | static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { |
| 301 | .name = "adc_tsc", |
| 302 | .sysc = &am33xx_adc_tsc_sysc, |
| 303 | }; |
| 304 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 305 | static struct omap_hwmod am33xx_adc_tsc_hwmod = { |
| 306 | .name = "adc_tsc", |
| 307 | .class = &am33xx_adc_tsc_hwmod_class, |
| 308 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 309 | .main_clk = "adc_tsc_fck", |
| 310 | .prcm = { |
| 311 | .omap4 = { |
| 312 | .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET, |
| 313 | .modulemode = MODULEMODE_SWCTRL, |
| 314 | }, |
| 315 | }, |
| 316 | }; |
| 317 | |
| 318 | /* |
| 319 | * Modules omap_hwmod structures |
| 320 | * |
| 321 | * The following IPs are excluded for the moment because: |
| 322 | * - They do not need an explicit SW control using omap_hwmod API. |
| 323 | * - They still need to be validated with the driver |
| 324 | * properly adapted to omap_hwmod / omap_device |
| 325 | * |
| 326 | * - cEFUSE (doesn't fall under any ocp_if) |
| 327 | * - clkdiv32k |
| 328 | * - debugss |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 329 | * - ocp watch point |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 330 | */ |
| 331 | #if 0 |
| 332 | /* |
| 333 | * 'cefuse' class |
| 334 | */ |
| 335 | static struct omap_hwmod_class am33xx_cefuse_hwmod_class = { |
| 336 | .name = "cefuse", |
| 337 | }; |
| 338 | |
| 339 | static struct omap_hwmod am33xx_cefuse_hwmod = { |
| 340 | .name = "cefuse", |
| 341 | .class = &am33xx_cefuse_hwmod_class, |
| 342 | .clkdm_name = "l4_cefuse_clkdm", |
| 343 | .main_clk = "cefuse_fck", |
| 344 | .prcm = { |
| 345 | .omap4 = { |
| 346 | .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET, |
| 347 | .modulemode = MODULEMODE_SWCTRL, |
| 348 | }, |
| 349 | }, |
| 350 | }; |
| 351 | |
| 352 | /* |
| 353 | * 'clkdiv32k' class |
| 354 | */ |
| 355 | static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = { |
| 356 | .name = "clkdiv32k", |
| 357 | }; |
| 358 | |
| 359 | static struct omap_hwmod am33xx_clkdiv32k_hwmod = { |
| 360 | .name = "clkdiv32k", |
| 361 | .class = &am33xx_clkdiv32k_hwmod_class, |
| 362 | .clkdm_name = "clk_24mhz_clkdm", |
| 363 | .main_clk = "clkdiv32k_ick", |
| 364 | .prcm = { |
| 365 | .omap4 = { |
| 366 | .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET, |
| 367 | .modulemode = MODULEMODE_SWCTRL, |
| 368 | }, |
| 369 | }, |
| 370 | }; |
| 371 | |
| 372 | /* |
| 373 | * 'debugss' class |
| 374 | * debug sub system |
| 375 | */ |
| 376 | static struct omap_hwmod_class am33xx_debugss_hwmod_class = { |
| 377 | .name = "debugss", |
| 378 | }; |
| 379 | |
| 380 | static struct omap_hwmod am33xx_debugss_hwmod = { |
| 381 | .name = "debugss", |
| 382 | .class = &am33xx_debugss_hwmod_class, |
| 383 | .clkdm_name = "l3_aon_clkdm", |
| 384 | .main_clk = "debugss_ick", |
| 385 | .prcm = { |
| 386 | .omap4 = { |
| 387 | .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, |
| 388 | .modulemode = MODULEMODE_SWCTRL, |
| 389 | }, |
| 390 | }, |
| 391 | }; |
| 392 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 393 | /* ocpwp */ |
| 394 | static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { |
| 395 | .name = "ocpwp", |
| 396 | }; |
| 397 | |
| 398 | static struct omap_hwmod am33xx_ocpwp_hwmod = { |
| 399 | .name = "ocpwp", |
| 400 | .class = &am33xx_ocpwp_hwmod_class, |
| 401 | .clkdm_name = "l4ls_clkdm", |
| 402 | .main_clk = "l4ls_gclk", |
| 403 | .prcm = { |
| 404 | .omap4 = { |
| 405 | .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET, |
| 406 | .modulemode = MODULEMODE_SWCTRL, |
| 407 | }, |
| 408 | }, |
| 409 | }; |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 410 | #endif |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 411 | |
| 412 | /* |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 413 | * 'aes0' class |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 414 | */ |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 415 | static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = { |
| 416 | .rev_offs = 0x80, |
| 417 | .sysc_offs = 0x84, |
| 418 | .syss_offs = 0x88, |
| 419 | .sysc_flags = SYSS_HAS_RESET_STATUS, |
| 420 | }; |
| 421 | |
| 422 | static struct omap_hwmod_class am33xx_aes0_hwmod_class = { |
| 423 | .name = "aes0", |
| 424 | .sysc = &am33xx_aes0_sysc, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 425 | }; |
| 426 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 427 | static struct omap_hwmod am33xx_aes0_hwmod = { |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 428 | .name = "aes", |
| 429 | .class = &am33xx_aes0_hwmod_class, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 430 | .clkdm_name = "l3_clkdm", |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 431 | .main_clk = "aes0_fck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 432 | .prcm = { |
| 433 | .omap4 = { |
| 434 | .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET, |
| 435 | .modulemode = MODULEMODE_SWCTRL, |
| 436 | }, |
| 437 | }, |
| 438 | }; |
| 439 | |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 440 | /* sha0 HIB2 (the 'P' (public) device) */ |
| 441 | static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = { |
| 442 | .rev_offs = 0x100, |
| 443 | .sysc_offs = 0x110, |
| 444 | .syss_offs = 0x114, |
| 445 | .sysc_flags = SYSS_HAS_RESET_STATUS, |
| 446 | }; |
| 447 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 448 | static struct omap_hwmod_class am33xx_sha0_hwmod_class = { |
| 449 | .name = "sha0", |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 450 | .sysc = &am33xx_sha0_sysc, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 451 | }; |
| 452 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 453 | static struct omap_hwmod am33xx_sha0_hwmod = { |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 454 | .name = "sham", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 455 | .class = &am33xx_sha0_hwmod_class, |
| 456 | .clkdm_name = "l3_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 457 | .main_clk = "l3_gclk", |
| 458 | .prcm = { |
| 459 | .omap4 = { |
| 460 | .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET, |
| 461 | .modulemode = MODULEMODE_SWCTRL, |
| 462 | }, |
| 463 | }, |
| 464 | }; |
| 465 | |
Vaibhav Bedia | ca903b6 | 2013-01-29 16:45:02 +0530 | [diff] [blame] | 466 | /* ocmcram */ |
| 467 | static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = { |
| 468 | .name = "ocmcram", |
| 469 | }; |
| 470 | |
| 471 | static struct omap_hwmod am33xx_ocmcram_hwmod = { |
| 472 | .name = "ocmcram", |
| 473 | .class = &am33xx_ocmcram_hwmod_class, |
| 474 | .clkdm_name = "l3_clkdm", |
| 475 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
| 476 | .main_clk = "l3_gclk", |
| 477 | .prcm = { |
| 478 | .omap4 = { |
| 479 | .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET, |
| 480 | .modulemode = MODULEMODE_SWCTRL, |
| 481 | }, |
| 482 | }, |
| 483 | }; |
| 484 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 485 | /* 'smartreflex' class */ |
| 486 | static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { |
| 487 | .name = "smartreflex", |
| 488 | }; |
| 489 | |
| 490 | /* smartreflex0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 491 | static struct omap_hwmod am33xx_smartreflex0_hwmod = { |
| 492 | .name = "smartreflex0", |
| 493 | .class = &am33xx_smartreflex_hwmod_class, |
| 494 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 495 | .main_clk = "smartreflex0_fck", |
| 496 | .prcm = { |
| 497 | .omap4 = { |
| 498 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET, |
| 499 | .modulemode = MODULEMODE_SWCTRL, |
| 500 | }, |
| 501 | }, |
| 502 | }; |
| 503 | |
| 504 | /* smartreflex1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 505 | static struct omap_hwmod am33xx_smartreflex1_hwmod = { |
| 506 | .name = "smartreflex1", |
| 507 | .class = &am33xx_smartreflex_hwmod_class, |
| 508 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 509 | .main_clk = "smartreflex1_fck", |
| 510 | .prcm = { |
| 511 | .omap4 = { |
| 512 | .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET, |
| 513 | .modulemode = MODULEMODE_SWCTRL, |
| 514 | }, |
| 515 | }, |
| 516 | }; |
| 517 | |
| 518 | /* |
| 519 | * 'control' module class |
| 520 | */ |
| 521 | static struct omap_hwmod_class am33xx_control_hwmod_class = { |
| 522 | .name = "control", |
| 523 | }; |
| 524 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 525 | static struct omap_hwmod am33xx_control_hwmod = { |
| 526 | .name = "control", |
| 527 | .class = &am33xx_control_hwmod_class, |
| 528 | .clkdm_name = "l4_wkup_clkdm", |
| 529 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 530 | .main_clk = "dpll_core_m4_div2_ck", |
| 531 | .prcm = { |
| 532 | .omap4 = { |
| 533 | .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET, |
| 534 | .modulemode = MODULEMODE_SWCTRL, |
| 535 | }, |
| 536 | }, |
| 537 | }; |
| 538 | |
| 539 | /* |
| 540 | * 'cpgmac' class |
| 541 | * cpsw/cpgmac sub system |
| 542 | */ |
| 543 | static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = { |
| 544 | .rev_offs = 0x0, |
| 545 | .sysc_offs = 0x8, |
| 546 | .syss_offs = 0x4, |
| 547 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 548 | SYSS_HAS_RESET_STATUS), |
| 549 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE | |
| 550 | MSTANDBY_NO), |
| 551 | .sysc_fields = &omap_hwmod_sysc_type3, |
| 552 | }; |
| 553 | |
| 554 | static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = { |
| 555 | .name = "cpgmac0", |
| 556 | .sysc = &am33xx_cpgmac_sysc, |
| 557 | }; |
| 558 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 559 | static struct omap_hwmod am33xx_cpgmac0_hwmod = { |
| 560 | .name = "cpgmac0", |
| 561 | .class = &am33xx_cpgmac0_hwmod_class, |
| 562 | .clkdm_name = "cpsw_125mhz_clkdm", |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 563 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 564 | .main_clk = "cpsw_125mhz_gclk", |
Afzal Mohammed | 50c2a3a | 2013-07-05 20:43:17 +0530 | [diff] [blame] | 565 | .mpu_rt_idx = 1, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 566 | .prcm = { |
| 567 | .omap4 = { |
| 568 | .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET, |
| 569 | .modulemode = MODULEMODE_SWCTRL, |
| 570 | }, |
| 571 | }, |
| 572 | }; |
| 573 | |
| 574 | /* |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 575 | * mdio class |
| 576 | */ |
| 577 | static struct omap_hwmod_class am33xx_mdio_hwmod_class = { |
| 578 | .name = "davinci_mdio", |
| 579 | }; |
| 580 | |
| 581 | static struct omap_hwmod am33xx_mdio_hwmod = { |
| 582 | .name = "davinci_mdio", |
| 583 | .class = &am33xx_mdio_hwmod_class, |
| 584 | .clkdm_name = "cpsw_125mhz_clkdm", |
| 585 | .main_clk = "cpsw_125mhz_gclk", |
| 586 | }; |
| 587 | |
| 588 | /* |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 589 | * dcan class |
| 590 | */ |
| 591 | static struct omap_hwmod_class am33xx_dcan_hwmod_class = { |
| 592 | .name = "d_can", |
| 593 | }; |
| 594 | |
| 595 | /* dcan0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 596 | static struct omap_hwmod am33xx_dcan0_hwmod = { |
| 597 | .name = "d_can0", |
| 598 | .class = &am33xx_dcan_hwmod_class, |
| 599 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 600 | .main_clk = "dcan0_fck", |
| 601 | .prcm = { |
| 602 | .omap4 = { |
| 603 | .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET, |
| 604 | .modulemode = MODULEMODE_SWCTRL, |
| 605 | }, |
| 606 | }, |
| 607 | }; |
| 608 | |
| 609 | /* dcan1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 610 | static struct omap_hwmod am33xx_dcan1_hwmod = { |
| 611 | .name = "d_can1", |
| 612 | .class = &am33xx_dcan_hwmod_class, |
| 613 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 614 | .main_clk = "dcan1_fck", |
| 615 | .prcm = { |
| 616 | .omap4 = { |
| 617 | .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET, |
| 618 | .modulemode = MODULEMODE_SWCTRL, |
| 619 | }, |
| 620 | }, |
| 621 | }; |
| 622 | |
| 623 | /* elm */ |
| 624 | static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = { |
| 625 | .rev_offs = 0x0000, |
| 626 | .sysc_offs = 0x0010, |
| 627 | .syss_offs = 0x0014, |
| 628 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 629 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 630 | SYSS_HAS_RESET_STATUS), |
| 631 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 632 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 633 | }; |
| 634 | |
| 635 | static struct omap_hwmod_class am33xx_elm_hwmod_class = { |
| 636 | .name = "elm", |
| 637 | .sysc = &am33xx_elm_sysc, |
| 638 | }; |
| 639 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 640 | static struct omap_hwmod am33xx_elm_hwmod = { |
| 641 | .name = "elm", |
| 642 | .class = &am33xx_elm_hwmod_class, |
| 643 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 644 | .main_clk = "l4ls_gclk", |
| 645 | .prcm = { |
| 646 | .omap4 = { |
| 647 | .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET, |
| 648 | .modulemode = MODULEMODE_SWCTRL, |
| 649 | }, |
| 650 | }, |
| 651 | }; |
| 652 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 653 | /* pwmss */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 654 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { |
| 655 | .rev_offs = 0x0, |
| 656 | .sysc_offs = 0x4, |
| 657 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), |
| 658 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 659 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
| 660 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
| 661 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 662 | }; |
| 663 | |
| 664 | static struct omap_hwmod_class am33xx_epwmss_hwmod_class = { |
| 665 | .name = "epwmss", |
| 666 | .sysc = &am33xx_epwmss_sysc, |
| 667 | }; |
| 668 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 669 | static struct omap_hwmod_class am33xx_ecap_hwmod_class = { |
| 670 | .name = "ecap", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 671 | }; |
| 672 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 673 | static struct omap_hwmod_class am33xx_eqep_hwmod_class = { |
| 674 | .name = "eqep", |
| 675 | }; |
| 676 | |
| 677 | static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = { |
| 678 | .name = "ehrpwm", |
| 679 | }; |
| 680 | |
| 681 | /* epwmss0 */ |
| 682 | static struct omap_hwmod am33xx_epwmss0_hwmod = { |
| 683 | .name = "epwmss0", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 684 | .class = &am33xx_epwmss_hwmod_class, |
| 685 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 686 | .main_clk = "l4ls_gclk", |
| 687 | .prcm = { |
| 688 | .omap4 = { |
| 689 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, |
| 690 | .modulemode = MODULEMODE_SWCTRL, |
| 691 | }, |
| 692 | }, |
| 693 | }; |
| 694 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 695 | /* ecap0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 696 | static struct omap_hwmod am33xx_ecap0_hwmod = { |
| 697 | .name = "ecap0", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 698 | .class = &am33xx_ecap_hwmod_class, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 699 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 700 | .main_clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 701 | }; |
| 702 | |
| 703 | /* eqep0 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 704 | static struct omap_hwmod am33xx_eqep0_hwmod = { |
| 705 | .name = "eqep0", |
| 706 | .class = &am33xx_eqep_hwmod_class, |
| 707 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 708 | .main_clk = "l4ls_gclk", |
| 709 | }; |
| 710 | |
| 711 | /* ehrpwm0 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 712 | static struct omap_hwmod am33xx_ehrpwm0_hwmod = { |
| 713 | .name = "ehrpwm0", |
| 714 | .class = &am33xx_ehrpwm_hwmod_class, |
| 715 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 716 | .main_clk = "l4ls_gclk", |
| 717 | }; |
| 718 | |
| 719 | /* epwmss1 */ |
| 720 | static struct omap_hwmod am33xx_epwmss1_hwmod = { |
| 721 | .name = "epwmss1", |
| 722 | .class = &am33xx_epwmss_hwmod_class, |
| 723 | .clkdm_name = "l4ls_clkdm", |
| 724 | .main_clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 725 | .prcm = { |
| 726 | .omap4 = { |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 727 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 728 | .modulemode = MODULEMODE_SWCTRL, |
| 729 | }, |
| 730 | }, |
| 731 | }; |
| 732 | |
| 733 | /* ecap1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 734 | static struct omap_hwmod am33xx_ecap1_hwmod = { |
| 735 | .name = "ecap1", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 736 | .class = &am33xx_ecap_hwmod_class, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 737 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 738 | .main_clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 739 | }; |
| 740 | |
| 741 | /* eqep1 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 742 | static struct omap_hwmod am33xx_eqep1_hwmod = { |
| 743 | .name = "eqep1", |
| 744 | .class = &am33xx_eqep_hwmod_class, |
| 745 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 746 | .main_clk = "l4ls_gclk", |
| 747 | }; |
| 748 | |
| 749 | /* ehrpwm1 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 750 | static struct omap_hwmod am33xx_ehrpwm1_hwmod = { |
| 751 | .name = "ehrpwm1", |
| 752 | .class = &am33xx_ehrpwm_hwmod_class, |
| 753 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 754 | .main_clk = "l4ls_gclk", |
| 755 | }; |
| 756 | |
| 757 | /* epwmss2 */ |
| 758 | static struct omap_hwmod am33xx_epwmss2_hwmod = { |
| 759 | .name = "epwmss2", |
| 760 | .class = &am33xx_epwmss_hwmod_class, |
| 761 | .clkdm_name = "l4ls_clkdm", |
| 762 | .main_clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 763 | .prcm = { |
| 764 | .omap4 = { |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 765 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 766 | .modulemode = MODULEMODE_SWCTRL, |
| 767 | }, |
| 768 | }, |
| 769 | }; |
| 770 | |
| 771 | /* ecap2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 772 | static struct omap_hwmod am33xx_ecap2_hwmod = { |
| 773 | .name = "ecap2", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 774 | .class = &am33xx_ecap_hwmod_class, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 775 | .clkdm_name = "l4ls_clkdm", |
| 776 | .main_clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 777 | }; |
| 778 | |
| 779 | /* eqep2 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 780 | static struct omap_hwmod am33xx_eqep2_hwmod = { |
| 781 | .name = "eqep2", |
| 782 | .class = &am33xx_eqep_hwmod_class, |
| 783 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 784 | .main_clk = "l4ls_gclk", |
| 785 | }; |
| 786 | |
| 787 | /* ehrpwm2 */ |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 788 | static struct omap_hwmod am33xx_ehrpwm2_hwmod = { |
| 789 | .name = "ehrpwm2", |
| 790 | .class = &am33xx_ehrpwm_hwmod_class, |
| 791 | .clkdm_name = "l4ls_clkdm", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 792 | .main_clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 793 | }; |
| 794 | |
| 795 | /* |
| 796 | * 'gpio' class: for gpio 0,1,2,3 |
| 797 | */ |
| 798 | static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = { |
| 799 | .rev_offs = 0x0000, |
| 800 | .sysc_offs = 0x0010, |
| 801 | .syss_offs = 0x0114, |
| 802 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
| 803 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 804 | SYSS_HAS_RESET_STATUS), |
| 805 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 806 | SIDLE_SMART_WKUP), |
| 807 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 808 | }; |
| 809 | |
| 810 | static struct omap_hwmod_class am33xx_gpio_hwmod_class = { |
| 811 | .name = "gpio", |
| 812 | .sysc = &am33xx_gpio_sysc, |
| 813 | .rev = 2, |
| 814 | }; |
| 815 | |
| 816 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 817 | .bank_width = 32, |
| 818 | .dbck_flag = true, |
| 819 | }; |
| 820 | |
| 821 | /* gpio0 */ |
| 822 | static struct omap_hwmod_opt_clk gpio0_opt_clks[] = { |
| 823 | { .role = "dbclk", .clk = "gpio0_dbclk" }, |
| 824 | }; |
| 825 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 826 | static struct omap_hwmod am33xx_gpio0_hwmod = { |
| 827 | .name = "gpio1", |
| 828 | .class = &am33xx_gpio_hwmod_class, |
| 829 | .clkdm_name = "l4_wkup_clkdm", |
| 830 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 831 | .main_clk = "dpll_core_m4_div2_ck", |
| 832 | .prcm = { |
| 833 | .omap4 = { |
| 834 | .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET, |
| 835 | .modulemode = MODULEMODE_SWCTRL, |
| 836 | }, |
| 837 | }, |
| 838 | .opt_clks = gpio0_opt_clks, |
| 839 | .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks), |
| 840 | .dev_attr = &gpio_dev_attr, |
| 841 | }; |
| 842 | |
| 843 | /* gpio1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 844 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
| 845 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
| 846 | }; |
| 847 | |
| 848 | static struct omap_hwmod am33xx_gpio1_hwmod = { |
| 849 | .name = "gpio2", |
| 850 | .class = &am33xx_gpio_hwmod_class, |
| 851 | .clkdm_name = "l4ls_clkdm", |
| 852 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 853 | .main_clk = "l4ls_gclk", |
| 854 | .prcm = { |
| 855 | .omap4 = { |
| 856 | .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET, |
| 857 | .modulemode = MODULEMODE_SWCTRL, |
| 858 | }, |
| 859 | }, |
| 860 | .opt_clks = gpio1_opt_clks, |
| 861 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), |
| 862 | .dev_attr = &gpio_dev_attr, |
| 863 | }; |
| 864 | |
| 865 | /* gpio2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 866 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
| 867 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
| 868 | }; |
| 869 | |
| 870 | static struct omap_hwmod am33xx_gpio2_hwmod = { |
| 871 | .name = "gpio3", |
| 872 | .class = &am33xx_gpio_hwmod_class, |
| 873 | .clkdm_name = "l4ls_clkdm", |
| 874 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 875 | .main_clk = "l4ls_gclk", |
| 876 | .prcm = { |
| 877 | .omap4 = { |
| 878 | .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET, |
| 879 | .modulemode = MODULEMODE_SWCTRL, |
| 880 | }, |
| 881 | }, |
| 882 | .opt_clks = gpio2_opt_clks, |
| 883 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), |
| 884 | .dev_attr = &gpio_dev_attr, |
| 885 | }; |
| 886 | |
| 887 | /* gpio3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 888 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
| 889 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
| 890 | }; |
| 891 | |
| 892 | static struct omap_hwmod am33xx_gpio3_hwmod = { |
| 893 | .name = "gpio4", |
| 894 | .class = &am33xx_gpio_hwmod_class, |
| 895 | .clkdm_name = "l4ls_clkdm", |
| 896 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 897 | .main_clk = "l4ls_gclk", |
| 898 | .prcm = { |
| 899 | .omap4 = { |
| 900 | .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET, |
| 901 | .modulemode = MODULEMODE_SWCTRL, |
| 902 | }, |
| 903 | }, |
| 904 | .opt_clks = gpio3_opt_clks, |
| 905 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), |
| 906 | .dev_attr = &gpio_dev_attr, |
| 907 | }; |
| 908 | |
| 909 | /* gpmc */ |
| 910 | static struct omap_hwmod_class_sysconfig gpmc_sysc = { |
| 911 | .rev_offs = 0x0, |
| 912 | .sysc_offs = 0x10, |
| 913 | .syss_offs = 0x14, |
| 914 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
| 915 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 916 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 917 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 918 | }; |
| 919 | |
| 920 | static struct omap_hwmod_class am33xx_gpmc_hwmod_class = { |
| 921 | .name = "gpmc", |
| 922 | .sysc = &gpmc_sysc, |
| 923 | }; |
| 924 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 925 | static struct omap_hwmod am33xx_gpmc_hwmod = { |
| 926 | .name = "gpmc", |
| 927 | .class = &am33xx_gpmc_hwmod_class, |
| 928 | .clkdm_name = "l3s_clkdm", |
| 929 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 930 | .main_clk = "l3s_gclk", |
| 931 | .prcm = { |
| 932 | .omap4 = { |
| 933 | .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET, |
| 934 | .modulemode = MODULEMODE_SWCTRL, |
| 935 | }, |
| 936 | }, |
| 937 | }; |
| 938 | |
| 939 | /* 'i2c' class */ |
| 940 | static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = { |
| 941 | .sysc_offs = 0x0010, |
| 942 | .syss_offs = 0x0090, |
| 943 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 944 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 945 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 946 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 947 | SIDLE_SMART_WKUP), |
| 948 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 949 | }; |
| 950 | |
| 951 | static struct omap_hwmod_class i2c_class = { |
| 952 | .name = "i2c", |
| 953 | .sysc = &am33xx_i2c_sysc, |
| 954 | .rev = OMAP_I2C_IP_VERSION_2, |
| 955 | .reset = &omap_i2c_reset, |
| 956 | }; |
| 957 | |
| 958 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
Shubhrajyoti D | 972deb4 | 2012-11-26 15:25:11 +0530 | [diff] [blame] | 959 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 960 | }; |
| 961 | |
| 962 | /* i2c1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 963 | static struct omap_hwmod am33xx_i2c1_hwmod = { |
| 964 | .name = "i2c1", |
| 965 | .class = &i2c_class, |
| 966 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 967 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 968 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
| 969 | .prcm = { |
| 970 | .omap4 = { |
| 971 | .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET, |
| 972 | .modulemode = MODULEMODE_SWCTRL, |
| 973 | }, |
| 974 | }, |
| 975 | .dev_attr = &i2c_dev_attr, |
| 976 | }; |
| 977 | |
| 978 | /* i2c1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 979 | static struct omap_hwmod am33xx_i2c2_hwmod = { |
| 980 | .name = "i2c2", |
| 981 | .class = &i2c_class, |
| 982 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 983 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 984 | .main_clk = "dpll_per_m2_div4_ck", |
| 985 | .prcm = { |
| 986 | .omap4 = { |
| 987 | .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET, |
| 988 | .modulemode = MODULEMODE_SWCTRL, |
| 989 | }, |
| 990 | }, |
| 991 | .dev_attr = &i2c_dev_attr, |
| 992 | }; |
| 993 | |
| 994 | /* i2c3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 995 | static struct omap_hwmod am33xx_i2c3_hwmod = { |
| 996 | .name = "i2c3", |
| 997 | .class = &i2c_class, |
| 998 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 999 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
| 1000 | .main_clk = "dpll_per_m2_div4_ck", |
| 1001 | .prcm = { |
| 1002 | .omap4 = { |
| 1003 | .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET, |
| 1004 | .modulemode = MODULEMODE_SWCTRL, |
| 1005 | }, |
| 1006 | }, |
| 1007 | .dev_attr = &i2c_dev_attr, |
| 1008 | }; |
| 1009 | |
| 1010 | |
| 1011 | /* lcdc */ |
| 1012 | static struct omap_hwmod_class_sysconfig lcdc_sysc = { |
| 1013 | .rev_offs = 0x0, |
| 1014 | .sysc_offs = 0x54, |
| 1015 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), |
| 1016 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1017 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1018 | }; |
| 1019 | |
| 1020 | static struct omap_hwmod_class am33xx_lcdc_hwmod_class = { |
| 1021 | .name = "lcdc", |
| 1022 | .sysc = &lcdc_sysc, |
| 1023 | }; |
| 1024 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1025 | static struct omap_hwmod am33xx_lcdc_hwmod = { |
| 1026 | .name = "lcdc", |
| 1027 | .class = &am33xx_lcdc_hwmod_class, |
| 1028 | .clkdm_name = "lcdc_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1029 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 1030 | .main_clk = "lcd_gclk", |
| 1031 | .prcm = { |
| 1032 | .omap4 = { |
| 1033 | .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET, |
| 1034 | .modulemode = MODULEMODE_SWCTRL, |
| 1035 | }, |
| 1036 | }, |
| 1037 | }; |
| 1038 | |
| 1039 | /* |
| 1040 | * 'mailbox' class |
| 1041 | * mailbox module allowing communication between the on-chip processors using a |
| 1042 | * queued mailbox-interrupt mechanism. |
| 1043 | */ |
| 1044 | static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = { |
| 1045 | .rev_offs = 0x0000, |
| 1046 | .sysc_offs = 0x0010, |
| 1047 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | |
| 1048 | SYSC_HAS_SOFTRESET), |
| 1049 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1050 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1051 | }; |
| 1052 | |
| 1053 | static struct omap_hwmod_class am33xx_mailbox_hwmod_class = { |
| 1054 | .name = "mailbox", |
| 1055 | .sysc = &am33xx_mailbox_sysc, |
| 1056 | }; |
| 1057 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1058 | static struct omap_hwmod am33xx_mailbox_hwmod = { |
| 1059 | .name = "mailbox", |
| 1060 | .class = &am33xx_mailbox_hwmod_class, |
| 1061 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1062 | .main_clk = "l4ls_gclk", |
| 1063 | .prcm = { |
| 1064 | .omap4 = { |
| 1065 | .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET, |
| 1066 | .modulemode = MODULEMODE_SWCTRL, |
| 1067 | }, |
| 1068 | }, |
| 1069 | }; |
| 1070 | |
| 1071 | /* |
| 1072 | * 'mcasp' class |
| 1073 | */ |
| 1074 | static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = { |
| 1075 | .rev_offs = 0x0, |
| 1076 | .sysc_offs = 0x4, |
| 1077 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
| 1078 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1079 | .sysc_fields = &omap_hwmod_sysc_type3, |
| 1080 | }; |
| 1081 | |
| 1082 | static struct omap_hwmod_class am33xx_mcasp_hwmod_class = { |
| 1083 | .name = "mcasp", |
| 1084 | .sysc = &am33xx_mcasp_sysc, |
| 1085 | }; |
| 1086 | |
| 1087 | /* mcasp0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1088 | static struct omap_hwmod am33xx_mcasp0_hwmod = { |
| 1089 | .name = "mcasp0", |
| 1090 | .class = &am33xx_mcasp_hwmod_class, |
| 1091 | .clkdm_name = "l3s_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1092 | .main_clk = "mcasp0_fck", |
| 1093 | .prcm = { |
| 1094 | .omap4 = { |
| 1095 | .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET, |
| 1096 | .modulemode = MODULEMODE_SWCTRL, |
| 1097 | }, |
| 1098 | }, |
| 1099 | }; |
| 1100 | |
| 1101 | /* mcasp1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1102 | static struct omap_hwmod am33xx_mcasp1_hwmod = { |
| 1103 | .name = "mcasp1", |
| 1104 | .class = &am33xx_mcasp_hwmod_class, |
| 1105 | .clkdm_name = "l3s_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1106 | .main_clk = "mcasp1_fck", |
| 1107 | .prcm = { |
| 1108 | .omap4 = { |
| 1109 | .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET, |
| 1110 | .modulemode = MODULEMODE_SWCTRL, |
| 1111 | }, |
| 1112 | }, |
| 1113 | }; |
| 1114 | |
| 1115 | /* 'mmc' class */ |
| 1116 | static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = { |
| 1117 | .rev_offs = 0x1fc, |
| 1118 | .sysc_offs = 0x10, |
| 1119 | .syss_offs = 0x14, |
| 1120 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1121 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 1122 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 1123 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1124 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1125 | }; |
| 1126 | |
| 1127 | static struct omap_hwmod_class am33xx_mmc_hwmod_class = { |
| 1128 | .name = "mmc", |
| 1129 | .sysc = &am33xx_mmc_sysc, |
| 1130 | }; |
| 1131 | |
| 1132 | /* mmc0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1133 | static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { |
| 1134 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1135 | }; |
| 1136 | |
| 1137 | static struct omap_hwmod am33xx_mmc0_hwmod = { |
| 1138 | .name = "mmc1", |
| 1139 | .class = &am33xx_mmc_hwmod_class, |
| 1140 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1141 | .main_clk = "mmc_clk", |
| 1142 | .prcm = { |
| 1143 | .omap4 = { |
| 1144 | .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET, |
| 1145 | .modulemode = MODULEMODE_SWCTRL, |
| 1146 | }, |
| 1147 | }, |
| 1148 | .dev_attr = &am33xx_mmc0_dev_attr, |
| 1149 | }; |
| 1150 | |
| 1151 | /* mmc1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1152 | static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { |
| 1153 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1154 | }; |
| 1155 | |
| 1156 | static struct omap_hwmod am33xx_mmc1_hwmod = { |
| 1157 | .name = "mmc2", |
| 1158 | .class = &am33xx_mmc_hwmod_class, |
| 1159 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1160 | .main_clk = "mmc_clk", |
| 1161 | .prcm = { |
| 1162 | .omap4 = { |
| 1163 | .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET, |
| 1164 | .modulemode = MODULEMODE_SWCTRL, |
| 1165 | }, |
| 1166 | }, |
| 1167 | .dev_attr = &am33xx_mmc1_dev_attr, |
| 1168 | }; |
| 1169 | |
| 1170 | /* mmc2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1171 | static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { |
| 1172 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 1173 | }; |
| 1174 | static struct omap_hwmod am33xx_mmc2_hwmod = { |
| 1175 | .name = "mmc3", |
| 1176 | .class = &am33xx_mmc_hwmod_class, |
| 1177 | .clkdm_name = "l3s_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1178 | .main_clk = "mmc_clk", |
| 1179 | .prcm = { |
| 1180 | .omap4 = { |
| 1181 | .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET, |
| 1182 | .modulemode = MODULEMODE_SWCTRL, |
| 1183 | }, |
| 1184 | }, |
| 1185 | .dev_attr = &am33xx_mmc2_dev_attr, |
| 1186 | }; |
| 1187 | |
| 1188 | /* |
| 1189 | * 'rtc' class |
| 1190 | * rtc subsystem |
| 1191 | */ |
| 1192 | static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { |
| 1193 | .rev_offs = 0x0074, |
| 1194 | .sysc_offs = 0x0078, |
| 1195 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
| 1196 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | |
| 1197 | SIDLE_SMART | SIDLE_SMART_WKUP), |
| 1198 | .sysc_fields = &omap_hwmod_sysc_type3, |
| 1199 | }; |
| 1200 | |
| 1201 | static struct omap_hwmod_class am33xx_rtc_hwmod_class = { |
| 1202 | .name = "rtc", |
| 1203 | .sysc = &am33xx_rtc_sysc, |
| 1204 | }; |
| 1205 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1206 | static struct omap_hwmod am33xx_rtc_hwmod = { |
| 1207 | .name = "rtc", |
| 1208 | .class = &am33xx_rtc_hwmod_class, |
| 1209 | .clkdm_name = "l4_rtc_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1210 | .main_clk = "clk_32768_ck", |
| 1211 | .prcm = { |
| 1212 | .omap4 = { |
| 1213 | .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET, |
| 1214 | .modulemode = MODULEMODE_SWCTRL, |
| 1215 | }, |
| 1216 | }, |
| 1217 | }; |
| 1218 | |
| 1219 | /* 'spi' class */ |
| 1220 | static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = { |
| 1221 | .rev_offs = 0x0000, |
| 1222 | .sysc_offs = 0x0110, |
| 1223 | .syss_offs = 0x0114, |
| 1224 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1225 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 1226 | SYSS_HAS_RESET_STATUS), |
| 1227 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1228 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1229 | }; |
| 1230 | |
| 1231 | static struct omap_hwmod_class am33xx_spi_hwmod_class = { |
| 1232 | .name = "mcspi", |
| 1233 | .sysc = &am33xx_mcspi_sysc, |
| 1234 | .rev = OMAP4_MCSPI_REV, |
| 1235 | }; |
| 1236 | |
| 1237 | /* spi0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1238 | static struct omap2_mcspi_dev_attr mcspi_attrib = { |
| 1239 | .num_chipselect = 2, |
| 1240 | }; |
| 1241 | static struct omap_hwmod am33xx_spi0_hwmod = { |
| 1242 | .name = "spi0", |
| 1243 | .class = &am33xx_spi_hwmod_class, |
| 1244 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1245 | .main_clk = "dpll_per_m2_div4_ck", |
| 1246 | .prcm = { |
| 1247 | .omap4 = { |
| 1248 | .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET, |
| 1249 | .modulemode = MODULEMODE_SWCTRL, |
| 1250 | }, |
| 1251 | }, |
| 1252 | .dev_attr = &mcspi_attrib, |
| 1253 | }; |
| 1254 | |
| 1255 | /* spi1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1256 | static struct omap_hwmod am33xx_spi1_hwmod = { |
| 1257 | .name = "spi1", |
| 1258 | .class = &am33xx_spi_hwmod_class, |
| 1259 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1260 | .main_clk = "dpll_per_m2_div4_ck", |
| 1261 | .prcm = { |
| 1262 | .omap4 = { |
| 1263 | .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET, |
| 1264 | .modulemode = MODULEMODE_SWCTRL, |
| 1265 | }, |
| 1266 | }, |
| 1267 | .dev_attr = &mcspi_attrib, |
| 1268 | }; |
| 1269 | |
| 1270 | /* |
| 1271 | * 'spinlock' class |
| 1272 | * spinlock provides hardware assistance for synchronizing the |
| 1273 | * processes running on multiple processors |
| 1274 | */ |
| 1275 | static struct omap_hwmod_class am33xx_spinlock_hwmod_class = { |
| 1276 | .name = "spinlock", |
| 1277 | }; |
| 1278 | |
| 1279 | static struct omap_hwmod am33xx_spinlock_hwmod = { |
| 1280 | .name = "spinlock", |
| 1281 | .class = &am33xx_spinlock_hwmod_class, |
| 1282 | .clkdm_name = "l4ls_clkdm", |
| 1283 | .main_clk = "l4ls_gclk", |
| 1284 | .prcm = { |
| 1285 | .omap4 = { |
| 1286 | .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET, |
| 1287 | .modulemode = MODULEMODE_SWCTRL, |
| 1288 | }, |
| 1289 | }, |
| 1290 | }; |
| 1291 | |
| 1292 | /* 'timer 2-7' class */ |
| 1293 | static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { |
| 1294 | .rev_offs = 0x0000, |
| 1295 | .sysc_offs = 0x0010, |
| 1296 | .syss_offs = 0x0014, |
| 1297 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 1298 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1299 | SIDLE_SMART_WKUP), |
| 1300 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1301 | }; |
| 1302 | |
| 1303 | static struct omap_hwmod_class am33xx_timer_hwmod_class = { |
| 1304 | .name = "timer", |
| 1305 | .sysc = &am33xx_timer_sysc, |
| 1306 | }; |
| 1307 | |
| 1308 | /* timer1 1ms */ |
| 1309 | static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = { |
| 1310 | .rev_offs = 0x0000, |
| 1311 | .sysc_offs = 0x0010, |
| 1312 | .syss_offs = 0x0014, |
| 1313 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 1314 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 1315 | SYSS_HAS_RESET_STATUS), |
| 1316 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1317 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1318 | }; |
| 1319 | |
| 1320 | static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = { |
| 1321 | .name = "timer", |
| 1322 | .sysc = &am33xx_timer1ms_sysc, |
| 1323 | }; |
| 1324 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1325 | static struct omap_hwmod am33xx_timer1_hwmod = { |
| 1326 | .name = "timer1", |
| 1327 | .class = &am33xx_timer1ms_hwmod_class, |
| 1328 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1329 | .main_clk = "timer1_fck", |
| 1330 | .prcm = { |
| 1331 | .omap4 = { |
| 1332 | .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
| 1333 | .modulemode = MODULEMODE_SWCTRL, |
| 1334 | }, |
| 1335 | }, |
| 1336 | }; |
| 1337 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1338 | static struct omap_hwmod am33xx_timer2_hwmod = { |
| 1339 | .name = "timer2", |
| 1340 | .class = &am33xx_timer_hwmod_class, |
| 1341 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1342 | .main_clk = "timer2_fck", |
| 1343 | .prcm = { |
| 1344 | .omap4 = { |
| 1345 | .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET, |
| 1346 | .modulemode = MODULEMODE_SWCTRL, |
| 1347 | }, |
| 1348 | }, |
| 1349 | }; |
| 1350 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1351 | static struct omap_hwmod am33xx_timer3_hwmod = { |
| 1352 | .name = "timer3", |
| 1353 | .class = &am33xx_timer_hwmod_class, |
| 1354 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1355 | .main_clk = "timer3_fck", |
| 1356 | .prcm = { |
| 1357 | .omap4 = { |
| 1358 | .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET, |
| 1359 | .modulemode = MODULEMODE_SWCTRL, |
| 1360 | }, |
| 1361 | }, |
| 1362 | }; |
| 1363 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1364 | static struct omap_hwmod am33xx_timer4_hwmod = { |
| 1365 | .name = "timer4", |
| 1366 | .class = &am33xx_timer_hwmod_class, |
| 1367 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1368 | .main_clk = "timer4_fck", |
| 1369 | .prcm = { |
| 1370 | .omap4 = { |
| 1371 | .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET, |
| 1372 | .modulemode = MODULEMODE_SWCTRL, |
| 1373 | }, |
| 1374 | }, |
| 1375 | }; |
| 1376 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1377 | static struct omap_hwmod am33xx_timer5_hwmod = { |
| 1378 | .name = "timer5", |
| 1379 | .class = &am33xx_timer_hwmod_class, |
| 1380 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1381 | .main_clk = "timer5_fck", |
| 1382 | .prcm = { |
| 1383 | .omap4 = { |
| 1384 | .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET, |
| 1385 | .modulemode = MODULEMODE_SWCTRL, |
| 1386 | }, |
| 1387 | }, |
| 1388 | }; |
| 1389 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1390 | static struct omap_hwmod am33xx_timer6_hwmod = { |
| 1391 | .name = "timer6", |
| 1392 | .class = &am33xx_timer_hwmod_class, |
| 1393 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1394 | .main_clk = "timer6_fck", |
| 1395 | .prcm = { |
| 1396 | .omap4 = { |
| 1397 | .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET, |
| 1398 | .modulemode = MODULEMODE_SWCTRL, |
| 1399 | }, |
| 1400 | }, |
| 1401 | }; |
| 1402 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1403 | static struct omap_hwmod am33xx_timer7_hwmod = { |
| 1404 | .name = "timer7", |
| 1405 | .class = &am33xx_timer_hwmod_class, |
| 1406 | .clkdm_name = "l4ls_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1407 | .main_clk = "timer7_fck", |
| 1408 | .prcm = { |
| 1409 | .omap4 = { |
| 1410 | .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET, |
| 1411 | .modulemode = MODULEMODE_SWCTRL, |
| 1412 | }, |
| 1413 | }, |
| 1414 | }; |
| 1415 | |
| 1416 | /* tpcc */ |
| 1417 | static struct omap_hwmod_class am33xx_tpcc_hwmod_class = { |
| 1418 | .name = "tpcc", |
| 1419 | }; |
| 1420 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1421 | static struct omap_hwmod am33xx_tpcc_hwmod = { |
| 1422 | .name = "tpcc", |
| 1423 | .class = &am33xx_tpcc_hwmod_class, |
| 1424 | .clkdm_name = "l3_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1425 | .main_clk = "l3_gclk", |
| 1426 | .prcm = { |
| 1427 | .omap4 = { |
| 1428 | .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET, |
| 1429 | .modulemode = MODULEMODE_SWCTRL, |
| 1430 | }, |
| 1431 | }, |
| 1432 | }; |
| 1433 | |
| 1434 | static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = { |
| 1435 | .rev_offs = 0x0, |
| 1436 | .sysc_offs = 0x10, |
| 1437 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 1438 | SYSC_HAS_MIDLEMODE), |
| 1439 | .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE), |
| 1440 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1441 | }; |
| 1442 | |
| 1443 | /* 'tptc' class */ |
| 1444 | static struct omap_hwmod_class am33xx_tptc_hwmod_class = { |
| 1445 | .name = "tptc", |
| 1446 | .sysc = &am33xx_tptc_sysc, |
| 1447 | }; |
| 1448 | |
| 1449 | /* tptc0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1450 | static struct omap_hwmod am33xx_tptc0_hwmod = { |
| 1451 | .name = "tptc0", |
| 1452 | .class = &am33xx_tptc_hwmod_class, |
| 1453 | .clkdm_name = "l3_clkdm", |
Vaibhav Bedia | 0bfbbde | 2013-01-29 16:45:03 +0530 | [diff] [blame] | 1454 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1455 | .main_clk = "l3_gclk", |
| 1456 | .prcm = { |
| 1457 | .omap4 = { |
| 1458 | .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET, |
| 1459 | .modulemode = MODULEMODE_SWCTRL, |
| 1460 | }, |
| 1461 | }, |
| 1462 | }; |
| 1463 | |
| 1464 | /* tptc1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1465 | static struct omap_hwmod am33xx_tptc1_hwmod = { |
| 1466 | .name = "tptc1", |
| 1467 | .class = &am33xx_tptc_hwmod_class, |
| 1468 | .clkdm_name = "l3_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1469 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
| 1470 | .main_clk = "l3_gclk", |
| 1471 | .prcm = { |
| 1472 | .omap4 = { |
| 1473 | .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET, |
| 1474 | .modulemode = MODULEMODE_SWCTRL, |
| 1475 | }, |
| 1476 | }, |
| 1477 | }; |
| 1478 | |
| 1479 | /* tptc2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1480 | static struct omap_hwmod am33xx_tptc2_hwmod = { |
| 1481 | .name = "tptc2", |
| 1482 | .class = &am33xx_tptc_hwmod_class, |
| 1483 | .clkdm_name = "l3_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1484 | .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), |
| 1485 | .main_clk = "l3_gclk", |
| 1486 | .prcm = { |
| 1487 | .omap4 = { |
| 1488 | .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET, |
| 1489 | .modulemode = MODULEMODE_SWCTRL, |
| 1490 | }, |
| 1491 | }, |
| 1492 | }; |
| 1493 | |
| 1494 | /* 'uart' class */ |
| 1495 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 1496 | .rev_offs = 0x50, |
| 1497 | .sysc_offs = 0x54, |
| 1498 | .syss_offs = 0x58, |
| 1499 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | |
| 1500 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 1501 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1502 | SIDLE_SMART_WKUP), |
| 1503 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1504 | }; |
| 1505 | |
| 1506 | static struct omap_hwmod_class uart_class = { |
| 1507 | .name = "uart", |
| 1508 | .sysc = &uart_sysc, |
| 1509 | }; |
| 1510 | |
| 1511 | /* uart1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1512 | static struct omap_hwmod am33xx_uart1_hwmod = { |
| 1513 | .name = "uart1", |
| 1514 | .class = &uart_class, |
| 1515 | .clkdm_name = "l4_wkup_clkdm", |
Rajendra Nayak | 7dedd34 | 2013-07-28 23:01:48 -0600 | [diff] [blame] | 1516 | .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1517 | .main_clk = "dpll_per_m2_div4_wkupdm_ck", |
| 1518 | .prcm = { |
| 1519 | .omap4 = { |
| 1520 | .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET, |
| 1521 | .modulemode = MODULEMODE_SWCTRL, |
| 1522 | }, |
| 1523 | }, |
| 1524 | }; |
| 1525 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1526 | static struct omap_hwmod am33xx_uart2_hwmod = { |
| 1527 | .name = "uart2", |
| 1528 | .class = &uart_class, |
| 1529 | .clkdm_name = "l4ls_clkdm", |
Santosh Shilimkar | 66dde54 | 2013-05-15 20:18:39 +0530 | [diff] [blame] | 1530 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1531 | .main_clk = "dpll_per_m2_div4_ck", |
| 1532 | .prcm = { |
| 1533 | .omap4 = { |
| 1534 | .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET, |
| 1535 | .modulemode = MODULEMODE_SWCTRL, |
| 1536 | }, |
| 1537 | }, |
| 1538 | }; |
| 1539 | |
| 1540 | /* uart3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1541 | static struct omap_hwmod am33xx_uart3_hwmod = { |
| 1542 | .name = "uart3", |
| 1543 | .class = &uart_class, |
| 1544 | .clkdm_name = "l4ls_clkdm", |
Santosh Shilimkar | 66dde54 | 2013-05-15 20:18:39 +0530 | [diff] [blame] | 1545 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1546 | .main_clk = "dpll_per_m2_div4_ck", |
| 1547 | .prcm = { |
| 1548 | .omap4 = { |
| 1549 | .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET, |
| 1550 | .modulemode = MODULEMODE_SWCTRL, |
| 1551 | }, |
| 1552 | }, |
| 1553 | }; |
| 1554 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1555 | static struct omap_hwmod am33xx_uart4_hwmod = { |
| 1556 | .name = "uart4", |
| 1557 | .class = &uart_class, |
| 1558 | .clkdm_name = "l4ls_clkdm", |
Santosh Shilimkar | 66dde54 | 2013-05-15 20:18:39 +0530 | [diff] [blame] | 1559 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1560 | .main_clk = "dpll_per_m2_div4_ck", |
| 1561 | .prcm = { |
| 1562 | .omap4 = { |
| 1563 | .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET, |
| 1564 | .modulemode = MODULEMODE_SWCTRL, |
| 1565 | }, |
| 1566 | }, |
| 1567 | }; |
| 1568 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1569 | static struct omap_hwmod am33xx_uart5_hwmod = { |
| 1570 | .name = "uart5", |
| 1571 | .class = &uart_class, |
| 1572 | .clkdm_name = "l4ls_clkdm", |
Santosh Shilimkar | 66dde54 | 2013-05-15 20:18:39 +0530 | [diff] [blame] | 1573 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1574 | .main_clk = "dpll_per_m2_div4_ck", |
| 1575 | .prcm = { |
| 1576 | .omap4 = { |
| 1577 | .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET, |
| 1578 | .modulemode = MODULEMODE_SWCTRL, |
| 1579 | }, |
| 1580 | }, |
| 1581 | }; |
| 1582 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1583 | static struct omap_hwmod am33xx_uart6_hwmod = { |
| 1584 | .name = "uart6", |
| 1585 | .class = &uart_class, |
| 1586 | .clkdm_name = "l4ls_clkdm", |
Santosh Shilimkar | 66dde54 | 2013-05-15 20:18:39 +0530 | [diff] [blame] | 1587 | .flags = HWMOD_SWSUP_SIDLE_ACT, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1588 | .main_clk = "dpll_per_m2_div4_ck", |
| 1589 | .prcm = { |
| 1590 | .omap4 = { |
| 1591 | .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET, |
| 1592 | .modulemode = MODULEMODE_SWCTRL, |
| 1593 | }, |
| 1594 | }, |
| 1595 | }; |
| 1596 | |
| 1597 | /* 'wd_timer' class */ |
Vaibhav Hiremath | 05cf03b | 2013-03-31 20:22:21 -0600 | [diff] [blame] | 1598 | static struct omap_hwmod_class_sysconfig wdt_sysc = { |
| 1599 | .rev_offs = 0x0, |
| 1600 | .sysc_offs = 0x10, |
| 1601 | .syss_offs = 0x14, |
| 1602 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | |
| 1603 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 1604 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1605 | SIDLE_SMART_WKUP), |
| 1606 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1607 | }; |
| 1608 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1609 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { |
| 1610 | .name = "wd_timer", |
Vaibhav Hiremath | 05cf03b | 2013-03-31 20:22:21 -0600 | [diff] [blame] | 1611 | .sysc = &wdt_sysc, |
| 1612 | .pre_shutdown = &omap2_wd_timer_disable, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1613 | }; |
| 1614 | |
| 1615 | /* |
| 1616 | * XXX: device.c file uses hardcoded name for watchdog timer |
| 1617 | * driver "wd_timer2, so we are also using same name as of now... |
| 1618 | */ |
| 1619 | static struct omap_hwmod am33xx_wd_timer1_hwmod = { |
| 1620 | .name = "wd_timer2", |
| 1621 | .class = &am33xx_wd_timer_hwmod_class, |
| 1622 | .clkdm_name = "l4_wkup_clkdm", |
Vaibhav Hiremath | 05cf03b | 2013-03-31 20:22:21 -0600 | [diff] [blame] | 1623 | .flags = HWMOD_SWSUP_SIDLE, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1624 | .main_clk = "wdt1_fck", |
| 1625 | .prcm = { |
| 1626 | .omap4 = { |
| 1627 | .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET, |
| 1628 | .modulemode = MODULEMODE_SWCTRL, |
| 1629 | }, |
| 1630 | }, |
| 1631 | }; |
| 1632 | |
| 1633 | /* |
| 1634 | * 'usb_otg' class |
| 1635 | * high-speed on-the-go universal serial bus (usb_otg) controller |
| 1636 | */ |
| 1637 | static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = { |
| 1638 | .rev_offs = 0x0, |
| 1639 | .sysc_offs = 0x10, |
| 1640 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), |
| 1641 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1642 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 1643 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1644 | }; |
| 1645 | |
| 1646 | static struct omap_hwmod_class am33xx_usbotg_class = { |
| 1647 | .name = "usbotg", |
| 1648 | .sysc = &am33xx_usbhsotg_sysc, |
| 1649 | }; |
| 1650 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1651 | static struct omap_hwmod am33xx_usbss_hwmod = { |
| 1652 | .name = "usb_otg_hs", |
| 1653 | .class = &am33xx_usbotg_class, |
| 1654 | .clkdm_name = "l3s_clkdm", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1655 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 1656 | .main_clk = "usbotg_fck", |
| 1657 | .prcm = { |
| 1658 | .omap4 = { |
| 1659 | .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET, |
| 1660 | .modulemode = MODULEMODE_SWCTRL, |
| 1661 | }, |
| 1662 | }, |
| 1663 | }; |
| 1664 | |
| 1665 | |
| 1666 | /* |
| 1667 | * Interfaces |
| 1668 | */ |
| 1669 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1670 | static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { |
| 1671 | { |
| 1672 | .pa_start = 0x4c000000, |
| 1673 | .pa_end = 0x4c000fff, |
| 1674 | .flags = ADDR_TYPE_RT |
| 1675 | }, |
| 1676 | { } |
| 1677 | }; |
| 1678 | /* l3 main -> emif */ |
| 1679 | static struct omap_hwmod_ocp_if am33xx_l3_main__emif = { |
| 1680 | .master = &am33xx_l3_main_hwmod, |
| 1681 | .slave = &am33xx_emif_hwmod, |
| 1682 | .clk = "dpll_core_m4_ck", |
| 1683 | .addr = am33xx_emif_addrs, |
| 1684 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1685 | }; |
| 1686 | |
| 1687 | /* mpu -> l3 main */ |
| 1688 | static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = { |
| 1689 | .master = &am33xx_mpu_hwmod, |
| 1690 | .slave = &am33xx_l3_main_hwmod, |
| 1691 | .clk = "dpll_mpu_m2_ck", |
| 1692 | .user = OCP_USER_MPU, |
| 1693 | }; |
| 1694 | |
| 1695 | /* l3 main -> l4 hs */ |
| 1696 | static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = { |
| 1697 | .master = &am33xx_l3_main_hwmod, |
| 1698 | .slave = &am33xx_l4_hs_hwmod, |
| 1699 | .clk = "l3s_gclk", |
| 1700 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1701 | }; |
| 1702 | |
| 1703 | /* l3 main -> l3 s */ |
| 1704 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = { |
| 1705 | .master = &am33xx_l3_main_hwmod, |
| 1706 | .slave = &am33xx_l3_s_hwmod, |
| 1707 | .clk = "l3s_gclk", |
| 1708 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1709 | }; |
| 1710 | |
| 1711 | /* l3 s -> l4 per/ls */ |
| 1712 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = { |
| 1713 | .master = &am33xx_l3_s_hwmod, |
| 1714 | .slave = &am33xx_l4_ls_hwmod, |
| 1715 | .clk = "l3s_gclk", |
| 1716 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1717 | }; |
| 1718 | |
| 1719 | /* l3 s -> l4 wkup */ |
| 1720 | static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = { |
| 1721 | .master = &am33xx_l3_s_hwmod, |
| 1722 | .slave = &am33xx_l4_wkup_hwmod, |
| 1723 | .clk = "l3s_gclk", |
| 1724 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1725 | }; |
| 1726 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1727 | /* l3 main -> l3 instr */ |
| 1728 | static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { |
| 1729 | .master = &am33xx_l3_main_hwmod, |
| 1730 | .slave = &am33xx_l3_instr_hwmod, |
| 1731 | .clk = "l3s_gclk", |
| 1732 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1733 | }; |
| 1734 | |
| 1735 | /* mpu -> prcm */ |
| 1736 | static struct omap_hwmod_ocp_if am33xx_mpu__prcm = { |
| 1737 | .master = &am33xx_mpu_hwmod, |
| 1738 | .slave = &am33xx_prcm_hwmod, |
| 1739 | .clk = "dpll_mpu_m2_ck", |
| 1740 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1741 | }; |
| 1742 | |
| 1743 | /* l3 s -> l3 main*/ |
| 1744 | static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { |
| 1745 | .master = &am33xx_l3_s_hwmod, |
| 1746 | .slave = &am33xx_l3_main_hwmod, |
| 1747 | .clk = "l3s_gclk", |
| 1748 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1749 | }; |
| 1750 | |
| 1751 | /* pru-icss -> l3 main */ |
| 1752 | static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = { |
| 1753 | .master = &am33xx_pruss_hwmod, |
| 1754 | .slave = &am33xx_l3_main_hwmod, |
| 1755 | .clk = "l3_gclk", |
| 1756 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1757 | }; |
| 1758 | |
| 1759 | /* wkup m3 -> l4 wkup */ |
| 1760 | static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = { |
| 1761 | .master = &am33xx_wkup_m3_hwmod, |
| 1762 | .slave = &am33xx_l4_wkup_hwmod, |
| 1763 | .clk = "dpll_core_m4_div2_ck", |
| 1764 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1765 | }; |
| 1766 | |
| 1767 | /* gfx -> l3 main */ |
| 1768 | static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { |
| 1769 | .master = &am33xx_gfx_hwmod, |
| 1770 | .slave = &am33xx_l3_main_hwmod, |
| 1771 | .clk = "dpll_core_m4_ck", |
| 1772 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1773 | }; |
| 1774 | |
| 1775 | /* l4 wkup -> wkup m3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1776 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { |
| 1777 | .master = &am33xx_l4_wkup_hwmod, |
| 1778 | .slave = &am33xx_wkup_m3_hwmod, |
| 1779 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1780 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1781 | }; |
| 1782 | |
| 1783 | /* l4 hs -> pru-icss */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1784 | static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { |
| 1785 | .master = &am33xx_l4_hs_hwmod, |
| 1786 | .slave = &am33xx_pruss_hwmod, |
| 1787 | .clk = "dpll_core_m4_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1788 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1789 | }; |
| 1790 | |
| 1791 | /* l3 main -> gfx */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1792 | static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { |
| 1793 | .master = &am33xx_l3_main_hwmod, |
| 1794 | .slave = &am33xx_gfx_hwmod, |
| 1795 | .clk = "dpll_core_m4_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1796 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1797 | }; |
| 1798 | |
| 1799 | /* l4 wkup -> smartreflex0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1800 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { |
| 1801 | .master = &am33xx_l4_wkup_hwmod, |
| 1802 | .slave = &am33xx_smartreflex0_hwmod, |
| 1803 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1804 | .user = OCP_USER_MPU, |
| 1805 | }; |
| 1806 | |
| 1807 | /* l4 wkup -> smartreflex1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1808 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { |
| 1809 | .master = &am33xx_l4_wkup_hwmod, |
| 1810 | .slave = &am33xx_smartreflex1_hwmod, |
| 1811 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1812 | .user = OCP_USER_MPU, |
| 1813 | }; |
| 1814 | |
| 1815 | /* l4 wkup -> control */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1816 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { |
| 1817 | .master = &am33xx_l4_wkup_hwmod, |
| 1818 | .slave = &am33xx_control_hwmod, |
| 1819 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1820 | .user = OCP_USER_MPU, |
| 1821 | }; |
| 1822 | |
| 1823 | /* l4 wkup -> rtc */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1824 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { |
| 1825 | .master = &am33xx_l4_wkup_hwmod, |
| 1826 | .slave = &am33xx_rtc_hwmod, |
| 1827 | .clk = "clkdiv32k_ick", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1828 | .user = OCP_USER_MPU, |
| 1829 | }; |
| 1830 | |
| 1831 | /* l4 per/ls -> DCAN0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1832 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { |
| 1833 | .master = &am33xx_l4_ls_hwmod, |
| 1834 | .slave = &am33xx_dcan0_hwmod, |
| 1835 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1836 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1837 | }; |
| 1838 | |
| 1839 | /* l4 per/ls -> DCAN1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1840 | static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { |
| 1841 | .master = &am33xx_l4_ls_hwmod, |
| 1842 | .slave = &am33xx_dcan1_hwmod, |
| 1843 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1844 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1845 | }; |
| 1846 | |
| 1847 | /* l4 per/ls -> GPIO2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1848 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { |
| 1849 | .master = &am33xx_l4_ls_hwmod, |
| 1850 | .slave = &am33xx_gpio1_hwmod, |
| 1851 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1852 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1853 | }; |
| 1854 | |
| 1855 | /* l4 per/ls -> gpio3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1856 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { |
| 1857 | .master = &am33xx_l4_ls_hwmod, |
| 1858 | .slave = &am33xx_gpio2_hwmod, |
| 1859 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1860 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1861 | }; |
| 1862 | |
| 1863 | /* l4 per/ls -> gpio4 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1864 | static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { |
| 1865 | .master = &am33xx_l4_ls_hwmod, |
| 1866 | .slave = &am33xx_gpio3_hwmod, |
| 1867 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1868 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1869 | }; |
| 1870 | |
| 1871 | /* L4 WKUP -> I2C1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1872 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { |
| 1873 | .master = &am33xx_l4_wkup_hwmod, |
| 1874 | .slave = &am33xx_i2c1_hwmod, |
| 1875 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1876 | .user = OCP_USER_MPU, |
| 1877 | }; |
| 1878 | |
| 1879 | /* L4 WKUP -> GPIO1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1880 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { |
| 1881 | .master = &am33xx_l4_wkup_hwmod, |
| 1882 | .slave = &am33xx_gpio0_hwmod, |
| 1883 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1884 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 1885 | }; |
| 1886 | |
| 1887 | /* L4 WKUP -> ADC_TSC */ |
| 1888 | static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = { |
| 1889 | { |
| 1890 | .pa_start = 0x44E0D000, |
| 1891 | .pa_end = 0x44E0D000 + SZ_8K - 1, |
| 1892 | .flags = ADDR_TYPE_RT |
| 1893 | }, |
| 1894 | { } |
| 1895 | }; |
| 1896 | |
| 1897 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = { |
| 1898 | .master = &am33xx_l4_wkup_hwmod, |
| 1899 | .slave = &am33xx_adc_tsc_hwmod, |
| 1900 | .clk = "dpll_core_m4_div2_ck", |
| 1901 | .addr = am33xx_adc_tsc_addrs, |
| 1902 | .user = OCP_USER_MPU, |
| 1903 | }; |
| 1904 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1905 | static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { |
| 1906 | .master = &am33xx_l4_hs_hwmod, |
| 1907 | .slave = &am33xx_cpgmac0_hwmod, |
| 1908 | .clk = "cpsw_125mhz_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1909 | .user = OCP_USER_MPU, |
| 1910 | }; |
| 1911 | |
Paul Walmsley | 9816aa8 | 2012-12-28 02:09:07 -0700 | [diff] [blame] | 1912 | static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 1913 | .master = &am33xx_cpgmac0_hwmod, |
| 1914 | .slave = &am33xx_mdio_hwmod, |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 1915 | .user = OCP_USER_MPU, |
| 1916 | }; |
| 1917 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1918 | static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = { |
| 1919 | { |
| 1920 | .pa_start = 0x48080000, |
| 1921 | .pa_end = 0x48080000 + SZ_8K - 1, |
| 1922 | .flags = ADDR_TYPE_RT |
| 1923 | }, |
| 1924 | { } |
| 1925 | }; |
| 1926 | |
| 1927 | static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = { |
| 1928 | .master = &am33xx_l4_ls_hwmod, |
| 1929 | .slave = &am33xx_elm_hwmod, |
| 1930 | .clk = "l4ls_gclk", |
| 1931 | .addr = am33xx_elm_addr_space, |
| 1932 | .user = OCP_USER_MPU, |
| 1933 | }; |
| 1934 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1935 | static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1936 | { |
| 1937 | .pa_start = 0x48300000, |
| 1938 | .pa_end = 0x48300000 + SZ_16 - 1, |
| 1939 | .flags = ADDR_TYPE_RT |
| 1940 | }, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1941 | { } |
| 1942 | }; |
| 1943 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1944 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1945 | .master = &am33xx_l4_ls_hwmod, |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1946 | .slave = &am33xx_epwmss0_hwmod, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1947 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1948 | .addr = am33xx_epwmss0_addr_space, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1949 | .user = OCP_USER_MPU, |
| 1950 | }; |
| 1951 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1952 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { |
| 1953 | .master = &am33xx_epwmss0_hwmod, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1954 | .slave = &am33xx_ecap0_hwmod, |
| 1955 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1956 | .user = OCP_USER_MPU, |
| 1957 | }; |
| 1958 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1959 | static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { |
| 1960 | .master = &am33xx_epwmss0_hwmod, |
| 1961 | .slave = &am33xx_eqep0_hwmod, |
| 1962 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1963 | .user = OCP_USER_MPU, |
| 1964 | }; |
| 1965 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1966 | static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { |
| 1967 | .master = &am33xx_epwmss0_hwmod, |
| 1968 | .slave = &am33xx_ehrpwm0_hwmod, |
| 1969 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1970 | .user = OCP_USER_MPU, |
| 1971 | }; |
| 1972 | |
| 1973 | |
| 1974 | static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1975 | { |
| 1976 | .pa_start = 0x48302000, |
| 1977 | .pa_end = 0x48302000 + SZ_16 - 1, |
| 1978 | .flags = ADDR_TYPE_RT |
| 1979 | }, |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1980 | { } |
| 1981 | }; |
| 1982 | |
| 1983 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = { |
| 1984 | .master = &am33xx_l4_ls_hwmod, |
| 1985 | .slave = &am33xx_epwmss1_hwmod, |
| 1986 | .clk = "l4ls_gclk", |
| 1987 | .addr = am33xx_epwmss1_addr_space, |
| 1988 | .user = OCP_USER_MPU, |
| 1989 | }; |
| 1990 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1991 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { |
| 1992 | .master = &am33xx_epwmss1_hwmod, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1993 | .slave = &am33xx_ecap1_hwmod, |
| 1994 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 1995 | .user = OCP_USER_MPU, |
| 1996 | }; |
| 1997 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 1998 | static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { |
| 1999 | .master = &am33xx_epwmss1_hwmod, |
| 2000 | .slave = &am33xx_eqep1_hwmod, |
| 2001 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2002 | .user = OCP_USER_MPU, |
| 2003 | }; |
| 2004 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2005 | static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { |
| 2006 | .master = &am33xx_epwmss1_hwmod, |
| 2007 | .slave = &am33xx_ehrpwm1_hwmod, |
| 2008 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2009 | .user = OCP_USER_MPU, |
| 2010 | }; |
| 2011 | |
| 2012 | static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2013 | { |
| 2014 | .pa_start = 0x48304000, |
| 2015 | .pa_end = 0x48304000 + SZ_16 - 1, |
| 2016 | .flags = ADDR_TYPE_RT |
| 2017 | }, |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2018 | { } |
| 2019 | }; |
| 2020 | |
| 2021 | static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = { |
| 2022 | .master = &am33xx_l4_ls_hwmod, |
| 2023 | .slave = &am33xx_epwmss2_hwmod, |
| 2024 | .clk = "l4ls_gclk", |
| 2025 | .addr = am33xx_epwmss2_addr_space, |
| 2026 | .user = OCP_USER_MPU, |
| 2027 | }; |
| 2028 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2029 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { |
| 2030 | .master = &am33xx_epwmss2_hwmod, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2031 | .slave = &am33xx_ecap2_hwmod, |
| 2032 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2033 | .user = OCP_USER_MPU, |
| 2034 | }; |
| 2035 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2036 | static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { |
| 2037 | .master = &am33xx_epwmss2_hwmod, |
| 2038 | .slave = &am33xx_eqep2_hwmod, |
| 2039 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2040 | .user = OCP_USER_MPU, |
| 2041 | }; |
| 2042 | |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2043 | static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { |
| 2044 | .master = &am33xx_epwmss2_hwmod, |
| 2045 | .slave = &am33xx_ehrpwm2_hwmod, |
| 2046 | .clk = "l4ls_gclk", |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2047 | .user = OCP_USER_MPU, |
| 2048 | }; |
| 2049 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2050 | /* l3s cfg -> gpmc */ |
| 2051 | static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { |
| 2052 | { |
| 2053 | .pa_start = 0x50000000, |
| 2054 | .pa_end = 0x50000000 + SZ_8K - 1, |
| 2055 | .flags = ADDR_TYPE_RT, |
| 2056 | }, |
| 2057 | { } |
| 2058 | }; |
| 2059 | |
| 2060 | static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { |
| 2061 | .master = &am33xx_l3_s_hwmod, |
| 2062 | .slave = &am33xx_gpmc_hwmod, |
| 2063 | .clk = "l3s_gclk", |
| 2064 | .addr = am33xx_gpmc_addr_space, |
| 2065 | .user = OCP_USER_MPU, |
| 2066 | }; |
| 2067 | |
| 2068 | /* i2c2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2069 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { |
| 2070 | .master = &am33xx_l4_ls_hwmod, |
| 2071 | .slave = &am33xx_i2c2_hwmod, |
| 2072 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2073 | .user = OCP_USER_MPU, |
| 2074 | }; |
| 2075 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2076 | static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { |
| 2077 | .master = &am33xx_l4_ls_hwmod, |
| 2078 | .slave = &am33xx_i2c3_hwmod, |
| 2079 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2080 | .user = OCP_USER_MPU, |
| 2081 | }; |
| 2082 | |
| 2083 | static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = { |
| 2084 | { |
| 2085 | .pa_start = 0x4830E000, |
| 2086 | .pa_end = 0x4830E000 + SZ_8K - 1, |
| 2087 | .flags = ADDR_TYPE_RT, |
| 2088 | }, |
| 2089 | { } |
| 2090 | }; |
| 2091 | |
| 2092 | static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = { |
| 2093 | .master = &am33xx_l3_main_hwmod, |
| 2094 | .slave = &am33xx_lcdc_hwmod, |
| 2095 | .clk = "dpll_core_m4_ck", |
| 2096 | .addr = am33xx_lcdc_addr_space, |
| 2097 | .user = OCP_USER_MPU, |
| 2098 | }; |
| 2099 | |
| 2100 | static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = { |
| 2101 | { |
| 2102 | .pa_start = 0x480C8000, |
| 2103 | .pa_end = 0x480C8000 + (SZ_4K - 1), |
| 2104 | .flags = ADDR_TYPE_RT |
| 2105 | }, |
| 2106 | { } |
| 2107 | }; |
| 2108 | |
| 2109 | /* l4 ls -> mailbox */ |
| 2110 | static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = { |
| 2111 | .master = &am33xx_l4_ls_hwmod, |
| 2112 | .slave = &am33xx_mailbox_hwmod, |
| 2113 | .clk = "l4ls_gclk", |
| 2114 | .addr = am33xx_mailbox_addrs, |
| 2115 | .user = OCP_USER_MPU, |
| 2116 | }; |
| 2117 | |
| 2118 | /* l4 ls -> spinlock */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2119 | static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { |
| 2120 | .master = &am33xx_l4_ls_hwmod, |
| 2121 | .slave = &am33xx_spinlock_hwmod, |
| 2122 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2123 | .user = OCP_USER_MPU, |
| 2124 | }; |
| 2125 | |
| 2126 | /* l4 ls -> mcasp0 */ |
| 2127 | static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = { |
| 2128 | { |
| 2129 | .pa_start = 0x48038000, |
| 2130 | .pa_end = 0x48038000 + SZ_8K - 1, |
| 2131 | .flags = ADDR_TYPE_RT |
| 2132 | }, |
| 2133 | { } |
| 2134 | }; |
| 2135 | |
| 2136 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = { |
| 2137 | .master = &am33xx_l4_ls_hwmod, |
| 2138 | .slave = &am33xx_mcasp0_hwmod, |
| 2139 | .clk = "l4ls_gclk", |
| 2140 | .addr = am33xx_mcasp0_addr_space, |
| 2141 | .user = OCP_USER_MPU, |
| 2142 | }; |
| 2143 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2144 | /* l4 ls -> mcasp1 */ |
| 2145 | static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { |
| 2146 | { |
| 2147 | .pa_start = 0x4803C000, |
| 2148 | .pa_end = 0x4803C000 + SZ_8K - 1, |
| 2149 | .flags = ADDR_TYPE_RT |
| 2150 | }, |
| 2151 | { } |
| 2152 | }; |
| 2153 | |
| 2154 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = { |
| 2155 | .master = &am33xx_l4_ls_hwmod, |
| 2156 | .slave = &am33xx_mcasp1_hwmod, |
| 2157 | .clk = "l4ls_gclk", |
| 2158 | .addr = am33xx_mcasp1_addr_space, |
| 2159 | .user = OCP_USER_MPU, |
| 2160 | }; |
| 2161 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2162 | /* l4 ls -> mmc0 */ |
| 2163 | static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { |
| 2164 | { |
| 2165 | .pa_start = 0x48060100, |
| 2166 | .pa_end = 0x48060100 + SZ_4K - 1, |
| 2167 | .flags = ADDR_TYPE_RT, |
| 2168 | }, |
| 2169 | { } |
| 2170 | }; |
| 2171 | |
| 2172 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = { |
| 2173 | .master = &am33xx_l4_ls_hwmod, |
| 2174 | .slave = &am33xx_mmc0_hwmod, |
| 2175 | .clk = "l4ls_gclk", |
| 2176 | .addr = am33xx_mmc0_addr_space, |
| 2177 | .user = OCP_USER_MPU, |
| 2178 | }; |
| 2179 | |
| 2180 | /* l4 ls -> mmc1 */ |
| 2181 | static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = { |
| 2182 | { |
| 2183 | .pa_start = 0x481d8100, |
| 2184 | .pa_end = 0x481d8100 + SZ_4K - 1, |
| 2185 | .flags = ADDR_TYPE_RT, |
| 2186 | }, |
| 2187 | { } |
| 2188 | }; |
| 2189 | |
| 2190 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = { |
| 2191 | .master = &am33xx_l4_ls_hwmod, |
| 2192 | .slave = &am33xx_mmc1_hwmod, |
| 2193 | .clk = "l4ls_gclk", |
| 2194 | .addr = am33xx_mmc1_addr_space, |
| 2195 | .user = OCP_USER_MPU, |
| 2196 | }; |
| 2197 | |
| 2198 | /* l3 s -> mmc2 */ |
| 2199 | static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = { |
| 2200 | { |
| 2201 | .pa_start = 0x47810100, |
| 2202 | .pa_end = 0x47810100 + SZ_64K - 1, |
| 2203 | .flags = ADDR_TYPE_RT, |
| 2204 | }, |
| 2205 | { } |
| 2206 | }; |
| 2207 | |
| 2208 | static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = { |
| 2209 | .master = &am33xx_l3_s_hwmod, |
| 2210 | .slave = &am33xx_mmc2_hwmod, |
| 2211 | .clk = "l3s_gclk", |
| 2212 | .addr = am33xx_mmc2_addr_space, |
| 2213 | .user = OCP_USER_MPU, |
| 2214 | }; |
| 2215 | |
| 2216 | /* l4 ls -> mcspi0 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2217 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { |
| 2218 | .master = &am33xx_l4_ls_hwmod, |
| 2219 | .slave = &am33xx_spi0_hwmod, |
| 2220 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2221 | .user = OCP_USER_MPU, |
| 2222 | }; |
| 2223 | |
| 2224 | /* l4 ls -> mcspi1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2225 | static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { |
| 2226 | .master = &am33xx_l4_ls_hwmod, |
| 2227 | .slave = &am33xx_spi1_hwmod, |
| 2228 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2229 | .user = OCP_USER_MPU, |
| 2230 | }; |
| 2231 | |
| 2232 | /* l4 wkup -> timer1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2233 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { |
| 2234 | .master = &am33xx_l4_wkup_hwmod, |
| 2235 | .slave = &am33xx_timer1_hwmod, |
| 2236 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2237 | .user = OCP_USER_MPU, |
| 2238 | }; |
| 2239 | |
| 2240 | /* l4 per -> timer2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2241 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { |
| 2242 | .master = &am33xx_l4_ls_hwmod, |
| 2243 | .slave = &am33xx_timer2_hwmod, |
| 2244 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2245 | .user = OCP_USER_MPU, |
| 2246 | }; |
| 2247 | |
| 2248 | /* l4 per -> timer3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2249 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { |
| 2250 | .master = &am33xx_l4_ls_hwmod, |
| 2251 | .slave = &am33xx_timer3_hwmod, |
| 2252 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2253 | .user = OCP_USER_MPU, |
| 2254 | }; |
| 2255 | |
| 2256 | /* l4 per -> timer4 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2257 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { |
| 2258 | .master = &am33xx_l4_ls_hwmod, |
| 2259 | .slave = &am33xx_timer4_hwmod, |
| 2260 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2261 | .user = OCP_USER_MPU, |
| 2262 | }; |
| 2263 | |
| 2264 | /* l4 per -> timer5 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2265 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { |
| 2266 | .master = &am33xx_l4_ls_hwmod, |
| 2267 | .slave = &am33xx_timer5_hwmod, |
| 2268 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2269 | .user = OCP_USER_MPU, |
| 2270 | }; |
| 2271 | |
| 2272 | /* l4 per -> timer6 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2273 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { |
| 2274 | .master = &am33xx_l4_ls_hwmod, |
| 2275 | .slave = &am33xx_timer6_hwmod, |
| 2276 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2277 | .user = OCP_USER_MPU, |
| 2278 | }; |
| 2279 | |
| 2280 | /* l4 per -> timer7 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2281 | static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { |
| 2282 | .master = &am33xx_l4_ls_hwmod, |
| 2283 | .slave = &am33xx_timer7_hwmod, |
| 2284 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2285 | .user = OCP_USER_MPU, |
| 2286 | }; |
| 2287 | |
| 2288 | /* l3 main -> tpcc */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2289 | static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { |
| 2290 | .master = &am33xx_l3_main_hwmod, |
| 2291 | .slave = &am33xx_tpcc_hwmod, |
| 2292 | .clk = "l3_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2293 | .user = OCP_USER_MPU, |
| 2294 | }; |
| 2295 | |
| 2296 | /* l3 main -> tpcc0 */ |
| 2297 | static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = { |
| 2298 | { |
| 2299 | .pa_start = 0x49800000, |
| 2300 | .pa_end = 0x49800000 + SZ_8K - 1, |
| 2301 | .flags = ADDR_TYPE_RT, |
| 2302 | }, |
| 2303 | { } |
| 2304 | }; |
| 2305 | |
| 2306 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = { |
| 2307 | .master = &am33xx_l3_main_hwmod, |
| 2308 | .slave = &am33xx_tptc0_hwmod, |
| 2309 | .clk = "l3_gclk", |
| 2310 | .addr = am33xx_tptc0_addr_space, |
| 2311 | .user = OCP_USER_MPU, |
| 2312 | }; |
| 2313 | |
| 2314 | /* l3 main -> tpcc1 */ |
| 2315 | static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = { |
| 2316 | { |
| 2317 | .pa_start = 0x49900000, |
| 2318 | .pa_end = 0x49900000 + SZ_8K - 1, |
| 2319 | .flags = ADDR_TYPE_RT, |
| 2320 | }, |
| 2321 | { } |
| 2322 | }; |
| 2323 | |
| 2324 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = { |
| 2325 | .master = &am33xx_l3_main_hwmod, |
| 2326 | .slave = &am33xx_tptc1_hwmod, |
| 2327 | .clk = "l3_gclk", |
| 2328 | .addr = am33xx_tptc1_addr_space, |
| 2329 | .user = OCP_USER_MPU, |
| 2330 | }; |
| 2331 | |
| 2332 | /* l3 main -> tpcc2 */ |
| 2333 | static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = { |
| 2334 | { |
| 2335 | .pa_start = 0x49a00000, |
| 2336 | .pa_end = 0x49a00000 + SZ_8K - 1, |
| 2337 | .flags = ADDR_TYPE_RT, |
| 2338 | }, |
| 2339 | { } |
| 2340 | }; |
| 2341 | |
| 2342 | static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = { |
| 2343 | .master = &am33xx_l3_main_hwmod, |
| 2344 | .slave = &am33xx_tptc2_hwmod, |
| 2345 | .clk = "l3_gclk", |
| 2346 | .addr = am33xx_tptc2_addr_space, |
| 2347 | .user = OCP_USER_MPU, |
| 2348 | }; |
| 2349 | |
| 2350 | /* l4 wkup -> uart1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2351 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { |
| 2352 | .master = &am33xx_l4_wkup_hwmod, |
| 2353 | .slave = &am33xx_uart1_hwmod, |
| 2354 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2355 | .user = OCP_USER_MPU, |
| 2356 | }; |
| 2357 | |
| 2358 | /* l4 ls -> uart2 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2359 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { |
| 2360 | .master = &am33xx_l4_ls_hwmod, |
| 2361 | .slave = &am33xx_uart2_hwmod, |
| 2362 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2363 | .user = OCP_USER_MPU, |
| 2364 | }; |
| 2365 | |
| 2366 | /* l4 ls -> uart3 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2367 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { |
| 2368 | .master = &am33xx_l4_ls_hwmod, |
| 2369 | .slave = &am33xx_uart3_hwmod, |
| 2370 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2371 | .user = OCP_USER_MPU, |
| 2372 | }; |
| 2373 | |
| 2374 | /* l4 ls -> uart4 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2375 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { |
| 2376 | .master = &am33xx_l4_ls_hwmod, |
| 2377 | .slave = &am33xx_uart4_hwmod, |
| 2378 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2379 | .user = OCP_USER_MPU, |
| 2380 | }; |
| 2381 | |
| 2382 | /* l4 ls -> uart5 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2383 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { |
| 2384 | .master = &am33xx_l4_ls_hwmod, |
| 2385 | .slave = &am33xx_uart5_hwmod, |
| 2386 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2387 | .user = OCP_USER_MPU, |
| 2388 | }; |
| 2389 | |
| 2390 | /* l4 ls -> uart6 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2391 | static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { |
| 2392 | .master = &am33xx_l4_ls_hwmod, |
| 2393 | .slave = &am33xx_uart6_hwmod, |
| 2394 | .clk = "l4ls_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2395 | .user = OCP_USER_MPU, |
| 2396 | }; |
| 2397 | |
| 2398 | /* l4 wkup -> wd_timer1 */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2399 | static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { |
| 2400 | .master = &am33xx_l4_wkup_hwmod, |
| 2401 | .slave = &am33xx_wd_timer1_hwmod, |
| 2402 | .clk = "dpll_core_m4_div2_ck", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2403 | .user = OCP_USER_MPU, |
| 2404 | }; |
| 2405 | |
| 2406 | /* usbss */ |
| 2407 | /* l3 s -> USBSS interface */ |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2408 | static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { |
| 2409 | .master = &am33xx_l3_s_hwmod, |
| 2410 | .slave = &am33xx_usbss_hwmod, |
| 2411 | .clk = "l3s_gclk", |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2412 | .user = OCP_USER_MPU, |
| 2413 | .flags = OCPIF_SWSUP_IDLE, |
| 2414 | }; |
| 2415 | |
Vaibhav Bedia | ca903b6 | 2013-01-29 16:45:02 +0530 | [diff] [blame] | 2416 | /* l3 main -> ocmc */ |
| 2417 | static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = { |
| 2418 | .master = &am33xx_l3_main_hwmod, |
| 2419 | .slave = &am33xx_ocmcram_hwmod, |
| 2420 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2421 | }; |
| 2422 | |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 2423 | /* l3 main -> sha0 HIB2 */ |
| 2424 | static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = { |
| 2425 | { |
| 2426 | .pa_start = 0x53100000, |
| 2427 | .pa_end = 0x53100000 + SZ_512 - 1, |
| 2428 | .flags = ADDR_TYPE_RT |
| 2429 | }, |
| 2430 | { } |
| 2431 | }; |
| 2432 | |
| 2433 | static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = { |
| 2434 | .master = &am33xx_l3_main_hwmod, |
| 2435 | .slave = &am33xx_sha0_hwmod, |
| 2436 | .clk = "sha0_fck", |
| 2437 | .addr = am33xx_sha0_addrs, |
| 2438 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2439 | }; |
| 2440 | |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 2441 | /* l3 main -> AES0 HIB2 */ |
| 2442 | static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = { |
| 2443 | { |
| 2444 | .pa_start = 0x53500000, |
| 2445 | .pa_end = 0x53500000 + SZ_1M - 1, |
| 2446 | .flags = ADDR_TYPE_RT |
| 2447 | }, |
| 2448 | { } |
| 2449 | }; |
| 2450 | |
| 2451 | static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = { |
| 2452 | .master = &am33xx_l3_main_hwmod, |
| 2453 | .slave = &am33xx_aes0_hwmod, |
| 2454 | .clk = "aes0_fck", |
| 2455 | .addr = am33xx_aes0_addrs, |
| 2456 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 2457 | }; |
| 2458 | |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2459 | static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2460 | &am33xx_l3_main__emif, |
| 2461 | &am33xx_mpu__l3_main, |
| 2462 | &am33xx_mpu__prcm, |
| 2463 | &am33xx_l3_s__l4_ls, |
| 2464 | &am33xx_l3_s__l4_wkup, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2465 | &am33xx_l3_main__l4_hs, |
| 2466 | &am33xx_l3_main__l3_s, |
| 2467 | &am33xx_l3_main__l3_instr, |
| 2468 | &am33xx_l3_main__gfx, |
| 2469 | &am33xx_l3_s__l3_main, |
| 2470 | &am33xx_pruss__l3_main, |
| 2471 | &am33xx_wkup_m3__l4_wkup, |
| 2472 | &am33xx_gfx__l3_main, |
| 2473 | &am33xx_l4_wkup__wkup_m3, |
| 2474 | &am33xx_l4_wkup__control, |
| 2475 | &am33xx_l4_wkup__smartreflex0, |
| 2476 | &am33xx_l4_wkup__smartreflex1, |
| 2477 | &am33xx_l4_wkup__uart1, |
| 2478 | &am33xx_l4_wkup__timer1, |
| 2479 | &am33xx_l4_wkup__rtc, |
| 2480 | &am33xx_l4_wkup__i2c1, |
| 2481 | &am33xx_l4_wkup__gpio0, |
| 2482 | &am33xx_l4_wkup__adc_tsc, |
| 2483 | &am33xx_l4_wkup__wd_timer1, |
| 2484 | &am33xx_l4_hs__pruss, |
| 2485 | &am33xx_l4_per__dcan0, |
| 2486 | &am33xx_l4_per__dcan1, |
| 2487 | &am33xx_l4_per__gpio1, |
| 2488 | &am33xx_l4_per__gpio2, |
| 2489 | &am33xx_l4_per__gpio3, |
| 2490 | &am33xx_l4_per__i2c2, |
| 2491 | &am33xx_l4_per__i2c3, |
| 2492 | &am33xx_l4_per__mailbox, |
| 2493 | &am33xx_l4_ls__mcasp0, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2494 | &am33xx_l4_ls__mcasp1, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2495 | &am33xx_l4_ls__mmc0, |
| 2496 | &am33xx_l4_ls__mmc1, |
| 2497 | &am33xx_l3_s__mmc2, |
| 2498 | &am33xx_l4_ls__timer2, |
| 2499 | &am33xx_l4_ls__timer3, |
| 2500 | &am33xx_l4_ls__timer4, |
| 2501 | &am33xx_l4_ls__timer5, |
| 2502 | &am33xx_l4_ls__timer6, |
| 2503 | &am33xx_l4_ls__timer7, |
| 2504 | &am33xx_l3_main__tpcc, |
| 2505 | &am33xx_l4_ls__uart2, |
| 2506 | &am33xx_l4_ls__uart3, |
| 2507 | &am33xx_l4_ls__uart4, |
| 2508 | &am33xx_l4_ls__uart5, |
| 2509 | &am33xx_l4_ls__uart6, |
| 2510 | &am33xx_l4_ls__spinlock, |
| 2511 | &am33xx_l4_ls__elm, |
Philip Avinash | 9652d19 | 2013-01-02 18:54:49 +0530 | [diff] [blame] | 2512 | &am33xx_l4_ls__epwmss0, |
| 2513 | &am33xx_epwmss0__ecap0, |
| 2514 | &am33xx_epwmss0__eqep0, |
| 2515 | &am33xx_epwmss0__ehrpwm0, |
| 2516 | &am33xx_l4_ls__epwmss1, |
| 2517 | &am33xx_epwmss1__ecap1, |
| 2518 | &am33xx_epwmss1__eqep1, |
| 2519 | &am33xx_epwmss1__ehrpwm1, |
| 2520 | &am33xx_l4_ls__epwmss2, |
| 2521 | &am33xx_epwmss2__ecap2, |
| 2522 | &am33xx_epwmss2__eqep2, |
| 2523 | &am33xx_epwmss2__ehrpwm2, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2524 | &am33xx_l3_s__gpmc, |
| 2525 | &am33xx_l3_main__lcdc, |
| 2526 | &am33xx_l4_ls__mcspi0, |
| 2527 | &am33xx_l4_ls__mcspi1, |
| 2528 | &am33xx_l3_main__tptc0, |
| 2529 | &am33xx_l3_main__tptc1, |
| 2530 | &am33xx_l3_main__tptc2, |
Vaibhav Bedia | ca903b6 | 2013-01-29 16:45:02 +0530 | [diff] [blame] | 2531 | &am33xx_l3_main__ocmc, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2532 | &am33xx_l3_s__usbss, |
| 2533 | &am33xx_l4_hs__cpgmac0, |
Mugunthan V N | 70384a6 | 2012-11-14 09:07:58 +0000 | [diff] [blame] | 2534 | &am33xx_cpgmac0__mdio, |
Mark A. Greer | aec94bf | 2013-03-18 10:06:35 -0600 | [diff] [blame] | 2535 | &am33xx_l3_main__sha0, |
Mark A. Greer | 1cb804b | 2012-12-21 09:28:14 -0700 | [diff] [blame] | 2536 | &am33xx_l3_main__aes0, |
Vaibhav Hiremath | a2cfc50 | 2012-07-25 13:51:13 -0600 | [diff] [blame] | 2537 | NULL, |
| 2538 | }; |
| 2539 | |
| 2540 | int __init am33xx_hwmod_init(void) |
| 2541 | { |
| 2542 | omap_hwmod_init(); |
| 2543 | return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs); |
| 2544 | } |