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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
6
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
13
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28
29
30 Linux kernel version history:
31
32 LK1.1.0:
33 - Jeff Garzik: softnet 'n stuff
34
35 LK1.1.1:
36 - Justin Guyett: softnet and locking fixes
37 - Jeff Garzik: use PCI interface
38
39 LK1.1.2:
40 - Urban Widmark: minor cleanups, merges from Becker 1.03a/1.04 versions
41
42 LK1.1.3:
43 - Urban Widmark: use PCI DMA interface (with thanks to the eepro100.c
44 code) update "Theory of Operation" with
45 softnet/locking changes
46 - Dave Miller: PCI DMA and endian fixups
47 - Jeff Garzik: MOD_xxx race fixes, updated PCI resource allocation
48
49 LK1.1.4:
50 - Urban Widmark: fix gcc 2.95.2 problem and
51 remove writel's to fixed address 0x7c
52
53 LK1.1.5:
54 - Urban Widmark: mdio locking, bounce buffer changes
55 merges from Beckers 1.05 version
56 added netif_running_on/off support
57
58 LK1.1.6:
59 - Urban Widmark: merges from Beckers 1.08b version (VT6102 + mdio)
60 set netif_running_on/off on startup, del_timer_sync
61
62 LK1.1.7:
63 - Manfred Spraul: added reset into tx_timeout
64
65 LK1.1.9:
66 - Urban Widmark: merges from Beckers 1.10 version
67 (media selection + eeprom reload)
68 - David Vrabel: merges from D-Link "1.11" version
69 (disable WOL and PME on startup)
70
71 LK1.1.10:
72 - Manfred Spraul: use "singlecopy" for unaligned buffers
73 don't allocate bounce buffers for !ReqTxAlign cards
74
75 LK1.1.11:
76 - David Woodhouse: Set dev->base_addr before the first time we call
77 wait_for_reset(). It's a lot happier that way.
78 Free np->tx_bufs only if we actually allocated it.
79
80 LK1.1.12:
81 - Martin Eriksson: Allow Memory-Mapped IO to be enabled.
82
83 LK1.1.13 (jgarzik):
84 - Add ethtool support
85 - Replace some MII-related magic numbers with constants
86
87 LK1.1.14 (Ivan G.):
88 - fixes comments for Rhine-III
89 - removes W_MAX_TIMEOUT (unused)
90 - adds HasDavicomPhy for Rhine-I (basis: linuxfet driver; my card
91 is R-I and has Davicom chip, flag is referenced in kernel driver)
92 - sends chip_id as a parameter to wait_for_reset since np is not
93 initialized on first call
94 - changes mmio "else if (chip_id==VT6102)" to "else" so it will work
95 for Rhine-III's (documentation says same bit is correct)
96 - transmit frame queue message is off by one - fixed
97 - adds IntrNormalSummary to "Something Wicked" exclusion list
98 so normal interrupts will not trigger the message (src: Donald Becker)
99 (Roger Luethi)
100 - show confused chip where to continue after Tx error
101 - location of collision counter is chip specific
102 - allow selecting backoff algorithm (module parameter)
103
104 LK1.1.15 (jgarzik):
105 - Use new MII lib helper generic_mii_ioctl
106
107 LK1.1.16 (Roger Luethi)
108 - Etherleak fix
109 - Handle Tx buffer underrun
110 - Fix bugs in full duplex handling
111 - New reset code uses "force reset" cmd on Rhine-II
112 - Various clean ups
113
114 LK1.1.17 (Roger Luethi)
115 - Fix race in via_rhine_start_tx()
116 - On errors, wait for Tx engine to turn off before scavenging
117 - Handle Tx descriptor write-back race on Rhine-II
118 - Force flushing for PCI posted writes
119 - More reset code changes
120
121 LK1.1.18 (Roger Luethi)
122 - No filtering multicast in promisc mode (Edward Peng)
123 - Fix for Rhine-I Tx timeouts
124
125 LK1.1.19 (Roger Luethi)
126 - Increase Tx threshold for unspecified errors
127
128 LK1.2.0-2.6 (Roger Luethi)
129 - Massive clean-up
130 - Rewrite PHY, media handling (remove options, full_duplex, backoff)
131 - Fix Tx engine race for good
Craig Brind3e0d1672006-04-27 02:30:46 -0700132 - Craig Brind: Zero padded aligned buffers for short packets.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133
134*/
135
136#define DRV_NAME "via-rhine"
137#define DRV_VERSION "1.2.0-2.6"
138#define DRV_RELDATE "June-10-2004"
139
140
141/* A few user-configurable values.
142 These may be modified when a driver module is loaded. */
143
144static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
145static int max_interrupt_work = 20;
146
147/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
148 Setting to > 1518 effectively disables this feature. */
149static int rx_copybreak;
150
151/*
152 * In case you are looking for 'options[]' or 'full_duplex[]', they
153 * are gone. Use ethtool(8) instead.
154 */
155
156/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
157 The Rhine has a 64 element 8390-like hash table. */
158static const int multicast_filter_limit = 32;
159
160
161/* Operational parameters that are set at compile time. */
162
163/* Keep the ring sizes a power of two for compile efficiency.
164 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
165 Making the Tx ring too large decreases the effectiveness of channel
166 bonding and packet priority.
167 There are no ill effects from too-large receive rings. */
168#define TX_RING_SIZE 16
169#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
170#define RX_RING_SIZE 16
171
172
173/* Operational parameters that usually are not changed. */
174
175/* Time in jiffies before concluding the transmitter is hung. */
176#define TX_TIMEOUT (2*HZ)
177
178#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
179
180#include <linux/module.h>
181#include <linux/moduleparam.h>
182#include <linux/kernel.h>
183#include <linux/string.h>
184#include <linux/timer.h>
185#include <linux/errno.h>
186#include <linux/ioport.h>
187#include <linux/slab.h>
188#include <linux/interrupt.h>
189#include <linux/pci.h>
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400190#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191#include <linux/netdevice.h>
192#include <linux/etherdevice.h>
193#include <linux/skbuff.h>
194#include <linux/init.h>
195#include <linux/delay.h>
196#include <linux/mii.h>
197#include <linux/ethtool.h>
198#include <linux/crc32.h>
199#include <linux/bitops.h>
200#include <asm/processor.h> /* Processor type for cache alignment. */
201#include <asm/io.h>
202#include <asm/irq.h>
203#include <asm/uaccess.h>
204
205/* These identify the driver base version and may not be removed. */
206static char version[] __devinitdata =
207KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
208
209/* This driver was written to use PCI memory space. Some early versions
210 of the Rhine may only work correctly with I/O space accesses. */
211#ifdef CONFIG_VIA_RHINE_MMIO
212#define USE_MMIO
213#else
214#endif
215
216MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
217MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
218MODULE_LICENSE("GPL");
219
220module_param(max_interrupt_work, int, 0);
221module_param(debug, int, 0);
222module_param(rx_copybreak, int, 0);
223MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
224MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
225MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
226
227/*
228 Theory of Operation
229
230I. Board Compatibility
231
232This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
233controller.
234
235II. Board-specific settings
236
237Boards with this chip are functional only in a bus-master PCI slot.
238
239Many operational settings are loaded from the EEPROM to the Config word at
240offset 0x78. For most of these settings, this driver assumes that they are
241correct.
242If this driver is compiled to use PCI memory space operations the EEPROM
243must be configured to enable memory ops.
244
245III. Driver operation
246
247IIIa. Ring buffers
248
249This driver uses two statically allocated fixed-size descriptor lists
250formed into rings by a branch from the final descriptor to the beginning of
251the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
252
253IIIb/c. Transmit/Receive Structure
254
255This driver attempts to use a zero-copy receive and transmit scheme.
256
257Alas, all data buffers are required to start on a 32 bit boundary, so
258the driver must often copy transmit packets into bounce buffers.
259
260The driver allocates full frame size skbuffs for the Rx ring buffers at
261open() time and passes the skb->data field to the chip as receive data
262buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
263a fresh skbuff is allocated and the frame is copied to the new skbuff.
264When the incoming frame is larger, the skbuff is passed directly up the
265protocol stack. Buffers consumed this way are replaced by newly allocated
266skbuffs in the last phase of rhine_rx().
267
268The RX_COPYBREAK value is chosen to trade-off the memory wasted by
269using a full-sized skbuff for small frames vs. the copying costs of larger
270frames. New boards are typically used in generously configured machines
271and the underfilled buffers have negligible impact compared to the benefit of
272a single allocation size, so the default value of zero results in never
273copying packets. When copying is done, the cost is usually mitigated by using
274a combined copy/checksum routine. Copying also preloads the cache, which is
275most useful with small frames.
276
277Since the VIA chips are only able to transfer data to buffers on 32 bit
278boundaries, the IP header at offset 14 in an ethernet frame isn't
279longword aligned for further processing. Copying these unaligned buffers
280has the beneficial effect of 16-byte aligning the IP header.
281
282IIId. Synchronization
283
284The driver runs as two independent, single-threaded flows of control. One
285is the send-packet routine, which enforces single-threaded use by the
286dev->priv->lock spinlock. The other thread is the interrupt handler, which
287is single threaded by the hardware and interrupt handling software.
288
289The send packet thread has partial control over the Tx ring. It locks the
290dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
291is not available it stops the transmit queue by calling netif_stop_queue.
292
293The interrupt handler has exclusive control over the Rx ring and records stats
294from the Tx ring. After reaping the stats, it marks the Tx queue entry as
295empty by incrementing the dirty_tx mark. If at least half of the entries in
296the Rx ring are available the transmit queue is woken up if it was stopped.
297
298IV. Notes
299
300IVb. References
301
302Preliminary VT86C100A manual from http://www.via.com.tw/
303http://www.scyld.com/expert/100mbps.html
304http://www.scyld.com/expert/NWay.html
305ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
306ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
307
308
309IVc. Errata
310
311The VT86C100A manual is not reliable information.
312The 3043 chip does not handle unaligned transmit or receive buffers, resulting
313in significant performance degradation for bounce buffer copies on transmit
314and unaligned IP headers on receive.
315The chip does not pad to minimum transmit length.
316
317*/
318
319
320/* This table drives the PCI probe routines. It's mostly boilerplate in all
321 of the drivers, and will likely be provided by some future kernel.
322 Note the matching code -- the first table entry matchs all 56** cards but
323 second only the 1234 card.
324*/
325
326enum rhine_revs {
327 VT86C100A = 0x00,
328 VTunknown0 = 0x20,
329 VT6102 = 0x40,
330 VT8231 = 0x50, /* Integrated MAC */
331 VT8233 = 0x60, /* Integrated MAC */
332 VT8235 = 0x74, /* Integrated MAC */
333 VT8237 = 0x78, /* Integrated MAC */
334 VTunknown1 = 0x7C,
335 VT6105 = 0x80,
336 VT6105_B0 = 0x83,
337 VT6105L = 0x8A,
338 VT6107 = 0x8C,
339 VTunknown2 = 0x8E,
340 VT6105M = 0x90, /* Management adapter */
341};
342
343enum rhine_quirks {
344 rqWOL = 0x0001, /* Wake-On-LAN support */
345 rqForceReset = 0x0002,
346 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
347 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
348 rqRhineI = 0x0100, /* See comment below */
349};
350/*
351 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
352 * MMIO as well as for the collision counter and the Tx FIFO underflow
353 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
354 */
355
356/* Beware of PCI posted writes */
357#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
358
359static struct pci_device_id rhine_pci_tbl[] =
360{
361 {0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT86C100A */
362 {0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6102 */
363 {0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* 6105{,L,LOM} */
364 {0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, /* VT6105M */
365 { } /* terminate list */
366};
367MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
368
369
370/* Offsets to the device registers. */
371enum register_offsets {
372 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
373 ChipCmd1=0x09,
374 IntrStatus=0x0C, IntrEnable=0x0E,
375 MulticastFilter0=0x10, MulticastFilter1=0x14,
376 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
377 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
378 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
379 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
380 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
381 StickyHW=0x83, IntrStatus2=0x84,
382 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
383 WOLcrClr1=0xA6, WOLcgClr=0xA7,
384 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
385};
386
387/* Bits in ConfigD */
388enum backoff_bits {
389 BackOptional=0x01, BackModify=0x02,
390 BackCaptureEffect=0x04, BackRandom=0x08
391};
392
393#ifdef USE_MMIO
394/* Registers we check that mmio and reg are the same. */
395static const int mmio_verify_registers[] = {
396 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
397 0
398};
399#endif
400
401/* Bits in the interrupt status/mask registers. */
402enum intr_status_bits {
403 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
404 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
405 IntrPCIErr=0x0040,
406 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
407 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
408 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
409 IntrRxWakeUp=0x8000,
410 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
411 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
412 IntrTxErrSummary=0x082218,
413};
414
415/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
416enum wol_bits {
417 WOLucast = 0x10,
418 WOLmagic = 0x20,
419 WOLbmcast = 0x30,
420 WOLlnkon = 0x40,
421 WOLlnkoff = 0x80,
422};
423
424/* The Rx and Tx buffer descriptors. */
425struct rx_desc {
426 s32 rx_status;
427 u32 desc_length; /* Chain flag, Buffer/frame length */
428 u32 addr;
429 u32 next_desc;
430};
431struct tx_desc {
432 s32 tx_status;
433 u32 desc_length; /* Chain flag, Tx Config, Frame length */
434 u32 addr;
435 u32 next_desc;
436};
437
438/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
439#define TXDESC 0x00e08000
440
441enum rx_status_bits {
442 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
443};
444
445/* Bits in *_desc.*_status */
446enum desc_status_bits {
447 DescOwn=0x80000000
448};
449
450/* Bits in ChipCmd. */
451enum chip_cmd_bits {
452 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
453 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
454 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
455 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
456};
457
458struct rhine_private {
459 /* Descriptor rings */
460 struct rx_desc *rx_ring;
461 struct tx_desc *tx_ring;
462 dma_addr_t rx_ring_dma;
463 dma_addr_t tx_ring_dma;
464
465 /* The addresses of receive-in-place skbuffs. */
466 struct sk_buff *rx_skbuff[RX_RING_SIZE];
467 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
468
469 /* The saved address of a sent-in-place packet/buffer, for later free(). */
470 struct sk_buff *tx_skbuff[TX_RING_SIZE];
471 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
472
Roger Luethi4be5de22006-04-04 20:49:16 +0200473 /* Tx bounce buffers (Rhine-I only) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474 unsigned char *tx_buf[TX_RING_SIZE];
475 unsigned char *tx_bufs;
476 dma_addr_t tx_bufs_dma;
477
478 struct pci_dev *pdev;
479 long pioaddr;
480 struct net_device_stats stats;
481 spinlock_t lock;
482
483 /* Frequently used values: keep some adjacent for cache effect. */
484 u32 quirks;
485 struct rx_desc *rx_head_desc;
486 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
487 unsigned int cur_tx, dirty_tx;
488 unsigned int rx_buf_sz; /* Based on MTU+slack. */
489 u8 wolopts;
490
491 u8 tx_thresh, rx_thresh;
492
493 struct mii_if_info mii_if;
494 void __iomem *base;
495};
496
497static int mdio_read(struct net_device *dev, int phy_id, int location);
498static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
499static int rhine_open(struct net_device *dev);
500static void rhine_tx_timeout(struct net_device *dev);
501static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
502static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
503static void rhine_tx(struct net_device *dev);
504static void rhine_rx(struct net_device *dev);
505static void rhine_error(struct net_device *dev, int intr_status);
506static void rhine_set_rx_mode(struct net_device *dev);
507static struct net_device_stats *rhine_get_stats(struct net_device *dev);
508static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
509static struct ethtool_ops netdev_ethtool_ops;
510static int rhine_close(struct net_device *dev);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -0700511static void rhine_shutdown (struct pci_dev *pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
513#define RHINE_WAIT_FOR(condition) do { \
514 int i=1024; \
515 while (!(condition) && --i) \
516 ; \
517 if (debug > 1 && i < 512) \
518 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
519 DRV_NAME, 1024-i, __func__, __LINE__); \
520} while(0)
521
522static inline u32 get_intr_status(struct net_device *dev)
523{
524 struct rhine_private *rp = netdev_priv(dev);
525 void __iomem *ioaddr = rp->base;
526 u32 intr_status;
527
528 intr_status = ioread16(ioaddr + IntrStatus);
529 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
530 if (rp->quirks & rqStatusWBRace)
531 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
532 return intr_status;
533}
534
535/*
536 * Get power related registers into sane state.
537 * Notify user about past WOL event.
538 */
539static void rhine_power_init(struct net_device *dev)
540{
541 struct rhine_private *rp = netdev_priv(dev);
542 void __iomem *ioaddr = rp->base;
543 u16 wolstat;
544
545 if (rp->quirks & rqWOL) {
546 /* Make sure chip is in power state D0 */
547 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
548
549 /* Disable "force PME-enable" */
550 iowrite8(0x80, ioaddr + WOLcgClr);
551
552 /* Clear power-event config bits (WOL) */
553 iowrite8(0xFF, ioaddr + WOLcrClr);
554 /* More recent cards can manage two additional patterns */
555 if (rp->quirks & rq6patterns)
556 iowrite8(0x03, ioaddr + WOLcrClr1);
557
558 /* Save power-event status bits */
559 wolstat = ioread8(ioaddr + PwrcsrSet);
560 if (rp->quirks & rq6patterns)
561 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
562
563 /* Clear power-event status bits */
564 iowrite8(0xFF, ioaddr + PwrcsrClr);
565 if (rp->quirks & rq6patterns)
566 iowrite8(0x03, ioaddr + PwrcsrClr1);
567
568 if (wolstat) {
569 char *reason;
570 switch (wolstat) {
571 case WOLmagic:
572 reason = "Magic packet";
573 break;
574 case WOLlnkon:
575 reason = "Link went up";
576 break;
577 case WOLlnkoff:
578 reason = "Link went down";
579 break;
580 case WOLucast:
581 reason = "Unicast packet";
582 break;
583 case WOLbmcast:
584 reason = "Multicast/broadcast packet";
585 break;
586 default:
587 reason = "Unknown";
588 }
589 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
590 DRV_NAME, reason);
591 }
592 }
593}
594
595static void rhine_chip_reset(struct net_device *dev)
596{
597 struct rhine_private *rp = netdev_priv(dev);
598 void __iomem *ioaddr = rp->base;
599
600 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
601 IOSYNC;
602
603 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
604 printk(KERN_INFO "%s: Reset not complete yet. "
605 "Trying harder.\n", DRV_NAME);
606
607 /* Force reset */
608 if (rp->quirks & rqForceReset)
609 iowrite8(0x40, ioaddr + MiscCmd);
610
611 /* Reset can take somewhat longer (rare) */
612 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
613 }
614
615 if (debug > 1)
616 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
617 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
618 "failed" : "succeeded");
619}
620
621#ifdef USE_MMIO
622static void enable_mmio(long pioaddr, u32 quirks)
623{
624 int n;
625 if (quirks & rqRhineI) {
626 /* More recent docs say that this bit is reserved ... */
627 n = inb(pioaddr + ConfigA) | 0x20;
628 outb(n, pioaddr + ConfigA);
629 } else {
630 n = inb(pioaddr + ConfigD) | 0x80;
631 outb(n, pioaddr + ConfigD);
632 }
633}
634#endif
635
636/*
637 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
638 * (plus 0x6C for Rhine-I/II)
639 */
640static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
641{
642 struct rhine_private *rp = netdev_priv(dev);
643 void __iomem *ioaddr = rp->base;
644
645 outb(0x20, pioaddr + MACRegEEcsr);
646 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
647
648#ifdef USE_MMIO
649 /*
650 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
651 * MMIO. If reloading EEPROM was done first this could be avoided, but
652 * it is not known if that still works with the "win98-reboot" problem.
653 */
654 enable_mmio(pioaddr, rp->quirks);
655#endif
656
657 /* Turn off EEPROM-controlled wake-up (magic packet) */
658 if (rp->quirks & rqWOL)
659 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
660
661}
662
663#ifdef CONFIG_NET_POLL_CONTROLLER
664static void rhine_poll(struct net_device *dev)
665{
666 disable_irq(dev->irq);
667 rhine_interrupt(dev->irq, (void *)dev, NULL);
668 enable_irq(dev->irq);
669}
670#endif
671
672static void rhine_hw_init(struct net_device *dev, long pioaddr)
673{
674 struct rhine_private *rp = netdev_priv(dev);
675
676 /* Reset the chip to erase previous misconfiguration. */
677 rhine_chip_reset(dev);
678
679 /* Rhine-I needs extra time to recuperate before EEPROM reload */
680 if (rp->quirks & rqRhineI)
681 msleep(5);
682
683 /* Reload EEPROM controlled bytes cleared by soft reset */
684 rhine_reload_eeprom(pioaddr, dev);
685}
686
687static int __devinit rhine_init_one(struct pci_dev *pdev,
688 const struct pci_device_id *ent)
689{
690 struct net_device *dev;
691 struct rhine_private *rp;
692 int i, rc;
693 u8 pci_rev;
694 u32 quirks;
695 long pioaddr;
696 long memaddr;
697 void __iomem *ioaddr;
698 int io_size, phy_id;
699 const char *name;
700#ifdef USE_MMIO
701 int bar = 1;
702#else
703 int bar = 0;
704#endif
705
706/* when built into the kernel, we only print version if device is found */
707#ifndef MODULE
708 static int printed_version;
709 if (!printed_version++)
710 printk(version);
711#endif
712
713 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
714
715 io_size = 256;
716 phy_id = 0;
717 quirks = 0;
718 name = "Rhine";
719 if (pci_rev < VTunknown0) {
720 quirks = rqRhineI;
721 io_size = 128;
722 }
723 else if (pci_rev >= VT6102) {
724 quirks = rqWOL | rqForceReset;
725 if (pci_rev < VT6105) {
726 name = "Rhine II";
727 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
728 }
729 else {
730 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
731 if (pci_rev >= VT6105_B0)
732 quirks |= rq6patterns;
733 if (pci_rev < VT6105M)
734 name = "Rhine III";
735 else
736 name = "Rhine III (Management Adapter)";
737 }
738 }
739
740 rc = pci_enable_device(pdev);
741 if (rc)
742 goto err_out;
743
744 /* this should always be supported */
Domen Puncer1e7f0bd2005-06-26 18:22:14 -0400745 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746 if (rc) {
747 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
748 "the card!?\n");
749 goto err_out;
750 }
751
752 /* sanity check */
753 if ((pci_resource_len(pdev, 0) < io_size) ||
754 (pci_resource_len(pdev, 1) < io_size)) {
755 rc = -EIO;
756 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
757 goto err_out;
758 }
759
760 pioaddr = pci_resource_start(pdev, 0);
761 memaddr = pci_resource_start(pdev, 1);
762
763 pci_set_master(pdev);
764
765 dev = alloc_etherdev(sizeof(struct rhine_private));
766 if (!dev) {
767 rc = -ENOMEM;
768 printk(KERN_ERR "alloc_etherdev failed\n");
769 goto err_out;
770 }
771 SET_MODULE_OWNER(dev);
772 SET_NETDEV_DEV(dev, &pdev->dev);
773
774 rp = netdev_priv(dev);
775 rp->quirks = quirks;
776 rp->pioaddr = pioaddr;
777 rp->pdev = pdev;
778
779 rc = pci_request_regions(pdev, DRV_NAME);
780 if (rc)
781 goto err_out_free_netdev;
782
783 ioaddr = pci_iomap(pdev, bar, io_size);
784 if (!ioaddr) {
785 rc = -EIO;
786 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
787 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
788 goto err_out_free_res;
789 }
790
791#ifdef USE_MMIO
792 enable_mmio(pioaddr, quirks);
793
794 /* Check that selected MMIO registers match the PIO ones */
795 i = 0;
796 while (mmio_verify_registers[i]) {
797 int reg = mmio_verify_registers[i++];
798 unsigned char a = inb(pioaddr+reg);
799 unsigned char b = readb(ioaddr+reg);
800 if (a != b) {
801 rc = -EIO;
802 printk(KERN_ERR "MMIO do not match PIO [%02x] "
803 "(%02x != %02x)\n", reg, a, b);
804 goto err_out_unmap;
805 }
806 }
807#endif /* USE_MMIO */
808
809 dev->base_addr = (unsigned long)ioaddr;
810 rp->base = ioaddr;
811
812 /* Get chip registers into a sane state */
813 rhine_power_init(dev);
814 rhine_hw_init(dev, pioaddr);
815
816 for (i = 0; i < 6; i++)
817 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400818 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819
John W. Linvilleb81e8e12005-09-12 10:48:58 -0400820 if (!is_valid_ether_addr(dev->perm_addr)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821 rc = -EIO;
822 printk(KERN_ERR "Invalid MAC address\n");
823 goto err_out_unmap;
824 }
825
826 /* For Rhine-I/II, phy_id is loaded from EEPROM */
827 if (!phy_id)
828 phy_id = ioread8(ioaddr + 0x6C);
829
830 dev->irq = pdev->irq;
831
832 spin_lock_init(&rp->lock);
833 rp->mii_if.dev = dev;
834 rp->mii_if.mdio_read = mdio_read;
835 rp->mii_if.mdio_write = mdio_write;
836 rp->mii_if.phy_id_mask = 0x1f;
837 rp->mii_if.reg_num_mask = 0x1f;
838
839 /* The chip-specific entries in the device structure. */
840 dev->open = rhine_open;
841 dev->hard_start_xmit = rhine_start_tx;
842 dev->stop = rhine_close;
843 dev->get_stats = rhine_get_stats;
844 dev->set_multicast_list = rhine_set_rx_mode;
845 dev->do_ioctl = netdev_ioctl;
846 dev->ethtool_ops = &netdev_ethtool_ops;
847 dev->tx_timeout = rhine_tx_timeout;
848 dev->watchdog_timeo = TX_TIMEOUT;
849#ifdef CONFIG_NET_POLL_CONTROLLER
850 dev->poll_controller = rhine_poll;
851#endif
852 if (rp->quirks & rqRhineI)
853 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
854
855 /* dev->name not defined before register_netdev()! */
856 rc = register_netdev(dev);
857 if (rc)
858 goto err_out_unmap;
859
860 printk(KERN_INFO "%s: VIA %s at 0x%lx, ",
861 dev->name, name,
862#ifdef USE_MMIO
863 memaddr
864#else
865 (long)ioaddr
866#endif
867 );
868
869 for (i = 0; i < 5; i++)
870 printk("%2.2x:", dev->dev_addr[i]);
871 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], pdev->irq);
872
873 pci_set_drvdata(pdev, dev);
874
875 {
876 u16 mii_cmd;
877 int mii_status = mdio_read(dev, phy_id, 1);
878 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
879 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
880 if (mii_status != 0xffff && mii_status != 0x0000) {
881 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
882 printk(KERN_INFO "%s: MII PHY found at address "
883 "%d, status 0x%4.4x advertising %4.4x "
884 "Link %4.4x.\n", dev->name, phy_id,
885 mii_status, rp->mii_if.advertising,
886 mdio_read(dev, phy_id, 5));
887
888 /* set IFF_RUNNING */
889 if (mii_status & BMSR_LSTATUS)
890 netif_carrier_on(dev);
891 else
892 netif_carrier_off(dev);
893
894 }
895 }
896 rp->mii_if.phy_id = phy_id;
897
898 return 0;
899
900err_out_unmap:
901 pci_iounmap(pdev, ioaddr);
902err_out_free_res:
903 pci_release_regions(pdev);
904err_out_free_netdev:
905 free_netdev(dev);
906err_out:
907 return rc;
908}
909
910static int alloc_ring(struct net_device* dev)
911{
912 struct rhine_private *rp = netdev_priv(dev);
913 void *ring;
914 dma_addr_t ring_dma;
915
916 ring = pci_alloc_consistent(rp->pdev,
917 RX_RING_SIZE * sizeof(struct rx_desc) +
918 TX_RING_SIZE * sizeof(struct tx_desc),
919 &ring_dma);
920 if (!ring) {
921 printk(KERN_ERR "Could not allocate DMA memory.\n");
922 return -ENOMEM;
923 }
924 if (rp->quirks & rqRhineI) {
925 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
926 PKT_BUF_SZ * TX_RING_SIZE,
927 &rp->tx_bufs_dma);
928 if (rp->tx_bufs == NULL) {
929 pci_free_consistent(rp->pdev,
930 RX_RING_SIZE * sizeof(struct rx_desc) +
931 TX_RING_SIZE * sizeof(struct tx_desc),
932 ring, ring_dma);
933 return -ENOMEM;
934 }
935 }
936
937 rp->rx_ring = ring;
938 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
939 rp->rx_ring_dma = ring_dma;
940 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
941
942 return 0;
943}
944
945static void free_ring(struct net_device* dev)
946{
947 struct rhine_private *rp = netdev_priv(dev);
948
949 pci_free_consistent(rp->pdev,
950 RX_RING_SIZE * sizeof(struct rx_desc) +
951 TX_RING_SIZE * sizeof(struct tx_desc),
952 rp->rx_ring, rp->rx_ring_dma);
953 rp->tx_ring = NULL;
954
955 if (rp->tx_bufs)
956 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
957 rp->tx_bufs, rp->tx_bufs_dma);
958
959 rp->tx_bufs = NULL;
960
961}
962
963static void alloc_rbufs(struct net_device *dev)
964{
965 struct rhine_private *rp = netdev_priv(dev);
966 dma_addr_t next;
967 int i;
968
969 rp->dirty_rx = rp->cur_rx = 0;
970
971 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
972 rp->rx_head_desc = &rp->rx_ring[0];
973 next = rp->rx_ring_dma;
974
975 /* Init the ring entries */
976 for (i = 0; i < RX_RING_SIZE; i++) {
977 rp->rx_ring[i].rx_status = 0;
978 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
979 next += sizeof(struct rx_desc);
980 rp->rx_ring[i].next_desc = cpu_to_le32(next);
981 rp->rx_skbuff[i] = NULL;
982 }
983 /* Mark the last entry as wrapping the ring. */
984 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
985
986 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
987 for (i = 0; i < RX_RING_SIZE; i++) {
988 struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz);
989 rp->rx_skbuff[i] = skb;
990 if (skb == NULL)
991 break;
992 skb->dev = dev; /* Mark as being used by this device. */
993
994 rp->rx_skbuff_dma[i] =
David S. Miller689be432005-06-28 15:25:31 -0700995 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996 PCI_DMA_FROMDEVICE);
997
998 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
999 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
1000 }
1001 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1002}
1003
1004static void free_rbufs(struct net_device* dev)
1005{
1006 struct rhine_private *rp = netdev_priv(dev);
1007 int i;
1008
1009 /* Free all the skbuffs in the Rx queue. */
1010 for (i = 0; i < RX_RING_SIZE; i++) {
1011 rp->rx_ring[i].rx_status = 0;
1012 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1013 if (rp->rx_skbuff[i]) {
1014 pci_unmap_single(rp->pdev,
1015 rp->rx_skbuff_dma[i],
1016 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1017 dev_kfree_skb(rp->rx_skbuff[i]);
1018 }
1019 rp->rx_skbuff[i] = NULL;
1020 }
1021}
1022
1023static void alloc_tbufs(struct net_device* dev)
1024{
1025 struct rhine_private *rp = netdev_priv(dev);
1026 dma_addr_t next;
1027 int i;
1028
1029 rp->dirty_tx = rp->cur_tx = 0;
1030 next = rp->tx_ring_dma;
1031 for (i = 0; i < TX_RING_SIZE; i++) {
1032 rp->tx_skbuff[i] = NULL;
1033 rp->tx_ring[i].tx_status = 0;
1034 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1035 next += sizeof(struct tx_desc);
1036 rp->tx_ring[i].next_desc = cpu_to_le32(next);
Roger Luethi4be5de22006-04-04 20:49:16 +02001037 if (rp->quirks & rqRhineI)
1038 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001039 }
1040 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
1041
1042}
1043
1044static void free_tbufs(struct net_device* dev)
1045{
1046 struct rhine_private *rp = netdev_priv(dev);
1047 int i;
1048
1049 for (i = 0; i < TX_RING_SIZE; i++) {
1050 rp->tx_ring[i].tx_status = 0;
1051 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
1052 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1053 if (rp->tx_skbuff[i]) {
1054 if (rp->tx_skbuff_dma[i]) {
1055 pci_unmap_single(rp->pdev,
1056 rp->tx_skbuff_dma[i],
1057 rp->tx_skbuff[i]->len,
1058 PCI_DMA_TODEVICE);
1059 }
1060 dev_kfree_skb(rp->tx_skbuff[i]);
1061 }
1062 rp->tx_skbuff[i] = NULL;
1063 rp->tx_buf[i] = NULL;
1064 }
1065}
1066
1067static void rhine_check_media(struct net_device *dev, unsigned int init_media)
1068{
1069 struct rhine_private *rp = netdev_priv(dev);
1070 void __iomem *ioaddr = rp->base;
1071
1072 mii_check_media(&rp->mii_if, debug, init_media);
1073
1074 if (rp->mii_if.full_duplex)
1075 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1076 ioaddr + ChipCmd1);
1077 else
1078 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1079 ioaddr + ChipCmd1);
Roger Luethi00b428c2006-03-28 20:53:56 +02001080 if (debug > 1)
1081 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1082 rp->mii_if.force_media, netif_carrier_ok(dev));
1083}
1084
1085/* Called after status of force_media possibly changed */
Adrian Bunk0761be42006-04-10 23:22:21 -07001086static void rhine_set_carrier(struct mii_if_info *mii)
Roger Luethi00b428c2006-03-28 20:53:56 +02001087{
1088 if (mii->force_media) {
1089 /* autoneg is off: Link is always assumed to be up */
1090 if (!netif_carrier_ok(mii->dev))
1091 netif_carrier_on(mii->dev);
1092 }
1093 else /* Let MMI library update carrier status */
1094 rhine_check_media(mii->dev, 0);
1095 if (debug > 1)
1096 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1097 mii->dev->name, mii->force_media,
1098 netif_carrier_ok(mii->dev));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099}
1100
1101static void init_registers(struct net_device *dev)
1102{
1103 struct rhine_private *rp = netdev_priv(dev);
1104 void __iomem *ioaddr = rp->base;
1105 int i;
1106
1107 for (i = 0; i < 6; i++)
1108 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1109
1110 /* Initialize other registers. */
1111 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1112 /* Configure initial FIFO thresholds. */
1113 iowrite8(0x20, ioaddr + TxConfig);
1114 rp->tx_thresh = 0x20;
1115 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1116
1117 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1118 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1119
1120 rhine_set_rx_mode(dev);
1121
1122 /* Enable interrupts by setting the interrupt mask. */
1123 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1124 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1125 IntrTxDone | IntrTxError | IntrTxUnderrun |
1126 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1127 ioaddr + IntrEnable);
1128
1129 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1130 ioaddr + ChipCmd);
1131 rhine_check_media(dev, 1);
1132}
1133
1134/* Enable MII link status auto-polling (required for IntrLinkChange) */
1135static void rhine_enable_linkmon(void __iomem *ioaddr)
1136{
1137 iowrite8(0, ioaddr + MIICmd);
1138 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1139 iowrite8(0x80, ioaddr + MIICmd);
1140
1141 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1142
1143 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1144}
1145
1146/* Disable MII link status auto-polling (required for MDIO access) */
1147static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1148{
1149 iowrite8(0, ioaddr + MIICmd);
1150
1151 if (quirks & rqRhineI) {
1152 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1153
John W. Linville38bb6b22006-05-19 10:51:21 -04001154 /* Can be called from ISR. Evil. */
1155 mdelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156
1157 /* 0x80 must be set immediately before turning it off */
1158 iowrite8(0x80, ioaddr + MIICmd);
1159
1160 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1161
1162 /* Heh. Now clear 0x80 again. */
1163 iowrite8(0, ioaddr + MIICmd);
1164 }
1165 else
1166 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1167}
1168
1169/* Read and write over the MII Management Data I/O (MDIO) interface. */
1170
1171static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1172{
1173 struct rhine_private *rp = netdev_priv(dev);
1174 void __iomem *ioaddr = rp->base;
1175 int result;
1176
1177 rhine_disable_linkmon(ioaddr, rp->quirks);
1178
1179 /* rhine_disable_linkmon already cleared MIICmd */
1180 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1181 iowrite8(regnum, ioaddr + MIIRegAddr);
1182 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1183 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1184 result = ioread16(ioaddr + MIIData);
1185
1186 rhine_enable_linkmon(ioaddr);
1187 return result;
1188}
1189
1190static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1191{
1192 struct rhine_private *rp = netdev_priv(dev);
1193 void __iomem *ioaddr = rp->base;
1194
1195 rhine_disable_linkmon(ioaddr, rp->quirks);
1196
1197 /* rhine_disable_linkmon already cleared MIICmd */
1198 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1199 iowrite8(regnum, ioaddr + MIIRegAddr);
1200 iowrite16(value, ioaddr + MIIData);
1201 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1202 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1203
1204 rhine_enable_linkmon(ioaddr);
1205}
1206
1207static int rhine_open(struct net_device *dev)
1208{
1209 struct rhine_private *rp = netdev_priv(dev);
1210 void __iomem *ioaddr = rp->base;
1211 int rc;
1212
1213 rc = request_irq(rp->pdev->irq, &rhine_interrupt, SA_SHIRQ, dev->name,
1214 dev);
1215 if (rc)
1216 return rc;
1217
1218 if (debug > 1)
1219 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1220 dev->name, rp->pdev->irq);
1221
1222 rc = alloc_ring(dev);
1223 if (rc) {
1224 free_irq(rp->pdev->irq, dev);
1225 return rc;
1226 }
1227 alloc_rbufs(dev);
1228 alloc_tbufs(dev);
1229 rhine_chip_reset(dev);
1230 init_registers(dev);
1231 if (debug > 2)
1232 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1233 "MII status: %4.4x.\n",
1234 dev->name, ioread16(ioaddr + ChipCmd),
1235 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1236
1237 netif_start_queue(dev);
1238
1239 return 0;
1240}
1241
1242static void rhine_tx_timeout(struct net_device *dev)
1243{
1244 struct rhine_private *rp = netdev_priv(dev);
1245 void __iomem *ioaddr = rp->base;
1246
1247 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1248 "%4.4x, resetting...\n",
1249 dev->name, ioread16(ioaddr + IntrStatus),
1250 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1251
1252 /* protect against concurrent rx interrupts */
1253 disable_irq(rp->pdev->irq);
1254
1255 spin_lock(&rp->lock);
1256
1257 /* clear all descriptors */
1258 free_tbufs(dev);
1259 free_rbufs(dev);
1260 alloc_tbufs(dev);
1261 alloc_rbufs(dev);
1262
1263 /* Reinitialize the hardware. */
1264 rhine_chip_reset(dev);
1265 init_registers(dev);
1266
1267 spin_unlock(&rp->lock);
1268 enable_irq(rp->pdev->irq);
1269
1270 dev->trans_start = jiffies;
1271 rp->stats.tx_errors++;
1272 netif_wake_queue(dev);
1273}
1274
1275static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1276{
1277 struct rhine_private *rp = netdev_priv(dev);
1278 void __iomem *ioaddr = rp->base;
1279 unsigned entry;
1280
1281 /* Caution: the write order is important here, set the field
1282 with the "ownership" bits last. */
1283
1284 /* Calculate the next Tx descriptor entry. */
1285 entry = rp->cur_tx % TX_RING_SIZE;
1286
1287 if (skb->len < ETH_ZLEN) {
1288 skb = skb_padto(skb, ETH_ZLEN);
1289 if (skb == NULL)
1290 return 0;
1291 }
1292
1293 rp->tx_skbuff[entry] = skb;
1294
1295 if ((rp->quirks & rqRhineI) &&
1296 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_HW)) {
1297 /* Must use alignment buffer. */
1298 if (skb->len > PKT_BUF_SZ) {
1299 /* packet too long, drop it */
1300 dev_kfree_skb(skb);
1301 rp->tx_skbuff[entry] = NULL;
1302 rp->stats.tx_dropped++;
1303 return 0;
1304 }
Craig Brind3e0d1672006-04-27 02:30:46 -07001305
1306 /* Padding is not copied and so must be redone. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
Craig Brind3e0d1672006-04-27 02:30:46 -07001308 if (skb->len < ETH_ZLEN)
1309 memset(rp->tx_buf[entry] + skb->len, 0,
1310 ETH_ZLEN - skb->len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311 rp->tx_skbuff_dma[entry] = 0;
1312 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1313 (rp->tx_buf[entry] -
1314 rp->tx_bufs));
1315 } else {
1316 rp->tx_skbuff_dma[entry] =
1317 pci_map_single(rp->pdev, skb->data, skb->len,
1318 PCI_DMA_TODEVICE);
1319 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1320 }
1321
1322 rp->tx_ring[entry].desc_length =
1323 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1324
1325 /* lock eth irq */
1326 spin_lock_irq(&rp->lock);
1327 wmb();
1328 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1329 wmb();
1330
1331 rp->cur_tx++;
1332
1333 /* Non-x86 Todo: explicitly flush cache lines here. */
1334
1335 /* Wake the potentially-idle transmit channel */
1336 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1337 ioaddr + ChipCmd1);
1338 IOSYNC;
1339
1340 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1341 netif_stop_queue(dev);
1342
1343 dev->trans_start = jiffies;
1344
1345 spin_unlock_irq(&rp->lock);
1346
1347 if (debug > 4) {
1348 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1349 dev->name, rp->cur_tx-1, entry);
1350 }
1351 return 0;
1352}
1353
1354/* The interrupt handler does all of the Rx thread work and cleans up
1355 after the Tx thread. */
1356static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1357{
1358 struct net_device *dev = dev_instance;
1359 struct rhine_private *rp = netdev_priv(dev);
1360 void __iomem *ioaddr = rp->base;
1361 u32 intr_status;
1362 int boguscnt = max_interrupt_work;
1363 int handled = 0;
1364
1365 while ((intr_status = get_intr_status(dev))) {
1366 handled = 1;
1367
1368 /* Acknowledge all of the current interrupt sources ASAP. */
1369 if (intr_status & IntrTxDescRace)
1370 iowrite8(0x08, ioaddr + IntrStatus2);
1371 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1372 IOSYNC;
1373
1374 if (debug > 4)
1375 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1376 dev->name, intr_status);
1377
1378 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1379 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf))
1380 rhine_rx(dev);
1381
1382 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1383 if (intr_status & IntrTxErrSummary) {
1384 /* Avoid scavenging before Tx engine turned off */
1385 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1386 if (debug > 2 &&
1387 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1388 printk(KERN_WARNING "%s: "
1389 "rhine_interrupt() Tx engine"
1390 "still on.\n", dev->name);
1391 }
1392 rhine_tx(dev);
1393 }
1394
1395 /* Abnormal error summary/uncommon events handlers. */
1396 if (intr_status & (IntrPCIErr | IntrLinkChange |
1397 IntrStatsMax | IntrTxError | IntrTxAborted |
1398 IntrTxUnderrun | IntrTxDescRace))
1399 rhine_error(dev, intr_status);
1400
1401 if (--boguscnt < 0) {
1402 printk(KERN_WARNING "%s: Too much work at interrupt, "
1403 "status=%#8.8x.\n",
1404 dev->name, intr_status);
1405 break;
1406 }
1407 }
1408
1409 if (debug > 3)
1410 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1411 dev->name, ioread16(ioaddr + IntrStatus));
1412 return IRQ_RETVAL(handled);
1413}
1414
1415/* This routine is logically part of the interrupt handler, but isolated
1416 for clarity. */
1417static void rhine_tx(struct net_device *dev)
1418{
1419 struct rhine_private *rp = netdev_priv(dev);
1420 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1421
1422 spin_lock(&rp->lock);
1423
1424 /* find and cleanup dirty tx descriptors */
1425 while (rp->dirty_tx != rp->cur_tx) {
1426 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1427 if (debug > 6)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001428 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429 entry, txstatus);
1430 if (txstatus & DescOwn)
1431 break;
1432 if (txstatus & 0x8000) {
1433 if (debug > 1)
1434 printk(KERN_DEBUG "%s: Transmit error, "
1435 "Tx status %8.8x.\n",
1436 dev->name, txstatus);
1437 rp->stats.tx_errors++;
1438 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1439 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1440 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1441 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1442 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1443 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1444 rp->stats.tx_fifo_errors++;
1445 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1446 break; /* Keep the skb - we try again */
1447 }
1448 /* Transmitter restarted in 'abnormal' handler. */
1449 } else {
1450 if (rp->quirks & rqRhineI)
1451 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1452 else
1453 rp->stats.collisions += txstatus & 0x0F;
1454 if (debug > 6)
1455 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1456 (txstatus >> 3) & 0xF,
1457 txstatus & 0xF);
1458 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1459 rp->stats.tx_packets++;
1460 }
1461 /* Free the original skb. */
1462 if (rp->tx_skbuff_dma[entry]) {
1463 pci_unmap_single(rp->pdev,
1464 rp->tx_skbuff_dma[entry],
1465 rp->tx_skbuff[entry]->len,
1466 PCI_DMA_TODEVICE);
1467 }
1468 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1469 rp->tx_skbuff[entry] = NULL;
1470 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1471 }
1472 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1473 netif_wake_queue(dev);
1474
1475 spin_unlock(&rp->lock);
1476}
1477
1478/* This routine is logically part of the interrupt handler, but isolated
1479 for clarity and better register allocation. */
1480static void rhine_rx(struct net_device *dev)
1481{
1482 struct rhine_private *rp = netdev_priv(dev);
1483 int entry = rp->cur_rx % RX_RING_SIZE;
1484 int boguscnt = rp->dirty_rx + RX_RING_SIZE - rp->cur_rx;
1485
1486 if (debug > 4) {
1487 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1488 dev->name, entry,
1489 le32_to_cpu(rp->rx_head_desc->rx_status));
1490 }
1491
1492 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1493 while (!(rp->rx_head_desc->rx_status & cpu_to_le32(DescOwn))) {
1494 struct rx_desc *desc = rp->rx_head_desc;
1495 u32 desc_status = le32_to_cpu(desc->rx_status);
1496 int data_size = desc_status >> 16;
1497
1498 if (debug > 4)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001499 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500 desc_status);
1501 if (--boguscnt < 0)
1502 break;
1503 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1504 if ((desc_status & RxWholePkt) != RxWholePkt) {
1505 printk(KERN_WARNING "%s: Oversized Ethernet "
1506 "frame spanned multiple buffers, entry "
1507 "%#x length %d status %8.8x!\n",
1508 dev->name, entry, data_size,
1509 desc_status);
1510 printk(KERN_WARNING "%s: Oversized Ethernet "
1511 "frame %p vs %p.\n", dev->name,
1512 rp->rx_head_desc, &rp->rx_ring[entry]);
1513 rp->stats.rx_length_errors++;
1514 } else if (desc_status & RxErr) {
1515 /* There was a error. */
1516 if (debug > 2)
Denis Vlasenkoed4030d2005-06-17 08:23:17 +03001517 printk(KERN_DEBUG "rhine_rx() Rx "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001518 "error was %8.8x.\n",
1519 desc_status);
1520 rp->stats.rx_errors++;
1521 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1522 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1523 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1524 if (desc_status & 0x0002) {
1525 /* this can also be updated outside the interrupt handler */
1526 spin_lock(&rp->lock);
1527 rp->stats.rx_crc_errors++;
1528 spin_unlock(&rp->lock);
1529 }
1530 }
1531 } else {
1532 struct sk_buff *skb;
1533 /* Length should omit the CRC */
1534 int pkt_len = data_size - 4;
1535
1536 /* Check if the packet is long enough to accept without
1537 copying to a minimally-sized skbuff. */
1538 if (pkt_len < rx_copybreak &&
1539 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1540 skb->dev = dev;
1541 skb_reserve(skb, 2); /* 16 byte align the IP header */
1542 pci_dma_sync_single_for_cpu(rp->pdev,
1543 rp->rx_skbuff_dma[entry],
1544 rp->rx_buf_sz,
1545 PCI_DMA_FROMDEVICE);
1546
1547 eth_copy_and_sum(skb,
David S. Miller689be432005-06-28 15:25:31 -07001548 rp->rx_skbuff[entry]->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001549 pkt_len, 0);
1550 skb_put(skb, pkt_len);
1551 pci_dma_sync_single_for_device(rp->pdev,
1552 rp->rx_skbuff_dma[entry],
1553 rp->rx_buf_sz,
1554 PCI_DMA_FROMDEVICE);
1555 } else {
1556 skb = rp->rx_skbuff[entry];
1557 if (skb == NULL) {
1558 printk(KERN_ERR "%s: Inconsistent Rx "
1559 "descriptor chain.\n",
1560 dev->name);
1561 break;
1562 }
1563 rp->rx_skbuff[entry] = NULL;
1564 skb_put(skb, pkt_len);
1565 pci_unmap_single(rp->pdev,
1566 rp->rx_skbuff_dma[entry],
1567 rp->rx_buf_sz,
1568 PCI_DMA_FROMDEVICE);
1569 }
1570 skb->protocol = eth_type_trans(skb, dev);
1571 netif_rx(skb);
1572 dev->last_rx = jiffies;
1573 rp->stats.rx_bytes += pkt_len;
1574 rp->stats.rx_packets++;
1575 }
1576 entry = (++rp->cur_rx) % RX_RING_SIZE;
1577 rp->rx_head_desc = &rp->rx_ring[entry];
1578 }
1579
1580 /* Refill the Rx ring buffers. */
1581 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1582 struct sk_buff *skb;
1583 entry = rp->dirty_rx % RX_RING_SIZE;
1584 if (rp->rx_skbuff[entry] == NULL) {
1585 skb = dev_alloc_skb(rp->rx_buf_sz);
1586 rp->rx_skbuff[entry] = skb;
1587 if (skb == NULL)
1588 break; /* Better luck next round. */
1589 skb->dev = dev; /* Mark as being used by this device. */
1590 rp->rx_skbuff_dma[entry] =
David S. Miller689be432005-06-28 15:25:31 -07001591 pci_map_single(rp->pdev, skb->data,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001592 rp->rx_buf_sz,
1593 PCI_DMA_FROMDEVICE);
1594 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1595 }
1596 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1597 }
1598}
1599
1600/*
1601 * Clears the "tally counters" for CRC errors and missed frames(?).
1602 * It has been reported that some chips need a write of 0 to clear
1603 * these, for others the counters are set to 1 when written to and
1604 * instead cleared when read. So we clear them both ways ...
1605 */
1606static inline void clear_tally_counters(void __iomem *ioaddr)
1607{
1608 iowrite32(0, ioaddr + RxMissed);
1609 ioread16(ioaddr + RxCRCErrs);
1610 ioread16(ioaddr + RxMissed);
1611}
1612
1613static void rhine_restart_tx(struct net_device *dev) {
1614 struct rhine_private *rp = netdev_priv(dev);
1615 void __iomem *ioaddr = rp->base;
1616 int entry = rp->dirty_tx % TX_RING_SIZE;
1617 u32 intr_status;
1618
1619 /*
1620 * If new errors occured, we need to sort them out before doing Tx.
1621 * In that case the ISR will be back here RSN anyway.
1622 */
1623 intr_status = get_intr_status(dev);
1624
1625 if ((intr_status & IntrTxErrSummary) == 0) {
1626
1627 /* We know better than the chip where it should continue. */
1628 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1629 ioaddr + TxRingPtr);
1630
1631 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1632 ioaddr + ChipCmd);
1633 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1634 ioaddr + ChipCmd1);
1635 IOSYNC;
1636 }
1637 else {
1638 /* This should never happen */
1639 if (debug > 1)
1640 printk(KERN_WARNING "%s: rhine_restart_tx() "
1641 "Another error occured %8.8x.\n",
1642 dev->name, intr_status);
1643 }
1644
1645}
1646
1647static void rhine_error(struct net_device *dev, int intr_status)
1648{
1649 struct rhine_private *rp = netdev_priv(dev);
1650 void __iomem *ioaddr = rp->base;
1651
1652 spin_lock(&rp->lock);
1653
1654 if (intr_status & IntrLinkChange)
John W. Linville38bb6b22006-05-19 10:51:21 -04001655 rhine_check_media(dev, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656 if (intr_status & IntrStatsMax) {
1657 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1658 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1659 clear_tally_counters(ioaddr);
1660 }
1661 if (intr_status & IntrTxAborted) {
1662 if (debug > 1)
1663 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1664 dev->name, intr_status);
1665 }
1666 if (intr_status & IntrTxUnderrun) {
1667 if (rp->tx_thresh < 0xE0)
1668 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1669 if (debug > 1)
1670 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1671 "threshold now %2.2x.\n",
1672 dev->name, rp->tx_thresh);
1673 }
1674 if (intr_status & IntrTxDescRace) {
1675 if (debug > 2)
1676 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1677 dev->name);
1678 }
1679 if ((intr_status & IntrTxError) &&
1680 (intr_status & (IntrTxAborted |
1681 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1682 if (rp->tx_thresh < 0xE0) {
1683 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1684 }
1685 if (debug > 1)
1686 printk(KERN_INFO "%s: Unspecified error. Tx "
1687 "threshold now %2.2x.\n",
1688 dev->name, rp->tx_thresh);
1689 }
1690 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1691 IntrTxError))
1692 rhine_restart_tx(dev);
1693
1694 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1695 IntrTxError | IntrTxAborted | IntrNormalSummary |
1696 IntrTxDescRace)) {
1697 if (debug > 1)
1698 printk(KERN_ERR "%s: Something Wicked happened! "
1699 "%8.8x.\n", dev->name, intr_status);
1700 }
1701
1702 spin_unlock(&rp->lock);
1703}
1704
1705static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1706{
1707 struct rhine_private *rp = netdev_priv(dev);
1708 void __iomem *ioaddr = rp->base;
1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&rp->lock, flags);
1712 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1713 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1714 clear_tally_counters(ioaddr);
1715 spin_unlock_irqrestore(&rp->lock, flags);
1716
1717 return &rp->stats;
1718}
1719
1720static void rhine_set_rx_mode(struct net_device *dev)
1721{
1722 struct rhine_private *rp = netdev_priv(dev);
1723 void __iomem *ioaddr = rp->base;
1724 u32 mc_filter[2]; /* Multicast hash filter */
1725 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1726
1727 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1728 /* Unconditionally log net taps. */
1729 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1730 dev->name);
1731 rx_mode = 0x1C;
1732 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1733 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1734 } else if ((dev->mc_count > multicast_filter_limit)
1735 || (dev->flags & IFF_ALLMULTI)) {
1736 /* Too many to match, or accept all multicasts. */
1737 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1738 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1739 rx_mode = 0x0C;
1740 } else {
1741 struct dev_mc_list *mclist;
1742 int i;
1743 memset(mc_filter, 0, sizeof(mc_filter));
1744 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1745 i++, mclist = mclist->next) {
1746 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1747
1748 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1749 }
1750 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1751 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1752 rx_mode = 0x0C;
1753 }
1754 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1755}
1756
1757static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1758{
1759 struct rhine_private *rp = netdev_priv(dev);
1760
1761 strcpy(info->driver, DRV_NAME);
1762 strcpy(info->version, DRV_VERSION);
1763 strcpy(info->bus_info, pci_name(rp->pdev));
1764}
1765
1766static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1767{
1768 struct rhine_private *rp = netdev_priv(dev);
1769 int rc;
1770
1771 spin_lock_irq(&rp->lock);
1772 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1773 spin_unlock_irq(&rp->lock);
1774
1775 return rc;
1776}
1777
1778static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1779{
1780 struct rhine_private *rp = netdev_priv(dev);
1781 int rc;
1782
1783 spin_lock_irq(&rp->lock);
1784 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1785 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001786 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787
1788 return rc;
1789}
1790
1791static int netdev_nway_reset(struct net_device *dev)
1792{
1793 struct rhine_private *rp = netdev_priv(dev);
1794
1795 return mii_nway_restart(&rp->mii_if);
1796}
1797
1798static u32 netdev_get_link(struct net_device *dev)
1799{
1800 struct rhine_private *rp = netdev_priv(dev);
1801
1802 return mii_link_ok(&rp->mii_if);
1803}
1804
1805static u32 netdev_get_msglevel(struct net_device *dev)
1806{
1807 return debug;
1808}
1809
1810static void netdev_set_msglevel(struct net_device *dev, u32 value)
1811{
1812 debug = value;
1813}
1814
1815static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1816{
1817 struct rhine_private *rp = netdev_priv(dev);
1818
1819 if (!(rp->quirks & rqWOL))
1820 return;
1821
1822 spin_lock_irq(&rp->lock);
1823 wol->supported = WAKE_PHY | WAKE_MAGIC |
1824 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1825 wol->wolopts = rp->wolopts;
1826 spin_unlock_irq(&rp->lock);
1827}
1828
1829static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1830{
1831 struct rhine_private *rp = netdev_priv(dev);
1832 u32 support = WAKE_PHY | WAKE_MAGIC |
1833 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1834
1835 if (!(rp->quirks & rqWOL))
1836 return -EINVAL;
1837
1838 if (wol->wolopts & ~support)
1839 return -EINVAL;
1840
1841 spin_lock_irq(&rp->lock);
1842 rp->wolopts = wol->wolopts;
1843 spin_unlock_irq(&rp->lock);
1844
1845 return 0;
1846}
1847
1848static struct ethtool_ops netdev_ethtool_ops = {
1849 .get_drvinfo = netdev_get_drvinfo,
1850 .get_settings = netdev_get_settings,
1851 .set_settings = netdev_set_settings,
1852 .nway_reset = netdev_nway_reset,
1853 .get_link = netdev_get_link,
1854 .get_msglevel = netdev_get_msglevel,
1855 .set_msglevel = netdev_set_msglevel,
1856 .get_wol = rhine_get_wol,
1857 .set_wol = rhine_set_wol,
1858 .get_sg = ethtool_op_get_sg,
1859 .get_tx_csum = ethtool_op_get_tx_csum,
John W. Linvilleb81e8e12005-09-12 10:48:58 -04001860 .get_perm_addr = ethtool_op_get_perm_addr,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001861};
1862
1863static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1864{
1865 struct rhine_private *rp = netdev_priv(dev);
1866 int rc;
1867
1868 if (!netif_running(dev))
1869 return -EINVAL;
1870
1871 spin_lock_irq(&rp->lock);
1872 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1873 spin_unlock_irq(&rp->lock);
Roger Luethi00b428c2006-03-28 20:53:56 +02001874 rhine_set_carrier(&rp->mii_if);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875
1876 return rc;
1877}
1878
1879static int rhine_close(struct net_device *dev)
1880{
1881 struct rhine_private *rp = netdev_priv(dev);
1882 void __iomem *ioaddr = rp->base;
1883
1884 spin_lock_irq(&rp->lock);
1885
1886 netif_stop_queue(dev);
1887
1888 if (debug > 1)
1889 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1890 "status was %4.4x.\n",
1891 dev->name, ioread16(ioaddr + ChipCmd));
1892
1893 /* Switch to loopback mode to avoid hardware races. */
1894 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1895
1896 /* Disable interrupts by clearing the interrupt mask. */
1897 iowrite16(0x0000, ioaddr + IntrEnable);
1898
1899 /* Stop the chip's Tx and Rx processes. */
1900 iowrite16(CmdStop, ioaddr + ChipCmd);
1901
1902 spin_unlock_irq(&rp->lock);
1903
1904 free_irq(rp->pdev->irq, dev);
1905 free_rbufs(dev);
1906 free_tbufs(dev);
1907 free_ring(dev);
1908
1909 return 0;
1910}
1911
1912
1913static void __devexit rhine_remove_one(struct pci_dev *pdev)
1914{
1915 struct net_device *dev = pci_get_drvdata(pdev);
1916 struct rhine_private *rp = netdev_priv(dev);
1917
1918 unregister_netdev(dev);
1919
1920 pci_iounmap(pdev, rp->base);
1921 pci_release_regions(pdev);
1922
1923 free_netdev(dev);
1924 pci_disable_device(pdev);
1925 pci_set_drvdata(pdev, NULL);
1926}
1927
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001928static void rhine_shutdown (struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930 struct net_device *dev = pci_get_drvdata(pdev);
1931 struct rhine_private *rp = netdev_priv(dev);
1932 void __iomem *ioaddr = rp->base;
1933
1934 if (!(rp->quirks & rqWOL))
1935 return; /* Nothing to do for non-WOL adapters */
1936
1937 rhine_power_init(dev);
1938
1939 /* Make sure we use pattern 0, 1 and not 4, 5 */
1940 if (rp->quirks & rq6patterns)
1941 iowrite8(0x04, ioaddr + 0xA7);
1942
1943 if (rp->wolopts & WAKE_MAGIC) {
1944 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1945 /*
1946 * Turn EEPROM-controlled wake-up back on -- some hardware may
1947 * not cooperate otherwise.
1948 */
1949 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1950 }
1951
1952 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1953 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1954
1955 if (rp->wolopts & WAKE_PHY)
1956 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1957
1958 if (rp->wolopts & WAKE_UCAST)
1959 iowrite8(WOLucast, ioaddr + WOLcrSet);
1960
1961 if (rp->wolopts) {
1962 /* Enable legacy WOL (for old motherboards) */
1963 iowrite8(0x01, ioaddr + PwcfgSet);
1964 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1965 }
1966
1967 /* Hit power state D3 (sleep) */
1968 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1969
1970 /* TODO: Check use of pci_enable_wake() */
1971
1972}
1973
1974#ifdef CONFIG_PM
1975static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1976{
1977 struct net_device *dev = pci_get_drvdata(pdev);
1978 struct rhine_private *rp = netdev_priv(dev);
1979 unsigned long flags;
1980
1981 if (!netif_running(dev))
1982 return 0;
1983
1984 netif_device_detach(dev);
1985 pci_save_state(pdev);
1986
1987 spin_lock_irqsave(&rp->lock, flags);
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07001988 rhine_shutdown(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001989 spin_unlock_irqrestore(&rp->lock, flags);
1990
1991 free_irq(dev->irq, dev);
1992 return 0;
1993}
1994
1995static int rhine_resume(struct pci_dev *pdev)
1996{
1997 struct net_device *dev = pci_get_drvdata(pdev);
1998 struct rhine_private *rp = netdev_priv(dev);
1999 unsigned long flags;
2000 int ret;
2001
2002 if (!netif_running(dev))
2003 return 0;
2004
2005 if (request_irq(dev->irq, rhine_interrupt, SA_SHIRQ, dev->name, dev))
2006 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
2007
2008 ret = pci_set_power_state(pdev, PCI_D0);
2009 if (debug > 1)
2010 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
2011 dev->name, ret ? "failed" : "succeeded", ret);
2012
2013 pci_restore_state(pdev);
2014
2015 spin_lock_irqsave(&rp->lock, flags);
2016#ifdef USE_MMIO
2017 enable_mmio(rp->pioaddr, rp->quirks);
2018#endif
2019 rhine_power_init(dev);
2020 free_tbufs(dev);
2021 free_rbufs(dev);
2022 alloc_tbufs(dev);
2023 alloc_rbufs(dev);
2024 init_registers(dev);
2025 spin_unlock_irqrestore(&rp->lock, flags);
2026
2027 netif_device_attach(dev);
2028
2029 return 0;
2030}
2031#endif /* CONFIG_PM */
2032
2033static struct pci_driver rhine_driver = {
2034 .name = DRV_NAME,
2035 .id_table = rhine_pci_tbl,
2036 .probe = rhine_init_one,
2037 .remove = __devexit_p(rhine_remove_one),
2038#ifdef CONFIG_PM
2039 .suspend = rhine_suspend,
2040 .resume = rhine_resume,
2041#endif /* CONFIG_PM */
Greg Kroah-Hartmand18c3db2005-06-23 17:35:56 -07002042 .shutdown = rhine_shutdown,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043};
2044
2045
2046static int __init rhine_init(void)
2047{
2048/* when a module, this is printed whether or not devices are found in probe */
2049#ifdef MODULE
2050 printk(version);
2051#endif
2052 return pci_module_init(&rhine_driver);
2053}
2054
2055
2056static void __exit rhine_cleanup(void)
2057{
2058 pci_unregister_driver(&rhine_driver);
2059}
2060
2061
2062module_init(rhine_init);
2063module_exit(rhine_cleanup);