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Catalin Marinas6170a972012-03-05 11:49:29 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_FUTEX_H
17#define __ASM_FUTEX_H
18
19#ifdef __KERNEL__
20
21#include <linux/futex.h>
22#include <linux/uaccess.h>
James Morse338d4f42015-07-22 19:05:54 +010023
Catalin Marinas6170a972012-03-05 11:49:29 +000024#include <asm/errno.h>
25
26#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
Catalin Marinas2962f1d2016-07-01 14:58:21 +010027do { \
28 uaccess_enable(); \
Catalin Marinas6170a972012-03-05 11:49:29 +000029 asm volatile( \
Will Deacon0ea366f2015-05-29 13:31:10 +010030" prfm pstl1strm, %2\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000031"1: ldxr %w1, %2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000032 insn "\n" \
Will Deacon32810f92019-04-08 12:45:09 +010033"2: stlxr %w0, %w3, %2\n" \
34" cbnz %w0, 1b\n" \
Will Deacon8e86f0b2014-02-04 12:29:12 +000035" dmb ish\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000036"3:\n" \
37" .pushsection .fixup,\"ax\"\n" \
Will Deacon4da7a562013-11-06 19:31:24 +000038" .align 2\n" \
Catalin Marinas6170a972012-03-05 11:49:29 +000039"4: mov %w0, %w5\n" \
40" b 3b\n" \
41" .popsection\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010042 _ASM_EXTABLE(1b, 4b) \
43 _ASM_EXTABLE(2b, 4b) \
Catalin Marinas6170a972012-03-05 11:49:29 +000044 : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
45 : "r" (oparg), "Ir" (-EFAULT) \
Catalin Marinas2962f1d2016-07-01 14:58:21 +010046 : "memory"); \
47 uaccess_disable(); \
48} while (0)
Catalin Marinas6170a972012-03-05 11:49:29 +000049
50static inline int
Jiri Slaby81da9f82017-08-24 09:31:05 +020051arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
Catalin Marinas6170a972012-03-05 11:49:29 +000052{
Nathan Chancellor8e6a1ef2019-04-17 00:21:21 -070053 int oldval = 0, ret, tmp;
Catalin Marinas6170a972012-03-05 11:49:29 +000054
David Hildenbrand2f09b222015-05-11 17:52:17 +020055 pagefault_disable();
Catalin Marinas6170a972012-03-05 11:49:29 +000056
57 switch (op) {
58 case FUTEX_OP_SET:
Will Deacon32810f92019-04-08 12:45:09 +010059 __futex_atomic_op("mov %w3, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000060 ret, oldval, uaddr, tmp, oparg);
61 break;
62 case FUTEX_OP_ADD:
Will Deacon32810f92019-04-08 12:45:09 +010063 __futex_atomic_op("add %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000064 ret, oldval, uaddr, tmp, oparg);
65 break;
66 case FUTEX_OP_OR:
Will Deacon32810f92019-04-08 12:45:09 +010067 __futex_atomic_op("orr %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000068 ret, oldval, uaddr, tmp, oparg);
69 break;
70 case FUTEX_OP_ANDN:
Will Deacon32810f92019-04-08 12:45:09 +010071 __futex_atomic_op("and %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000072 ret, oldval, uaddr, tmp, ~oparg);
73 break;
74 case FUTEX_OP_XOR:
Will Deacon32810f92019-04-08 12:45:09 +010075 __futex_atomic_op("eor %w3, %w1, %w4",
Catalin Marinas6170a972012-03-05 11:49:29 +000076 ret, oldval, uaddr, tmp, oparg);
77 break;
78 default:
79 ret = -ENOSYS;
80 }
81
David Hildenbrand2f09b222015-05-11 17:52:17 +020082 pagefault_enable();
Catalin Marinas6170a972012-03-05 11:49:29 +000083
Jiri Slaby81da9f82017-08-24 09:31:05 +020084 if (!ret)
85 *oval = oldval;
86
Catalin Marinas6170a972012-03-05 11:49:29 +000087 return ret;
88}
89
90static inline int
Will Deacon1cd969f2018-02-05 15:34:24 +000091futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
Catalin Marinas6170a972012-03-05 11:49:29 +000092 u32 oldval, u32 newval)
93{
94 int ret = 0;
95 u32 val, tmp;
Will Deacon1cd969f2018-02-05 15:34:24 +000096 u32 __user *uaddr;
Catalin Marinas6170a972012-03-05 11:49:29 +000097
Will Deacon1cd969f2018-02-05 15:34:24 +000098 if (!access_ok(VERIFY_WRITE, _uaddr, sizeof(u32)))
Catalin Marinas6170a972012-03-05 11:49:29 +000099 return -EFAULT;
100
Will Deacon1cd969f2018-02-05 15:34:24 +0000101 uaddr = __uaccess_mask_ptr(_uaddr);
Catalin Marinas2962f1d2016-07-01 14:58:21 +0100102 uaccess_enable();
Catalin Marinas6170a972012-03-05 11:49:29 +0000103 asm volatile("// futex_atomic_cmpxchg_inatomic\n"
Will Deacon0ea366f2015-05-29 13:31:10 +0100104" prfm pstl1strm, %2\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000105"1: ldxr %w1, %2\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000106" sub %w3, %w1, %w4\n"
107" cbnz %w3, 3f\n"
108"2: stlxr %w3, %w5, %2\n"
109" cbnz %w3, 1b\n"
Will Deacon8e86f0b2014-02-04 12:29:12 +0000110" dmb ish\n"
Catalin Marinas6170a972012-03-05 11:49:29 +0000111"3:\n"
112" .pushsection .fixup,\"ax\"\n"
113"4: mov %w0, %w6\n"
114" b 3b\n"
115" .popsection\n"
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100116 _ASM_EXTABLE(1b, 4b)
117 _ASM_EXTABLE(2b, 4b)
Catalin Marinas6170a972012-03-05 11:49:29 +0000118 : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp)
119 : "r" (oldval), "r" (newval), "Ir" (-EFAULT)
Will Deacon95c41892014-02-04 12:29:13 +0000120 : "memory");
Catalin Marinas2962f1d2016-07-01 14:58:21 +0100121 uaccess_disable();
Catalin Marinas6170a972012-03-05 11:49:29 +0000122
123 *uval = val;
124 return ret;
125}
126
127#endif /* __KERNEL__ */
128#endif /* __ASM_FUTEX_H */