Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2003 - 2006 NetXen, Inc. |
| 3 | * All rights reserved. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 4 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 9 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 14 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
| 18 | * MA 02111-1307, USA. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 19 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 20 | * The full GNU General Public License is included in this distribution |
| 21 | * in the file called LICENSE. |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 22 | * |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 23 | * Contact Information: |
| 24 | * info@netxen.com |
| 25 | * NetXen, |
| 26 | * 3965 Freedom Circle, Fourth floor, |
| 27 | * Santa Clara, CA 95054 |
| 28 | * |
| 29 | * |
| 30 | * Source file for NIC routines to access the Phantom hardware |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #include "netxen_nic.h" |
| 35 | #include "netxen_nic_hw.h" |
| 36 | #include "netxen_nic_phan_reg.h" |
| 37 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 38 | |
Arnaldo Carvalho de Melo | c9bdd4b | 2007-03-12 20:09:15 -0300 | [diff] [blame] | 39 | #include <net/ip.h> |
| 40 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 41 | #define MASK(n) ((1ULL<<(n))-1) |
| 42 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 43 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) |
| 44 | #define MS_WIN(addr) (addr & 0x0ffc0000) |
| 45 | |
| 46 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) |
| 47 | |
| 48 | #define CRB_BLK(off) ((off >> 20) & 0x3f) |
| 49 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) |
| 50 | #define CRB_WINDOW_2M (0x130060) |
| 51 | #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000)) |
| 52 | #define CRB_INDIRECT_2M (0x1e0000UL) |
| 53 | |
| 54 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 55 | static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { |
| 56 | {{{0, 0, 0, 0} } }, /* 0: PCI */ |
| 57 | {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ |
| 58 | {1, 0x0110000, 0x0120000, 0x130000}, |
| 59 | {1, 0x0120000, 0x0122000, 0x124000}, |
| 60 | {1, 0x0130000, 0x0132000, 0x126000}, |
| 61 | {1, 0x0140000, 0x0142000, 0x128000}, |
| 62 | {1, 0x0150000, 0x0152000, 0x12a000}, |
| 63 | {1, 0x0160000, 0x0170000, 0x110000}, |
| 64 | {1, 0x0170000, 0x0172000, 0x12e000}, |
| 65 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 66 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 67 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 68 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 69 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 70 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 71 | {1, 0x01e0000, 0x01e0800, 0x122000}, |
| 72 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 73 | {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ |
| 74 | {{{0, 0, 0, 0} } }, /* 3: */ |
| 75 | {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ |
| 76 | {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ |
| 77 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ |
| 78 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ |
| 79 | {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ |
| 80 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 81 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 82 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 83 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 84 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 85 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 86 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 87 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 88 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 89 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 90 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 91 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 92 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 93 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 94 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, |
| 95 | {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ |
| 96 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 97 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 98 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 99 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 100 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 101 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 102 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 103 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 104 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 105 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 106 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 107 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 108 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 109 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 110 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, |
| 111 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ |
| 112 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 113 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 114 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 115 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 116 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 117 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 118 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 119 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 120 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 121 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 122 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 123 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 124 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 125 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 126 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, |
| 127 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ |
| 128 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 129 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 130 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 131 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 132 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 133 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 134 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 135 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 136 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 137 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 138 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 139 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 140 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 141 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 142 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, |
| 143 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ |
| 144 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ |
| 145 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ |
| 146 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ |
| 147 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ |
| 148 | {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ |
| 149 | {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ |
| 150 | {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ |
| 151 | {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ |
| 152 | {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ |
| 153 | {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ |
| 154 | {{{0, 0, 0, 0} } }, /* 23: */ |
| 155 | {{{0, 0, 0, 0} } }, /* 24: */ |
| 156 | {{{0, 0, 0, 0} } }, /* 25: */ |
| 157 | {{{0, 0, 0, 0} } }, /* 26: */ |
| 158 | {{{0, 0, 0, 0} } }, /* 27: */ |
| 159 | {{{0, 0, 0, 0} } }, /* 28: */ |
| 160 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ |
| 161 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ |
| 162 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ |
| 163 | {{{0} } }, /* 32: PCI */ |
| 164 | {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ |
| 165 | {1, 0x2110000, 0x2120000, 0x130000}, |
| 166 | {1, 0x2120000, 0x2122000, 0x124000}, |
| 167 | {1, 0x2130000, 0x2132000, 0x126000}, |
| 168 | {1, 0x2140000, 0x2142000, 0x128000}, |
| 169 | {1, 0x2150000, 0x2152000, 0x12a000}, |
| 170 | {1, 0x2160000, 0x2170000, 0x110000}, |
| 171 | {1, 0x2170000, 0x2172000, 0x12e000}, |
| 172 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 173 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 174 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 175 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 176 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 177 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 178 | {0, 0x0000000, 0x0000000, 0x000000}, |
| 179 | {0, 0x0000000, 0x0000000, 0x000000} } }, |
| 180 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ |
| 181 | {{{0} } }, /* 35: */ |
| 182 | {{{0} } }, /* 36: */ |
| 183 | {{{0} } }, /* 37: */ |
| 184 | {{{0} } }, /* 38: */ |
| 185 | {{{0} } }, /* 39: */ |
| 186 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ |
| 187 | {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ |
| 188 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ |
| 189 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ |
| 190 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ |
| 191 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ |
| 192 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ |
| 193 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ |
| 194 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ |
| 195 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ |
| 196 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ |
| 197 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ |
| 198 | {{{0} } }, /* 52: */ |
| 199 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ |
| 200 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ |
| 201 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ |
| 202 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ |
| 203 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ |
| 204 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ |
| 205 | {{{0} } }, /* 59: I2C0 */ |
| 206 | {{{0} } }, /* 60: I2C1 */ |
| 207 | {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */ |
| 208 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ |
| 209 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ |
| 210 | }; |
| 211 | |
| 212 | /* |
| 213 | * top 12 bits of crb internal address (hub, agent) |
| 214 | */ |
| 215 | static unsigned crb_hub_agt[64] = |
| 216 | { |
| 217 | 0, |
| 218 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 219 | NETXEN_HW_CRB_HUB_AGT_ADR_MN, |
| 220 | NETXEN_HW_CRB_HUB_AGT_ADR_MS, |
| 221 | 0, |
| 222 | NETXEN_HW_CRB_HUB_AGT_ADR_SRE, |
| 223 | NETXEN_HW_CRB_HUB_AGT_ADR_NIU, |
| 224 | NETXEN_HW_CRB_HUB_AGT_ADR_QMN, |
| 225 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN0, |
| 226 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN1, |
| 227 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN2, |
| 228 | NETXEN_HW_CRB_HUB_AGT_ADR_SQN3, |
| 229 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 230 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 231 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 232 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN4, |
| 233 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 234 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN0, |
| 235 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN1, |
| 236 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN2, |
| 237 | NETXEN_HW_CRB_HUB_AGT_ADR_PGN3, |
| 238 | NETXEN_HW_CRB_HUB_AGT_ADR_PGND, |
| 239 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNI, |
| 240 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS0, |
| 241 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS1, |
| 242 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS2, |
| 243 | NETXEN_HW_CRB_HUB_AGT_ADR_PGS3, |
| 244 | 0, |
| 245 | NETXEN_HW_CRB_HUB_AGT_ADR_PGSI, |
| 246 | NETXEN_HW_CRB_HUB_AGT_ADR_SN, |
| 247 | 0, |
| 248 | NETXEN_HW_CRB_HUB_AGT_ADR_EG, |
| 249 | 0, |
| 250 | NETXEN_HW_CRB_HUB_AGT_ADR_PS, |
| 251 | NETXEN_HW_CRB_HUB_AGT_ADR_CAM, |
| 252 | 0, |
| 253 | 0, |
| 254 | 0, |
| 255 | 0, |
| 256 | 0, |
| 257 | NETXEN_HW_CRB_HUB_AGT_ADR_TIMR, |
| 258 | 0, |
| 259 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1, |
| 260 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2, |
| 261 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3, |
| 262 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4, |
| 263 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5, |
| 264 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6, |
| 265 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7, |
| 266 | NETXEN_HW_CRB_HUB_AGT_ADR_XDMA, |
| 267 | NETXEN_HW_CRB_HUB_AGT_ADR_I2Q, |
| 268 | NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB, |
| 269 | 0, |
| 270 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0, |
| 271 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8, |
| 272 | NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9, |
| 273 | NETXEN_HW_CRB_HUB_AGT_ADR_OCM0, |
| 274 | 0, |
| 275 | NETXEN_HW_CRB_HUB_AGT_ADR_SMB, |
| 276 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C0, |
| 277 | NETXEN_HW_CRB_HUB_AGT_ADR_I2C1, |
| 278 | 0, |
| 279 | NETXEN_HW_CRB_HUB_AGT_ADR_PGNC, |
| 280 | 0, |
| 281 | }; |
| 282 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 283 | struct netxen_recv_crb recv_crb_registers[] = { |
| 284 | /* |
| 285 | * Instance 0. |
| 286 | */ |
| 287 | { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 288 | /* crb_rcv_producer: */ |
| 289 | { |
| 290 | NETXEN_NIC_REG(0x100), |
| 291 | /* Jumbo frames */ |
| 292 | NETXEN_NIC_REG(0x110), |
| 293 | /* LRO */ |
| 294 | NETXEN_NIC_REG(0x120) |
| 295 | }, |
| 296 | /* crb_sts_consumer: */ |
| 297 | NETXEN_NIC_REG(0x138), |
| 298 | }, |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 299 | /* |
| 300 | * Instance 1, |
| 301 | */ |
| 302 | { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 303 | /* crb_rcv_producer: */ |
| 304 | { |
| 305 | NETXEN_NIC_REG(0x144), |
| 306 | /* Jumbo frames */ |
| 307 | NETXEN_NIC_REG(0x154), |
| 308 | /* LRO */ |
| 309 | NETXEN_NIC_REG(0x164) |
| 310 | }, |
| 311 | /* crb_sts_consumer: */ |
| 312 | NETXEN_NIC_REG(0x17c), |
| 313 | }, |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 314 | /* |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 315 | * Instance 2, |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 316 | */ |
| 317 | { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 318 | /* crb_rcv_producer: */ |
| 319 | { |
| 320 | NETXEN_NIC_REG(0x1d8), |
| 321 | /* Jumbo frames */ |
| 322 | NETXEN_NIC_REG(0x1f8), |
| 323 | /* LRO */ |
| 324 | NETXEN_NIC_REG(0x208) |
| 325 | }, |
| 326 | /* crb_sts_consumer: */ |
| 327 | NETXEN_NIC_REG(0x220), |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 328 | }, |
| 329 | /* |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 330 | * Instance 3, |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 331 | */ |
| 332 | { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 333 | /* crb_rcv_producer: */ |
| 334 | { |
| 335 | NETXEN_NIC_REG(0x22c), |
| 336 | /* Jumbo frames */ |
| 337 | NETXEN_NIC_REG(0x23c), |
| 338 | /* LRO */ |
| 339 | NETXEN_NIC_REG(0x24c) |
| 340 | }, |
| 341 | /* crb_sts_consumer: */ |
| 342 | NETXEN_NIC_REG(0x264), |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 343 | }, |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 344 | }; |
| 345 | |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 346 | static u64 ctx_addr_sig_regs[][3] = { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 347 | {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)}, |
| 348 | {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)}, |
| 349 | {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)}, |
| 350 | {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)} |
| 351 | }; |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 352 | #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0]) |
| 353 | #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2]) |
| 354 | #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1]) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 355 | |
| 356 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 357 | /* PCI Windowing for DDR regions. */ |
| 358 | |
| 359 | #define ADDR_IN_RANGE(addr, low, high) \ |
| 360 | (((addr) <= (high)) && ((addr) >= (low))) |
| 361 | |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 362 | #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 363 | #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE) |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 364 | #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 365 | #define NETXEN_MIN_MTU 64 |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 366 | #define NETXEN_ETH_FCS_SIZE 4 |
| 367 | #define NETXEN_ENET_HEADER_SIZE 14 |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 368 | #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 369 | #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4) |
| 370 | #define NETXEN_NIU_HDRSIZE (0x1 << 6) |
| 371 | #define NETXEN_NIU_TLRSIZE (0x1 << 5) |
| 372 | |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 373 | #define lower32(x) ((u32)((x) & 0xffffffff)) |
| 374 | #define upper32(x) \ |
| 375 | ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff)) |
| 376 | |
| 377 | #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL |
| 378 | #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL |
| 379 | #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL |
| 380 | #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL |
| 381 | |
| 382 | #define NETXEN_NIC_WINDOW_MARGIN 0x100000 |
| 383 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 384 | void netxen_free_hw_resources(struct netxen_adapter *adapter); |
| 385 | |
| 386 | int netxen_nic_set_mac(struct net_device *netdev, void *p) |
| 387 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 388 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 389 | struct sockaddr *addr = p; |
| 390 | |
| 391 | if (netif_running(netdev)) |
| 392 | return -EBUSY; |
| 393 | |
| 394 | if (!is_valid_ether_addr(addr->sa_data)) |
| 395 | return -EADDRNOTAVAIL; |
| 396 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 397 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
| 398 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 399 | if (adapter->macaddr_set) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 400 | adapter->macaddr_set(adapter, addr->sa_data); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 401 | |
| 402 | return 0; |
| 403 | } |
| 404 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 405 | #define NETXEN_UNICAST_ADDR(port, index) \ |
| 406 | (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8)) |
| 407 | #define NETXEN_MCAST_ADDR(port, index) \ |
| 408 | (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8)) |
| 409 | #define MAC_HI(addr) \ |
| 410 | ((addr[2] << 16) | (addr[1] << 8) | (addr[0])) |
| 411 | #define MAC_LO(addr) \ |
| 412 | ((addr[5] << 16) | (addr[4] << 8) | (addr[3])) |
| 413 | |
| 414 | static int |
| 415 | netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter) |
| 416 | { |
| 417 | u32 val = 0; |
| 418 | u16 port = adapter->physical_port; |
| 419 | u8 *addr = adapter->netdev->dev_addr; |
| 420 | |
| 421 | if (adapter->mc_enabled) |
| 422 | return 0; |
| 423 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 424 | adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 425 | val |= (1UL << (28+port)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 426 | adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 427 | |
| 428 | /* add broadcast addr to filter */ |
| 429 | val = 0xffffff; |
| 430 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
| 431 | netxen_crb_writelit_adapter(adapter, |
| 432 | NETXEN_UNICAST_ADDR(port, 0)+4, val); |
| 433 | |
| 434 | /* add station addr to filter */ |
| 435 | val = MAC_HI(addr); |
| 436 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); |
| 437 | val = MAC_LO(addr); |
| 438 | netxen_crb_writelit_adapter(adapter, |
| 439 | NETXEN_UNICAST_ADDR(port, 1)+4, val); |
| 440 | |
| 441 | adapter->mc_enabled = 1; |
| 442 | return 0; |
| 443 | } |
| 444 | |
| 445 | static int |
| 446 | netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter) |
| 447 | { |
| 448 | u32 val = 0; |
| 449 | u16 port = adapter->physical_port; |
| 450 | u8 *addr = adapter->netdev->dev_addr; |
| 451 | |
| 452 | if (!adapter->mc_enabled) |
| 453 | return 0; |
| 454 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 455 | adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 456 | val &= ~(1UL << (28+port)); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 457 | adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4); |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 458 | |
| 459 | val = MAC_HI(addr); |
| 460 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); |
| 461 | val = MAC_LO(addr); |
| 462 | netxen_crb_writelit_adapter(adapter, |
| 463 | NETXEN_UNICAST_ADDR(port, 0)+4, val); |
| 464 | |
| 465 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); |
| 466 | netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); |
| 467 | |
| 468 | adapter->mc_enabled = 0; |
| 469 | return 0; |
| 470 | } |
| 471 | |
| 472 | static int |
| 473 | netxen_nic_set_mcast_addr(struct netxen_adapter *adapter, |
| 474 | int index, u8 *addr) |
| 475 | { |
| 476 | u32 hi = 0, lo = 0; |
| 477 | u16 port = adapter->physical_port; |
| 478 | |
| 479 | lo = MAC_LO(addr); |
| 480 | hi = MAC_HI(addr); |
| 481 | |
| 482 | netxen_crb_writelit_adapter(adapter, |
| 483 | NETXEN_MCAST_ADDR(port, index), hi); |
| 484 | netxen_crb_writelit_adapter(adapter, |
| 485 | NETXEN_MCAST_ADDR(port, index)+4, lo); |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 490 | /* |
| 491 | * netxen_nic_set_multi - Multicast |
| 492 | */ |
| 493 | void netxen_nic_set_multi(struct net_device *netdev) |
| 494 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 495 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 496 | struct dev_mc_list *mc_ptr; |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 497 | u8 null_addr[6]; |
| 498 | int index = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 499 | |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 500 | memset(null_addr, 0, 6); |
| 501 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 502 | if (netdev->flags & IFF_PROMISC) { |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 503 | |
| 504 | adapter->set_promisc(adapter, |
| 505 | NETXEN_NIU_PROMISC_MODE); |
| 506 | |
| 507 | /* Full promiscuous mode */ |
| 508 | netxen_nic_disable_mcast_filter(adapter); |
| 509 | |
| 510 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 511 | } |
Dhananjay Phadke | 623621b | 2008-07-21 19:44:01 -0700 | [diff] [blame] | 512 | |
| 513 | if (netdev->mc_count == 0) { |
| 514 | adapter->set_promisc(adapter, |
| 515 | NETXEN_NIU_NON_PROMISC_MODE); |
| 516 | netxen_nic_disable_mcast_filter(adapter); |
| 517 | return; |
| 518 | } |
| 519 | |
| 520 | adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE); |
| 521 | if (netdev->flags & IFF_ALLMULTI || |
| 522 | netdev->mc_count > adapter->max_mc_count) { |
| 523 | netxen_nic_disable_mcast_filter(adapter); |
| 524 | return; |
| 525 | } |
| 526 | |
| 527 | netxen_nic_enable_mcast_filter(adapter); |
| 528 | |
| 529 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++) |
| 530 | netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr); |
| 531 | |
| 532 | if (index != netdev->mc_count) |
| 533 | printk(KERN_WARNING "%s: %s multicast address count mismatch\n", |
| 534 | netxen_nic_driver_name, netdev->name); |
| 535 | |
| 536 | /* Clear out remaining addresses */ |
| 537 | for (; index < adapter->max_mc_count; index++) |
| 538 | netxen_nic_set_mcast_addr(adapter, index, null_addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 539 | } |
| 540 | |
| 541 | /* |
| 542 | * netxen_nic_change_mtu - Change the Maximum Transfer Unit |
| 543 | * @returns 0 on success, negative on failure |
| 544 | */ |
| 545 | int netxen_nic_change_mtu(struct net_device *netdev, int mtu) |
| 546 | { |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 547 | struct netxen_adapter *adapter = netdev_priv(netdev); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 548 | int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE; |
| 549 | |
| 550 | if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) { |
| 551 | printk(KERN_ERR "%s: %s %d is not supported.\n", |
| 552 | netxen_nic_driver_name, netdev->name, mtu); |
| 553 | return -EINVAL; |
| 554 | } |
| 555 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 556 | if (adapter->set_mtu) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 557 | adapter->set_mtu(adapter, mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 558 | netdev->mtu = mtu; |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
| 563 | /* |
| 564 | * check if the firmware has been downloaded and ready to run and |
| 565 | * setup the address for the descriptors in the adapter |
| 566 | */ |
| 567 | int netxen_nic_hw_resources(struct netxen_adapter *adapter) |
| 568 | { |
| 569 | struct netxen_hardware_context *hw = &adapter->ahw; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 570 | u32 state = 0; |
| 571 | void *addr; |
| 572 | int loops = 0, err = 0; |
| 573 | int ctx, ring; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 574 | struct netxen_recv_context *recv_ctx; |
| 575 | struct netxen_rcv_desc_ctx *rcv_desc; |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 576 | int func_id = adapter->portnum; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 577 | |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 578 | DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE, |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 579 | PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE)); |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 580 | DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM, |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 581 | pci_base_offset(adapter, NETXEN_CRB_CAM)); |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 582 | DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE, |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 583 | pci_base_offset(adapter, NETXEN_CAM_RAM_BASE)); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 584 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 585 | |
| 586 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 587 | loops = 0; |
| 588 | state = 0; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 589 | do { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 590 | /* Window 1 call */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 591 | state = adapter->pci_read_normalize(adapter, |
| 592 | CRB_RCVPEG_STATE); |
| 593 | msleep(1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 594 | loops++; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 595 | } while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 596 | if (loops >= 20) { |
| 597 | printk(KERN_ERR "Rcv Peg initialization not complete:" |
| 598 | "%x.\n", state); |
| 599 | err = -EIO; |
| 600 | return err; |
| 601 | } |
| 602 | } |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 603 | adapter->intr_scheme = adapter->pci_read_normalize(adapter, |
| 604 | CRB_NIC_CAPABILITIES_FW); |
| 605 | adapter->msi_mode = adapter->pci_read_normalize(adapter, |
| 606 | CRB_NIC_MSI_MODE_FW); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 607 | |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 608 | addr = pci_alloc_consistent(adapter->pdev, |
| 609 | sizeof(struct netxen_ring_ctx) + sizeof(uint32_t), |
| 610 | &adapter->ctx_desc_phys_addr); |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 611 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 612 | if (addr == NULL) { |
| 613 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); |
| 614 | err = -ENOMEM; |
| 615 | return err; |
| 616 | } |
| 617 | memset(addr, 0, sizeof(struct netxen_ring_ctx)); |
| 618 | adapter->ctx_desc = (struct netxen_ring_ctx *)addr; |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 619 | adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum); |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 620 | adapter->ctx_desc->cmd_consumer_offset = |
| 621 | cpu_to_le64(adapter->ctx_desc_phys_addr + |
| 622 | sizeof(struct netxen_ring_ctx)); |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 623 | adapter->cmd_consumer = (__le32 *) (((char *)addr) + |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 624 | sizeof(struct netxen_ring_ctx)); |
| 625 | |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 626 | addr = pci_alloc_consistent(adapter->pdev, |
Amit S. Kale | 9de0661 | 2007-02-21 06:37:06 -0800 | [diff] [blame] | 627 | sizeof(struct cmd_desc_type0) * |
| 628 | adapter->max_tx_desc_count, |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 629 | &hw->cmd_desc_phys_addr); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 630 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 631 | if (addr == NULL) { |
| 632 | DPRINTK(ERR, "bad return from pci_alloc_consistent\n"); |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 633 | netxen_free_hw_resources(adapter); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 634 | return -ENOMEM; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 635 | } |
| 636 | |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 637 | adapter->ctx_desc->cmd_ring_addr = |
| 638 | cpu_to_le64(hw->cmd_desc_phys_addr); |
| 639 | adapter->ctx_desc->cmd_ring_size = |
| 640 | cpu_to_le32(adapter->max_tx_desc_count); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 641 | |
| 642 | hw->cmd_desc_head = (struct cmd_desc_type0 *)addr; |
| 643 | |
| 644 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { |
| 645 | recv_ctx = &adapter->recv_ctx[ctx]; |
| 646 | |
| 647 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { |
| 648 | rcv_desc = &recv_ctx->rcv_desc[ring]; |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 649 | addr = pci_alloc_consistent(adapter->pdev, |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 650 | RCV_DESC_RINGSIZE, |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 651 | &rcv_desc->phys_addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 652 | if (addr == NULL) { |
| 653 | DPRINTK(ERR, "bad return from " |
| 654 | "pci_alloc_consistent\n"); |
| 655 | netxen_free_hw_resources(adapter); |
| 656 | err = -ENOMEM; |
| 657 | return err; |
| 658 | } |
| 659 | rcv_desc->desc_head = (struct rcv_desc *)addr; |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 660 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr = |
| 661 | cpu_to_le64(rcv_desc->phys_addr); |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 662 | adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size = |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 663 | cpu_to_le32(rcv_desc->max_rx_desc_count); |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 664 | rcv_desc->crb_rcv_producer = |
| 665 | recv_crb_registers[adapter->portnum]. |
| 666 | crb_rcv_producer[ring]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 667 | } |
| 668 | |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 669 | addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE, |
| 670 | &recv_ctx->rcv_status_desc_phys_addr); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 671 | if (addr == NULL) { |
| 672 | DPRINTK(ERR, "bad return from" |
| 673 | " pci_alloc_consistent\n"); |
| 674 | netxen_free_hw_resources(adapter); |
| 675 | err = -ENOMEM; |
| 676 | return err; |
| 677 | } |
| 678 | recv_ctx->rcv_status_desc_head = (struct status_desc *)addr; |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 679 | adapter->ctx_desc->sts_ring_addr = |
| 680 | cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr); |
| 681 | adapter->ctx_desc->sts_ring_size = |
| 682 | cpu_to_le32(adapter->max_rx_desc_count); |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 683 | recv_ctx->crb_sts_consumer = |
| 684 | recv_crb_registers[adapter->portnum].crb_sts_consumer; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 685 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 686 | } |
| 687 | /* Window = 1 */ |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 688 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 689 | adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id), |
| 690 | lower32(adapter->ctx_desc_phys_addr)); |
| 691 | adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id), |
| 692 | upper32(adapter->ctx_desc_phys_addr)); |
| 693 | adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id), |
| 694 | NETXEN_CTX_SIGNATURE | func_id); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 695 | return err; |
| 696 | } |
| 697 | |
| 698 | void netxen_free_hw_resources(struct netxen_adapter *adapter) |
| 699 | { |
| 700 | struct netxen_recv_context *recv_ctx; |
| 701 | struct netxen_rcv_desc_ctx *rcv_desc; |
| 702 | int ctx, ring; |
| 703 | |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 704 | if (adapter->ctx_desc != NULL) { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 705 | pci_free_consistent(adapter->pdev, |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 706 | sizeof(struct netxen_ring_ctx) + |
| 707 | sizeof(uint32_t), |
| 708 | adapter->ctx_desc, |
| 709 | adapter->ctx_desc_phys_addr); |
| 710 | adapter->ctx_desc = NULL; |
| 711 | } |
| 712 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 713 | if (adapter->ahw.cmd_desc_head != NULL) { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 714 | pci_free_consistent(adapter->pdev, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 715 | sizeof(struct cmd_desc_type0) * |
| 716 | adapter->max_tx_desc_count, |
| 717 | adapter->ahw.cmd_desc_head, |
| 718 | adapter->ahw.cmd_desc_phys_addr); |
| 719 | adapter->ahw.cmd_desc_head = NULL; |
| 720 | } |
| 721 | |
| 722 | for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) { |
| 723 | recv_ctx = &adapter->recv_ctx[ctx]; |
| 724 | for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) { |
| 725 | rcv_desc = &recv_ctx->rcv_desc[ring]; |
| 726 | |
| 727 | if (rcv_desc->desc_head != NULL) { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 728 | pci_free_consistent(adapter->pdev, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 729 | RCV_DESC_RINGSIZE, |
| 730 | rcv_desc->desc_head, |
| 731 | rcv_desc->phys_addr); |
| 732 | rcv_desc->desc_head = NULL; |
| 733 | } |
| 734 | } |
| 735 | |
| 736 | if (recv_ctx->rcv_status_desc_head != NULL) { |
Dhananjay Phadke | 7830b22 | 2008-07-21 19:44:00 -0700 | [diff] [blame] | 737 | pci_free_consistent(adapter->pdev, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 738 | STATUS_DESC_RINGSIZE, |
| 739 | recv_ctx->rcv_status_desc_head, |
| 740 | recv_ctx-> |
| 741 | rcv_status_desc_phys_addr); |
| 742 | recv_ctx->rcv_status_desc_head = NULL; |
| 743 | } |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | void netxen_tso_check(struct netxen_adapter *adapter, |
| 748 | struct cmd_desc_type0 *desc, struct sk_buff *skb) |
| 749 | { |
| 750 | if (desc->mss) { |
Arnaldo Carvalho de Melo | c9bdd4b | 2007-03-12 20:09:15 -0300 | [diff] [blame] | 751 | desc->total_hdr_length = (sizeof(struct ethhdr) + |
Arnaldo Carvalho de Melo | ab6a5bb | 2007-03-18 17:43:48 -0700 | [diff] [blame] | 752 | ip_hdrlen(skb) + tcp_hdrlen(skb)); |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 753 | netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO); |
Amit S. Kale | c75e86b | 2006-12-18 05:51:58 -0800 | [diff] [blame] | 754 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 755 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) { |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 756 | netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT); |
Arnaldo Carvalho de Melo | eddc9ec | 2007-04-20 22:47:35 -0700 | [diff] [blame] | 757 | } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 758 | netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 759 | } else { |
| 760 | return; |
| 761 | } |
| 762 | } |
Arnaldo Carvalho de Melo | ea2ae17 | 2007-04-25 17:55:53 -0700 | [diff] [blame] | 763 | desc->tcp_hdr_offset = skb_transport_offset(skb); |
Arnaldo Carvalho de Melo | bbe735e | 2007-03-10 22:16:10 -0300 | [diff] [blame] | 764 | desc->ip_hdr_offset = skb_network_offset(skb); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 765 | } |
| 766 | |
| 767 | int netxen_is_flash_supported(struct netxen_adapter *adapter) |
| 768 | { |
| 769 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; |
| 770 | int addr, val01, val02, i, j; |
| 771 | |
| 772 | /* if the flash size less than 4Mb, make huge war cry and die */ |
| 773 | for (j = 1; j < 4; j++) { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 774 | addr = j * NETXEN_NIC_WINDOW_MARGIN; |
Denis Cheng | ff8ac60 | 2007-09-02 18:30:18 +0800 | [diff] [blame] | 775 | for (i = 0; i < ARRAY_SIZE(locs); i++) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 776 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 |
| 777 | && netxen_rom_fast_read(adapter, (addr + locs[i]), |
| 778 | &val02) == 0) { |
| 779 | if (val01 == val02) |
| 780 | return -1; |
| 781 | } else |
| 782 | return -1; |
| 783 | } |
| 784 | } |
| 785 | |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 790 | int size, __le32 * buf) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 791 | { |
| 792 | int i, addr; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 793 | __le32 *ptr32; |
| 794 | u32 v; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 795 | |
| 796 | addr = base; |
| 797 | ptr32 = buf; |
| 798 | for (i = 0; i < size / sizeof(u32); i++) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 799 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 800 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 801 | *ptr32 = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 802 | ptr32++; |
| 803 | addr += sizeof(u32); |
| 804 | } |
| 805 | if ((char *)buf + size > (char *)ptr32) { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 806 | __le32 local; |
| 807 | if (netxen_rom_fast_read(adapter, addr, &v) == -1) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 808 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 809 | local = cpu_to_le32(v); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 810 | memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32); |
| 811 | } |
| 812 | |
| 813 | return 0; |
| 814 | } |
| 815 | |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 816 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 817 | { |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 818 | __le32 *pmac = (__le32 *) & mac[0]; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 819 | |
| 820 | if (netxen_get_flash_block(adapter, |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 821 | NETXEN_USER_START + |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 822 | offsetof(struct netxen_new_user_info, |
| 823 | mac_addr), |
| 824 | FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) { |
| 825 | return -1; |
| 826 | } |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 827 | if (*mac == cpu_to_le64(~0ULL)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 828 | if (netxen_get_flash_block(adapter, |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 829 | NETXEN_USER_START_OLD + |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 830 | offsetof(struct netxen_user_old_info, |
| 831 | mac_addr), |
| 832 | FLASH_NUM_PORTS * sizeof(u64), |
| 833 | pmac) == -1) |
| 834 | return -1; |
Al Viro | f305f78 | 2007-12-22 19:44:00 +0000 | [diff] [blame] | 835 | if (*mac == cpu_to_le64(~0ULL)) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 836 | return -1; |
| 837 | } |
| 838 | return 0; |
| 839 | } |
| 840 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 841 | #define CRB_WIN_LOCK_TIMEOUT 100000000 |
| 842 | |
| 843 | static int crb_win_lock(struct netxen_adapter *adapter) |
| 844 | { |
| 845 | int done = 0, timeout = 0; |
| 846 | |
| 847 | while (!done) { |
| 848 | /* acquire semaphore3 from PCI HW block */ |
| 849 | adapter->hw_read_wx(adapter, |
| 850 | NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4); |
| 851 | if (done == 1) |
| 852 | break; |
| 853 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) |
| 854 | return -1; |
| 855 | timeout++; |
| 856 | udelay(1); |
| 857 | } |
| 858 | netxen_crb_writelit_adapter(adapter, |
| 859 | NETXEN_CRB_WIN_LOCK_ID, adapter->portnum); |
| 860 | return 0; |
| 861 | } |
| 862 | |
| 863 | static void crb_win_unlock(struct netxen_adapter *adapter) |
| 864 | { |
| 865 | int val; |
| 866 | |
| 867 | adapter->hw_read_wx(adapter, |
| 868 | NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4); |
| 869 | } |
| 870 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 871 | /* |
| 872 | * Changes the CRB window to the specified window. |
| 873 | */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 874 | void |
| 875 | netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 876 | { |
| 877 | void __iomem *offset; |
| 878 | u32 tmp; |
| 879 | int count = 0; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 880 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 881 | |
| 882 | if (adapter->curr_window == wndw) |
| 883 | return; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 884 | /* |
| 885 | * Move the CRB window. |
| 886 | * We need to write to the "direct access" region of PCI |
| 887 | * to avoid a race condition where the window register has |
| 888 | * not been successfully written across CRB before the target |
| 889 | * register address is received by PCI. The direct region bypasses |
| 890 | * the CRB bus. |
| 891 | */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 892 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 893 | NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func))); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 894 | |
| 895 | if (wndw & 0x1) |
| 896 | wndw = NETXEN_WINDOW_ONE; |
| 897 | |
| 898 | writel(wndw, offset); |
| 899 | |
| 900 | /* MUST make sure window is set before we forge on... */ |
| 901 | while ((tmp = readl(offset)) != wndw) { |
| 902 | printk(KERN_WARNING "%s: %s WARNING: CRB window value not " |
| 903 | "registered properly: 0x%08x.\n", |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 904 | netxen_nic_driver_name, __func__, tmp); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 905 | mdelay(1); |
| 906 | if (count >= 10) |
| 907 | break; |
| 908 | count++; |
| 909 | } |
| 910 | |
Mithlesh Thukral | 6c80b18 | 2007-04-20 07:55:26 -0700 | [diff] [blame] | 911 | if (wndw == NETXEN_WINDOW_ONE) |
| 912 | adapter->curr_window = 1; |
| 913 | else |
| 914 | adapter->curr_window = 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 915 | } |
| 916 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 917 | /* |
| 918 | * Return -1 if off is not valid, |
| 919 | * 1 if window access is needed. 'off' is set to offset from |
| 920 | * CRB space in 128M pci map |
| 921 | * 0 if no window access is needed. 'off' is set to 2M addr |
| 922 | * In: 'off' is offset from base in 128M pci map |
| 923 | */ |
| 924 | static int |
| 925 | netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, |
| 926 | ulong *off, int len) |
| 927 | { |
| 928 | unsigned long end = *off + len; |
| 929 | crb_128M_2M_sub_block_map_t *m; |
| 930 | |
| 931 | |
| 932 | if (*off >= NETXEN_CRB_MAX) |
| 933 | return -1; |
| 934 | |
| 935 | if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) { |
| 936 | *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE + |
| 937 | (ulong)adapter->ahw.pci_base0; |
| 938 | return 0; |
| 939 | } |
| 940 | |
| 941 | if (*off < NETXEN_PCI_CRBSPACE) |
| 942 | return -1; |
| 943 | |
| 944 | *off -= NETXEN_PCI_CRBSPACE; |
| 945 | end = *off + len; |
| 946 | |
| 947 | /* |
| 948 | * Try direct map |
| 949 | */ |
| 950 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; |
| 951 | |
| 952 | if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) { |
| 953 | *off = *off + m->start_2M - m->start_128M + |
| 954 | (ulong)adapter->ahw.pci_base0; |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | /* |
| 959 | * Not in direct map, use crb window |
| 960 | */ |
| 961 | return 1; |
| 962 | } |
| 963 | |
| 964 | /* |
| 965 | * In: 'off' is offset from CRB space in 128M pci map |
| 966 | * Out: 'off' is 2M pci map addr |
| 967 | * side effect: lock crb window |
| 968 | */ |
| 969 | static void |
| 970 | netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off) |
| 971 | { |
| 972 | u32 win_read; |
| 973 | |
| 974 | adapter->crb_win = CRB_HI(*off); |
| 975 | writel(adapter->crb_win, (void *)(CRB_WINDOW_2M + |
| 976 | adapter->ahw.pci_base0)); |
| 977 | /* |
| 978 | * Read back value to make sure write has gone through before trying |
| 979 | * to use it. |
| 980 | */ |
| 981 | win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0)); |
| 982 | if (win_read != adapter->crb_win) { |
| 983 | printk(KERN_ERR "%s: Written crbwin (0x%x) != " |
| 984 | "Read crbwin (0x%x), off=0x%lx\n", |
| 985 | __func__, adapter->crb_win, win_read, *off); |
| 986 | } |
| 987 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + |
| 988 | (ulong)adapter->ahw.pci_base0; |
| 989 | } |
| 990 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 991 | int netxen_load_firmware(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 992 | { |
| 993 | int i; |
Linsys Contractor Mithlesh Thukral | e0e20a1 | 2007-02-28 05:16:40 -0800 | [diff] [blame] | 994 | u32 data, size = 0; |
| 995 | u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 996 | |
| 997 | size = NETXEN_FIRMWARE_LEN; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 998 | adapter->pci_write_normalize(adapter, |
| 999 | NETXEN_ROMUSB_GLB_CAS_RST, 1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1000 | |
| 1001 | for (i = 0; i < size; i++) { |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1002 | if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) |
| 1003 | return -EIO; |
| 1004 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1005 | adapter->pci_mem_write(adapter, memaddr, &data, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1006 | flashaddr += 4; |
| 1007 | memaddr += 4; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1008 | cond_resched(); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1009 | } |
| 1010 | udelay(100); |
| 1011 | /* make sure Casper is powered on */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1012 | adapter->pci_write_normalize(adapter, |
| 1013 | NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); |
| 1014 | adapter->pci_write_normalize(adapter, |
| 1015 | NETXEN_ROMUSB_GLB_CAS_RST, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1016 | |
Dhananjay Phadke | 96acb6e | 2007-07-02 09:37:57 +0530 | [diff] [blame] | 1017 | return 0; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | int |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1021 | netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, |
| 1022 | ulong off, void *data, int len) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1023 | { |
| 1024 | void __iomem *addr; |
| 1025 | |
| 1026 | if (ADDR_IN_WINDOW1(off)) { |
| 1027 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 1028 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1029 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1030 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1031 | } |
| 1032 | |
| 1033 | DPRINTK(INFO, "writing to base %lx offset %llx addr %p" |
| 1034 | " data %llx len %d\n", |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1035 | pci_base(adapter, off), off, addr, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1036 | *(unsigned long long *)data, len); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1037 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1038 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1039 | return 1; |
| 1040 | } |
| 1041 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1042 | switch (len) { |
| 1043 | case 1: |
| 1044 | writeb(*(u8 *) data, addr); |
| 1045 | break; |
| 1046 | case 2: |
| 1047 | writew(*(u16 *) data, addr); |
| 1048 | break; |
| 1049 | case 4: |
| 1050 | writel(*(u32 *) data, addr); |
| 1051 | break; |
| 1052 | case 8: |
| 1053 | writeq(*(u64 *) data, addr); |
| 1054 | break; |
| 1055 | default: |
| 1056 | DPRINTK(INFO, |
| 1057 | "writing data %lx to offset %llx, num words=%d\n", |
| 1058 | *(unsigned long *)data, off, (len >> 3)); |
| 1059 | |
| 1060 | netxen_nic_hw_block_write64((u64 __iomem *) data, addr, |
| 1061 | (len >> 3)); |
| 1062 | break; |
| 1063 | } |
| 1064 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1065 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1066 | |
| 1067 | return 0; |
| 1068 | } |
| 1069 | |
| 1070 | int |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1071 | netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, |
| 1072 | ulong off, void *data, int len) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1073 | { |
| 1074 | void __iomem *addr; |
| 1075 | |
| 1076 | if (ADDR_IN_WINDOW1(off)) { /* Window 1 */ |
| 1077 | addr = NETXEN_CRB_NORMALIZE(adapter, off); |
| 1078 | } else { /* Window 0 */ |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1079 | addr = pci_base_offset(adapter, off); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1080 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n", |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1084 | pci_base(adapter, off), off, addr); |
| 1085 | if (!addr) { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1086 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1087 | return 1; |
| 1088 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1089 | switch (len) { |
| 1090 | case 1: |
| 1091 | *(u8 *) data = readb(addr); |
| 1092 | break; |
| 1093 | case 2: |
| 1094 | *(u16 *) data = readw(addr); |
| 1095 | break; |
| 1096 | case 4: |
| 1097 | *(u32 *) data = readl(addr); |
| 1098 | break; |
| 1099 | case 8: |
| 1100 | *(u64 *) data = readq(addr); |
| 1101 | break; |
| 1102 | default: |
| 1103 | netxen_nic_hw_block_read64((u64 __iomem *) data, addr, |
| 1104 | (len >> 3)); |
| 1105 | break; |
| 1106 | } |
| 1107 | DPRINTK(INFO, "read %lx\n", *(unsigned long *)data); |
| 1108 | |
| 1109 | if (!ADDR_IN_WINDOW1(off)) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1110 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1111 | |
| 1112 | return 0; |
| 1113 | } |
| 1114 | |
| 1115 | int |
| 1116 | netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, |
| 1117 | ulong off, void *data, int len) |
| 1118 | { |
| 1119 | unsigned long flags = 0; |
| 1120 | int rv; |
| 1121 | |
| 1122 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); |
| 1123 | |
| 1124 | if (rv == -1) { |
| 1125 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1126 | __func__, off); |
| 1127 | dump_stack(); |
| 1128 | return -1; |
| 1129 | } |
| 1130 | |
| 1131 | if (rv == 1) { |
| 1132 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1133 | crb_win_lock(adapter); |
| 1134 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
| 1135 | } |
| 1136 | |
| 1137 | DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n", |
| 1138 | *(unsigned long *)data, off, len); |
| 1139 | |
| 1140 | switch (len) { |
| 1141 | case 1: |
| 1142 | writeb(*(uint8_t *)data, (void *)off); |
| 1143 | break; |
| 1144 | case 2: |
| 1145 | writew(*(uint16_t *)data, (void *)off); |
| 1146 | break; |
| 1147 | case 4: |
| 1148 | writel(*(uint32_t *)data, (void *)off); |
| 1149 | break; |
| 1150 | case 8: |
| 1151 | writeq(*(uint64_t *)data, (void *)off); |
| 1152 | break; |
| 1153 | default: |
| 1154 | DPRINTK(1, INFO, |
| 1155 | "writing data %lx to offset %llx, num words=%d\n", |
| 1156 | *(unsigned long *)data, off, (len>>3)); |
| 1157 | break; |
| 1158 | } |
| 1159 | if (rv == 1) { |
| 1160 | crb_win_unlock(adapter); |
| 1161 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1162 | } |
| 1163 | |
| 1164 | return 0; |
| 1165 | } |
| 1166 | |
| 1167 | int |
| 1168 | netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, |
| 1169 | ulong off, void *data, int len) |
| 1170 | { |
| 1171 | unsigned long flags = 0; |
| 1172 | int rv; |
| 1173 | |
| 1174 | rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len); |
| 1175 | |
| 1176 | if (rv == -1) { |
| 1177 | printk(KERN_ERR "%s: invalid offset: 0x%016lx\n", |
| 1178 | __func__, off); |
| 1179 | dump_stack(); |
| 1180 | return -1; |
| 1181 | } |
| 1182 | |
| 1183 | if (rv == 1) { |
| 1184 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1185 | crb_win_lock(adapter); |
| 1186 | netxen_nic_pci_set_crbwindow_2M(adapter, &off); |
| 1187 | } |
| 1188 | |
| 1189 | DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len); |
| 1190 | |
| 1191 | switch (len) { |
| 1192 | case 1: |
| 1193 | *(uint8_t *)data = readb((void *)off); |
| 1194 | break; |
| 1195 | case 2: |
| 1196 | *(uint16_t *)data = readw((void *)off); |
| 1197 | break; |
| 1198 | case 4: |
| 1199 | *(uint32_t *)data = readl((void *)off); |
| 1200 | break; |
| 1201 | case 8: |
| 1202 | *(uint64_t *)data = readq((void *)off); |
| 1203 | break; |
| 1204 | default: |
| 1205 | break; |
| 1206 | } |
| 1207 | |
| 1208 | DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data); |
| 1209 | |
| 1210 | if (rv == 1) { |
| 1211 | crb_win_unlock(adapter); |
| 1212 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1213 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1214 | |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1219 | { |
| 1220 | adapter->hw_write_wx(adapter, off, &val, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1221 | } |
| 1222 | |
| 1223 | int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off) |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1224 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1225 | int val; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1226 | adapter->hw_read_wx(adapter, off, &val, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1227 | return val; |
| 1228 | } |
| 1229 | |
| 1230 | /* Change the window to 0, write and change back to window 1. */ |
| 1231 | void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value) |
| 1232 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1233 | adapter->hw_write_wx(adapter, index, &value, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1234 | } |
| 1235 | |
| 1236 | /* Change the window to 0, read and change back to window 1. */ |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1237 | void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1238 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1239 | adapter->hw_read_wx(adapter, index, value, 4); |
| 1240 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1241 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1242 | void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value) |
| 1243 | { |
| 1244 | adapter->hw_write_wx(adapter, index, &value, 4); |
| 1245 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1246 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1247 | void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value) |
| 1248 | { |
| 1249 | adapter->hw_read_wx(adapter, index, value, 4); |
| 1250 | } |
| 1251 | |
| 1252 | /* |
| 1253 | * check memory access boundary. |
| 1254 | * used by test agent. support ddr access only for now |
| 1255 | */ |
| 1256 | static unsigned long |
| 1257 | netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter, |
| 1258 | unsigned long long addr, int size) |
| 1259 | { |
| 1260 | if (!ADDR_IN_RANGE(addr, |
| 1261 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1262 | !ADDR_IN_RANGE(addr+size-1, |
| 1263 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) || |
| 1264 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { |
| 1265 | return 0; |
| 1266 | } |
| 1267 | |
| 1268 | return 1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1269 | } |
| 1270 | |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 1271 | static int netxen_pci_set_window_warning_count; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1272 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1273 | unsigned long |
| 1274 | netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter, |
| 1275 | unsigned long long addr) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1276 | { |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1277 | void __iomem *offset; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1278 | int window; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1279 | unsigned long long qdr_max; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1280 | uint8_t func = adapter->ahw.pci_func; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1281 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1282 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { |
| 1283 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1284 | } else { |
| 1285 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1286 | } |
| 1287 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1288 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1289 | /* DDR network side */ |
| 1290 | addr -= NETXEN_ADDR_DDR_NET; |
| 1291 | window = (addr >> 25) & 0x3ff; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1292 | if (adapter->ahw.ddr_mn_window != window) { |
| 1293 | adapter->ahw.ddr_mn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1294 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1295 | NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func))); |
| 1296 | writel(window, offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1297 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1298 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1299 | } |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 1300 | addr -= (window * NETXEN_WINDOW_ONE); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1301 | addr += NETXEN_PCI_DDR_NET; |
| 1302 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1303 | addr -= NETXEN_ADDR_OCM0; |
| 1304 | addr += NETXEN_PCI_OCM0; |
| 1305 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1306 | addr -= NETXEN_ADDR_OCM1; |
| 1307 | addr += NETXEN_PCI_OCM1; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1308 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1309 | /* QDR network side */ |
| 1310 | addr -= NETXEN_ADDR_QDR_NET; |
| 1311 | window = (addr >> 22) & 0x3f; |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1312 | if (adapter->ahw.qdr_sn_window != window) { |
| 1313 | adapter->ahw.qdr_sn_window = window; |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1314 | offset = PCI_OFFSET_SECOND_RANGE(adapter, |
| 1315 | NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func))); |
| 1316 | writel((window << 22), offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1317 | /* MUST make sure window is set before we forge on... */ |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 1318 | readl(offset); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1319 | } |
| 1320 | addr -= (window * 0x400000); |
| 1321 | addr += NETXEN_PCI_QDR_NET; |
| 1322 | } else { |
| 1323 | /* |
| 1324 | * peg gdb frequently accesses memory that doesn't exist, |
| 1325 | * this limits the chit chat so debugging isn't slowed down. |
| 1326 | */ |
| 1327 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1328 | || (netxen_pci_set_window_warning_count % 64 == 0)) |
| 1329 | printk("%s: Warning:netxen_nic_pci_set_window()" |
| 1330 | " Unknown address range!\n", |
| 1331 | netxen_nic_driver_name); |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1332 | addr = -1UL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 1333 | } |
| 1334 | return addr; |
| 1335 | } |
| 1336 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 1337 | /* |
| 1338 | * Note : only 32-bit writes! |
| 1339 | */ |
| 1340 | int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter, |
| 1341 | u64 off, u32 data) |
| 1342 | { |
| 1343 | writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off))); |
| 1344 | return 0; |
| 1345 | } |
| 1346 | |
| 1347 | u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off) |
| 1348 | { |
| 1349 | return readl((void __iomem *)(pci_base_offset(adapter, off))); |
| 1350 | } |
| 1351 | |
| 1352 | void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter, |
| 1353 | u64 off, u32 data) |
| 1354 | { |
| 1355 | writel(data, NETXEN_CRB_NORMALIZE(adapter, off)); |
| 1356 | } |
| 1357 | |
| 1358 | u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off) |
| 1359 | { |
| 1360 | return readl(NETXEN_CRB_NORMALIZE(adapter, off)); |
| 1361 | } |
| 1362 | |
| 1363 | unsigned long |
| 1364 | netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter, |
| 1365 | unsigned long long addr) |
| 1366 | { |
| 1367 | int window; |
| 1368 | u32 win_read; |
| 1369 | |
| 1370 | if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1371 | /* DDR network side */ |
| 1372 | window = MN_WIN(addr); |
| 1373 | adapter->ahw.ddr_mn_window = window; |
| 1374 | adapter->hw_write_wx(adapter, |
| 1375 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1376 | &window, 4); |
| 1377 | adapter->hw_read_wx(adapter, |
| 1378 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1379 | &win_read, 4); |
| 1380 | if ((win_read << 17) != window) { |
| 1381 | printk(KERN_INFO "Written MNwin (0x%x) != " |
| 1382 | "Read MNwin (0x%x)\n", window, win_read); |
| 1383 | } |
| 1384 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET; |
| 1385 | } else if (ADDR_IN_RANGE(addr, |
| 1386 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1387 | if ((addr & 0x00ff800) == 0xff800) { |
| 1388 | printk("%s: QM access not handled.\n", __func__); |
| 1389 | addr = -1UL; |
| 1390 | } |
| 1391 | |
| 1392 | window = OCM_WIN(addr); |
| 1393 | adapter->ahw.ddr_mn_window = window; |
| 1394 | adapter->hw_write_wx(adapter, |
| 1395 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1396 | &window, 4); |
| 1397 | adapter->hw_read_wx(adapter, |
| 1398 | adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE, |
| 1399 | &win_read, 4); |
| 1400 | if ((win_read >> 7) != window) { |
| 1401 | printk(KERN_INFO "%s: Written OCMwin (0x%x) != " |
| 1402 | "Read OCMwin (0x%x)\n", |
| 1403 | __func__, window, win_read); |
| 1404 | } |
| 1405 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M; |
| 1406 | |
| 1407 | } else if (ADDR_IN_RANGE(addr, |
| 1408 | NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) { |
| 1409 | /* QDR network side */ |
| 1410 | window = MS_WIN(addr); |
| 1411 | adapter->ahw.qdr_sn_window = window; |
| 1412 | adapter->hw_write_wx(adapter, |
| 1413 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, |
| 1414 | &window, 4); |
| 1415 | adapter->hw_read_wx(adapter, |
| 1416 | adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE, |
| 1417 | &win_read, 4); |
| 1418 | if (win_read != window) { |
| 1419 | printk(KERN_INFO "%s: Written MSwin (0x%x) != " |
| 1420 | "Read MSwin (0x%x)\n", |
| 1421 | __func__, window, win_read); |
| 1422 | } |
| 1423 | addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET; |
| 1424 | |
| 1425 | } else { |
| 1426 | /* |
| 1427 | * peg gdb frequently accesses memory that doesn't exist, |
| 1428 | * this limits the chit chat so debugging isn't slowed down. |
| 1429 | */ |
| 1430 | if ((netxen_pci_set_window_warning_count++ < 8) |
| 1431 | || (netxen_pci_set_window_warning_count%64 == 0)) { |
| 1432 | printk("%s: Warning:%s Unknown address range!\n", |
| 1433 | __func__, netxen_nic_driver_name); |
| 1434 | } |
| 1435 | addr = -1UL; |
| 1436 | } |
| 1437 | return addr; |
| 1438 | } |
| 1439 | |
| 1440 | static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter, |
| 1441 | unsigned long long addr) |
| 1442 | { |
| 1443 | int window; |
| 1444 | unsigned long long qdr_max; |
| 1445 | |
| 1446 | if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) |
| 1447 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2; |
| 1448 | else |
| 1449 | qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3; |
| 1450 | |
| 1451 | if (ADDR_IN_RANGE(addr, |
| 1452 | NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) { |
| 1453 | /* DDR network side */ |
| 1454 | BUG(); /* MN access can not come here */ |
| 1455 | } else if (ADDR_IN_RANGE(addr, |
| 1456 | NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) { |
| 1457 | return 1; |
| 1458 | } else if (ADDR_IN_RANGE(addr, |
| 1459 | NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) { |
| 1460 | return 1; |
| 1461 | } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) { |
| 1462 | /* QDR network side */ |
| 1463 | window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f; |
| 1464 | if (adapter->ahw.qdr_sn_window == window) |
| 1465 | return 1; |
| 1466 | } |
| 1467 | |
| 1468 | return 0; |
| 1469 | } |
| 1470 | |
| 1471 | static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter, |
| 1472 | u64 off, void *data, int size) |
| 1473 | { |
| 1474 | unsigned long flags; |
| 1475 | void *addr; |
| 1476 | int ret = 0; |
| 1477 | u64 start; |
| 1478 | uint8_t *mem_ptr = NULL; |
| 1479 | unsigned long mem_base; |
| 1480 | unsigned long mem_page; |
| 1481 | |
| 1482 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1483 | |
| 1484 | /* |
| 1485 | * If attempting to access unknown address or straddle hw windows, |
| 1486 | * do not access. |
| 1487 | */ |
| 1488 | start = adapter->pci_set_window(adapter, off); |
| 1489 | if ((start == -1UL) || |
| 1490 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1491 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1492 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1493 | "offset is 0x%llx\n", netxen_nic_driver_name, off); |
| 1494 | return -1; |
| 1495 | } |
| 1496 | |
| 1497 | addr = (void *)(pci_base_offset(adapter, start)); |
| 1498 | if (!addr) { |
| 1499 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1500 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1501 | mem_page = start & PAGE_MASK; |
| 1502 | /* Map two pages whenever user tries to access addresses in two |
| 1503 | consecutive pages. |
| 1504 | */ |
| 1505 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1506 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); |
| 1507 | else |
| 1508 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 1509 | if (mem_ptr == 0UL) { |
| 1510 | *(uint8_t *)data = 0; |
| 1511 | return -1; |
| 1512 | } |
| 1513 | addr = mem_ptr; |
| 1514 | addr += start & (PAGE_SIZE - 1); |
| 1515 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1516 | } |
| 1517 | |
| 1518 | switch (size) { |
| 1519 | case 1: |
| 1520 | *(uint8_t *)data = readb(addr); |
| 1521 | break; |
| 1522 | case 2: |
| 1523 | *(uint16_t *)data = readw(addr); |
| 1524 | break; |
| 1525 | case 4: |
| 1526 | *(uint32_t *)data = readl(addr); |
| 1527 | break; |
| 1528 | case 8: |
| 1529 | *(uint64_t *)data = readq(addr); |
| 1530 | break; |
| 1531 | default: |
| 1532 | ret = -1; |
| 1533 | break; |
| 1534 | } |
| 1535 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1536 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 1537 | |
| 1538 | if (mem_ptr) |
| 1539 | iounmap(mem_ptr); |
| 1540 | return ret; |
| 1541 | } |
| 1542 | |
| 1543 | static int |
| 1544 | netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off, |
| 1545 | void *data, int size) |
| 1546 | { |
| 1547 | unsigned long flags; |
| 1548 | void *addr; |
| 1549 | int ret = 0; |
| 1550 | u64 start; |
| 1551 | uint8_t *mem_ptr = NULL; |
| 1552 | unsigned long mem_base; |
| 1553 | unsigned long mem_page; |
| 1554 | |
| 1555 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1556 | |
| 1557 | /* |
| 1558 | * If attempting to access unknown address or straddle hw windows, |
| 1559 | * do not access. |
| 1560 | */ |
| 1561 | start = adapter->pci_set_window(adapter, off); |
| 1562 | if ((start == -1UL) || |
| 1563 | (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) { |
| 1564 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1565 | printk(KERN_ERR "%s out of bound pci memory access. " |
| 1566 | "offset is 0x%llx\n", netxen_nic_driver_name, off); |
| 1567 | return -1; |
| 1568 | } |
| 1569 | |
| 1570 | addr = (void *)(pci_base_offset(adapter, start)); |
| 1571 | if (!addr) { |
| 1572 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1573 | mem_base = pci_resource_start(adapter->pdev, 0); |
| 1574 | mem_page = start & PAGE_MASK; |
| 1575 | /* Map two pages whenever user tries to access addresses in two |
| 1576 | * consecutive pages. |
| 1577 | */ |
| 1578 | if (mem_page != ((start + size - 1) & PAGE_MASK)) |
| 1579 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); |
| 1580 | else |
| 1581 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); |
| 1582 | if (mem_ptr == 0UL) |
| 1583 | return -1; |
| 1584 | addr = mem_ptr; |
| 1585 | addr += start & (PAGE_SIZE - 1); |
| 1586 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1587 | } |
| 1588 | |
| 1589 | switch (size) { |
| 1590 | case 1: |
| 1591 | writeb(*(uint8_t *)data, addr); |
| 1592 | break; |
| 1593 | case 2: |
| 1594 | writew(*(uint16_t *)data, addr); |
| 1595 | break; |
| 1596 | case 4: |
| 1597 | writel(*(uint32_t *)data, addr); |
| 1598 | break; |
| 1599 | case 8: |
| 1600 | writeq(*(uint64_t *)data, addr); |
| 1601 | break; |
| 1602 | default: |
| 1603 | ret = -1; |
| 1604 | break; |
| 1605 | } |
| 1606 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1607 | DPRINTK(1, INFO, "writing data %llx to offset %llx\n", |
| 1608 | *(unsigned long long *)data, start); |
| 1609 | if (mem_ptr) |
| 1610 | iounmap(mem_ptr); |
| 1611 | return ret; |
| 1612 | } |
| 1613 | |
| 1614 | #define MAX_CTL_CHECK 1000 |
| 1615 | |
| 1616 | int |
| 1617 | netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter, |
| 1618 | u64 off, void *data, int size) |
| 1619 | { |
| 1620 | unsigned long flags, mem_crb; |
| 1621 | int i, j, ret = 0, loop, sz[2], off0; |
| 1622 | uint32_t temp; |
| 1623 | uint64_t off8, tmpw, word[2] = {0, 0}; |
| 1624 | |
| 1625 | /* |
| 1626 | * If not MN, go check for MS or invalid. |
| 1627 | */ |
| 1628 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1629 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1630 | off, data, size); |
| 1631 | |
| 1632 | off8 = off & 0xfffffff8; |
| 1633 | off0 = off & 0x7; |
| 1634 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1635 | sz[1] = size - sz[0]; |
| 1636 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1637 | mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
| 1638 | |
| 1639 | if ((size != 8) || (off0 != 0)) { |
| 1640 | for (i = 0; i < loop; i++) { |
| 1641 | if (adapter->pci_mem_read(adapter, |
| 1642 | off8 + (i << 3), &word[i], 8)) |
| 1643 | return -1; |
| 1644 | } |
| 1645 | } |
| 1646 | |
| 1647 | switch (size) { |
| 1648 | case 1: |
| 1649 | tmpw = *((uint8_t *)data); |
| 1650 | break; |
| 1651 | case 2: |
| 1652 | tmpw = *((uint16_t *)data); |
| 1653 | break; |
| 1654 | case 4: |
| 1655 | tmpw = *((uint32_t *)data); |
| 1656 | break; |
| 1657 | case 8: |
| 1658 | default: |
| 1659 | tmpw = *((uint64_t *)data); |
| 1660 | break; |
| 1661 | } |
| 1662 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1663 | word[0] |= tmpw << (off0 * 8); |
| 1664 | |
| 1665 | if (loop == 2) { |
| 1666 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1667 | word[1] |= tmpw >> (sz[0] * 8); |
| 1668 | } |
| 1669 | |
| 1670 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1671 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1672 | |
| 1673 | for (i = 0; i < loop; i++) { |
| 1674 | writel((uint32_t)(off8 + (i << 3)), |
| 1675 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); |
| 1676 | writel(0, |
| 1677 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); |
| 1678 | writel(word[i] & 0xffffffff, |
| 1679 | (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO)); |
| 1680 | writel((word[i] >> 32) & 0xffffffff, |
| 1681 | (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI)); |
| 1682 | writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
| 1683 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1684 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE, |
| 1685 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1686 | |
| 1687 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1688 | temp = readl( |
| 1689 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1690 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1691 | break; |
| 1692 | } |
| 1693 | |
| 1694 | if (j >= MAX_CTL_CHECK) { |
| 1695 | printk("%s: %s Fail to write through agent\n", |
| 1696 | __func__, netxen_nic_driver_name); |
| 1697 | ret = -1; |
| 1698 | break; |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1703 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1704 | return ret; |
| 1705 | } |
| 1706 | |
| 1707 | int |
| 1708 | netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter, |
| 1709 | u64 off, void *data, int size) |
| 1710 | { |
| 1711 | unsigned long flags, mem_crb; |
| 1712 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1713 | uint32_t temp; |
| 1714 | uint64_t off8, val, word[2] = {0, 0}; |
| 1715 | |
| 1716 | |
| 1717 | /* |
| 1718 | * If not MN, go check for MS or invalid. |
| 1719 | */ |
| 1720 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1721 | return netxen_nic_pci_mem_read_direct(adapter, off, data, size); |
| 1722 | |
| 1723 | off8 = off & 0xfffffff8; |
| 1724 | off0[0] = off & 0x7; |
| 1725 | off0[1] = 0; |
| 1726 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1727 | sz[1] = size - sz[0]; |
| 1728 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1729 | mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET); |
| 1730 | |
| 1731 | write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1732 | netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1733 | |
| 1734 | for (i = 0; i < loop; i++) { |
| 1735 | writel((uint32_t)(off8 + (i << 3)), |
| 1736 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO)); |
| 1737 | writel(0, |
| 1738 | (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI)); |
| 1739 | writel(MIU_TA_CTL_ENABLE, |
| 1740 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1741 | writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE, |
| 1742 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1743 | |
| 1744 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1745 | temp = readl( |
| 1746 | (void *)(mem_crb+MIU_TEST_AGT_CTRL)); |
| 1747 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1748 | break; |
| 1749 | } |
| 1750 | |
| 1751 | if (j >= MAX_CTL_CHECK) { |
| 1752 | printk(KERN_ERR "%s: %s Fail to read through agent\n", |
| 1753 | __func__, netxen_nic_driver_name); |
| 1754 | break; |
| 1755 | } |
| 1756 | |
| 1757 | start = off0[i] >> 2; |
| 1758 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1759 | for (k = start; k <= end; k++) { |
| 1760 | word[i] |= ((uint64_t) readl( |
| 1761 | (void *)(mem_crb + |
| 1762 | MIU_TEST_AGT_RDDATA(k))) << (32*k)); |
| 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1767 | write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1768 | |
| 1769 | if (j >= MAX_CTL_CHECK) |
| 1770 | return -1; |
| 1771 | |
| 1772 | if (sz[0] == 8) { |
| 1773 | val = word[0]; |
| 1774 | } else { |
| 1775 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1776 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1777 | } |
| 1778 | |
| 1779 | switch (size) { |
| 1780 | case 1: |
| 1781 | *(uint8_t *)data = val; |
| 1782 | break; |
| 1783 | case 2: |
| 1784 | *(uint16_t *)data = val; |
| 1785 | break; |
| 1786 | case 4: |
| 1787 | *(uint32_t *)data = val; |
| 1788 | break; |
| 1789 | case 8: |
| 1790 | *(uint64_t *)data = val; |
| 1791 | break; |
| 1792 | } |
| 1793 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 1794 | return 0; |
| 1795 | } |
| 1796 | |
| 1797 | int |
| 1798 | netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, |
| 1799 | u64 off, void *data, int size) |
| 1800 | { |
| 1801 | int i, j, ret = 0, loop, sz[2], off0; |
| 1802 | uint32_t temp; |
| 1803 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; |
| 1804 | |
| 1805 | /* |
| 1806 | * If not MN, go check for MS or invalid. |
| 1807 | */ |
| 1808 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1809 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1810 | else { |
| 1811 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1812 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1813 | return netxen_nic_pci_mem_write_direct(adapter, |
| 1814 | off, data, size); |
| 1815 | } |
| 1816 | |
| 1817 | off8 = off & 0xfffffff8; |
| 1818 | off0 = off & 0x7; |
| 1819 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); |
| 1820 | sz[1] = size - sz[0]; |
| 1821 | loop = ((off0 + size - 1) >> 3) + 1; |
| 1822 | |
| 1823 | if ((size != 8) || (off0 != 0)) { |
| 1824 | for (i = 0; i < loop; i++) { |
| 1825 | if (adapter->pci_mem_read(adapter, off8 + (i << 3), |
| 1826 | &word[i], 8)) |
| 1827 | return -1; |
| 1828 | } |
| 1829 | } |
| 1830 | |
| 1831 | switch (size) { |
| 1832 | case 1: |
| 1833 | tmpw = *((uint8_t *)data); |
| 1834 | break; |
| 1835 | case 2: |
| 1836 | tmpw = *((uint16_t *)data); |
| 1837 | break; |
| 1838 | case 4: |
| 1839 | tmpw = *((uint32_t *)data); |
| 1840 | break; |
| 1841 | case 8: |
| 1842 | default: |
| 1843 | tmpw = *((uint64_t *)data); |
| 1844 | break; |
| 1845 | } |
| 1846 | |
| 1847 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); |
| 1848 | word[0] |= tmpw << (off0 * 8); |
| 1849 | |
| 1850 | if (loop == 2) { |
| 1851 | word[1] &= ~(~0ULL << (sz[1] * 8)); |
| 1852 | word[1] |= tmpw >> (sz[0] * 8); |
| 1853 | } |
| 1854 | |
| 1855 | /* |
| 1856 | * don't lock here - write_wx gets the lock if each time |
| 1857 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1858 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1859 | */ |
| 1860 | |
| 1861 | for (i = 0; i < loop; i++) { |
| 1862 | temp = off8 + (i << 3); |
| 1863 | adapter->hw_write_wx(adapter, |
| 1864 | mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4); |
| 1865 | temp = 0; |
| 1866 | adapter->hw_write_wx(adapter, |
| 1867 | mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4); |
| 1868 | temp = word[i] & 0xffffffff; |
| 1869 | adapter->hw_write_wx(adapter, |
| 1870 | mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4); |
| 1871 | temp = (word[i] >> 32) & 0xffffffff; |
| 1872 | adapter->hw_write_wx(adapter, |
| 1873 | mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4); |
| 1874 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
| 1875 | adapter->hw_write_wx(adapter, |
| 1876 | mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); |
| 1877 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; |
| 1878 | adapter->hw_write_wx(adapter, |
| 1879 | mem_crb+MIU_TEST_AGT_CTRL, &temp, 4); |
| 1880 | |
| 1881 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1882 | adapter->hw_read_wx(adapter, |
| 1883 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1884 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1885 | break; |
| 1886 | } |
| 1887 | |
| 1888 | if (j >= MAX_CTL_CHECK) { |
| 1889 | printk(KERN_ERR "%s: Fail to write through agent\n", |
| 1890 | netxen_nic_driver_name); |
| 1891 | ret = -1; |
| 1892 | break; |
| 1893 | } |
| 1894 | } |
| 1895 | |
| 1896 | /* |
| 1897 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1898 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1899 | */ |
| 1900 | return ret; |
| 1901 | } |
| 1902 | |
| 1903 | int |
| 1904 | netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter, |
| 1905 | u64 off, void *data, int size) |
| 1906 | { |
| 1907 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; |
| 1908 | uint32_t temp; |
| 1909 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; |
| 1910 | |
| 1911 | /* |
| 1912 | * If not MN, go check for MS or invalid. |
| 1913 | */ |
| 1914 | |
| 1915 | if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3) |
| 1916 | mem_crb = NETXEN_CRB_QDR_NET; |
| 1917 | else { |
| 1918 | mem_crb = NETXEN_CRB_DDR_NET; |
| 1919 | if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0) |
| 1920 | return netxen_nic_pci_mem_read_direct(adapter, |
| 1921 | off, data, size); |
| 1922 | } |
| 1923 | |
| 1924 | off8 = off & 0xfffffff8; |
| 1925 | off0[0] = off & 0x7; |
| 1926 | off0[1] = 0; |
| 1927 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); |
| 1928 | sz[1] = size - sz[0]; |
| 1929 | loop = ((off0[0] + size - 1) >> 3) + 1; |
| 1930 | |
| 1931 | /* |
| 1932 | * don't lock here - write_wx gets the lock if each time |
| 1933 | * write_lock_irqsave(&adapter->adapter_lock, flags); |
| 1934 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); |
| 1935 | */ |
| 1936 | |
| 1937 | for (i = 0; i < loop; i++) { |
| 1938 | temp = off8 + (i << 3); |
| 1939 | adapter->hw_write_wx(adapter, |
| 1940 | mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4); |
| 1941 | temp = 0; |
| 1942 | adapter->hw_write_wx(adapter, |
| 1943 | mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4); |
| 1944 | temp = MIU_TA_CTL_ENABLE; |
| 1945 | adapter->hw_write_wx(adapter, |
| 1946 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1947 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; |
| 1948 | adapter->hw_write_wx(adapter, |
| 1949 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1950 | |
| 1951 | for (j = 0; j < MAX_CTL_CHECK; j++) { |
| 1952 | adapter->hw_read_wx(adapter, |
| 1953 | mem_crb + MIU_TEST_AGT_CTRL, &temp, 4); |
| 1954 | if ((temp & MIU_TA_CTL_BUSY) == 0) |
| 1955 | break; |
| 1956 | } |
| 1957 | |
| 1958 | if (j >= MAX_CTL_CHECK) { |
| 1959 | printk(KERN_ERR "%s: Fail to read through agent\n", |
| 1960 | netxen_nic_driver_name); |
| 1961 | break; |
| 1962 | } |
| 1963 | |
| 1964 | start = off0[i] >> 2; |
| 1965 | end = (off0[i] + sz[i] - 1) >> 2; |
| 1966 | for (k = start; k <= end; k++) { |
| 1967 | adapter->hw_read_wx(adapter, |
| 1968 | mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4); |
| 1969 | word[i] |= ((uint64_t)temp << (32 * k)); |
| 1970 | } |
| 1971 | } |
| 1972 | |
| 1973 | /* |
| 1974 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); |
| 1975 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); |
| 1976 | */ |
| 1977 | |
| 1978 | if (j >= MAX_CTL_CHECK) |
| 1979 | return -1; |
| 1980 | |
| 1981 | if (sz[0] == 8) { |
| 1982 | val = word[0]; |
| 1983 | } else { |
| 1984 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | |
| 1985 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); |
| 1986 | } |
| 1987 | |
| 1988 | switch (size) { |
| 1989 | case 1: |
| 1990 | *(uint8_t *)data = val; |
| 1991 | break; |
| 1992 | case 2: |
| 1993 | *(uint16_t *)data = val; |
| 1994 | break; |
| 1995 | case 4: |
| 1996 | *(uint32_t *)data = val; |
| 1997 | break; |
| 1998 | case 8: |
| 1999 | *(uint64_t *)data = val; |
| 2000 | break; |
| 2001 | } |
| 2002 | DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data); |
| 2003 | return 0; |
| 2004 | } |
| 2005 | |
| 2006 | /* |
| 2007 | * Note : only 32-bit writes! |
| 2008 | */ |
| 2009 | int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, |
| 2010 | u64 off, u32 data) |
| 2011 | { |
| 2012 | adapter->hw_write_wx(adapter, off, &data, 4); |
| 2013 | |
| 2014 | return 0; |
| 2015 | } |
| 2016 | |
| 2017 | u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) |
| 2018 | { |
| 2019 | u32 temp; |
| 2020 | adapter->hw_read_wx(adapter, off, &temp, 4); |
| 2021 | return temp; |
| 2022 | } |
| 2023 | |
| 2024 | void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter, |
| 2025 | u64 off, u32 data) |
| 2026 | { |
| 2027 | adapter->hw_write_wx(adapter, off, &data, 4); |
| 2028 | } |
| 2029 | |
| 2030 | u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off) |
| 2031 | { |
| 2032 | u32 temp; |
| 2033 | adapter->hw_read_wx(adapter, off, &temp, 4); |
| 2034 | return temp; |
| 2035 | } |
| 2036 | |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 2037 | #if 0 |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2038 | int |
| 2039 | netxen_nic_erase_pxe(struct netxen_adapter *adapter) |
| 2040 | { |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 2041 | if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) { |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 2042 | printk(KERN_ERR "%s: erase pxe failed\n", |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2043 | netxen_nic_driver_name); |
| 2044 | return -1; |
| 2045 | } |
| 2046 | return 0; |
| 2047 | } |
Adrian Bunk | 993fb90 | 2007-11-05 18:07:31 +0100 | [diff] [blame] | 2048 | #endif /* 0 */ |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2049 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2050 | int netxen_nic_get_board_info(struct netxen_adapter *adapter) |
| 2051 | { |
| 2052 | int rv = 0; |
Mithlesh Thukral | 0d04761 | 2007-06-07 04:36:36 -0700 | [diff] [blame] | 2053 | int addr = NETXEN_BRDCFG_START; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2054 | struct netxen_board_info *boardinfo; |
| 2055 | int index; |
| 2056 | u32 *ptr32; |
| 2057 | |
| 2058 | boardinfo = &adapter->ahw.boardcfg; |
| 2059 | ptr32 = (u32 *) boardinfo; |
| 2060 | |
| 2061 | for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32); |
| 2062 | index++) { |
| 2063 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { |
| 2064 | return -EIO; |
| 2065 | } |
| 2066 | ptr32++; |
| 2067 | addr += sizeof(u32); |
| 2068 | } |
| 2069 | if (boardinfo->magic != NETXEN_BDINFO_MAGIC) { |
| 2070 | printk("%s: ERROR reading %s board config." |
| 2071 | " Read %x, expected %x\n", netxen_nic_driver_name, |
| 2072 | netxen_nic_driver_name, |
| 2073 | boardinfo->magic, NETXEN_BDINFO_MAGIC); |
| 2074 | rv = -1; |
| 2075 | } |
| 2076 | if (boardinfo->header_version != NETXEN_BDINFO_VERSION) { |
| 2077 | printk("%s: Unknown board config version." |
| 2078 | " Read %x, expected %x\n", netxen_nic_driver_name, |
| 2079 | boardinfo->header_version, NETXEN_BDINFO_VERSION); |
| 2080 | rv = -1; |
| 2081 | } |
| 2082 | |
| 2083 | DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type); |
| 2084 | switch ((netxen_brdtype_t) boardinfo->board_type) { |
| 2085 | case NETXEN_BRDTYPE_P2_SB35_4G: |
| 2086 | adapter->ahw.board_type = NETXEN_NIC_GBE; |
| 2087 | break; |
| 2088 | case NETXEN_BRDTYPE_P2_SB31_10G: |
| 2089 | case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ: |
| 2090 | case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ: |
| 2091 | case NETXEN_BRDTYPE_P2_SB31_10G_CX4: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 2092 | case NETXEN_BRDTYPE_P3_HMEZ: |
| 2093 | case NETXEN_BRDTYPE_P3_XG_LOM: |
| 2094 | case NETXEN_BRDTYPE_P3_10G_CX4: |
| 2095 | case NETXEN_BRDTYPE_P3_10G_CX4_LP: |
| 2096 | case NETXEN_BRDTYPE_P3_IMEZ: |
| 2097 | case NETXEN_BRDTYPE_P3_10G_SFP_PLUS: |
| 2098 | case NETXEN_BRDTYPE_P3_10G_XFP: |
| 2099 | case NETXEN_BRDTYPE_P3_10000_BASE_T: |
| 2100 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2101 | adapter->ahw.board_type = NETXEN_NIC_XGBE; |
| 2102 | break; |
| 2103 | case NETXEN_BRDTYPE_P1_BD: |
| 2104 | case NETXEN_BRDTYPE_P1_SB: |
| 2105 | case NETXEN_BRDTYPE_P1_SMAX: |
| 2106 | case NETXEN_BRDTYPE_P1_SOCK: |
Dhananjay Phadke | e4c93c8 | 2008-07-21 19:44:02 -0700 | [diff] [blame] | 2107 | case NETXEN_BRDTYPE_P3_REF_QG: |
| 2108 | case NETXEN_BRDTYPE_P3_4_GB: |
| 2109 | case NETXEN_BRDTYPE_P3_4_GB_MM: |
| 2110 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2111 | adapter->ahw.board_type = NETXEN_NIC_GBE; |
| 2112 | break; |
| 2113 | default: |
| 2114 | printk("%s: Unknown(%x)\n", netxen_nic_driver_name, |
| 2115 | boardinfo->board_type); |
| 2116 | break; |
| 2117 | } |
| 2118 | |
| 2119 | return rv; |
| 2120 | } |
| 2121 | |
| 2122 | /* NIU access sections */ |
| 2123 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2124 | int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2125 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2126 | netxen_nic_write_w0(adapter, |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 2127 | NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port), |
| 2128 | new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2129 | return 0; |
| 2130 | } |
| 2131 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2132 | int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2133 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2134 | new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE; |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 2135 | if (adapter->physical_port == 0) |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 2136 | netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 2137 | new_mtu); |
Jeff Garzik | 4790654 | 2007-11-23 21:23:36 -0500 | [diff] [blame] | 2138 | else |
Mithlesh Thukral | 595e3fb | 2007-04-20 07:53:52 -0700 | [diff] [blame] | 2139 | netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, |
| 2140 | new_mtu); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2141 | return 0; |
| 2142 | } |
| 2143 | |
| 2144 | void netxen_nic_init_niu_gb(struct netxen_adapter *adapter) |
| 2145 | { |
Dhananjay Phadke | 3276fba | 2008-06-15 22:59:44 -0700 | [diff] [blame] | 2146 | netxen_niu_gbe_init_port(adapter, adapter->physical_port); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2147 | } |
| 2148 | |
| 2149 | void |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 2150 | netxen_crb_writelit_adapter(struct netxen_adapter *adapter, |
| 2151 | unsigned long off, int data) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2152 | { |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 2153 | adapter->hw_write_wx(adapter, off, &data, 4); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2154 | } |
| 2155 | |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2156 | void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2157 | { |
Al Viro | a608ab9c | 2007-01-02 10:39:10 +0000 | [diff] [blame] | 2158 | __u32 status; |
| 2159 | __u32 autoneg; |
| 2160 | __u32 mode; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2161 | |
| 2162 | netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode); |
| 2163 | if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */ |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 2164 | if (adapter->phy_read |
| 2165 | && adapter-> |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2166 | phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2167 | NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, |
| 2168 | &status) == 0) { |
| 2169 | if (netxen_get_phy_link(status)) { |
| 2170 | switch (netxen_get_phy_speed(status)) { |
| 2171 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2172 | adapter->link_speed = SPEED_10; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2173 | break; |
| 2174 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2175 | adapter->link_speed = SPEED_100; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2176 | break; |
| 2177 | case 2: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2178 | adapter->link_speed = SPEED_1000; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2179 | break; |
| 2180 | default: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2181 | adapter->link_speed = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2182 | break; |
| 2183 | } |
| 2184 | switch (netxen_get_phy_duplex(status)) { |
| 2185 | case 0: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2186 | adapter->link_duplex = DUPLEX_HALF; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2187 | break; |
| 2188 | case 1: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2189 | adapter->link_duplex = DUPLEX_FULL; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2190 | break; |
| 2191 | default: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2192 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2193 | break; |
| 2194 | } |
Amit S. Kale | 80922fb | 2006-12-04 09:18:00 -0800 | [diff] [blame] | 2195 | if (adapter->phy_read |
| 2196 | && adapter-> |
Mithlesh Thukral | 13ba9c7 | 2007-04-20 07:53:05 -0700 | [diff] [blame] | 2197 | phy_read(adapter, |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2198 | NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG, |
Amit S. Kale | ed25ffa | 2006-12-04 09:23:25 -0800 | [diff] [blame] | 2199 | &autoneg) != 0) |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2200 | adapter->link_autoneg = autoneg; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2201 | } else |
| 2202 | goto link_down; |
| 2203 | } else { |
| 2204 | link_down: |
Mithlesh Thukral | 3176ff3 | 2007-04-20 07:52:37 -0700 | [diff] [blame] | 2205 | adapter->link_speed = -1; |
| 2206 | adapter->link_duplex = -1; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2207 | } |
| 2208 | } |
| 2209 | } |
| 2210 | |
| 2211 | void netxen_nic_flash_print(struct netxen_adapter *adapter) |
| 2212 | { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2213 | u32 fw_major = 0; |
| 2214 | u32 fw_minor = 0; |
| 2215 | u32 fw_build = 0; |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 2216 | char brd_name[NETXEN_MAX_SHORT_NAME]; |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2217 | char serial_num[32]; |
| 2218 | int i, addr; |
Mithlesh Thukral | 6d1495f | 2007-04-20 07:56:42 -0700 | [diff] [blame] | 2219 | __le32 *ptr32; |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2220 | |
| 2221 | struct netxen_board_info *board_info = &(adapter->ahw.boardcfg); |
Harvey Harrison | 8d74849 | 2008-04-22 11:48:35 -0700 | [diff] [blame] | 2222 | |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2223 | adapter->driver_mismatch = 0; |
| 2224 | |
| 2225 | ptr32 = (u32 *)&serial_num; |
| 2226 | addr = NETXEN_USER_START + |
| 2227 | offsetof(struct netxen_new_user_info, serial_num); |
| 2228 | for (i = 0; i < 8; i++) { |
| 2229 | if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) { |
| 2230 | printk("%s: ERROR reading %s board userarea.\n", |
| 2231 | netxen_nic_driver_name, |
| 2232 | netxen_nic_driver_name); |
| 2233 | adapter->driver_mismatch = 1; |
| 2234 | return; |
| 2235 | } |
| 2236 | ptr32++; |
| 2237 | addr += sizeof(u32); |
| 2238 | } |
| 2239 | |
Dhananjay Phadke | 3ce06a3 | 2008-07-21 19:44:03 -0700 | [diff] [blame^] | 2240 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4); |
| 2241 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4); |
| 2242 | adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4); |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2243 | |
| 2244 | if (adapter->portnum == 0) { |
Amit S. Kale | cb8011a | 2006-11-29 09:00:10 -0800 | [diff] [blame] | 2245 | get_brd_name_by_type(board_info->board_type, brd_name); |
| 2246 | |
| 2247 | printk("NetXen %s Board S/N %s Chip id 0x%x\n", |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2248 | brd_name, serial_num, board_info->chip_id); |
| 2249 | printk("NetXen Firmware version %d.%d.%d\n", fw_major, |
| 2250 | fw_minor, fw_build); |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2251 | } |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2252 | |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2253 | if (fw_major != _NETXEN_NIC_LINUX_MAJOR) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2254 | adapter->driver_mismatch = 1; |
| 2255 | } |
Amit S. Kale | 90f8b1d | 2007-01-22 06:38:05 -0800 | [diff] [blame] | 2256 | if (fw_minor != _NETXEN_NIC_LINUX_MINOR && |
| 2257 | fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) { |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2258 | adapter->driver_mismatch = 1; |
| 2259 | } |
Dhananjay Phadke | dcd56fd | 2008-06-15 22:59:45 -0700 | [diff] [blame] | 2260 | if (adapter->driver_mismatch) { |
| 2261 | printk(KERN_ERR "%s: driver and firmware version mismatch\n", |
| 2262 | adapter->netdev->name); |
| 2263 | return; |
| 2264 | } |
| 2265 | |
| 2266 | switch (adapter->ahw.board_type) { |
| 2267 | case NETXEN_NIC_GBE: |
| 2268 | dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n", |
| 2269 | adapter->netdev->name); |
| 2270 | break; |
| 2271 | case NETXEN_NIC_XGBE: |
| 2272 | dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n", |
| 2273 | adapter->netdev->name); |
| 2274 | break; |
| 2275 | } |
Amit S. Kale | 3d396eb | 2006-10-21 15:33:03 -0400 | [diff] [blame] | 2276 | } |
| 2277 | |