Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 3dd1247f4dee214a92b42e17818703ea71233288 / . / drivers / char / synclink_gt.c
blob: 5f6a5da696c755eb49e0232b7140424a268948ca [file] [log] [blame]
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1/*
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]2 * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26/*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45//#define DBGTBUF(info) dump_tbufs(info)
46//#define DBGRBUF(info) dump_rbufs(info)
47
48
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]49#include <linux/module.h>
50#include <linux/version.h>
51#include <linux/errno.h>
52#include <linux/signal.h>
53#include <linux/sched.h>
54#include <linux/timer.h>
55#include <linux/interrupt.h>
56#include <linux/pci.h>
57#include <linux/tty.h>
58#include <linux/tty_flip.h>
59#include <linux/serial.h>
60#include <linux/major.h>
61#include <linux/string.h>
62#include <linux/fcntl.h>
63#include <linux/ptrace.h>
64#include <linux/ioport.h>
65#include <linux/mm.h>
66#include <linux/slab.h>
67#include <linux/netdevice.h>
68#include <linux/vmalloc.h>
69#include <linux/init.h>
70#include <linux/delay.h>
71#include <linux/ioctl.h>
72#include <linux/termios.h>
73#include <linux/bitops.h>
74#include <linux/workqueue.h>
75#include <linux/hdlc.h>
Robert P. J. Day3dd12472008-02-06 01:37:17 -0800[diff] [blame^]76#include <linux/synclink.h>
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]77
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]78#include <asm/system.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/dma.h>
82#include <asm/types.h>
83#include <asm/uaccess.h>
84
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]85#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
86#define SYNCLINK_GENERIC_HDLC 1
87#else
88#define SYNCLINK_GENERIC_HDLC 0
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]89#endif
90
91/*
92 * module identification
93 */
94static char *driver_name = "SyncLink GT";
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]95static char *driver_version = "$Revision: 4.50 $";
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]96static char *tty_driver_name = "synclink_gt";
97static char *tty_dev_prefix = "ttySLG";
98MODULE_LICENSE("GPL");
99#define MGSL_MAGIC 0x5401
Paul Fulghuma077c1a2006-09-30 23:27:46 -0700[diff] [blame]100#define MAX_DEVICES 32
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]101
102static struct pci_device_id pci_table[] = {
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
Paul Fulghum6f84be82006-06-25 05:49:22 -0700[diff] [blame]104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {0,}, /* terminate list */
108};
109MODULE_DEVICE_TABLE(pci, pci_table);
110
111static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
112static void remove_one(struct pci_dev *dev);
113static struct pci_driver pci_driver = {
114 .name = "synclink_gt",
115 .id_table = pci_table,
116 .probe = init_one,
117 .remove = __devexit_p(remove_one),
118};
119
120static int pci_registered;
121
122/*
123 * module configuration and status
124 */
125static struct slgt_info *slgt_device_list;
126static int slgt_device_count;
127
128static int ttymajor;
129static int debug_level;
130static int maxframe[MAX_DEVICES];
131static int dosyncppp[MAX_DEVICES];
132
133module_param(ttymajor, int, 0);
134module_param(debug_level, int, 0);
135module_param_array(maxframe, int, NULL, 0);
136module_param_array(dosyncppp, int, NULL, 0);
137
138MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
139MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
140MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
141MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
142
143/*
144 * tty support and callbacks
145 */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]146static struct tty_driver *serial_driver;
147
148static int open(struct tty_struct *tty, struct file * filp);
149static void close(struct tty_struct *tty, struct file * filp);
150static void hangup(struct tty_struct *tty);
Alan Cox606d0992006-12-08 02:38:45 -0800[diff] [blame]151static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]152
153static int write(struct tty_struct *tty, const unsigned char *buf, int count);
154static void put_char(struct tty_struct *tty, unsigned char ch);
155static void send_xchar(struct tty_struct *tty, char ch);
156static void wait_until_sent(struct tty_struct *tty, int timeout);
157static int write_room(struct tty_struct *tty);
158static void flush_chars(struct tty_struct *tty);
159static void flush_buffer(struct tty_struct *tty);
160static void tx_hold(struct tty_struct *tty);
161static void tx_release(struct tty_struct *tty);
162
163static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
164static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
165static int chars_in_buffer(struct tty_struct *tty);
166static void throttle(struct tty_struct * tty);
167static void unthrottle(struct tty_struct * tty);
168static void set_break(struct tty_struct *tty, int break_state);
169
170/*
171 * generic HDLC support and callbacks
172 */
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]173#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]174#define dev_to_port(D) (dev_to_hdlc(D)->priv)
175static void hdlcdev_tx_done(struct slgt_info *info);
176static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
177static int hdlcdev_init(struct slgt_info *info);
178static void hdlcdev_exit(struct slgt_info *info);
179#endif
180
181
182/*
183 * device specific structures, macros and functions
184 */
185
186#define SLGT_MAX_PORTS 4
187#define SLGT_REG_SIZE 256
188
189/*
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]190 * conditional wait facility
191 */
192struct cond_wait {
193 struct cond_wait *next;
194 wait_queue_head_t q;
195 wait_queue_t wait;
196 unsigned int data;
197};
198static void init_cond_wait(struct cond_wait *w, unsigned int data);
199static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
200static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
201static void flush_cond_wait(struct cond_wait **head);
202
203/*
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]204 * DMA buffer descriptor and access macros
205 */
206struct slgt_desc
207{
Al Viro51ef9c52007-10-14 19:34:30 +0100[diff] [blame]208 __le16 count;
209 __le16 status;
210 __le32 pbuf; /* physical address of data buffer */
211 __le32 next; /* physical address of next descriptor */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]212
213 /* driver book keeping */
214 char *buf; /* virtual address of data buffer */
215 unsigned int pdesc; /* physical address of this descriptor */
216 dma_addr_t buf_dma_addr;
217};
218
219#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
220#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
221#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
222#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
223#define desc_count(a) (le16_to_cpu((a).count))
224#define desc_status(a) (le16_to_cpu((a).status))
225#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
226#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
227#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
228#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
229#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
230
231struct _input_signal_events {
232 int ri_up;
233 int ri_down;
234 int dsr_up;
235 int dsr_down;
236 int dcd_up;
237 int dcd_down;
238 int cts_up;
239 int cts_down;
240};
241
242/*
243 * device instance data structure
244 */
245struct slgt_info {
246 void *if_ptr; /* General purpose pointer (used by SPPP) */
247
248 struct slgt_info *next_device; /* device list link */
249
250 int magic;
251 int flags;
252
253 char device_name[25];
254 struct pci_dev *pdev;
255
256 int port_count; /* count of ports on adapter */
257 int adapter_num; /* adapter instance number */
258 int port_num; /* port instance number */
259
260 /* array of pointers to port contexts on this adapter */
261 struct slgt_info *port_array[SLGT_MAX_PORTS];
262
263 int count; /* count of opens */
264 int line; /* tty line instance number */
265 unsigned short close_delay;
266 unsigned short closing_wait; /* time to wait before closing */
267
268 struct mgsl_icount icount;
269
270 struct tty_struct *tty;
271 int timeout;
272 int x_char; /* xon/xoff character */
273 int blocked_open; /* # of blocked opens */
274 unsigned int read_status_mask;
275 unsigned int ignore_status_mask;
276
277 wait_queue_head_t open_wait;
278 wait_queue_head_t close_wait;
279
280 wait_queue_head_t status_event_wait_q;
281 wait_queue_head_t event_wait_q;
282 struct timer_list tx_timer;
283 struct timer_list rx_timer;
284
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]285 unsigned int gpio_present;
286 struct cond_wait *gpio_wait_q;
287
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]288 spinlock_t lock; /* spinlock for synchronizing with ISR */
289
290 struct work_struct task;
291 u32 pending_bh;
292 int bh_requested;
293 int bh_running;
294
295 int isr_overflow;
296 int irq_requested; /* nonzero if IRQ requested */
297 int irq_occurred; /* for diagnostics use */
298
299 /* device configuration */
300
301 unsigned int bus_type;
302 unsigned int irq_level;
303 unsigned long irq_flags;
304
305 unsigned char __iomem * reg_addr; /* memory mapped registers address */
306 u32 phys_reg_addr;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]307 int reg_addr_requested;
308
309 MGSL_PARAMS params; /* communications parameters */
310 u32 idle_mode;
311 u32 max_frame_size; /* as set by device config */
312
313 unsigned int raw_rx_size;
314 unsigned int if_mode;
315
316 /* device status */
317
318 int rx_enabled;
319 int rx_restart;
320
321 int tx_enabled;
322 int tx_active;
323
324 unsigned char signals; /* serial signal states */
Darren Jenkins2641dfd2006-02-28 16:59:20 -0800[diff] [blame]325 int init_error; /* initialization error */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]326
327 unsigned char *tx_buf;
328 int tx_count;
329
330 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
331 char char_buf[MAX_ASYNC_BUFFER_SIZE];
332 BOOLEAN drop_rts_on_tx_done;
333 struct _input_signal_events input_signal_events;
334
335 int dcd_chkcount; /* check counts to prevent */
336 int cts_chkcount; /* too many IRQs if a signal */
337 int dsr_chkcount; /* is floating */
338 int ri_chkcount;
339
340 char *bufs; /* virtual address of DMA buffer lists */
341 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
342
343 unsigned int rbuf_count;
344 struct slgt_desc *rbufs;
345 unsigned int rbuf_current;
346 unsigned int rbuf_index;
347
348 unsigned int tbuf_count;
349 struct slgt_desc *tbufs;
350 unsigned int tbuf_current;
351 unsigned int tbuf_start;
352
353 unsigned char *tmp_rbuf;
354 unsigned int tmp_rbuf_count;
355
356 /* SPPP/Cisco HDLC device parts */
357
358 int netcount;
359 int dosyncppp;
360 spinlock_t netlock;
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]361#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]362 struct net_device *netdev;
363#endif
364
365};
366
367static MGSL_PARAMS default_params = {
368 .mode = MGSL_MODE_HDLC,
369 .loopback = 0,
370 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
371 .encoding = HDLC_ENCODING_NRZI_SPACE,
372 .clock_speed = 0,
373 .addr_filter = 0xff,
374 .crc_type = HDLC_CRC_16_CCITT,
375 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
376 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
377 .data_rate = 9600,
378 .data_bits = 8,
379 .stop_bits = 1,
380 .parity = ASYNC_PARITY_NONE
381};
382
383
384#define BH_RECEIVE 1
385#define BH_TRANSMIT 2
386#define BH_STATUS 4
387#define IO_PIN_SHUTDOWN_LIMIT 100
388
389#define DMABUFSIZE 256
390#define DESC_LIST_SIZE 4096
391
392#define MASK_PARITY BIT1
Paul Fulghum202af6d2006-08-31 21:27:36 -0700[diff] [blame]393#define MASK_FRAMING BIT0
394#define MASK_BREAK BIT14
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]395#define MASK_OVERRUN BIT4
396
397#define GSR 0x00 /* global status */
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]398#define JCR 0x04 /* JTAG control */
399#define IODR 0x08 /* GPIO direction */
400#define IOER 0x0c /* GPIO interrupt enable */
401#define IOVR 0x10 /* GPIO value */
402#define IOSR 0x14 /* GPIO interrupt status */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]403#define TDR 0x80 /* tx data */
404#define RDR 0x80 /* rx data */
405#define TCR 0x82 /* tx control */
406#define TIR 0x84 /* tx idle */
407#define TPR 0x85 /* tx preamble */
408#define RCR 0x86 /* rx control */
409#define VCR 0x88 /* V.24 control */
410#define CCR 0x89 /* clock control */
411#define BDR 0x8a /* baud divisor */
412#define SCR 0x8c /* serial control */
413#define SSR 0x8e /* serial status */
414#define RDCSR 0x90 /* rx DMA control/status */
415#define TDCSR 0x94 /* tx DMA control/status */
416#define RDDAR 0x98 /* rx DMA descriptor address */
417#define TDDAR 0x9c /* tx DMA descriptor address */
418
419#define RXIDLE BIT14
420#define RXBREAK BIT14
421#define IRQ_TXDATA BIT13
422#define IRQ_TXIDLE BIT12
423#define IRQ_TXUNDER BIT11 /* HDLC */
424#define IRQ_RXDATA BIT10
425#define IRQ_RXIDLE BIT9 /* HDLC */
426#define IRQ_RXBREAK BIT9 /* async */
427#define IRQ_RXOVER BIT8
428#define IRQ_DSR BIT7
429#define IRQ_CTS BIT6
430#define IRQ_DCD BIT5
431#define IRQ_RI BIT4
432#define IRQ_ALL 0x3ff0
433#define IRQ_MASTER BIT0
434
435#define slgt_irq_on(info, mask) \
436 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
437#define slgt_irq_off(info, mask) \
438 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
439
440static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
441static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
442static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
443static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
444static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
445static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
446
447static void msc_set_vcr(struct slgt_info *info);
448
449static int startup(struct slgt_info *info);
450static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
451static void shutdown(struct slgt_info *info);
452static void program_hw(struct slgt_info *info);
453static void change_params(struct slgt_info *info);
454
455static int register_test(struct slgt_info *info);
456static int irq_test(struct slgt_info *info);
457static int loopback_test(struct slgt_info *info);
458static int adapter_test(struct slgt_info *info);
459
460static void reset_adapter(struct slgt_info *info);
461static void reset_port(struct slgt_info *info);
462static void async_mode(struct slgt_info *info);
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]463static void sync_mode(struct slgt_info *info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]464
465static void rx_stop(struct slgt_info *info);
466static void rx_start(struct slgt_info *info);
467static void reset_rbufs(struct slgt_info *info);
468static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
469static void rdma_reset(struct slgt_info *info);
470static int rx_get_frame(struct slgt_info *info);
471static int rx_get_buf(struct slgt_info *info);
472
473static void tx_start(struct slgt_info *info);
474static void tx_stop(struct slgt_info *info);
475static void tx_set_idle(struct slgt_info *info);
476static unsigned int free_tbuf_count(struct slgt_info *info);
477static void reset_tbufs(struct slgt_info *info);
478static void tdma_reset(struct slgt_info *info);
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]479static void tdma_start(struct slgt_info *info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]480static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
481
482static void get_signals(struct slgt_info *info);
483static void set_signals(struct slgt_info *info);
484static void enable_loopback(struct slgt_info *info);
485static void set_rate(struct slgt_info *info, u32 data_rate);
486
487static int bh_action(struct slgt_info *info);
David Howellsc4028952006-11-22 14:57:56 +0000[diff] [blame]488static void bh_handler(struct work_struct *work);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]489static void bh_transmit(struct slgt_info *info);
490static void isr_serial(struct slgt_info *info);
491static void isr_rdma(struct slgt_info *info);
492static void isr_txeom(struct slgt_info *info, unsigned short status);
493static void isr_tdma(struct slgt_info *info);
David Howells7d12e782006-10-05 14:55:46 +0100[diff] [blame]494static irqreturn_t slgt_interrupt(int irq, void *dev_id);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]495
496static int alloc_dma_bufs(struct slgt_info *info);
497static void free_dma_bufs(struct slgt_info *info);
498static int alloc_desc(struct slgt_info *info);
499static void free_desc(struct slgt_info *info);
500static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
501static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
502
503static int alloc_tmp_rbuf(struct slgt_info *info);
504static void free_tmp_rbuf(struct slgt_info *info);
505
506static void tx_timeout(unsigned long context);
507static void rx_timeout(unsigned long context);
508
509/*
510 * ioctl handlers
511 */
512static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
513static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
514static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
515static int get_txidle(struct slgt_info *info, int __user *idle_mode);
516static int set_txidle(struct slgt_info *info, int idle_mode);
517static int tx_enable(struct slgt_info *info, int enable);
518static int tx_abort(struct slgt_info *info);
519static int rx_enable(struct slgt_info *info, int enable);
520static int modem_input_wait(struct slgt_info *info,int arg);
521static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
522static int tiocmget(struct tty_struct *tty, struct file *file);
523static int tiocmset(struct tty_struct *tty, struct file *file,
524 unsigned int set, unsigned int clear);
525static void set_break(struct tty_struct *tty, int break_state);
526static int get_interface(struct slgt_info *info, int __user *if_mode);
527static int set_interface(struct slgt_info *info, int if_mode);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]528static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
529static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]531
532/*
533 * driver functions
534 */
535static void add_device(struct slgt_info *info);
536static void device_init(int adapter_num, struct pci_dev *pdev);
537static int claim_resources(struct slgt_info *info);
538static void release_resources(struct slgt_info *info);
539
540/*
541 * DEBUG OUTPUT CODE
542 */
543#ifndef DBGINFO
544#define DBGINFO(fmt)
545#endif
546#ifndef DBGERR
547#define DBGERR(fmt)
548#endif
549#ifndef DBGBH
550#define DBGBH(fmt)
551#endif
552#ifndef DBGISR
553#define DBGISR(fmt)
554#endif
555
556#ifdef DBGDATA
557static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
558{
559 int i;
560 int linecount;
561 printk("%s %s data:\n",info->device_name, label);
562 while(count) {
563 linecount = (count > 16) ? 16 : count;
564 for(i=0; i < linecount; i++)
565 printk("%02X ",(unsigned char)data[i]);
566 for(;i<17;i++)
567 printk(" ");
568 for(i=0;i<linecount;i++) {
569 if (data[i]>=040 && data[i]<=0176)
570 printk("%c",data[i]);
571 else
572 printk(".");
573 }
574 printk("\n");
575 data += linecount;
576 count -= linecount;
577 }
578}
579#else
580#define DBGDATA(info, buf, size, label)
581#endif
582
583#ifdef DBGTBUF
584static void dump_tbufs(struct slgt_info *info)
585{
586 int i;
587 printk("tbuf_current=%d\n", info->tbuf_current);
588 for (i=0 ; i < info->tbuf_count ; i++) {
589 printk("%d: count=%04X status=%04X\n",
590 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
591 }
592}
593#else
594#define DBGTBUF(info)
595#endif
596
597#ifdef DBGRBUF
598static void dump_rbufs(struct slgt_info *info)
599{
600 int i;
601 printk("rbuf_current=%d\n", info->rbuf_current);
602 for (i=0 ; i < info->rbuf_count ; i++) {
603 printk("%d: count=%04X status=%04X\n",
604 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
605 }
606}
607#else
608#define DBGRBUF(info)
609#endif
610
611static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
612{
613#ifdef SANITY_CHECK
614 if (!info) {
615 printk("null struct slgt_info for (%s) in %s\n", devname, name);
616 return 1;
617 }
618 if (info->magic != MGSL_MAGIC) {
619 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
620 return 1;
621 }
622#else
623 if (!info)
624 return 1;
625#endif
626 return 0;
627}
628
629/**
630 * line discipline callback wrappers
631 *
632 * The wrappers maintain line discipline references
633 * while calling into the line discipline.
634 *
635 * ldisc_receive_buf - pass receive data to line discipline
636 */
637static void ldisc_receive_buf(struct tty_struct *tty,
638 const __u8 *data, char *flags, int count)
639{
640 struct tty_ldisc *ld;
641 if (!tty)
642 return;
643 ld = tty_ldisc_ref(tty);
644 if (ld) {
645 if (ld->receive_buf)
646 ld->receive_buf(tty, data, flags, count);
647 tty_ldisc_deref(ld);
648 }
649}
650
651/* tty callbacks */
652
653static int open(struct tty_struct *tty, struct file *filp)
654{
655 struct slgt_info *info;
656 int retval, line;
657 unsigned long flags;
658
659 line = tty->index;
660 if ((line < 0) || (line >= slgt_device_count)) {
661 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
662 return -ENODEV;
663 }
664
665 info = slgt_device_list;
666 while(info && info->line != line)
667 info = info->next_device;
668 if (sanity_check(info, tty->name, "open"))
669 return -ENODEV;
670 if (info->init_error) {
671 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
672 return -ENODEV;
673 }
674
675 tty->driver_data = info;
676 info->tty = tty;
677
678 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
679
680 /* If port is closing, signal caller to try again */
681 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
682 if (info->flags & ASYNC_CLOSING)
683 interruptible_sleep_on(&info->close_wait);
684 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
685 -EAGAIN : -ERESTARTSYS);
686 goto cleanup;
687 }
688
689 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
690
691 spin_lock_irqsave(&info->netlock, flags);
692 if (info->netcount) {
693 retval = -EBUSY;
694 spin_unlock_irqrestore(&info->netlock, flags);
695 goto cleanup;
696 }
697 info->count++;
698 spin_unlock_irqrestore(&info->netlock, flags);
699
700 if (info->count == 1) {
701 /* 1st open on this device, init hardware */
702 retval = startup(info);
703 if (retval < 0)
704 goto cleanup;
705 }
706
707 retval = block_til_ready(tty, filp, info);
708 if (retval) {
709 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
710 goto cleanup;
711 }
712
713 retval = 0;
714
715cleanup:
716 if (retval) {
717 if (tty->count == 1)
718 info->tty = NULL; /* tty layer will release tty struct */
719 if(info->count)
720 info->count--;
721 }
722
723 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
724 return retval;
725}
726
727static void close(struct tty_struct *tty, struct file *filp)
728{
729 struct slgt_info *info = tty->driver_data;
730
731 if (sanity_check(info, tty->name, "close"))
732 return;
733 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
734
735 if (!info->count)
736 return;
737
738 if (tty_hung_up_p(filp))
739 goto cleanup;
740
741 if ((tty->count == 1) && (info->count != 1)) {
742 /*
743 * tty->count is 1 and the tty structure will be freed.
744 * info->count should be one in this case.
745 * if it's not, correct it so that the port is shutdown.
746 */
747 DBGERR(("%s close: bad refcount; tty->count=1, "
748 "info->count=%d\n", info->device_name, info->count));
749 info->count = 1;
750 }
751
752 info->count--;
753
754 /* if at least one open remaining, leave hardware active */
755 if (info->count)
756 goto cleanup;
757
758 info->flags |= ASYNC_CLOSING;
759
760 /* set tty->closing to notify line discipline to
761 * only process XON/XOFF characters. Only the N_TTY
762 * discipline appears to use this (ppp does not).
763 */
764 tty->closing = 1;
765
766 /* wait for transmit data to clear all layers */
767
768 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
769 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
770 tty_wait_until_sent(tty, info->closing_wait);
771 }
772
773 if (info->flags & ASYNC_INITIALIZED)
774 wait_until_sent(tty, info->timeout);
775 if (tty->driver->flush_buffer)
776 tty->driver->flush_buffer(tty);
777 tty_ldisc_flush(tty);
778
779 shutdown(info);
780
781 tty->closing = 0;
782 info->tty = NULL;
783
784 if (info->blocked_open) {
785 if (info->close_delay) {
786 msleep_interruptible(jiffies_to_msecs(info->close_delay));
787 }
788 wake_up_interruptible(&info->open_wait);
789 }
790
791 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
792
793 wake_up_interruptible(&info->close_wait);
794
795cleanup:
796 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
797}
798
799static void hangup(struct tty_struct *tty)
800{
801 struct slgt_info *info = tty->driver_data;
802
803 if (sanity_check(info, tty->name, "hangup"))
804 return;
805 DBGINFO(("%s hangup\n", info->device_name));
806
807 flush_buffer(tty);
808 shutdown(info);
809
810 info->count = 0;
811 info->flags &= ~ASYNC_NORMAL_ACTIVE;
812 info->tty = NULL;
813
814 wake_up_interruptible(&info->open_wait);
815}
816
Alan Cox606d0992006-12-08 02:38:45 -0800[diff] [blame]817static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]818{
819 struct slgt_info *info = tty->driver_data;
820 unsigned long flags;
821
822 DBGINFO(("%s set_termios\n", tty->driver->name));
823
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]824 change_params(info);
825
826 /* Handle transition to B0 status */
827 if (old_termios->c_cflag & CBAUD &&
828 !(tty->termios->c_cflag & CBAUD)) {
829 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
830 spin_lock_irqsave(&info->lock,flags);
831 set_signals(info);
832 spin_unlock_irqrestore(&info->lock,flags);
833 }
834
835 /* Handle transition away from B0 status */
836 if (!(old_termios->c_cflag & CBAUD) &&
837 tty->termios->c_cflag & CBAUD) {
838 info->signals |= SerialSignal_DTR;
839 if (!(tty->termios->c_cflag & CRTSCTS) ||
840 !test_bit(TTY_THROTTLED, &tty->flags)) {
841 info->signals |= SerialSignal_RTS;
842 }
843 spin_lock_irqsave(&info->lock,flags);
844 set_signals(info);
845 spin_unlock_irqrestore(&info->lock,flags);
846 }
847
848 /* Handle turning off CRTSCTS */
849 if (old_termios->c_cflag & CRTSCTS &&
850 !(tty->termios->c_cflag & CRTSCTS)) {
851 tty->hw_stopped = 0;
852 tx_release(tty);
853 }
854}
855
856static int write(struct tty_struct *tty,
857 const unsigned char *buf, int count)
858{
859 int ret = 0;
860 struct slgt_info *info = tty->driver_data;
861 unsigned long flags;
862
863 if (sanity_check(info, tty->name, "write"))
864 goto cleanup;
865 DBGINFO(("%s write count=%d\n", info->device_name, count));
866
Eric Sesterhenn326f28e92006-06-25 05:48:48 -0700[diff] [blame]867 if (!info->tx_buf)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]868 goto cleanup;
869
870 if (count > info->max_frame_size) {
871 ret = -EIO;
872 goto cleanup;
873 }
874
875 if (!count)
876 goto cleanup;
877
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]878 if (info->params.mode == MGSL_MODE_RAW ||
879 info->params.mode == MGSL_MODE_MONOSYNC ||
880 info->params.mode == MGSL_MODE_BISYNC) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]881 unsigned int bufs_needed = (count/DMABUFSIZE);
882 unsigned int bufs_free = free_tbuf_count(info);
883 if (count % DMABUFSIZE)
884 ++bufs_needed;
885 if (bufs_needed > bufs_free)
886 goto cleanup;
887 } else {
888 if (info->tx_active)
889 goto cleanup;
890 if (info->tx_count) {
891 /* send accumulated data from send_char() calls */
892 /* as frame and wait before accepting more data. */
893 tx_load(info, info->tx_buf, info->tx_count);
894 goto start;
895 }
896 }
897
898 ret = info->tx_count = count;
899 tx_load(info, buf, count);
900 goto start;
901
902start:
903 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
904 spin_lock_irqsave(&info->lock,flags);
905 if (!info->tx_active)
906 tx_start(info);
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]907 else
908 tdma_start(info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]909 spin_unlock_irqrestore(&info->lock,flags);
910 }
911
912cleanup:
913 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
914 return ret;
915}
916
917static void put_char(struct tty_struct *tty, unsigned char ch)
918{
919 struct slgt_info *info = tty->driver_data;
920 unsigned long flags;
921
922 if (sanity_check(info, tty->name, "put_char"))
923 return;
924 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
Eric Sesterhenn326f28e92006-06-25 05:48:48 -0700[diff] [blame]925 if (!info->tx_buf)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]926 return;
927 spin_lock_irqsave(&info->lock,flags);
928 if (!info->tx_active && (info->tx_count < info->max_frame_size))
929 info->tx_buf[info->tx_count++] = ch;
930 spin_unlock_irqrestore(&info->lock,flags);
931}
932
933static void send_xchar(struct tty_struct *tty, char ch)
934{
935 struct slgt_info *info = tty->driver_data;
936 unsigned long flags;
937
938 if (sanity_check(info, tty->name, "send_xchar"))
939 return;
940 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
941 info->x_char = ch;
942 if (ch) {
943 spin_lock_irqsave(&info->lock,flags);
944 if (!info->tx_enabled)
945 tx_start(info);
946 spin_unlock_irqrestore(&info->lock,flags);
947 }
948}
949
950static void wait_until_sent(struct tty_struct *tty, int timeout)
951{
952 struct slgt_info *info = tty->driver_data;
953 unsigned long orig_jiffies, char_time;
954
955 if (!info )
956 return;
957 if (sanity_check(info, tty->name, "wait_until_sent"))
958 return;
959 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
960 if (!(info->flags & ASYNC_INITIALIZED))
961 goto exit;
962
963 orig_jiffies = jiffies;
964
965 /* Set check interval to 1/5 of estimated time to
966 * send a character, and make it at least 1. The check
967 * interval should also be less than the timeout.
968 * Note: use tight timings here to satisfy the NIST-PCTS.
969 */
970
971 if (info->params.data_rate) {
972 char_time = info->timeout/(32 * 5);
973 if (!char_time)
974 char_time++;
975 } else
976 char_time = 1;
977
978 if (timeout)
979 char_time = min_t(unsigned long, char_time, timeout);
980
981 while (info->tx_active) {
982 msleep_interruptible(jiffies_to_msecs(char_time));
983 if (signal_pending(current))
984 break;
985 if (timeout && time_after(jiffies, orig_jiffies + timeout))
986 break;
987 }
988
989exit:
990 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
991}
992
993static int write_room(struct tty_struct *tty)
994{
995 struct slgt_info *info = tty->driver_data;
996 int ret;
997
998 if (sanity_check(info, tty->name, "write_room"))
999 return 0;
1000 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1001 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1002 return ret;
1003}
1004
1005static void flush_chars(struct tty_struct *tty)
1006{
1007 struct slgt_info *info = tty->driver_data;
1008 unsigned long flags;
1009
1010 if (sanity_check(info, tty->name, "flush_chars"))
1011 return;
1012 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1013
1014 if (info->tx_count <= 0 || tty->stopped ||
1015 tty->hw_stopped || !info->tx_buf)
1016 return;
1017
1018 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1019
1020 spin_lock_irqsave(&info->lock,flags);
1021 if (!info->tx_active && info->tx_count) {
1022 tx_load(info, info->tx_buf,info->tx_count);
1023 tx_start(info);
1024 }
1025 spin_unlock_irqrestore(&info->lock,flags);
1026}
1027
1028static void flush_buffer(struct tty_struct *tty)
1029{
1030 struct slgt_info *info = tty->driver_data;
1031 unsigned long flags;
1032
1033 if (sanity_check(info, tty->name, "flush_buffer"))
1034 return;
1035 DBGINFO(("%s flush_buffer\n", info->device_name));
1036
1037 spin_lock_irqsave(&info->lock,flags);
1038 if (!info->tx_active)
1039 info->tx_count = 0;
1040 spin_unlock_irqrestore(&info->lock,flags);
1041
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1042 tty_wakeup(tty);
1043}
1044
1045/*
1046 * throttle (stop) transmitter
1047 */
1048static void tx_hold(struct tty_struct *tty)
1049{
1050 struct slgt_info *info = tty->driver_data;
1051 unsigned long flags;
1052
1053 if (sanity_check(info, tty->name, "tx_hold"))
1054 return;
1055 DBGINFO(("%s tx_hold\n", info->device_name));
1056 spin_lock_irqsave(&info->lock,flags);
1057 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1058 tx_stop(info);
1059 spin_unlock_irqrestore(&info->lock,flags);
1060}
1061
1062/*
1063 * release (start) transmitter
1064 */
1065static void tx_release(struct tty_struct *tty)
1066{
1067 struct slgt_info *info = tty->driver_data;
1068 unsigned long flags;
1069
1070 if (sanity_check(info, tty->name, "tx_release"))
1071 return;
1072 DBGINFO(("%s tx_release\n", info->device_name));
1073 spin_lock_irqsave(&info->lock,flags);
1074 if (!info->tx_active && info->tx_count) {
1075 tx_load(info, info->tx_buf, info->tx_count);
1076 tx_start(info);
1077 }
1078 spin_unlock_irqrestore(&info->lock,flags);
1079}
1080
1081/*
1082 * Service an IOCTL request
1083 *
1084 * Arguments
1085 *
1086 * tty pointer to tty instance data
1087 * file pointer to associated file object for device
1088 * cmd IOCTL command code
1089 * arg command argument/context
1090 *
1091 * Return 0 if success, otherwise error code
1092 */
1093static int ioctl(struct tty_struct *tty, struct file *file,
1094 unsigned int cmd, unsigned long arg)
1095{
1096 struct slgt_info *info = tty->driver_data;
1097 struct mgsl_icount cnow; /* kernel counter temps */
1098 struct serial_icounter_struct __user *p_cuser; /* user space */
1099 unsigned long flags;
1100 void __user *argp = (void __user *)arg;
1101
1102 if (sanity_check(info, tty->name, "ioctl"))
1103 return -ENODEV;
1104 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1105
1106 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1107 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1108 if (tty->flags & (1 << TTY_IO_ERROR))
1109 return -EIO;
1110 }
1111
1112 switch (cmd) {
1113 case MGSL_IOCGPARAMS:
1114 return get_params(info, argp);
1115 case MGSL_IOCSPARAMS:
1116 return set_params(info, argp);
1117 case MGSL_IOCGTXIDLE:
1118 return get_txidle(info, argp);
1119 case MGSL_IOCSTXIDLE:
1120 return set_txidle(info, (int)arg);
1121 case MGSL_IOCTXENABLE:
1122 return tx_enable(info, (int)arg);
1123 case MGSL_IOCRXENABLE:
1124 return rx_enable(info, (int)arg);
1125 case MGSL_IOCTXABORT:
1126 return tx_abort(info);
1127 case MGSL_IOCGSTATS:
1128 return get_stats(info, argp);
1129 case MGSL_IOCWAITEVENT:
1130 return wait_mgsl_event(info, argp);
1131 case TIOCMIWAIT:
1132 return modem_input_wait(info,(int)arg);
1133 case MGSL_IOCGIF:
1134 return get_interface(info, argp);
1135 case MGSL_IOCSIF:
1136 return set_interface(info,(int)arg);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]1137 case MGSL_IOCSGPIO:
1138 return set_gpio(info, argp);
1139 case MGSL_IOCGGPIO:
1140 return get_gpio(info, argp);
1141 case MGSL_IOCWAITGPIO:
1142 return wait_gpio(info, argp);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1143 case TIOCGICOUNT:
1144 spin_lock_irqsave(&info->lock,flags);
1145 cnow = info->icount;
1146 spin_unlock_irqrestore(&info->lock,flags);
1147 p_cuser = argp;
1148 if (put_user(cnow.cts, &p_cuser->cts) ||
1149 put_user(cnow.dsr, &p_cuser->dsr) ||
1150 put_user(cnow.rng, &p_cuser->rng) ||
1151 put_user(cnow.dcd, &p_cuser->dcd) ||
1152 put_user(cnow.rx, &p_cuser->rx) ||
1153 put_user(cnow.tx, &p_cuser->tx) ||
1154 put_user(cnow.frame, &p_cuser->frame) ||
1155 put_user(cnow.overrun, &p_cuser->overrun) ||
1156 put_user(cnow.parity, &p_cuser->parity) ||
1157 put_user(cnow.brk, &p_cuser->brk) ||
1158 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1159 return -EFAULT;
1160 return 0;
1161 default:
1162 return -ENOIOCTLCMD;
1163 }
1164 return 0;
1165}
1166
1167/*
Paul Fulghum2acdb162007-05-10 22:22:43 -0700[diff] [blame]1168 * support for 32 bit ioctl calls on 64 bit systems
1169 */
1170#ifdef CONFIG_COMPAT
1171static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1172{
1173 struct MGSL_PARAMS32 tmp_params;
1174
1175 DBGINFO(("%s get_params32\n", info->device_name));
1176 tmp_params.mode = (compat_ulong_t)info->params.mode;
1177 tmp_params.loopback = info->params.loopback;
1178 tmp_params.flags = info->params.flags;
1179 tmp_params.encoding = info->params.encoding;
1180 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1181 tmp_params.addr_filter = info->params.addr_filter;
1182 tmp_params.crc_type = info->params.crc_type;
1183 tmp_params.preamble_length = info->params.preamble_length;
1184 tmp_params.preamble = info->params.preamble;
1185 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1186 tmp_params.data_bits = info->params.data_bits;
1187 tmp_params.stop_bits = info->params.stop_bits;
1188 tmp_params.parity = info->params.parity;
1189 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1190 return -EFAULT;
1191 return 0;
1192}
1193
1194static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1195{
1196 struct MGSL_PARAMS32 tmp_params;
1197
1198 DBGINFO(("%s set_params32\n", info->device_name));
1199 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1200 return -EFAULT;
1201
1202 spin_lock(&info->lock);
1203 info->params.mode = tmp_params.mode;
1204 info->params.loopback = tmp_params.loopback;
1205 info->params.flags = tmp_params.flags;
1206 info->params.encoding = tmp_params.encoding;
1207 info->params.clock_speed = tmp_params.clock_speed;
1208 info->params.addr_filter = tmp_params.addr_filter;
1209 info->params.crc_type = tmp_params.crc_type;
1210 info->params.preamble_length = tmp_params.preamble_length;
1211 info->params.preamble = tmp_params.preamble;
1212 info->params.data_rate = tmp_params.data_rate;
1213 info->params.data_bits = tmp_params.data_bits;
1214 info->params.stop_bits = tmp_params.stop_bits;
1215 info->params.parity = tmp_params.parity;
1216 spin_unlock(&info->lock);
1217
1218 change_params(info);
1219
1220 return 0;
1221}
1222
1223static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1224 unsigned int cmd, unsigned long arg)
1225{
1226 struct slgt_info *info = tty->driver_data;
1227 int rc = -ENOIOCTLCMD;
1228
1229 if (sanity_check(info, tty->name, "compat_ioctl"))
1230 return -ENODEV;
1231 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1232
1233 switch (cmd) {
1234
1235 case MGSL_IOCSPARAMS32:
1236 rc = set_params32(info, compat_ptr(arg));
1237 break;
1238
1239 case MGSL_IOCGPARAMS32:
1240 rc = get_params32(info, compat_ptr(arg));
1241 break;
1242
1243 case MGSL_IOCGPARAMS:
1244 case MGSL_IOCSPARAMS:
1245 case MGSL_IOCGTXIDLE:
1246 case MGSL_IOCGSTATS:
1247 case MGSL_IOCWAITEVENT:
1248 case MGSL_IOCGIF:
1249 case MGSL_IOCSGPIO:
1250 case MGSL_IOCGGPIO:
1251 case MGSL_IOCWAITGPIO:
1252 case TIOCGICOUNT:
1253 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1254 break;
1255
1256 case MGSL_IOCSTXIDLE:
1257 case MGSL_IOCTXENABLE:
1258 case MGSL_IOCRXENABLE:
1259 case MGSL_IOCTXABORT:
1260 case TIOCMIWAIT:
1261 case MGSL_IOCSIF:
1262 rc = ioctl(tty, file, cmd, arg);
1263 break;
1264 }
1265
1266 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1267 return rc;
1268}
1269#else
1270#define slgt_compat_ioctl NULL
1271#endif /* ifdef CONFIG_COMPAT */
1272
1273/*
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1274 * proc fs support
1275 */
1276static inline int line_info(char *buf, struct slgt_info *info)
1277{
1278 char stat_buf[30];
1279 int ret;
1280 unsigned long flags;
1281
1282 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1283 info->device_name, info->phys_reg_addr,
1284 info->irq_level, info->max_frame_size);
1285
1286 /* output current serial signal states */
1287 spin_lock_irqsave(&info->lock,flags);
1288 get_signals(info);
1289 spin_unlock_irqrestore(&info->lock,flags);
1290
1291 stat_buf[0] = 0;
1292 stat_buf[1] = 0;
1293 if (info->signals & SerialSignal_RTS)
1294 strcat(stat_buf, "|RTS");
1295 if (info->signals & SerialSignal_CTS)
1296 strcat(stat_buf, "|CTS");
1297 if (info->signals & SerialSignal_DTR)
1298 strcat(stat_buf, "|DTR");
1299 if (info->signals & SerialSignal_DSR)
1300 strcat(stat_buf, "|DSR");
1301 if (info->signals & SerialSignal_DCD)
1302 strcat(stat_buf, "|CD");
1303 if (info->signals & SerialSignal_RI)
1304 strcat(stat_buf, "|RI");
1305
1306 if (info->params.mode != MGSL_MODE_ASYNC) {
1307 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1308 info->icount.txok, info->icount.rxok);
1309 if (info->icount.txunder)
1310 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1311 if (info->icount.txabort)
1312 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1313 if (info->icount.rxshort)
1314 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1315 if (info->icount.rxlong)
1316 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1317 if (info->icount.rxover)
1318 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1319 if (info->icount.rxcrc)
1320 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1321 } else {
1322 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1323 info->icount.tx, info->icount.rx);
1324 if (info->icount.frame)
1325 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1326 if (info->icount.parity)
1327 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1328 if (info->icount.brk)
1329 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1330 if (info->icount.overrun)
1331 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1332 }
1333
1334 /* Append serial signal status to end */
1335 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1336
1337 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1338 info->tx_active,info->bh_requested,info->bh_running,
1339 info->pending_bh);
1340
1341 return ret;
1342}
1343
1344/* Called to print information about devices
1345 */
1346static int read_proc(char *page, char **start, off_t off, int count,
1347 int *eof, void *data)
1348{
1349 int len = 0, l;
1350 off_t begin = 0;
1351 struct slgt_info *info;
1352
1353 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1354
1355 info = slgt_device_list;
1356 while( info ) {
1357 l = line_info(page + len, info);
1358 len += l;
1359 if (len+begin > off+count)
1360 goto done;
1361 if (len+begin < off) {
1362 begin += len;
1363 len = 0;
1364 }
1365 info = info->next_device;
1366 }
1367
1368 *eof = 1;
1369done:
1370 if (off >= len+begin)
1371 return 0;
1372 *start = page + (off-begin);
1373 return ((count < begin+len-off) ? count : begin+len-off);
1374}
1375
1376/*
1377 * return count of bytes in transmit buffer
1378 */
1379static int chars_in_buffer(struct tty_struct *tty)
1380{
1381 struct slgt_info *info = tty->driver_data;
1382 if (sanity_check(info, tty->name, "chars_in_buffer"))
1383 return 0;
1384 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1385 return info->tx_count;
1386}
1387
1388/*
1389 * signal remote device to throttle send data (our receive data)
1390 */
1391static void throttle(struct tty_struct * tty)
1392{
1393 struct slgt_info *info = tty->driver_data;
1394 unsigned long flags;
1395
1396 if (sanity_check(info, tty->name, "throttle"))
1397 return;
1398 DBGINFO(("%s throttle\n", info->device_name));
1399 if (I_IXOFF(tty))
1400 send_xchar(tty, STOP_CHAR(tty));
1401 if (tty->termios->c_cflag & CRTSCTS) {
1402 spin_lock_irqsave(&info->lock,flags);
1403 info->signals &= ~SerialSignal_RTS;
1404 set_signals(info);
1405 spin_unlock_irqrestore(&info->lock,flags);
1406 }
1407}
1408
1409/*
1410 * signal remote device to stop throttling send data (our receive data)
1411 */
1412static void unthrottle(struct tty_struct * tty)
1413{
1414 struct slgt_info *info = tty->driver_data;
1415 unsigned long flags;
1416
1417 if (sanity_check(info, tty->name, "unthrottle"))
1418 return;
1419 DBGINFO(("%s unthrottle\n", info->device_name));
1420 if (I_IXOFF(tty)) {
1421 if (info->x_char)
1422 info->x_char = 0;
1423 else
1424 send_xchar(tty, START_CHAR(tty));
1425 }
1426 if (tty->termios->c_cflag & CRTSCTS) {
1427 spin_lock_irqsave(&info->lock,flags);
1428 info->signals |= SerialSignal_RTS;
1429 set_signals(info);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431 }
1432}
1433
1434/*
1435 * set or clear transmit break condition
1436 * break_state -1=set break condition, 0=clear
1437 */
1438static void set_break(struct tty_struct *tty, int break_state)
1439{
1440 struct slgt_info *info = tty->driver_data;
1441 unsigned short value;
1442 unsigned long flags;
1443
1444 if (sanity_check(info, tty->name, "set_break"))
1445 return;
1446 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1447
1448 spin_lock_irqsave(&info->lock,flags);
1449 value = rd_reg16(info, TCR);
1450 if (break_state == -1)
1451 value |= BIT6;
1452 else
1453 value &= ~BIT6;
1454 wr_reg16(info, TCR, value);
1455 spin_unlock_irqrestore(&info->lock,flags);
1456}
1457
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]1458#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1459
1460/**
1461 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1462 * set encoding and frame check sequence (FCS) options
1463 *
1464 * dev pointer to network device structure
1465 * encoding serial encoding setting
1466 * parity FCS setting
1467 *
1468 * returns 0 if success, otherwise error code
1469 */
1470static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1471 unsigned short parity)
1472{
1473 struct slgt_info *info = dev_to_port(dev);
1474 unsigned char new_encoding;
1475 unsigned short new_crctype;
1476
1477 /* return error if TTY interface open */
1478 if (info->count)
1479 return -EBUSY;
1480
1481 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1482
1483 switch (encoding)
1484 {
1485 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1486 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1487 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1488 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1489 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1490 default: return -EINVAL;
1491 }
1492
1493 switch (parity)
1494 {
1495 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1496 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1497 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1498 default: return -EINVAL;
1499 }
1500
1501 info->params.encoding = new_encoding;
Alexey Dobriyan53b35312006-03-24 03:16:13 -0800[diff] [blame]1502 info->params.crc_type = new_crctype;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1503
1504 /* if network interface up, reprogram hardware */
1505 if (info->netcount)
1506 program_hw(info);
1507
1508 return 0;
1509}
1510
1511/**
1512 * called by generic HDLC layer to send frame
1513 *
1514 * skb socket buffer containing HDLC frame
1515 * dev pointer to network device structure
1516 *
1517 * returns 0 if success, otherwise error code
1518 */
1519static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1520{
1521 struct slgt_info *info = dev_to_port(dev);
1522 struct net_device_stats *stats = hdlc_stats(dev);
1523 unsigned long flags;
1524
1525 DBGINFO(("%s hdlc_xmit\n", dev->name));
1526
1527 /* stop sending until this frame completes */
1528 netif_stop_queue(dev);
1529
1530 /* copy data to device buffers */
1531 info->tx_count = skb->len;
1532 tx_load(info, skb->data, skb->len);
1533
1534 /* update network statistics */
1535 stats->tx_packets++;
1536 stats->tx_bytes += skb->len;
1537
1538 /* done with socket buffer, so free it */
1539 dev_kfree_skb(skb);
1540
1541 /* save start time for transmit timeout detection */
1542 dev->trans_start = jiffies;
1543
1544 /* start hardware transmitter if necessary */
1545 spin_lock_irqsave(&info->lock,flags);
1546 if (!info->tx_active)
1547 tx_start(info);
1548 spin_unlock_irqrestore(&info->lock,flags);
1549
1550 return 0;
1551}
1552
1553/**
1554 * called by network layer when interface enabled
1555 * claim resources and initialize hardware
1556 *
1557 * dev pointer to network device structure
1558 *
1559 * returns 0 if success, otherwise error code
1560 */
1561static int hdlcdev_open(struct net_device *dev)
1562{
1563 struct slgt_info *info = dev_to_port(dev);
1564 int rc;
1565 unsigned long flags;
1566
Paul Fulghumd4c63b72007-08-22 14:01:50 -0700[diff] [blame]1567 if (!try_module_get(THIS_MODULE))
1568 return -EBUSY;
1569
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1570 DBGINFO(("%s hdlcdev_open\n", dev->name));
1571
1572 /* generic HDLC layer open processing */
1573 if ((rc = hdlc_open(dev)))
1574 return rc;
1575
1576 /* arbitrate between network and tty opens */
1577 spin_lock_irqsave(&info->netlock, flags);
1578 if (info->count != 0 || info->netcount != 0) {
1579 DBGINFO(("%s hdlc_open busy\n", dev->name));
1580 spin_unlock_irqrestore(&info->netlock, flags);
1581 return -EBUSY;
1582 }
1583 info->netcount=1;
1584 spin_unlock_irqrestore(&info->netlock, flags);
1585
1586 /* claim resources and init adapter */
1587 if ((rc = startup(info)) != 0) {
1588 spin_lock_irqsave(&info->netlock, flags);
1589 info->netcount=0;
1590 spin_unlock_irqrestore(&info->netlock, flags);
1591 return rc;
1592 }
1593
1594 /* assert DTR and RTS, apply hardware settings */
1595 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1596 program_hw(info);
1597
1598 /* enable network layer transmit */
1599 dev->trans_start = jiffies;
1600 netif_start_queue(dev);
1601
1602 /* inform generic HDLC layer of current DCD status */
1603 spin_lock_irqsave(&info->lock, flags);
1604 get_signals(info);
1605 spin_unlock_irqrestore(&info->lock, flags);
Krzysztof Halasafbeff3c2006-07-21 14:44:55 -0700[diff] [blame]1606 if (info->signals & SerialSignal_DCD)
1607 netif_carrier_on(dev);
1608 else
1609 netif_carrier_off(dev);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1610 return 0;
1611}
1612
1613/**
1614 * called by network layer when interface is disabled
1615 * shutdown hardware and release resources
1616 *
1617 * dev pointer to network device structure
1618 *
1619 * returns 0 if success, otherwise error code
1620 */
1621static int hdlcdev_close(struct net_device *dev)
1622{
1623 struct slgt_info *info = dev_to_port(dev);
1624 unsigned long flags;
1625
1626 DBGINFO(("%s hdlcdev_close\n", dev->name));
1627
1628 netif_stop_queue(dev);
1629
1630 /* shutdown adapter and release resources */
1631 shutdown(info);
1632
1633 hdlc_close(dev);
1634
1635 spin_lock_irqsave(&info->netlock, flags);
1636 info->netcount=0;
1637 spin_unlock_irqrestore(&info->netlock, flags);
1638
Paul Fulghumd4c63b72007-08-22 14:01:50 -0700[diff] [blame]1639 module_put(THIS_MODULE);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1640 return 0;
1641}
1642
1643/**
1644 * called by network layer to process IOCTL call to network device
1645 *
1646 * dev pointer to network device structure
1647 * ifr pointer to network interface request structure
1648 * cmd IOCTL command code
1649 *
1650 * returns 0 if success, otherwise error code
1651 */
1652static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1653{
1654 const size_t size = sizeof(sync_serial_settings);
1655 sync_serial_settings new_line;
1656 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1657 struct slgt_info *info = dev_to_port(dev);
1658 unsigned int flags;
1659
1660 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1661
1662 /* return error if TTY interface open */
1663 if (info->count)
1664 return -EBUSY;
1665
1666 if (cmd != SIOCWANDEV)
1667 return hdlc_ioctl(dev, ifr, cmd);
1668
1669 switch(ifr->ifr_settings.type) {
1670 case IF_GET_IFACE: /* return current sync_serial_settings */
1671
1672 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1673 if (ifr->ifr_settings.size < size) {
1674 ifr->ifr_settings.size = size; /* data size wanted */
1675 return -ENOBUFS;
1676 }
1677
1678 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1679 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1680 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1681 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1682
1683 switch (flags){
1684 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1685 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1686 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1687 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1688 default: new_line.clock_type = CLOCK_DEFAULT;
1689 }
1690
1691 new_line.clock_rate = info->params.clock_speed;
1692 new_line.loopback = info->params.loopback ? 1:0;
1693
1694 if (copy_to_user(line, &new_line, size))
1695 return -EFAULT;
1696 return 0;
1697
1698 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1699
1700 if(!capable(CAP_NET_ADMIN))
1701 return -EPERM;
1702 if (copy_from_user(&new_line, line, size))
1703 return -EFAULT;
1704
1705 switch (new_line.clock_type)
1706 {
1707 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1708 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1709 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1710 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1711 case CLOCK_DEFAULT: flags = info->params.flags &
1712 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1713 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1714 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1715 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1716 default: return -EINVAL;
1717 }
1718
1719 if (new_line.loopback != 0 && new_line.loopback != 1)
1720 return -EINVAL;
1721
1722 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1723 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1724 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1725 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1726 info->params.flags |= flags;
1727
1728 info->params.loopback = new_line.loopback;
1729
1730 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1731 info->params.clock_speed = new_line.clock_rate;
1732 else
1733 info->params.clock_speed = 0;
1734
1735 /* if network interface up, reprogram hardware */
1736 if (info->netcount)
1737 program_hw(info);
1738 return 0;
1739
1740 default:
1741 return hdlc_ioctl(dev, ifr, cmd);
1742 }
1743}
1744
1745/**
1746 * called by network layer when transmit timeout is detected
1747 *
1748 * dev pointer to network device structure
1749 */
1750static void hdlcdev_tx_timeout(struct net_device *dev)
1751{
1752 struct slgt_info *info = dev_to_port(dev);
1753 struct net_device_stats *stats = hdlc_stats(dev);
1754 unsigned long flags;
1755
1756 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1757
1758 stats->tx_errors++;
1759 stats->tx_aborted_errors++;
1760
1761 spin_lock_irqsave(&info->lock,flags);
1762 tx_stop(info);
1763 spin_unlock_irqrestore(&info->lock,flags);
1764
1765 netif_wake_queue(dev);
1766}
1767
1768/**
1769 * called by device driver when transmit completes
1770 * reenable network layer transmit if stopped
1771 *
1772 * info pointer to device instance information
1773 */
1774static void hdlcdev_tx_done(struct slgt_info *info)
1775{
1776 if (netif_queue_stopped(info->netdev))
1777 netif_wake_queue(info->netdev);
1778}
1779
1780/**
1781 * called by device driver when frame received
1782 * pass frame to network layer
1783 *
1784 * info pointer to device instance information
1785 * buf pointer to buffer contianing frame data
1786 * size count of data bytes in buf
1787 */
1788static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1789{
1790 struct sk_buff *skb = dev_alloc_skb(size);
1791 struct net_device *dev = info->netdev;
1792 struct net_device_stats *stats = hdlc_stats(dev);
1793
1794 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1795
1796 if (skb == NULL) {
1797 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1798 stats->rx_dropped++;
1799 return;
1800 }
1801
1802 memcpy(skb_put(skb, size),buf,size);
1803
1804 skb->protocol = hdlc_type_trans(skb, info->netdev);
1805
1806 stats->rx_packets++;
1807 stats->rx_bytes += size;
1808
1809 netif_rx(skb);
1810
1811 info->netdev->last_rx = jiffies;
1812}
1813
1814/**
1815 * called by device driver when adding device instance
1816 * do generic HDLC initialization
1817 *
1818 * info pointer to device instance information
1819 *
1820 * returns 0 if success, otherwise error code
1821 */
1822static int hdlcdev_init(struct slgt_info *info)
1823{
1824 int rc;
1825 struct net_device *dev;
1826 hdlc_device *hdlc;
1827
1828 /* allocate and initialize network and HDLC layer objects */
1829
1830 if (!(dev = alloc_hdlcdev(info))) {
1831 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1832 return -ENOMEM;
1833 }
1834
1835 /* for network layer reporting purposes only */
1836 dev->mem_start = info->phys_reg_addr;
1837 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1838 dev->irq = info->irq_level;
1839
1840 /* network layer callbacks and settings */
1841 dev->do_ioctl = hdlcdev_ioctl;
1842 dev->open = hdlcdev_open;
1843 dev->stop = hdlcdev_close;
1844 dev->tx_timeout = hdlcdev_tx_timeout;
1845 dev->watchdog_timeo = 10*HZ;
1846 dev->tx_queue_len = 50;
1847
1848 /* generic HDLC layer callbacks and settings */
1849 hdlc = dev_to_hdlc(dev);
1850 hdlc->attach = hdlcdev_attach;
1851 hdlc->xmit = hdlcdev_xmit;
1852
1853 /* register objects with HDLC layer */
1854 if ((rc = register_hdlc_device(dev))) {
1855 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1856 free_netdev(dev);
1857 return rc;
1858 }
1859
1860 info->netdev = dev;
1861 return 0;
1862}
1863
1864/**
1865 * called by device driver when removing device instance
1866 * do generic HDLC cleanup
1867 *
1868 * info pointer to device instance information
1869 */
1870static void hdlcdev_exit(struct slgt_info *info)
1871{
1872 unregister_hdlc_device(info->netdev);
1873 free_netdev(info->netdev);
1874 info->netdev = NULL;
1875}
1876
1877#endif /* ifdef CONFIG_HDLC */
1878
1879/*
1880 * get async data from rx DMA buffers
1881 */
1882static void rx_async(struct slgt_info *info)
1883{
1884 struct tty_struct *tty = info->tty;
1885 struct mgsl_icount *icount = &info->icount;
1886 unsigned int start, end;
1887 unsigned char *p;
1888 unsigned char status;
1889 struct slgt_desc *bufs = info->rbufs;
1890 int i, count;
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1891 int chars = 0;
1892 int stat;
1893 unsigned char ch;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1894
1895 start = end = info->rbuf_current;
1896
1897 while(desc_complete(bufs[end])) {
1898 count = desc_count(bufs[end]) - info->rbuf_index;
1899 p = bufs[end].buf + info->rbuf_index;
1900
1901 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1902 DBGDATA(info, p, count, "rx");
1903
1904 for(i=0 ; i < count; i+=2, p+=2) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1905 ch = *p;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1906 icount->rx++;
1907
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1908 stat = 0;
1909
Paul Fulghum202af6d2006-08-31 21:27:36 -0700[diff] [blame]1910 if ((status = *(p+1) & (BIT1 + BIT0))) {
1911 if (status & BIT1)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1912 icount->parity++;
Paul Fulghum202af6d2006-08-31 21:27:36 -0700[diff] [blame]1913 else if (status & BIT0)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1914 icount->frame++;
1915 /* discard char if tty control flags say so */
1916 if (status & info->ignore_status_mask)
1917 continue;
Paul Fulghum202af6d2006-08-31 21:27:36 -0700[diff] [blame]1918 if (status & BIT1)
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1919 stat = TTY_PARITY;
Paul Fulghum202af6d2006-08-31 21:27:36 -0700[diff] [blame]1920 else if (status & BIT0)
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1921 stat = TTY_FRAME;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1922 }
1923 if (tty) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1924 tty_insert_flip_char(tty, ch, stat);
1925 chars++;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1926 }
1927 }
1928
1929 if (i < count) {
1930 /* receive buffer not completed */
1931 info->rbuf_index += i;
Jiri Slaby40565f12007-02-12 00:52:31 -0800[diff] [blame]1932 mod_timer(&info->rx_timer, jiffies + 1);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1933 break;
1934 }
1935
1936 info->rbuf_index = 0;
1937 free_rbufs(info, end, end);
1938
1939 if (++end == info->rbuf_count)
1940 end = 0;
1941
1942 /* if entire list searched then no frame available */
1943 if (end == start)
1944 break;
1945 }
1946
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]1947 if (tty && chars)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1948 tty_flip_buffer_push(tty);
1949}
1950
1951/*
1952 * return next bottom half action to perform
1953 */
1954static int bh_action(struct slgt_info *info)
1955{
1956 unsigned long flags;
1957 int rc;
1958
1959 spin_lock_irqsave(&info->lock,flags);
1960
1961 if (info->pending_bh & BH_RECEIVE) {
1962 info->pending_bh &= ~BH_RECEIVE;
1963 rc = BH_RECEIVE;
1964 } else if (info->pending_bh & BH_TRANSMIT) {
1965 info->pending_bh &= ~BH_TRANSMIT;
1966 rc = BH_TRANSMIT;
1967 } else if (info->pending_bh & BH_STATUS) {
1968 info->pending_bh &= ~BH_STATUS;
1969 rc = BH_STATUS;
1970 } else {
1971 /* Mark BH routine as complete */
1972 info->bh_running = 0;
1973 info->bh_requested = 0;
1974 rc = 0;
1975 }
1976
1977 spin_unlock_irqrestore(&info->lock,flags);
1978
1979 return rc;
1980}
1981
1982/*
1983 * perform bottom half processing
1984 */
David Howellsc4028952006-11-22 14:57:56 +0000[diff] [blame]1985static void bh_handler(struct work_struct *work)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1986{
David Howellsc4028952006-11-22 14:57:56 +0000[diff] [blame]1987 struct slgt_info *info = container_of(work, struct slgt_info, task);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]1988 int action;
1989
1990 if (!info)
1991 return;
1992 info->bh_running = 1;
1993
1994 while((action = bh_action(info))) {
1995 switch (action) {
1996 case BH_RECEIVE:
1997 DBGBH(("%s bh receive\n", info->device_name));
1998 switch(info->params.mode) {
1999 case MGSL_MODE_ASYNC:
2000 rx_async(info);
2001 break;
2002 case MGSL_MODE_HDLC:
2003 while(rx_get_frame(info));
2004 break;
2005 case MGSL_MODE_RAW:
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]2006 case MGSL_MODE_MONOSYNC:
2007 case MGSL_MODE_BISYNC:
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2008 while(rx_get_buf(info));
2009 break;
2010 }
2011 /* restart receiver if rx DMA buffers exhausted */
2012 if (info->rx_restart)
2013 rx_start(info);
2014 break;
2015 case BH_TRANSMIT:
2016 bh_transmit(info);
2017 break;
2018 case BH_STATUS:
2019 DBGBH(("%s bh status\n", info->device_name));
2020 info->ri_chkcount = 0;
2021 info->dsr_chkcount = 0;
2022 info->dcd_chkcount = 0;
2023 info->cts_chkcount = 0;
2024 break;
2025 default:
2026 DBGBH(("%s unknown action\n", info->device_name));
2027 break;
2028 }
2029 }
2030 DBGBH(("%s bh_handler exit\n", info->device_name));
2031}
2032
2033static void bh_transmit(struct slgt_info *info)
2034{
2035 struct tty_struct *tty = info->tty;
2036
2037 DBGBH(("%s bh_transmit\n", info->device_name));
Jiri Slabyb963a842007-02-10 01:44:55 -0800[diff] [blame]2038 if (tty)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2039 tty_wakeup(tty);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2040}
2041
2042static void dsr_change(struct slgt_info *info)
2043{
2044 get_signals(info);
2045 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2046 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2047 slgt_irq_off(info, IRQ_DSR);
2048 return;
2049 }
2050 info->icount.dsr++;
2051 if (info->signals & SerialSignal_DSR)
2052 info->input_signal_events.dsr_up++;
2053 else
2054 info->input_signal_events.dsr_down++;
2055 wake_up_interruptible(&info->status_event_wait_q);
2056 wake_up_interruptible(&info->event_wait_q);
2057 info->pending_bh |= BH_STATUS;
2058}
2059
2060static void cts_change(struct slgt_info *info)
2061{
2062 get_signals(info);
2063 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2064 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2065 slgt_irq_off(info, IRQ_CTS);
2066 return;
2067 }
2068 info->icount.cts++;
2069 if (info->signals & SerialSignal_CTS)
2070 info->input_signal_events.cts_up++;
2071 else
2072 info->input_signal_events.cts_down++;
2073 wake_up_interruptible(&info->status_event_wait_q);
2074 wake_up_interruptible(&info->event_wait_q);
2075 info->pending_bh |= BH_STATUS;
2076
2077 if (info->flags & ASYNC_CTS_FLOW) {
2078 if (info->tty) {
2079 if (info->tty->hw_stopped) {
2080 if (info->signals & SerialSignal_CTS) {
2081 info->tty->hw_stopped = 0;
2082 info->pending_bh |= BH_TRANSMIT;
2083 return;
2084 }
2085 } else {
2086 if (!(info->signals & SerialSignal_CTS))
2087 info->tty->hw_stopped = 1;
2088 }
2089 }
2090 }
2091}
2092
2093static void dcd_change(struct slgt_info *info)
2094{
2095 get_signals(info);
2096 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2097 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2098 slgt_irq_off(info, IRQ_DCD);
2099 return;
2100 }
2101 info->icount.dcd++;
2102 if (info->signals & SerialSignal_DCD) {
2103 info->input_signal_events.dcd_up++;
2104 } else {
2105 info->input_signal_events.dcd_down++;
2106 }
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]2107#if SYNCLINK_GENERIC_HDLC
Krzysztof Halasafbeff3c2006-07-21 14:44:55 -0700[diff] [blame]2108 if (info->netcount) {
2109 if (info->signals & SerialSignal_DCD)
2110 netif_carrier_on(info->netdev);
2111 else
2112 netif_carrier_off(info->netdev);
2113 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2114#endif
2115 wake_up_interruptible(&info->status_event_wait_q);
2116 wake_up_interruptible(&info->event_wait_q);
2117 info->pending_bh |= BH_STATUS;
2118
2119 if (info->flags & ASYNC_CHECK_CD) {
2120 if (info->signals & SerialSignal_DCD)
2121 wake_up_interruptible(&info->open_wait);
2122 else {
2123 if (info->tty)
2124 tty_hangup(info->tty);
2125 }
2126 }
2127}
2128
2129static void ri_change(struct slgt_info *info)
2130{
2131 get_signals(info);
2132 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2133 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2134 slgt_irq_off(info, IRQ_RI);
2135 return;
2136 }
2137 info->icount.dcd++;
2138 if (info->signals & SerialSignal_RI) {
2139 info->input_signal_events.ri_up++;
2140 } else {
2141 info->input_signal_events.ri_down++;
2142 }
2143 wake_up_interruptible(&info->status_event_wait_q);
2144 wake_up_interruptible(&info->event_wait_q);
2145 info->pending_bh |= BH_STATUS;
2146}
2147
2148static void isr_serial(struct slgt_info *info)
2149{
2150 unsigned short status = rd_reg16(info, SSR);
2151
2152 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2153
2154 wr_reg16(info, SSR, status); /* clear pending */
2155
2156 info->irq_occurred = 1;
2157
2158 if (info->params.mode == MGSL_MODE_ASYNC) {
2159 if (status & IRQ_TXIDLE) {
2160 if (info->tx_count)
2161 isr_txeom(info, status);
2162 }
2163 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2164 info->icount.brk++;
2165 /* process break detection if tty control allows */
2166 if (info->tty) {
2167 if (!(status & info->ignore_status_mask)) {
2168 if (info->read_status_mask & MASK_BREAK) {
Alan Cox33f0f882006-01-09 20:54:13 -0800[diff] [blame]2169 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2170 if (info->flags & ASYNC_SAK)
2171 do_SAK(info->tty);
2172 }
2173 }
2174 }
2175 }
2176 } else {
2177 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2178 isr_txeom(info, status);
2179
2180 if (status & IRQ_RXIDLE) {
2181 if (status & RXIDLE)
2182 info->icount.rxidle++;
2183 else
2184 info->icount.exithunt++;
2185 wake_up_interruptible(&info->event_wait_q);
2186 }
2187
2188 if (status & IRQ_RXOVER)
2189 rx_start(info);
2190 }
2191
2192 if (status & IRQ_DSR)
2193 dsr_change(info);
2194 if (status & IRQ_CTS)
2195 cts_change(info);
2196 if (status & IRQ_DCD)
2197 dcd_change(info);
2198 if (status & IRQ_RI)
2199 ri_change(info);
2200}
2201
2202static void isr_rdma(struct slgt_info *info)
2203{
2204 unsigned int status = rd_reg32(info, RDCSR);
2205
2206 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2207
2208 /* RDCSR (rx DMA control/status)
2209 *
2210 * 31..07 reserved
2211 * 06 save status byte to DMA buffer
2212 * 05 error
2213 * 04 eol (end of list)
2214 * 03 eob (end of buffer)
2215 * 02 IRQ enable
2216 * 01 reset
2217 * 00 enable
2218 */
2219 wr_reg32(info, RDCSR, status); /* clear pending */
2220
2221 if (status & (BIT5 + BIT4)) {
2222 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2223 info->rx_restart = 1;
2224 }
2225 info->pending_bh |= BH_RECEIVE;
2226}
2227
2228static void isr_tdma(struct slgt_info *info)
2229{
2230 unsigned int status = rd_reg32(info, TDCSR);
2231
2232 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2233
2234 /* TDCSR (tx DMA control/status)
2235 *
2236 * 31..06 reserved
2237 * 05 error
2238 * 04 eol (end of list)
2239 * 03 eob (end of buffer)
2240 * 02 IRQ enable
2241 * 01 reset
2242 * 00 enable
2243 */
2244 wr_reg32(info, TDCSR, status); /* clear pending */
2245
2246 if (status & (BIT5 + BIT4 + BIT3)) {
2247 // another transmit buffer has completed
2248 // run bottom half to get more send data from user
2249 info->pending_bh |= BH_TRANSMIT;
2250 }
2251}
2252
2253static void isr_txeom(struct slgt_info *info, unsigned short status)
2254{
2255 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2256
2257 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2258 tdma_reset(info);
2259 reset_tbufs(info);
2260 if (status & IRQ_TXUNDER) {
2261 unsigned short val = rd_reg16(info, TCR);
2262 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2263 wr_reg16(info, TCR, val); /* clear reset bit */
2264 }
2265
2266 if (info->tx_active) {
2267 if (info->params.mode != MGSL_MODE_ASYNC) {
2268 if (status & IRQ_TXUNDER)
2269 info->icount.txunder++;
2270 else if (status & IRQ_TXIDLE)
2271 info->icount.txok++;
2272 }
2273
2274 info->tx_active = 0;
2275 info->tx_count = 0;
2276
2277 del_timer(&info->tx_timer);
2278
2279 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2280 info->signals &= ~SerialSignal_RTS;
2281 info->drop_rts_on_tx_done = 0;
2282 set_signals(info);
2283 }
2284
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]2285#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2286 if (info->netcount)
2287 hdlcdev_tx_done(info);
2288 else
2289#endif
2290 {
2291 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2292 tx_stop(info);
2293 return;
2294 }
2295 info->pending_bh |= BH_TRANSMIT;
2296 }
2297 }
2298}
2299
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]2300static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2301{
2302 struct cond_wait *w, *prev;
2303
2304 /* wake processes waiting for specific transitions */
2305 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2306 if (w->data & changed) {
2307 w->data = state;
2308 wake_up_interruptible(&w->q);
2309 if (prev != NULL)
2310 prev->next = w->next;
2311 else
2312 info->gpio_wait_q = w->next;
2313 } else
2314 prev = w;
2315 }
2316}
2317
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2318/* interrupt service routine
2319 *
2320 * irq interrupt number
2321 * dev_id device ID supplied during interrupt registration
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2322 */
David Howells7d12e782006-10-05 14:55:46 +0100[diff] [blame]2323static irqreturn_t slgt_interrupt(int irq, void *dev_id)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2324{
2325 struct slgt_info *info;
2326 unsigned int gsr;
2327 unsigned int i;
2328
2329 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2330
2331 info = dev_id;
2332 if (!info)
2333 return IRQ_NONE;
2334
2335 spin_lock(&info->lock);
2336
2337 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2338 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2339 info->irq_occurred = 1;
2340 for(i=0; i < info->port_count ; i++) {
2341 if (info->port_array[i] == NULL)
2342 continue;
2343 if (gsr & (BIT8 << i))
2344 isr_serial(info->port_array[i]);
2345 if (gsr & (BIT16 << (i*2)))
2346 isr_rdma(info->port_array[i]);
2347 if (gsr & (BIT17 << (i*2)))
2348 isr_tdma(info->port_array[i]);
2349 }
2350 }
2351
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]2352 if (info->gpio_present) {
2353 unsigned int state;
2354 unsigned int changed;
2355 while ((changed = rd_reg32(info, IOSR)) != 0) {
2356 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2357 /* read latched state of GPIO signals */
2358 state = rd_reg32(info, IOVR);
2359 /* clear pending GPIO interrupt bits */
2360 wr_reg32(info, IOSR, changed);
2361 for (i=0 ; i < info->port_count ; i++) {
2362 if (info->port_array[i] != NULL)
2363 isr_gpio(info->port_array[i], changed, state);
2364 }
2365 }
2366 }
2367
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2368 for(i=0; i < info->port_count ; i++) {
2369 struct slgt_info *port = info->port_array[i];
2370
2371 if (port && (port->count || port->netcount) &&
2372 port->pending_bh && !port->bh_running &&
2373 !port->bh_requested) {
2374 DBGISR(("%s bh queued\n", port->device_name));
2375 schedule_work(&port->task);
2376 port->bh_requested = 1;
2377 }
2378 }
2379
2380 spin_unlock(&info->lock);
2381
2382 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2383 return IRQ_HANDLED;
2384}
2385
2386static int startup(struct slgt_info *info)
2387{
2388 DBGINFO(("%s startup\n", info->device_name));
2389
2390 if (info->flags & ASYNC_INITIALIZED)
2391 return 0;
2392
2393 if (!info->tx_buf) {
2394 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2395 if (!info->tx_buf) {
2396 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2397 return -ENOMEM;
2398 }
2399 }
2400
2401 info->pending_bh = 0;
2402
2403 memset(&info->icount, 0, sizeof(info->icount));
2404
2405 /* program hardware for current parameters */
2406 change_params(info);
2407
2408 if (info->tty)
2409 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2410
2411 info->flags |= ASYNC_INITIALIZED;
2412
2413 return 0;
2414}
2415
2416/*
2417 * called by close() and hangup() to shutdown hardware
2418 */
2419static void shutdown(struct slgt_info *info)
2420{
2421 unsigned long flags;
2422
2423 if (!(info->flags & ASYNC_INITIALIZED))
2424 return;
2425
2426 DBGINFO(("%s shutdown\n", info->device_name));
2427
2428 /* clear status wait queue because status changes */
2429 /* can't happen after shutting down the hardware */
2430 wake_up_interruptible(&info->status_event_wait_q);
2431 wake_up_interruptible(&info->event_wait_q);
2432
2433 del_timer_sync(&info->tx_timer);
2434 del_timer_sync(&info->rx_timer);
2435
2436 kfree(info->tx_buf);
2437 info->tx_buf = NULL;
2438
2439 spin_lock_irqsave(&info->lock,flags);
2440
2441 tx_stop(info);
2442 rx_stop(info);
2443
2444 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2445
2446 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2447 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2448 set_signals(info);
2449 }
2450
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]2451 flush_cond_wait(&info->gpio_wait_q);
2452
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2453 spin_unlock_irqrestore(&info->lock,flags);
2454
2455 if (info->tty)
2456 set_bit(TTY_IO_ERROR, &info->tty->flags);
2457
2458 info->flags &= ~ASYNC_INITIALIZED;
2459}
2460
2461static void program_hw(struct slgt_info *info)
2462{
2463 unsigned long flags;
2464
2465 spin_lock_irqsave(&info->lock,flags);
2466
2467 rx_stop(info);
2468 tx_stop(info);
2469
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]2470 if (info->params.mode != MGSL_MODE_ASYNC ||
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2471 info->netcount)
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]2472 sync_mode(info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2473 else
2474 async_mode(info);
2475
2476 set_signals(info);
2477
2478 info->dcd_chkcount = 0;
2479 info->cts_chkcount = 0;
2480 info->ri_chkcount = 0;
2481 info->dsr_chkcount = 0;
2482
2483 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2484 get_signals(info);
2485
2486 if (info->netcount ||
2487 (info->tty && info->tty->termios->c_cflag & CREAD))
2488 rx_start(info);
2489
2490 spin_unlock_irqrestore(&info->lock,flags);
2491}
2492
2493/*
2494 * reconfigure adapter based on new parameters
2495 */
2496static void change_params(struct slgt_info *info)
2497{
2498 unsigned cflag;
2499 int bits_per_char;
2500
2501 if (!info->tty || !info->tty->termios)
2502 return;
2503 DBGINFO(("%s change_params\n", info->device_name));
2504
2505 cflag = info->tty->termios->c_cflag;
2506
2507 /* if B0 rate (hangup) specified then negate DTR and RTS */
2508 /* otherwise assert DTR and RTS */
2509 if (cflag & CBAUD)
2510 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2511 else
2512 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2513
2514 /* byte size and parity */
2515
2516 switch (cflag & CSIZE) {
2517 case CS5: info->params.data_bits = 5; break;
2518 case CS6: info->params.data_bits = 6; break;
2519 case CS7: info->params.data_bits = 7; break;
2520 case CS8: info->params.data_bits = 8; break;
2521 default: info->params.data_bits = 7; break;
2522 }
2523
2524 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2525
2526 if (cflag & PARENB)
2527 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2528 else
2529 info->params.parity = ASYNC_PARITY_NONE;
2530
2531 /* calculate number of jiffies to transmit a full
2532 * FIFO (32 bytes) at specified data rate
2533 */
2534 bits_per_char = info->params.data_bits +
2535 info->params.stop_bits + 1;
2536
2537 info->params.data_rate = tty_get_baud_rate(info->tty);
2538
2539 if (info->params.data_rate) {
2540 info->timeout = (32*HZ*bits_per_char) /
2541 info->params.data_rate;
2542 }
2543 info->timeout += HZ/50; /* Add .02 seconds of slop */
2544
2545 if (cflag & CRTSCTS)
2546 info->flags |= ASYNC_CTS_FLOW;
2547 else
2548 info->flags &= ~ASYNC_CTS_FLOW;
2549
2550 if (cflag & CLOCAL)
2551 info->flags &= ~ASYNC_CHECK_CD;
2552 else
2553 info->flags |= ASYNC_CHECK_CD;
2554
2555 /* process tty input control flags */
2556
2557 info->read_status_mask = IRQ_RXOVER;
2558 if (I_INPCK(info->tty))
2559 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2560 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2561 info->read_status_mask |= MASK_BREAK;
2562 if (I_IGNPAR(info->tty))
2563 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2564 if (I_IGNBRK(info->tty)) {
2565 info->ignore_status_mask |= MASK_BREAK;
2566 /* If ignoring parity and break indicators, ignore
2567 * overruns too. (For real raw support).
2568 */
2569 if (I_IGNPAR(info->tty))
2570 info->ignore_status_mask |= MASK_OVERRUN;
2571 }
2572
2573 program_hw(info);
2574}
2575
2576static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2577{
2578 DBGINFO(("%s get_stats\n", info->device_name));
2579 if (!user_icount) {
2580 memset(&info->icount, 0, sizeof(info->icount));
2581 } else {
2582 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2583 return -EFAULT;
2584 }
2585 return 0;
2586}
2587
2588static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2589{
2590 DBGINFO(("%s get_params\n", info->device_name));
2591 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2592 return -EFAULT;
2593 return 0;
2594}
2595
2596static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2597{
2598 unsigned long flags;
2599 MGSL_PARAMS tmp_params;
2600
2601 DBGINFO(("%s set_params\n", info->device_name));
2602 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2603 return -EFAULT;
2604
2605 spin_lock_irqsave(&info->lock, flags);
2606 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2607 spin_unlock_irqrestore(&info->lock, flags);
2608
2609 change_params(info);
2610
2611 return 0;
2612}
2613
2614static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2615{
2616 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2617 if (put_user(info->idle_mode, idle_mode))
2618 return -EFAULT;
2619 return 0;
2620}
2621
2622static int set_txidle(struct slgt_info *info, int idle_mode)
2623{
2624 unsigned long flags;
2625 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2626 spin_lock_irqsave(&info->lock,flags);
2627 info->idle_mode = idle_mode;
Paul Fulghum643f3312006-06-25 05:49:20 -0700[diff] [blame]2628 if (info->params.mode != MGSL_MODE_ASYNC)
2629 tx_set_idle(info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2630 spin_unlock_irqrestore(&info->lock,flags);
2631 return 0;
2632}
2633
2634static int tx_enable(struct slgt_info *info, int enable)
2635{
2636 unsigned long flags;
2637 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2638 spin_lock_irqsave(&info->lock,flags);
2639 if (enable) {
2640 if (!info->tx_enabled)
2641 tx_start(info);
2642 } else {
2643 if (info->tx_enabled)
2644 tx_stop(info);
2645 }
2646 spin_unlock_irqrestore(&info->lock,flags);
2647 return 0;
2648}
2649
2650/*
2651 * abort transmit HDLC frame
2652 */
2653static int tx_abort(struct slgt_info *info)
2654{
2655 unsigned long flags;
2656 DBGINFO(("%s tx_abort\n", info->device_name));
2657 spin_lock_irqsave(&info->lock,flags);
2658 tdma_reset(info);
2659 spin_unlock_irqrestore(&info->lock,flags);
2660 return 0;
2661}
2662
2663static int rx_enable(struct slgt_info *info, int enable)
2664{
2665 unsigned long flags;
2666 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2667 spin_lock_irqsave(&info->lock,flags);
2668 if (enable) {
2669 if (!info->rx_enabled)
2670 rx_start(info);
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]2671 else if (enable == 2) {
2672 /* force hunt mode (write 1 to RCR[3]) */
2673 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2674 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2675 } else {
2676 if (info->rx_enabled)
2677 rx_stop(info);
2678 }
2679 spin_unlock_irqrestore(&info->lock,flags);
2680 return 0;
2681}
2682
2683/*
2684 * wait for specified event to occur
2685 */
2686static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2687{
2688 unsigned long flags;
2689 int s;
2690 int rc=0;
2691 struct mgsl_icount cprev, cnow;
2692 int events;
2693 int mask;
2694 struct _input_signal_events oldsigs, newsigs;
2695 DECLARE_WAITQUEUE(wait, current);
2696
2697 if (get_user(mask, mask_ptr))
2698 return -EFAULT;
2699
2700 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2701
2702 spin_lock_irqsave(&info->lock,flags);
2703
2704 /* return immediately if state matches requested events */
2705 get_signals(info);
2706 s = info->signals;
2707
2708 events = mask &
2709 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2710 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2711 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2712 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2713 if (events) {
2714 spin_unlock_irqrestore(&info->lock,flags);
2715 goto exit;
2716 }
2717
2718 /* save current irq counts */
2719 cprev = info->icount;
2720 oldsigs = info->input_signal_events;
2721
2722 /* enable hunt and idle irqs if needed */
2723 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2724 unsigned short val = rd_reg16(info, SCR);
2725 if (!(val & IRQ_RXIDLE))
2726 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2727 }
2728
2729 set_current_state(TASK_INTERRUPTIBLE);
2730 add_wait_queue(&info->event_wait_q, &wait);
2731
2732 spin_unlock_irqrestore(&info->lock,flags);
2733
2734 for(;;) {
2735 schedule();
2736 if (signal_pending(current)) {
2737 rc = -ERESTARTSYS;
2738 break;
2739 }
2740
2741 /* get current irq counts */
2742 spin_lock_irqsave(&info->lock,flags);
2743 cnow = info->icount;
2744 newsigs = info->input_signal_events;
2745 set_current_state(TASK_INTERRUPTIBLE);
2746 spin_unlock_irqrestore(&info->lock,flags);
2747
2748 /* if no change, wait aborted for some reason */
2749 if (newsigs.dsr_up == oldsigs.dsr_up &&
2750 newsigs.dsr_down == oldsigs.dsr_down &&
2751 newsigs.dcd_up == oldsigs.dcd_up &&
2752 newsigs.dcd_down == oldsigs.dcd_down &&
2753 newsigs.cts_up == oldsigs.cts_up &&
2754 newsigs.cts_down == oldsigs.cts_down &&
2755 newsigs.ri_up == oldsigs.ri_up &&
2756 newsigs.ri_down == oldsigs.ri_down &&
2757 cnow.exithunt == cprev.exithunt &&
2758 cnow.rxidle == cprev.rxidle) {
2759 rc = -EIO;
2760 break;
2761 }
2762
2763 events = mask &
2764 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2765 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2766 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2767 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2768 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2769 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2770 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2771 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2772 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2773 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2774 if (events)
2775 break;
2776
2777 cprev = cnow;
2778 oldsigs = newsigs;
2779 }
2780
2781 remove_wait_queue(&info->event_wait_q, &wait);
2782 set_current_state(TASK_RUNNING);
2783
2784
2785 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2786 spin_lock_irqsave(&info->lock,flags);
2787 if (!waitqueue_active(&info->event_wait_q)) {
2788 /* disable enable exit hunt mode/idle rcvd IRQs */
2789 wr_reg16(info, SCR,
2790 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2791 }
2792 spin_unlock_irqrestore(&info->lock,flags);
2793 }
2794exit:
2795 if (rc == 0)
2796 rc = put_user(events, mask_ptr);
2797 return rc;
2798}
2799
2800static int get_interface(struct slgt_info *info, int __user *if_mode)
2801{
2802 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2803 if (put_user(info->if_mode, if_mode))
2804 return -EFAULT;
2805 return 0;
2806}
2807
2808static int set_interface(struct slgt_info *info, int if_mode)
2809{
2810 unsigned long flags;
Paul Fulghum35fbd392006-01-18 17:42:24 -0800[diff] [blame]2811 unsigned short val;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]2812
2813 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2814 spin_lock_irqsave(&info->lock,flags);
2815 info->if_mode = if_mode;
2816
2817 msc_set_vcr(info);
2818
2819 /* TCR (tx control) 07 1=RTS driver control */
2820 val = rd_reg16(info, TCR);
2821 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2822 val |= BIT7;
2823 else
2824 val &= ~BIT7;
2825 wr_reg16(info, TCR, val);
2826
2827 spin_unlock_irqrestore(&info->lock,flags);
2828 return 0;
2829}
2830
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]2831/*
2832 * set general purpose IO pin state and direction
2833 *
2834 * user_gpio fields:
2835 * state each bit indicates a pin state
2836 * smask set bit indicates pin state to set
2837 * dir each bit indicates a pin direction (0=input, 1=output)
2838 * dmask set bit indicates pin direction to set
2839 */
2840static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2841{
2842 unsigned long flags;
2843 struct gpio_desc gpio;
2844 __u32 data;
2845
2846 if (!info->gpio_present)
2847 return -EINVAL;
2848 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2849 return -EFAULT;
2850 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2851 info->device_name, gpio.state, gpio.smask,
2852 gpio.dir, gpio.dmask));
2853
2854 spin_lock_irqsave(&info->lock,flags);
2855 if (gpio.dmask) {
2856 data = rd_reg32(info, IODR);
2857 data |= gpio.dmask & gpio.dir;
2858 data &= ~(gpio.dmask & ~gpio.dir);
2859 wr_reg32(info, IODR, data);
2860 }
2861 if (gpio.smask) {
2862 data = rd_reg32(info, IOVR);
2863 data |= gpio.smask & gpio.state;
2864 data &= ~(gpio.smask & ~gpio.state);
2865 wr_reg32(info, IOVR, data);
2866 }
2867 spin_unlock_irqrestore(&info->lock,flags);
2868
2869 return 0;
2870}
2871
2872/*
2873 * get general purpose IO pin state and direction
2874 */
2875static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2876{
2877 struct gpio_desc gpio;
2878 if (!info->gpio_present)
2879 return -EINVAL;
2880 gpio.state = rd_reg32(info, IOVR);
2881 gpio.smask = 0xffffffff;
2882 gpio.dir = rd_reg32(info, IODR);
2883 gpio.dmask = 0xffffffff;
2884 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2885 return -EFAULT;
2886 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2887 info->device_name, gpio.state, gpio.dir));
2888 return 0;
2889}
2890
2891/*
2892 * conditional wait facility
2893 */
2894static void init_cond_wait(struct cond_wait *w, unsigned int data)
2895{
2896 init_waitqueue_head(&w->q);
2897 init_waitqueue_entry(&w->wait, current);
2898 w->data = data;
2899}
2900
2901static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2902{
2903 set_current_state(TASK_INTERRUPTIBLE);
2904 add_wait_queue(&w->q, &w->wait);
2905 w->next = *head;
2906 *head = w;
2907}
2908
2909static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2910{
2911 struct cond_wait *w, *prev;
2912 remove_wait_queue(&cw->q, &cw->wait);
2913 set_current_state(TASK_RUNNING);
2914 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2915 if (w == cw) {
2916 if (prev != NULL)
2917 prev->next = w->next;
2918 else
2919 *head = w->next;
2920 break;
2921 }
2922 }
2923}
2924
2925static void flush_cond_wait(struct cond_wait **head)
2926{
2927 while (*head != NULL) {
2928 wake_up_interruptible(&(*head)->q);
2929 *head = (*head)->next;
2930 }
2931}
2932
2933/*
2934 * wait for general purpose I/O pin(s) to enter specified state
2935 *
2936 * user_gpio fields:
2937 * state - bit indicates target pin state
2938 * smask - set bit indicates watched pin
2939 *
2940 * The wait ends when at least one watched pin enters the specified
2941 * state. When 0 (no error) is returned, user_gpio->state is set to the
2942 * state of all GPIO pins when the wait ends.
2943 *
2944 * Note: Each pin may be a dedicated input, dedicated output, or
2945 * configurable input/output. The number and configuration of pins
2946 * varies with the specific adapter model. Only input pins (dedicated
2947 * or configured) can be monitored with this function.
2948 */
2949static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2950{
2951 unsigned long flags;
2952 int rc = 0;
2953 struct gpio_desc gpio;
2954 struct cond_wait wait;
2955 u32 state;
2956
2957 if (!info->gpio_present)
2958 return -EINVAL;
2959 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2960 return -EFAULT;
2961 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2962 info->device_name, gpio.state, gpio.smask));
2963 /* ignore output pins identified by set IODR bit */
2964 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2965 return -EINVAL;
2966 init_cond_wait(&wait, gpio.smask);
2967
2968 spin_lock_irqsave(&info->lock, flags);
2969 /* enable interrupts for watched pins */
2970 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2971 /* get current pin states */
2972 state = rd_reg32(info, IOVR);
2973
2974 if (gpio.smask & ~(state ^ gpio.state)) {
2975 /* already in target state */
2976 gpio.state = state;
2977 } else {
2978 /* wait for target state */
2979 add_cond_wait(&info->gpio_wait_q, &wait);
2980 spin_unlock_irqrestore(&info->lock, flags);
2981 schedule();
2982 if (signal_pending(current))
2983 rc = -ERESTARTSYS;
2984 else
2985 gpio.state = wait.data;
2986 spin_lock_irqsave(&info->lock, flags);
2987 remove_cond_wait(&info->gpio_wait_q, &wait);
2988 }
2989
2990 /* disable all GPIO interrupts if no waiting processes */
2991 if (info->gpio_wait_q == NULL)
2992 wr_reg32(info, IOER, 0);
2993 spin_unlock_irqrestore(&info->lock,flags);
2994
2995 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2996 rc = -EFAULT;
2997 return rc;
2998}
2999
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3000static int modem_input_wait(struct slgt_info *info,int arg)
3001{
3002 unsigned long flags;
3003 int rc;
3004 struct mgsl_icount cprev, cnow;
3005 DECLARE_WAITQUEUE(wait, current);
3006
3007 /* save current irq counts */
3008 spin_lock_irqsave(&info->lock,flags);
3009 cprev = info->icount;
3010 add_wait_queue(&info->status_event_wait_q, &wait);
3011 set_current_state(TASK_INTERRUPTIBLE);
3012 spin_unlock_irqrestore(&info->lock,flags);
3013
3014 for(;;) {
3015 schedule();
3016 if (signal_pending(current)) {
3017 rc = -ERESTARTSYS;
3018 break;
3019 }
3020
3021 /* get new irq counts */
3022 spin_lock_irqsave(&info->lock,flags);
3023 cnow = info->icount;
3024 set_current_state(TASK_INTERRUPTIBLE);
3025 spin_unlock_irqrestore(&info->lock,flags);
3026
3027 /* if no change, wait aborted for some reason */
3028 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3029 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3030 rc = -EIO;
3031 break;
3032 }
3033
3034 /* check for change in caller specified modem input */
3035 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3036 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3037 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3038 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3039 rc = 0;
3040 break;
3041 }
3042
3043 cprev = cnow;
3044 }
3045 remove_wait_queue(&info->status_event_wait_q, &wait);
3046 set_current_state(TASK_RUNNING);
3047 return rc;
3048}
3049
3050/*
3051 * return state of serial control and status signals
3052 */
3053static int tiocmget(struct tty_struct *tty, struct file *file)
3054{
3055 struct slgt_info *info = tty->driver_data;
3056 unsigned int result;
3057 unsigned long flags;
3058
3059 spin_lock_irqsave(&info->lock,flags);
3060 get_signals(info);
3061 spin_unlock_irqrestore(&info->lock,flags);
3062
3063 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3064 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3065 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3066 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3067 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3068 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3069
3070 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3071 return result;
3072}
3073
3074/*
3075 * set modem control signals (DTR/RTS)
3076 *
3077 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3078 * TIOCMSET = set/clear signal values
3079 * value bit mask for command
3080 */
3081static int tiocmset(struct tty_struct *tty, struct file *file,
3082 unsigned int set, unsigned int clear)
3083{
3084 struct slgt_info *info = tty->driver_data;
3085 unsigned long flags;
3086
3087 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3088
3089 if (set & TIOCM_RTS)
3090 info->signals |= SerialSignal_RTS;
3091 if (set & TIOCM_DTR)
3092 info->signals |= SerialSignal_DTR;
3093 if (clear & TIOCM_RTS)
3094 info->signals &= ~SerialSignal_RTS;
3095 if (clear & TIOCM_DTR)
3096 info->signals &= ~SerialSignal_DTR;
3097
3098 spin_lock_irqsave(&info->lock,flags);
3099 set_signals(info);
3100 spin_unlock_irqrestore(&info->lock,flags);
3101 return 0;
3102}
3103
3104/*
3105 * block current process until the device is ready to open
3106 */
3107static int block_til_ready(struct tty_struct *tty, struct file *filp,
3108 struct slgt_info *info)
3109{
3110 DECLARE_WAITQUEUE(wait, current);
3111 int retval;
3112 int do_clocal = 0, extra_count = 0;
3113 unsigned long flags;
3114
3115 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3116
3117 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3118 /* nonblock mode is set or port is not enabled */
3119 info->flags |= ASYNC_NORMAL_ACTIVE;
3120 return 0;
3121 }
3122
3123 if (tty->termios->c_cflag & CLOCAL)
3124 do_clocal = 1;
3125
3126 /* Wait for carrier detect and the line to become
3127 * free (i.e., not in use by the callout). While we are in
3128 * this loop, info->count is dropped by one, so that
3129 * close() knows when to free things. We restore it upon
3130 * exit, either normal or abnormal.
3131 */
3132
3133 retval = 0;
3134 add_wait_queue(&info->open_wait, &wait);
3135
3136 spin_lock_irqsave(&info->lock, flags);
3137 if (!tty_hung_up_p(filp)) {
3138 extra_count = 1;
3139 info->count--;
3140 }
3141 spin_unlock_irqrestore(&info->lock, flags);
3142 info->blocked_open++;
3143
3144 while (1) {
3145 if ((tty->termios->c_cflag & CBAUD)) {
3146 spin_lock_irqsave(&info->lock,flags);
3147 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3148 set_signals(info);
3149 spin_unlock_irqrestore(&info->lock,flags);
3150 }
3151
3152 set_current_state(TASK_INTERRUPTIBLE);
3153
3154 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3155 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3156 -EAGAIN : -ERESTARTSYS;
3157 break;
3158 }
3159
3160 spin_lock_irqsave(&info->lock,flags);
3161 get_signals(info);
3162 spin_unlock_irqrestore(&info->lock,flags);
3163
3164 if (!(info->flags & ASYNC_CLOSING) &&
3165 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3166 break;
3167 }
3168
3169 if (signal_pending(current)) {
3170 retval = -ERESTARTSYS;
3171 break;
3172 }
3173
3174 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3175 schedule();
3176 }
3177
3178 set_current_state(TASK_RUNNING);
3179 remove_wait_queue(&info->open_wait, &wait);
3180
3181 if (extra_count)
3182 info->count++;
3183 info->blocked_open--;
3184
3185 if (!retval)
3186 info->flags |= ASYNC_NORMAL_ACTIVE;
3187
3188 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3189 return retval;
3190}
3191
3192static int alloc_tmp_rbuf(struct slgt_info *info)
3193{
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]3194 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3195 if (info->tmp_rbuf == NULL)
3196 return -ENOMEM;
3197 return 0;
3198}
3199
3200static void free_tmp_rbuf(struct slgt_info *info)
3201{
3202 kfree(info->tmp_rbuf);
3203 info->tmp_rbuf = NULL;
3204}
3205
3206/*
3207 * allocate DMA descriptor lists.
3208 */
3209static int alloc_desc(struct slgt_info *info)
3210{
3211 unsigned int i;
3212 unsigned int pbufs;
3213
3214 /* allocate memory to hold descriptor lists */
3215 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3216 if (info->bufs == NULL)
3217 return -ENOMEM;
3218
3219 memset(info->bufs, 0, DESC_LIST_SIZE);
3220
3221 info->rbufs = (struct slgt_desc*)info->bufs;
3222 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3223
3224 pbufs = (unsigned int)info->bufs_dma_addr;
3225
3226 /*
3227 * Build circular lists of descriptors
3228 */
3229
3230 for (i=0; i < info->rbuf_count; i++) {
3231 /* physical address of this descriptor */
3232 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3233
3234 /* physical address of next descriptor */
3235 if (i == info->rbuf_count - 1)
3236 info->rbufs[i].next = cpu_to_le32(pbufs);
3237 else
3238 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3239 set_desc_count(info->rbufs[i], DMABUFSIZE);
3240 }
3241
3242 for (i=0; i < info->tbuf_count; i++) {
3243 /* physical address of this descriptor */
3244 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3245
3246 /* physical address of next descriptor */
3247 if (i == info->tbuf_count - 1)
3248 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3249 else
3250 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3251 }
3252
3253 return 0;
3254}
3255
3256static void free_desc(struct slgt_info *info)
3257{
3258 if (info->bufs != NULL) {
3259 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3260 info->bufs = NULL;
3261 info->rbufs = NULL;
3262 info->tbufs = NULL;
3263 }
3264}
3265
3266static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3267{
3268 int i;
3269 for (i=0; i < count; i++) {
3270 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3271 return -ENOMEM;
3272 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3273 }
3274 return 0;
3275}
3276
3277static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3278{
3279 int i;
3280 for (i=0; i < count; i++) {
3281 if (bufs[i].buf == NULL)
3282 continue;
3283 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3284 bufs[i].buf = NULL;
3285 }
3286}
3287
3288static int alloc_dma_bufs(struct slgt_info *info)
3289{
3290 info->rbuf_count = 32;
3291 info->tbuf_count = 32;
3292
3293 if (alloc_desc(info) < 0 ||
3294 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3295 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3296 alloc_tmp_rbuf(info) < 0) {
3297 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3298 return -ENOMEM;
3299 }
3300 reset_rbufs(info);
3301 return 0;
3302}
3303
3304static void free_dma_bufs(struct slgt_info *info)
3305{
3306 if (info->bufs) {
3307 free_bufs(info, info->rbufs, info->rbuf_count);
3308 free_bufs(info, info->tbufs, info->tbuf_count);
3309 free_desc(info);
3310 }
3311 free_tmp_rbuf(info);
3312}
3313
3314static int claim_resources(struct slgt_info *info)
3315{
3316 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3317 DBGERR(("%s reg addr conflict, addr=%08X\n",
3318 info->device_name, info->phys_reg_addr));
3319 info->init_error = DiagStatus_AddressConflict;
3320 goto errout;
3321 }
3322 else
3323 info->reg_addr_requested = 1;
3324
Paul Fulghum0c8365e2006-01-11 12:17:39 -0800[diff] [blame]3325 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3326 if (!info->reg_addr) {
3327 DBGERR(("%s cant map device registers, addr=%08X\n",
3328 info->device_name, info->phys_reg_addr));
3329 info->init_error = DiagStatus_CantAssignPciResources;
3330 goto errout;
3331 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3332 return 0;
3333
3334errout:
3335 release_resources(info);
3336 return -ENODEV;
3337}
3338
3339static void release_resources(struct slgt_info *info)
3340{
3341 if (info->irq_requested) {
3342 free_irq(info->irq_level, info);
3343 info->irq_requested = 0;
3344 }
3345
3346 if (info->reg_addr_requested) {
3347 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3348 info->reg_addr_requested = 0;
3349 }
3350
3351 if (info->reg_addr) {
Paul Fulghum0c8365e2006-01-11 12:17:39 -0800[diff] [blame]3352 iounmap(info->reg_addr);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3353 info->reg_addr = NULL;
3354 }
3355}
3356
3357/* Add the specified device instance data structure to the
3358 * global linked list of devices and increment the device count.
3359 */
3360static void add_device(struct slgt_info *info)
3361{
3362 char *devstr;
3363
3364 info->next_device = NULL;
3365 info->line = slgt_device_count;
3366 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3367
3368 if (info->line < MAX_DEVICES) {
3369 if (maxframe[info->line])
3370 info->max_frame_size = maxframe[info->line];
3371 info->dosyncppp = dosyncppp[info->line];
3372 }
3373
3374 slgt_device_count++;
3375
3376 if (!slgt_device_list)
3377 slgt_device_list = info;
3378 else {
3379 struct slgt_info *current_dev = slgt_device_list;
3380 while(current_dev->next_device)
3381 current_dev = current_dev->next_device;
3382 current_dev->next_device = info;
3383 }
3384
3385 if (info->max_frame_size < 4096)
3386 info->max_frame_size = 4096;
3387 else if (info->max_frame_size > 65535)
3388 info->max_frame_size = 65535;
3389
3390 switch(info->pdev->device) {
3391 case SYNCLINK_GT_DEVICE_ID:
3392 devstr = "GT";
3393 break;
Paul Fulghum6f84be82006-06-25 05:49:22 -0700[diff] [blame]3394 case SYNCLINK_GT2_DEVICE_ID:
3395 devstr = "GT2";
3396 break;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3397 case SYNCLINK_GT4_DEVICE_ID:
3398 devstr = "GT4";
3399 break;
3400 case SYNCLINK_AC_DEVICE_ID:
3401 devstr = "AC";
3402 info->params.mode = MGSL_MODE_ASYNC;
3403 break;
3404 default:
3405 devstr = "(unknown model)";
3406 }
3407 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3408 devstr, info->device_name, info->phys_reg_addr,
3409 info->irq_level, info->max_frame_size);
3410
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]3411#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3412 hdlcdev_init(info);
3413#endif
3414}
3415
3416/*
3417 * allocate device instance structure, return NULL on failure
3418 */
3419static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3420{
3421 struct slgt_info *info;
3422
Yoann Padioleaudd00cc42007-07-19 01:49:03 -0700[diff] [blame]3423 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3424
3425 if (!info) {
3426 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3427 driver_name, adapter_num, port_num));
3428 } else {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3429 info->magic = MGSL_MAGIC;
David Howellsc4028952006-11-22 14:57:56 +0000[diff] [blame]3430 INIT_WORK(&info->task, bh_handler);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3431 info->max_frame_size = 4096;
3432 info->raw_rx_size = DMABUFSIZE;
3433 info->close_delay = 5*HZ/10;
3434 info->closing_wait = 30*HZ;
3435 init_waitqueue_head(&info->open_wait);
3436 init_waitqueue_head(&info->close_wait);
3437 init_waitqueue_head(&info->status_event_wait_q);
3438 init_waitqueue_head(&info->event_wait_q);
3439 spin_lock_init(&info->netlock);
3440 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3441 info->idle_mode = HDLC_TXIDLE_FLAGS;
3442 info->adapter_num = adapter_num;
3443 info->port_num = port_num;
3444
Jiri Slaby40565f12007-02-12 00:52:31 -0800[diff] [blame]3445 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3446 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3447
3448 /* Copy configuration info to device instance data */
3449 info->pdev = pdev;
3450 info->irq_level = pdev->irq;
3451 info->phys_reg_addr = pci_resource_start(pdev,0);
3452
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3453 info->bus_type = MGSL_BUS_TYPE_PCI;
Thomas Gleixner0f2ed4c2006-07-01 19:29:33 -0700[diff] [blame]3454 info->irq_flags = IRQF_SHARED;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3455
3456 info->init_error = -1; /* assume error, set to 0 on successful init */
3457 }
3458
3459 return info;
3460}
3461
3462static void device_init(int adapter_num, struct pci_dev *pdev)
3463{
3464 struct slgt_info *port_array[SLGT_MAX_PORTS];
3465 int i;
3466 int port_count = 1;
3467
Paul Fulghum6f84be82006-06-25 05:49:22 -0700[diff] [blame]3468 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3469 port_count = 2;
3470 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3471 port_count = 4;
3472
3473 /* allocate device instances for all ports */
3474 for (i=0; i < port_count; ++i) {
3475 port_array[i] = alloc_dev(adapter_num, i, pdev);
3476 if (port_array[i] == NULL) {
3477 for (--i; i >= 0; --i)
3478 kfree(port_array[i]);
3479 return;
3480 }
3481 }
3482
3483 /* give copy of port_array to all ports and add to device list */
3484 for (i=0; i < port_count; ++i) {
3485 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3486 add_device(port_array[i]);
3487 port_array[i]->port_count = port_count;
3488 spin_lock_init(&port_array[i]->lock);
3489 }
3490
3491 /* Allocate and claim adapter resources */
3492 if (!claim_resources(port_array[0])) {
3493
3494 alloc_dma_bufs(port_array[0]);
3495
3496 /* copy resource information from first port to others */
3497 for (i = 1; i < port_count; ++i) {
3498 port_array[i]->lock = port_array[0]->lock;
3499 port_array[i]->irq_level = port_array[0]->irq_level;
3500 port_array[i]->reg_addr = port_array[0]->reg_addr;
3501 alloc_dma_bufs(port_array[i]);
3502 }
3503
3504 if (request_irq(port_array[0]->irq_level,
3505 slgt_interrupt,
3506 port_array[0]->irq_flags,
3507 port_array[0]->device_name,
3508 port_array[0]) < 0) {
3509 DBGERR(("%s request_irq failed IRQ=%d\n",
3510 port_array[0]->device_name,
3511 port_array[0]->irq_level));
3512 } else {
3513 port_array[0]->irq_requested = 1;
3514 adapter_test(port_array[0]);
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]3515 for (i=1 ; i < port_count ; i++) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3516 port_array[i]->init_error = port_array[0]->init_error;
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]3517 port_array[i]->gpio_present = port_array[0]->gpio_present;
3518 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3519 }
3520 }
Paul Fulghum62eb5b12007-05-08 00:31:48 -0700[diff] [blame]3521
3522 for (i=0; i < port_count; ++i)
3523 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3524}
3525
3526static int __devinit init_one(struct pci_dev *dev,
3527 const struct pci_device_id *ent)
3528{
3529 if (pci_enable_device(dev)) {
3530 printk("error enabling pci device %p\n", dev);
3531 return -EIO;
3532 }
3533 pci_set_master(dev);
3534 device_init(slgt_device_count, dev);
3535 return 0;
3536}
3537
3538static void __devexit remove_one(struct pci_dev *dev)
3539{
3540}
3541
Jeff Dikeb68e31d2006-10-02 02:17:18 -0700[diff] [blame]3542static const struct tty_operations ops = {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3543 .open = open,
3544 .close = close,
3545 .write = write,
3546 .put_char = put_char,
3547 .flush_chars = flush_chars,
3548 .write_room = write_room,
3549 .chars_in_buffer = chars_in_buffer,
3550 .flush_buffer = flush_buffer,
3551 .ioctl = ioctl,
Paul Fulghum2acdb162007-05-10 22:22:43 -0700[diff] [blame]3552 .compat_ioctl = slgt_compat_ioctl,
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3553 .throttle = throttle,
3554 .unthrottle = unthrottle,
3555 .send_xchar = send_xchar,
3556 .break_ctl = set_break,
3557 .wait_until_sent = wait_until_sent,
3558 .read_proc = read_proc,
3559 .set_termios = set_termios,
3560 .stop = tx_hold,
3561 .start = tx_release,
3562 .hangup = hangup,
3563 .tiocmget = tiocmget,
3564 .tiocmset = tiocmset,
3565};
3566
3567static void slgt_cleanup(void)
3568{
3569 int rc;
3570 struct slgt_info *info;
3571 struct slgt_info *tmp;
3572
3573 printk("unload %s %s\n", driver_name, driver_version);
3574
3575 if (serial_driver) {
Paul Fulghum62eb5b12007-05-08 00:31:48 -0700[diff] [blame]3576 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3577 tty_unregister_device(serial_driver, info->line);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3578 if ((rc = tty_unregister_driver(serial_driver)))
3579 DBGERR(("tty_unregister_driver error=%d\n", rc));
3580 put_tty_driver(serial_driver);
3581 }
3582
3583 /* reset devices */
3584 info = slgt_device_list;
3585 while(info) {
3586 reset_port(info);
3587 info = info->next_device;
3588 }
3589
3590 /* release devices */
3591 info = slgt_device_list;
3592 while(info) {
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]3593#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3594 hdlcdev_exit(info);
3595#endif
3596 free_dma_bufs(info);
3597 free_tmp_rbuf(info);
3598 if (info->port_num == 0)
3599 release_resources(info);
3600 tmp = info;
3601 info = info->next_device;
3602 kfree(tmp);
3603 }
3604
3605 if (pci_registered)
3606 pci_unregister_driver(&pci_driver);
3607}
3608
3609/*
3610 * Driver initialization entry point.
3611 */
3612static int __init slgt_init(void)
3613{
3614 int rc;
3615
3616 printk("%s %s\n", driver_name, driver_version);
3617
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3618 serial_driver = alloc_tty_driver(MAX_DEVICES);
3619 if (!serial_driver) {
Paul Fulghum62eb5b12007-05-08 00:31:48 -0700[diff] [blame]3620 printk("%s can't allocate tty driver\n", driver_name);
3621 return -ENOMEM;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3622 }
3623
3624 /* Initialize the tty_driver structure */
3625
3626 serial_driver->owner = THIS_MODULE;
3627 serial_driver->driver_name = tty_driver_name;
3628 serial_driver->name = tty_dev_prefix;
3629 serial_driver->major = ttymajor;
3630 serial_driver->minor_start = 64;
3631 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3632 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3633 serial_driver->init_termios = tty_std_termios;
3634 serial_driver->init_termios.c_cflag =
3635 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
Alan Cox606d0992006-12-08 02:38:45 -0800[diff] [blame]3636 serial_driver->init_termios.c_ispeed = 9600;
3637 serial_driver->init_termios.c_ospeed = 9600;
Paul Fulghum62eb5b12007-05-08 00:31:48 -0700[diff] [blame]3638 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3639 tty_set_operations(serial_driver, &ops);
3640 if ((rc = tty_register_driver(serial_driver)) < 0) {
3641 DBGERR(("%s can't register serial driver\n", driver_name));
3642 put_tty_driver(serial_driver);
3643 serial_driver = NULL;
3644 goto error;
3645 }
3646
3647 printk("%s %s, tty major#%d\n",
3648 driver_name, driver_version,
3649 serial_driver->major);
3650
Paul Fulghum62eb5b12007-05-08 00:31:48 -0700[diff] [blame]3651 slgt_device_count = 0;
3652 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3653 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3654 goto error;
3655 }
3656 pci_registered = 1;
3657
3658 if (!slgt_device_list)
3659 printk("%s no devices found\n",driver_name);
3660
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3661 return 0;
3662
3663error:
3664 slgt_cleanup();
3665 return rc;
3666}
3667
3668static void __exit slgt_exit(void)
3669{
3670 slgt_cleanup();
3671}
3672
3673module_init(slgt_init);
3674module_exit(slgt_exit);
3675
3676/*
3677 * register access routines
3678 */
3679
3680#define CALC_REGADDR() \
3681 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3682 if (addr >= 0x80) \
3683 reg_addr += (info->port_num) * 32;
3684
3685static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3686{
3687 CALC_REGADDR();
3688 return readb((void __iomem *)reg_addr);
3689}
3690
3691static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3692{
3693 CALC_REGADDR();
3694 writeb(value, (void __iomem *)reg_addr);
3695}
3696
3697static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3698{
3699 CALC_REGADDR();
3700 return readw((void __iomem *)reg_addr);
3701}
3702
3703static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3704{
3705 CALC_REGADDR();
3706 writew(value, (void __iomem *)reg_addr);
3707}
3708
3709static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3710{
3711 CALC_REGADDR();
3712 return readl((void __iomem *)reg_addr);
3713}
3714
3715static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3716{
3717 CALC_REGADDR();
3718 writel(value, (void __iomem *)reg_addr);
3719}
3720
3721static void rdma_reset(struct slgt_info *info)
3722{
3723 unsigned int i;
3724
3725 /* set reset bit */
3726 wr_reg32(info, RDCSR, BIT1);
3727
3728 /* wait for enable bit cleared */
3729 for(i=0 ; i < 1000 ; i++)
3730 if (!(rd_reg32(info, RDCSR) & BIT0))
3731 break;
3732}
3733
3734static void tdma_reset(struct slgt_info *info)
3735{
3736 unsigned int i;
3737
3738 /* set reset bit */
3739 wr_reg32(info, TDCSR, BIT1);
3740
3741 /* wait for enable bit cleared */
3742 for(i=0 ; i < 1000 ; i++)
3743 if (!(rd_reg32(info, TDCSR) & BIT0))
3744 break;
3745}
3746
3747/*
3748 * enable internal loopback
3749 * TxCLK and RxCLK are generated from BRG
3750 * and TxD is looped back to RxD internally.
3751 */
3752static void enable_loopback(struct slgt_info *info)
3753{
3754 /* SCR (serial control) BIT2=looopback enable */
3755 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3756
3757 if (info->params.mode != MGSL_MODE_ASYNC) {
3758 /* CCR (clock control)
3759 * 07..05 tx clock source (010 = BRG)
3760 * 04..02 rx clock source (010 = BRG)
3761 * 01 auxclk enable (0 = disable)
3762 * 00 BRG enable (1 = enable)
3763 *
3764 * 0100 1001
3765 */
3766 wr_reg8(info, CCR, 0x49);
3767
3768 /* set speed if available, otherwise use default */
3769 if (info->params.clock_speed)
3770 set_rate(info, info->params.clock_speed);
3771 else
3772 set_rate(info, 3686400);
3773 }
3774}
3775
3776/*
3777 * set baud rate generator to specified rate
3778 */
3779static void set_rate(struct slgt_info *info, u32 rate)
3780{
3781 unsigned int div;
3782 static unsigned int osc = 14745600;
3783
3784 /* div = osc/rate - 1
3785 *
3786 * Round div up if osc/rate is not integer to
3787 * force to next slowest rate.
3788 */
3789
3790 if (rate) {
3791 div = osc/rate;
3792 if (!(osc % rate) && div)
3793 div--;
3794 wr_reg16(info, BDR, (unsigned short)div);
3795 }
3796}
3797
3798static void rx_stop(struct slgt_info *info)
3799{
3800 unsigned short val;
3801
3802 /* disable and reset receiver */
3803 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3804 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3805 wr_reg16(info, RCR, val); /* clear reset bit */
3806
3807 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3808
3809 /* clear pending rx interrupts */
3810 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3811
3812 rdma_reset(info);
3813
3814 info->rx_enabled = 0;
3815 info->rx_restart = 0;
3816}
3817
3818static void rx_start(struct slgt_info *info)
3819{
3820 unsigned short val;
3821
3822 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3823
3824 /* clear pending rx overrun IRQ */
3825 wr_reg16(info, SSR, IRQ_RXOVER);
3826
3827 /* reset and disable receiver */
3828 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3829 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3830 wr_reg16(info, RCR, val); /* clear reset bit */
3831
3832 rdma_reset(info);
3833 reset_rbufs(info);
3834
3835 /* set 1st descriptor address */
3836 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3837
3838 if (info->params.mode != MGSL_MODE_ASYNC) {
3839 /* enable rx DMA and DMA interrupt */
3840 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3841 } else {
3842 /* enable saving of rx status, rx DMA and DMA interrupt */
3843 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3844 }
3845
3846 slgt_irq_on(info, IRQ_RXOVER);
3847
3848 /* enable receiver */
3849 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3850
3851 info->rx_restart = 0;
3852 info->rx_enabled = 1;
3853}
3854
3855static void tx_start(struct slgt_info *info)
3856{
3857 if (!info->tx_enabled) {
3858 wr_reg16(info, TCR,
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]3859 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3860 info->tx_enabled = TRUE;
3861 }
3862
3863 if (info->tx_count) {
3864 info->drop_rts_on_tx_done = 0;
3865
3866 if (info->params.mode != MGSL_MODE_ASYNC) {
3867 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3868 get_signals(info);
3869 if (!(info->signals & SerialSignal_RTS)) {
3870 info->signals |= SerialSignal_RTS;
3871 set_signals(info);
3872 info->drop_rts_on_tx_done = 1;
3873 }
3874 }
3875
3876 slgt_irq_off(info, IRQ_TXDATA);
3877 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3878 /* clear tx idle and underrun status bits */
3879 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
Jiri Slaby40565f12007-02-12 00:52:31 -0800[diff] [blame]3880 if (info->params.mode == MGSL_MODE_HDLC)
3881 mod_timer(&info->tx_timer, jiffies +
3882 msecs_to_jiffies(5000));
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3883 } else {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3884 slgt_irq_off(info, IRQ_TXDATA);
3885 slgt_irq_on(info, IRQ_TXIDLE);
3886 /* clear tx idle status bit */
3887 wr_reg16(info, SSR, IRQ_TXIDLE);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3888 }
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]3889 tdma_start(info);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3890 info->tx_active = 1;
3891 }
3892}
3893
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]3894/*
3895 * start transmit DMA if inactive and there are unsent buffers
3896 */
3897static void tdma_start(struct slgt_info *info)
3898{
3899 unsigned int i;
3900
3901 if (rd_reg32(info, TDCSR) & BIT0)
3902 return;
3903
3904 /* transmit DMA inactive, check for unsent buffers */
3905 i = info->tbuf_start;
3906 while (!desc_count(info->tbufs[i])) {
3907 if (++i == info->tbuf_count)
3908 i = 0;
3909 if (i == info->tbuf_current)
3910 return;
3911 }
3912 info->tbuf_start = i;
3913
3914 /* there are unsent buffers, start transmit DMA */
3915
3916 /* reset needed if previous error condition */
3917 tdma_reset(info);
3918
3919 /* set 1st descriptor address */
3920 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3921 switch(info->params.mode) {
3922 case MGSL_MODE_RAW:
3923 case MGSL_MODE_MONOSYNC:
3924 case MGSL_MODE_BISYNC:
3925 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3926 break;
3927 default:
3928 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3929 }
3930}
3931
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3932static void tx_stop(struct slgt_info *info)
3933{
3934 unsigned short val;
3935
3936 del_timer(&info->tx_timer);
3937
3938 tdma_reset(info);
3939
3940 /* reset and disable transmitter */
3941 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3942 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]3943
3944 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3945
3946 /* clear tx idle and underrun status bit */
3947 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3948
3949 reset_tbufs(info);
3950
3951 info->tx_enabled = 0;
3952 info->tx_active = 0;
3953}
3954
3955static void reset_port(struct slgt_info *info)
3956{
3957 if (!info->reg_addr)
3958 return;
3959
3960 tx_stop(info);
3961 rx_stop(info);
3962
3963 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3964 set_signals(info);
3965
3966 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3967}
3968
3969static void reset_adapter(struct slgt_info *info)
3970{
3971 int i;
3972 for (i=0; i < info->port_count; ++i) {
3973 if (info->port_array[i])
3974 reset_port(info->port_array[i]);
3975 }
3976}
3977
3978static void async_mode(struct slgt_info *info)
3979{
3980 unsigned short val;
3981
3982 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3983 tx_stop(info);
3984 rx_stop(info);
3985
3986 /* TCR (tx control)
3987 *
3988 * 15..13 mode, 010=async
3989 * 12..10 encoding, 000=NRZ
3990 * 09 parity enable
3991 * 08 1=odd parity, 0=even parity
3992 * 07 1=RTS driver control
3993 * 06 1=break enable
3994 * 05..04 character length
3995 * 00=5 bits
3996 * 01=6 bits
3997 * 10=7 bits
3998 * 11=8 bits
3999 * 03 0=1 stop bit, 1=2 stop bits
4000 * 02 reset
4001 * 01 enable
4002 * 00 auto-CTS enable
4003 */
4004 val = 0x4000;
4005
4006 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4007 val |= BIT7;
4008
4009 if (info->params.parity != ASYNC_PARITY_NONE) {
4010 val |= BIT9;
4011 if (info->params.parity == ASYNC_PARITY_ODD)
4012 val |= BIT8;
4013 }
4014
4015 switch (info->params.data_bits)
4016 {
4017 case 6: val |= BIT4; break;
4018 case 7: val |= BIT5; break;
4019 case 8: val |= BIT5 + BIT4; break;
4020 }
4021
4022 if (info->params.stop_bits != 1)
4023 val |= BIT3;
4024
4025 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4026 val |= BIT0;
4027
4028 wr_reg16(info, TCR, val);
4029
4030 /* RCR (rx control)
4031 *
4032 * 15..13 mode, 010=async
4033 * 12..10 encoding, 000=NRZ
4034 * 09 parity enable
4035 * 08 1=odd parity, 0=even parity
4036 * 07..06 reserved, must be 0
4037 * 05..04 character length
4038 * 00=5 bits
4039 * 01=6 bits
4040 * 10=7 bits
4041 * 11=8 bits
4042 * 03 reserved, must be zero
4043 * 02 reset
4044 * 01 enable
4045 * 00 auto-DCD enable
4046 */
4047 val = 0x4000;
4048
4049 if (info->params.parity != ASYNC_PARITY_NONE) {
4050 val |= BIT9;
4051 if (info->params.parity == ASYNC_PARITY_ODD)
4052 val |= BIT8;
4053 }
4054
4055 switch (info->params.data_bits)
4056 {
4057 case 6: val |= BIT4; break;
4058 case 7: val |= BIT5; break;
4059 case 8: val |= BIT5 + BIT4; break;
4060 }
4061
4062 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4063 val |= BIT0;
4064
4065 wr_reg16(info, RCR, val);
4066
4067 /* CCR (clock control)
4068 *
4069 * 07..05 011 = tx clock source is BRG/16
4070 * 04..02 010 = rx clock source is BRG
4071 * 01 0 = auxclk disabled
4072 * 00 1 = BRG enabled
4073 *
4074 * 0110 1001
4075 */
4076 wr_reg8(info, CCR, 0x69);
4077
4078 msc_set_vcr(info);
4079
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4080 /* SCR (serial control)
4081 *
4082 * 15 1=tx req on FIFO half empty
4083 * 14 1=rx req on FIFO half full
4084 * 13 tx data IRQ enable
4085 * 12 tx idle IRQ enable
4086 * 11 rx break on IRQ enable
4087 * 10 rx data IRQ enable
4088 * 09 rx break off IRQ enable
4089 * 08 overrun IRQ enable
4090 * 07 DSR IRQ enable
4091 * 06 CTS IRQ enable
4092 * 05 DCD IRQ enable
4093 * 04 RI IRQ enable
4094 * 03 reserved, must be zero
4095 * 02 1=txd->rxd internal loopback enable
4096 * 01 reserved, must be zero
4097 * 00 1=master IRQ enable
4098 */
4099 val = BIT15 + BIT14 + BIT0;
4100 wr_reg16(info, SCR, val);
4101
4102 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4103
4104 set_rate(info, info->params.data_rate * 16);
4105
4106 if (info->params.loopback)
4107 enable_loopback(info);
4108}
4109
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4110static void sync_mode(struct slgt_info *info)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4111{
4112 unsigned short val;
4113
4114 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4115 tx_stop(info);
4116 rx_stop(info);
4117
4118 /* TCR (tx control)
4119 *
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4120 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4121 * 12..10 encoding
4122 * 09 CRC enable
4123 * 08 CRC32
4124 * 07 1=RTS driver control
4125 * 06 preamble enable
4126 * 05..04 preamble length
4127 * 03 share open/close flag
4128 * 02 reset
4129 * 01 enable
4130 * 00 auto-CTS enable
4131 */
4132 val = 0;
4133
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4134 switch(info->params.mode) {
4135 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4136 case MGSL_MODE_BISYNC: val |= BIT15; break;
4137 case MGSL_MODE_RAW: val |= BIT13; break;
4138 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4139 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4140 val |= BIT7;
4141
4142 switch(info->params.encoding)
4143 {
4144 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4145 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4146 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4147 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4148 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4149 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4150 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4151 }
4152
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4153 switch (info->params.crc_type & HDLC_CRC_MASK)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4154 {
4155 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4156 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4157 }
4158
4159 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4160 val |= BIT6;
4161
4162 switch (info->params.preamble_length)
4163 {
4164 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4165 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4166 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4167 }
4168
4169 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4170 val |= BIT0;
4171
4172 wr_reg16(info, TCR, val);
4173
4174 /* TPR (transmit preamble) */
4175
4176 switch (info->params.preamble)
4177 {
4178 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4179 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4180 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4181 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4182 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4183 default: val = 0x7e; break;
4184 }
4185 wr_reg8(info, TPR, (unsigned char)val);
4186
4187 /* RCR (rx control)
4188 *
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4189 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4190 * 12..10 encoding
4191 * 09 CRC enable
4192 * 08 CRC32
4193 * 07..03 reserved, must be 0
4194 * 02 reset
4195 * 01 enable
4196 * 00 auto-DCD enable
4197 */
4198 val = 0;
4199
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4200 switch(info->params.mode) {
4201 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4202 case MGSL_MODE_BISYNC: val |= BIT15; break;
4203 case MGSL_MODE_RAW: val |= BIT13; break;
4204 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4205
4206 switch(info->params.encoding)
4207 {
4208 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4209 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4210 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4211 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4212 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4213 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4214 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4215 }
4216
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4217 switch (info->params.crc_type & HDLC_CRC_MASK)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4218 {
4219 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4220 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4221 }
4222
4223 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4224 val |= BIT0;
4225
4226 wr_reg16(info, RCR, val);
4227
4228 /* CCR (clock control)
4229 *
4230 * 07..05 tx clock source
4231 * 04..02 rx clock source
4232 * 01 auxclk enable
4233 * 00 BRG enable
4234 */
4235 val = 0;
4236
4237 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4238 {
4239 // when RxC source is DPLL, BRG generates 16X DPLL
4240 // reference clock, so take TxC from BRG/16 to get
4241 // transmit clock at actual data rate
4242 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4243 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4244 else
4245 val |= BIT6; /* 010, txclk = BRG */
4246 }
4247 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4248 val |= BIT7; /* 100, txclk = DPLL Input */
4249 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4250 val |= BIT5; /* 001, txclk = RXC Input */
4251
4252 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4253 val |= BIT3; /* 010, rxclk = BRG */
4254 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4255 val |= BIT4; /* 100, rxclk = DPLL */
4256 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4257 val |= BIT2; /* 001, rxclk = TXC Input */
4258
4259 if (info->params.clock_speed)
4260 val |= BIT1 + BIT0;
4261
4262 wr_reg8(info, CCR, (unsigned char)val);
4263
4264 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4265 {
4266 // program DPLL mode
4267 switch(info->params.encoding)
4268 {
4269 case HDLC_ENCODING_BIPHASE_MARK:
4270 case HDLC_ENCODING_BIPHASE_SPACE:
4271 val = BIT7; break;
4272 case HDLC_ENCODING_BIPHASE_LEVEL:
4273 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4274 val = BIT7 + BIT6; break;
4275 default: val = BIT6; // NRZ encodings
4276 }
4277 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4278
4279 // DPLL requires a 16X reference clock from BRG
4280 set_rate(info, info->params.clock_speed * 16);
4281 }
4282 else
4283 set_rate(info, info->params.clock_speed);
4284
4285 tx_set_idle(info);
4286
4287 msc_set_vcr(info);
4288
4289 /* SCR (serial control)
4290 *
4291 * 15 1=tx req on FIFO half empty
4292 * 14 1=rx req on FIFO half full
4293 * 13 tx data IRQ enable
4294 * 12 tx idle IRQ enable
4295 * 11 underrun IRQ enable
4296 * 10 rx data IRQ enable
4297 * 09 rx idle IRQ enable
4298 * 08 overrun IRQ enable
4299 * 07 DSR IRQ enable
4300 * 06 CTS IRQ enable
4301 * 05 DCD IRQ enable
4302 * 04 RI IRQ enable
4303 * 03 reserved, must be zero
4304 * 02 1=txd->rxd internal loopback enable
4305 * 01 reserved, must be zero
4306 * 00 1=master IRQ enable
4307 */
4308 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4309
4310 if (info->params.loopback)
4311 enable_loopback(info);
4312}
4313
4314/*
4315 * set transmit idle mode
4316 */
4317static void tx_set_idle(struct slgt_info *info)
4318{
Paul Fulghum643f3312006-06-25 05:49:20 -0700[diff] [blame]4319 unsigned char val;
4320 unsigned short tcr;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4321
Paul Fulghum643f3312006-06-25 05:49:20 -0700[diff] [blame]4322 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4323 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4324 */
4325 tcr = rd_reg16(info, TCR);
4326 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4327 /* disable preamble, set idle size to 16 bits */
4328 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4329 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4330 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4331 } else if (!(tcr & BIT6)) {
4332 /* preamble is disabled, set idle size to 8 bits */
4333 tcr &= ~(BIT5 + BIT4);
4334 }
4335 wr_reg16(info, TCR, tcr);
4336
4337 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4338 /* LSB of custom tx idle specified in tx idle register */
4339 val = (unsigned char)(info->idle_mode & 0xff);
4340 } else {
4341 /* standard 8 bit idle patterns */
4342 switch(info->idle_mode)
4343 {
4344 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4345 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4346 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4347 case HDLC_TXIDLE_ZEROS:
4348 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4349 default: val = 0xff;
4350 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4351 }
4352
4353 wr_reg8(info, TIR, val);
4354}
4355
4356/*
4357 * get state of V24 status (input) signals
4358 */
4359static void get_signals(struct slgt_info *info)
4360{
4361 unsigned short status = rd_reg16(info, SSR);
4362
4363 /* clear all serial signals except DTR and RTS */
4364 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4365
4366 if (status & BIT3)
4367 info->signals |= SerialSignal_DSR;
4368 if (status & BIT2)
4369 info->signals |= SerialSignal_CTS;
4370 if (status & BIT1)
4371 info->signals |= SerialSignal_DCD;
4372 if (status & BIT0)
4373 info->signals |= SerialSignal_RI;
4374}
4375
4376/*
4377 * set V.24 Control Register based on current configuration
4378 */
4379static void msc_set_vcr(struct slgt_info *info)
4380{
4381 unsigned char val = 0;
4382
4383 /* VCR (V.24 control)
4384 *
4385 * 07..04 serial IF select
4386 * 03 DTR
4387 * 02 RTS
4388 * 01 LL
4389 * 00 RL
4390 */
4391
4392 switch(info->if_mode & MGSL_INTERFACE_MASK)
4393 {
4394 case MGSL_INTERFACE_RS232:
4395 val |= BIT5; /* 0010 */
4396 break;
4397 case MGSL_INTERFACE_V35:
4398 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4399 break;
4400 case MGSL_INTERFACE_RS422:
4401 val |= BIT6; /* 0100 */
4402 break;
4403 }
4404
4405 if (info->signals & SerialSignal_DTR)
4406 val |= BIT3;
4407 if (info->signals & SerialSignal_RTS)
4408 val |= BIT2;
4409 if (info->if_mode & MGSL_INTERFACE_LL)
4410 val |= BIT1;
4411 if (info->if_mode & MGSL_INTERFACE_RL)
4412 val |= BIT0;
4413 wr_reg8(info, VCR, val);
4414}
4415
4416/*
4417 * set state of V24 control (output) signals
4418 */
4419static void set_signals(struct slgt_info *info)
4420{
4421 unsigned char val = rd_reg8(info, VCR);
4422 if (info->signals & SerialSignal_DTR)
4423 val |= BIT3;
4424 else
4425 val &= ~BIT3;
4426 if (info->signals & SerialSignal_RTS)
4427 val |= BIT2;
4428 else
4429 val &= ~BIT2;
4430 wr_reg8(info, VCR, val);
4431}
4432
4433/*
4434 * free range of receive DMA buffers (i to last)
4435 */
4436static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4437{
4438 int done = 0;
4439
4440 while(!done) {
4441 /* reset current buffer for reuse */
4442 info->rbufs[i].status = 0;
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4443 switch(info->params.mode) {
4444 case MGSL_MODE_RAW:
4445 case MGSL_MODE_MONOSYNC:
4446 case MGSL_MODE_BISYNC:
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4447 set_desc_count(info->rbufs[i], info->raw_rx_size);
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4448 break;
4449 default:
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4450 set_desc_count(info->rbufs[i], DMABUFSIZE);
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4451 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4452
4453 if (i == last)
4454 done = 1;
4455 if (++i == info->rbuf_count)
4456 i = 0;
4457 }
4458 info->rbuf_current = i;
4459}
4460
4461/*
4462 * mark all receive DMA buffers as free
4463 */
4464static void reset_rbufs(struct slgt_info *info)
4465{
4466 free_rbufs(info, 0, info->rbuf_count - 1);
4467}
4468
4469/*
4470 * pass receive HDLC frame to upper layer
4471 *
4472 * return 1 if frame available, otherwise 0
4473 */
4474static int rx_get_frame(struct slgt_info *info)
4475{
4476 unsigned int start, end;
4477 unsigned short status;
4478 unsigned int framesize = 0;
4479 int rc = 0;
4480 unsigned long flags;
4481 struct tty_struct *tty = info->tty;
4482 unsigned char addr_field = 0xff;
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4483 unsigned int crc_size = 0;
4484
4485 switch (info->params.crc_type & HDLC_CRC_MASK) {
4486 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4487 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4488 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4489
4490check_again:
4491
4492 framesize = 0;
4493 addr_field = 0xff;
4494 start = end = info->rbuf_current;
4495
4496 for (;;) {
4497 if (!desc_complete(info->rbufs[end]))
4498 goto cleanup;
4499
4500 if (framesize == 0 && info->params.addr_filter != 0xff)
4501 addr_field = info->rbufs[end].buf[0];
4502
4503 framesize += desc_count(info->rbufs[end]);
4504
4505 if (desc_eof(info->rbufs[end]))
4506 break;
4507
4508 if (++end == info->rbuf_count)
4509 end = 0;
4510
4511 if (end == info->rbuf_current) {
4512 if (info->rx_enabled){
4513 spin_lock_irqsave(&info->lock,flags);
4514 rx_start(info);
4515 spin_unlock_irqrestore(&info->lock,flags);
4516 }
4517 goto cleanup;
4518 }
4519 }
4520
4521 /* status
4522 *
4523 * 15 buffer complete
4524 * 14..06 reserved
4525 * 05..04 residue
4526 * 02 eof (end of frame)
4527 * 01 CRC error
4528 * 00 abort
4529 */
4530 status = desc_status(info->rbufs[end]);
4531
4532 /* ignore CRC bit if not using CRC (bit is undefined) */
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4533 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4534 status &= ~BIT1;
4535
4536 if (framesize == 0 ||
4537 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4538 free_rbufs(info, start, end);
4539 goto check_again;
4540 }
4541
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4542 if (framesize < (2 + crc_size) || status & BIT0) {
4543 info->icount.rxshort++;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4544 framesize = 0;
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4545 } else if (status & BIT1) {
4546 info->icount.rxcrc++;
4547 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4548 framesize = 0;
4549 }
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4550
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]4551#if SYNCLINK_GENERIC_HDLC
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4552 if (framesize == 0) {
4553 struct net_device_stats *stats = hdlc_stats(info->netdev);
4554 stats->rx_errors++;
4555 stats->rx_frame_errors++;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4556 }
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4557#endif
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4558
4559 DBGBH(("%s rx frame status=%04X size=%d\n",
4560 info->device_name, status, framesize));
4561 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4562
4563 if (framesize) {
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4564 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4565 framesize -= crc_size;
4566 crc_size = 0;
4567 }
4568
4569 if (framesize > info->max_frame_size + crc_size)
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4570 info->icount.rxlong++;
4571 else {
4572 /* copy dma buffer(s) to contiguous temp buffer */
4573 int copy_count = framesize;
4574 int i = start;
4575 unsigned char *p = info->tmp_rbuf;
4576 info->tmp_rbuf_count = framesize;
4577
4578 info->icount.rxok++;
4579
4580 while(copy_count) {
4581 int partial_count = min(copy_count, DMABUFSIZE);
4582 memcpy(p, info->rbufs[i].buf, partial_count);
4583 p += partial_count;
4584 copy_count -= partial_count;
4585 if (++i == info->rbuf_count)
4586 i = 0;
4587 }
4588
Paul Fulghum04b374d2006-06-25 05:49:21 -0700[diff] [blame]4589 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4590 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4591 framesize++;
4592 }
4593
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]4594#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4595 if (info->netcount)
4596 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4597 else
4598#endif
4599 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4600 }
4601 }
4602 free_rbufs(info, start, end);
4603 rc = 1;
4604
4605cleanup:
4606 return rc;
4607}
4608
4609/*
4610 * pass receive buffer (RAW synchronous mode) to tty layer
4611 * return 1 if buffer available, otherwise 0
4612 */
4613static int rx_get_buf(struct slgt_info *info)
4614{
4615 unsigned int i = info->rbuf_current;
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4616 unsigned int count;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4617
4618 if (!desc_complete(info->rbufs[i]))
4619 return 0;
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4620 count = desc_count(info->rbufs[i]);
4621 switch(info->params.mode) {
4622 case MGSL_MODE_MONOSYNC:
4623 case MGSL_MODE_BISYNC:
4624 /* ignore residue in byte synchronous modes */
4625 if (desc_residue(info->rbufs[i]))
4626 count--;
4627 break;
4628 }
4629 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4630 DBGINFO(("rx_get_buf size=%d\n", count));
4631 if (count)
4632 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4633 info->flag_buf, count);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4634 free_rbufs(info, i, i);
4635 return 1;
4636}
4637
4638static void reset_tbufs(struct slgt_info *info)
4639{
4640 unsigned int i;
4641 info->tbuf_current = 0;
4642 for (i=0 ; i < info->tbuf_count ; i++) {
4643 info->tbufs[i].status = 0;
4644 info->tbufs[i].count = 0;
4645 }
4646}
4647
4648/*
4649 * return number of free transmit DMA buffers
4650 */
4651static unsigned int free_tbuf_count(struct slgt_info *info)
4652{
4653 unsigned int count = 0;
4654 unsigned int i = info->tbuf_current;
4655
4656 do
4657 {
4658 if (desc_count(info->tbufs[i]))
4659 break; /* buffer in use */
4660 ++count;
4661 if (++i == info->tbuf_count)
4662 i=0;
4663 } while (i != info->tbuf_current);
4664
Paul Fulghumbb029c62007-07-31 00:37:35 -0700[diff] [blame]4665 /* if tx DMA active, last zero count buffer is in use */
4666 if (count && (rd_reg32(info, TDCSR) & BIT0))
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4667 --count;
4668
4669 return count;
4670}
4671
4672/*
4673 * load transmit DMA buffer(s) with data
4674 */
4675static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4676{
4677 unsigned short count;
4678 unsigned int i;
4679 struct slgt_desc *d;
4680
4681 if (size == 0)
4682 return;
4683
4684 DBGDATA(info, buf, size, "tx");
4685
4686 info->tbuf_start = i = info->tbuf_current;
4687
4688 while (size) {
4689 d = &info->tbufs[i];
4690 if (++i == info->tbuf_count)
4691 i = 0;
4692
4693 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4694 memcpy(d->buf, buf, count);
4695
4696 size -= count;
4697 buf += count;
4698
Paul Fulghumcb10dc92006-09-30 23:27:45 -0700[diff] [blame]4699 /*
4700 * set EOF bit for last buffer of HDLC frame or
4701 * for every buffer in raw mode
4702 */
4703 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4704 info->params.mode == MGSL_MODE_RAW)
4705 set_desc_eof(*d, 1);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4706 else
4707 set_desc_eof(*d, 0);
4708
4709 set_desc_count(*d, count);
4710 }
4711
4712 info->tbuf_current = i;
4713}
4714
4715static int register_test(struct slgt_info *info)
4716{
4717 static unsigned short patterns[] =
4718 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4719 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4720 unsigned int i;
4721 int rc = 0;
4722
4723 for (i=0 ; i < count ; i++) {
4724 wr_reg16(info, TIR, patterns[i]);
4725 wr_reg16(info, BDR, patterns[(i+1)%count]);
4726 if ((rd_reg16(info, TIR) != patterns[i]) ||
4727 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4728 rc = -ENODEV;
4729 break;
4730 }
4731 }
Paul Fulghum0080b7a2006-03-28 01:56:15 -0800[diff] [blame]4732 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4733 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4734 return rc;
4735}
4736
4737static int irq_test(struct slgt_info *info)
4738{
4739 unsigned long timeout;
4740 unsigned long flags;
4741 struct tty_struct *oldtty = info->tty;
4742 u32 speed = info->params.data_rate;
4743
4744 info->params.data_rate = 921600;
4745 info->tty = NULL;
4746
4747 spin_lock_irqsave(&info->lock, flags);
4748 async_mode(info);
4749 slgt_irq_on(info, IRQ_TXIDLE);
4750
4751 /* enable transmitter */
4752 wr_reg16(info, TCR,
4753 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4754
4755 /* write one byte and wait for tx idle */
4756 wr_reg16(info, TDR, 0);
4757
4758 /* assume failure */
4759 info->init_error = DiagStatus_IrqFailure;
4760 info->irq_occurred = FALSE;
4761
4762 spin_unlock_irqrestore(&info->lock, flags);
4763
4764 timeout=100;
4765 while(timeout-- && !info->irq_occurred)
4766 msleep_interruptible(10);
4767
4768 spin_lock_irqsave(&info->lock,flags);
4769 reset_port(info);
4770 spin_unlock_irqrestore(&info->lock,flags);
4771
4772 info->params.data_rate = speed;
4773 info->tty = oldtty;
4774
4775 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4776 return info->irq_occurred ? 0 : -ENODEV;
4777}
4778
4779static int loopback_test_rx(struct slgt_info *info)
4780{
4781 unsigned char *src, *dest;
4782 int count;
4783
4784 if (desc_complete(info->rbufs[0])) {
4785 count = desc_count(info->rbufs[0]);
4786 src = info->rbufs[0].buf;
4787 dest = info->tmp_rbuf;
4788
4789 for( ; count ; count-=2, src+=2) {
4790 /* src=data byte (src+1)=status byte */
4791 if (!(*(src+1) & (BIT9 + BIT8))) {
4792 *dest = *src;
4793 dest++;
4794 info->tmp_rbuf_count++;
4795 }
4796 }
4797 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4798 return 1;
4799 }
4800 return 0;
4801}
4802
4803static int loopback_test(struct slgt_info *info)
4804{
4805#define TESTFRAMESIZE 20
4806
4807 unsigned long timeout;
4808 u16 count = TESTFRAMESIZE;
4809 unsigned char buf[TESTFRAMESIZE];
4810 int rc = -ENODEV;
4811 unsigned long flags;
4812
4813 struct tty_struct *oldtty = info->tty;
4814 MGSL_PARAMS params;
4815
4816 memcpy(&params, &info->params, sizeof(params));
4817
4818 info->params.mode = MGSL_MODE_ASYNC;
4819 info->params.data_rate = 921600;
4820 info->params.loopback = 1;
4821 info->tty = NULL;
4822
4823 /* build and send transmit frame */
4824 for (count = 0; count < TESTFRAMESIZE; ++count)
4825 buf[count] = (unsigned char)count;
4826
4827 info->tmp_rbuf_count = 0;
4828 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4829
4830 /* program hardware for HDLC and enabled receiver */
4831 spin_lock_irqsave(&info->lock,flags);
4832 async_mode(info);
4833 rx_start(info);
4834 info->tx_count = count;
4835 tx_load(info, buf, count);
4836 tx_start(info);
4837 spin_unlock_irqrestore(&info->lock, flags);
4838
4839 /* wait for receive complete */
4840 for (timeout = 100; timeout; --timeout) {
4841 msleep_interruptible(10);
4842 if (loopback_test_rx(info)) {
4843 rc = 0;
4844 break;
4845 }
4846 }
4847
4848 /* verify received frame length and contents */
4849 if (!rc && (info->tmp_rbuf_count != count ||
4850 memcmp(buf, info->tmp_rbuf, count))) {
4851 rc = -ENODEV;
4852 }
4853
4854 spin_lock_irqsave(&info->lock,flags);
4855 reset_adapter(info);
4856 spin_unlock_irqrestore(&info->lock,flags);
4857
4858 memcpy(&info->params, &params, sizeof(info->params));
4859 info->tty = oldtty;
4860
4861 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4862 return rc;
4863}
4864
4865static int adapter_test(struct slgt_info *info)
4866{
4867 DBGINFO(("testing %s\n", info->device_name));
Paul Fulghum294dad02006-06-25 05:49:21 -0700[diff] [blame]4868 if (register_test(info) < 0) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4869 printk("register test failure %s addr=%08X\n",
4870 info->device_name, info->phys_reg_addr);
Paul Fulghum294dad02006-06-25 05:49:21 -0700[diff] [blame]4871 } else if (irq_test(info) < 0) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4872 printk("IRQ test failure %s IRQ=%d\n",
4873 info->device_name, info->irq_level);
Paul Fulghum294dad02006-06-25 05:49:21 -0700[diff] [blame]4874 } else if (loopback_test(info) < 0) {
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4875 printk("loopback test failure %s\n", info->device_name);
4876 }
4877 return info->init_error;
4878}
4879
4880/*
4881 * transmit timeout handler
4882 */
4883static void tx_timeout(unsigned long context)
4884{
4885 struct slgt_info *info = (struct slgt_info*)context;
4886 unsigned long flags;
4887
4888 DBGINFO(("%s tx_timeout\n", info->device_name));
4889 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4890 info->icount.txtimeout++;
4891 }
4892 spin_lock_irqsave(&info->lock,flags);
4893 info->tx_active = 0;
4894 info->tx_count = 0;
4895 spin_unlock_irqrestore(&info->lock,flags);
4896
Paul Fulghumaf69c7f2006-12-06 20:40:24 -0800[diff] [blame]4897#if SYNCLINK_GENERIC_HDLC
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4898 if (info->netcount)
4899 hdlcdev_tx_done(info);
4900 else
4901#endif
4902 bh_transmit(info);
4903}
4904
4905/*
4906 * receive buffer polling timer
4907 */
4908static void rx_timeout(unsigned long context)
4909{
4910 struct slgt_info *info = (struct slgt_info*)context;
4911 unsigned long flags;
4912
4913 DBGINFO(("%s rx_timeout\n", info->device_name));
4914 spin_lock_irqsave(&info->lock, flags);
4915 info->pending_bh |= BH_RECEIVE;
4916 spin_unlock_irqrestore(&info->lock, flags);
David Howellsc4028952006-11-22 14:57:56 +0000[diff] [blame]4917 bh_handler(&info->task);
Paul Fulghum705b6c72006-01-08 01:02:06 -0800[diff] [blame]4918}
4919