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gerrit-public.fairphone.software / kernel / msm-4.9 / 3e1868eb4266e3ef8b4b1420d313bade94d18de5 / . / arch / arm64 / boot / dts / qcom / sdm670-sde-display.dtsi
blob: 6f4dd3335db44e94966e4e29926c586604de3d35 [file] [log] [blame]
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]23#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame^]28#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]29#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
30
31&soc {
32 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 qcom,panel-supply-entry@0 {
37 reg = <0>;
38 qcom,supply-name = "vddio";
39 qcom,supply-min-voltage = <1800000>;
40 qcom,supply-max-voltage = <1800000>;
41 qcom,supply-enable-load = <62000>;
42 qcom,supply-disable-load = <80>;
43 qcom,supply-post-on-sleep = <20>;
44 };
45
46 qcom,panel-supply-entry@1 {
47 reg = <1>;
48 qcom,supply-name = "lab";
49 qcom,supply-min-voltage = <4600000>;
50 qcom,supply-max-voltage = <6000000>;
51 qcom,supply-enable-load = <100000>;
52 qcom,supply-disable-load = <100>;
53 };
54
55 qcom,panel-supply-entry@2 {
56 reg = <2>;
57 qcom,supply-name = "ibb";
58 qcom,supply-min-voltage = <4600000>;
59 qcom,supply-max-voltage = <6000000>;
60 qcom,supply-enable-load = <100000>;
61 qcom,supply-disable-load = <100>;
62 qcom,supply-post-on-sleep = <20>;
63 };
64 };
65
66 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 qcom,panel-supply-entry@0 {
71 reg = <0>;
72 qcom,supply-name = "vddio";
73 qcom,supply-min-voltage = <1800000>;
74 qcom,supply-max-voltage = <1800000>;
75 qcom,supply-enable-load = <62000>;
76 qcom,supply-disable-load = <80>;
77 qcom,supply-post-on-sleep = <20>;
78 };
79 };
80
81 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 qcom,panel-supply-entry@0 {
86 reg = <0>;
87 qcom,supply-name = "vddio";
88 qcom,supply-min-voltage = <1800000>;
89 qcom,supply-max-voltage = <1800000>;
90 qcom,supply-enable-load = <62000>;
91 qcom,supply-disable-load = <80>;
92 qcom,supply-post-on-sleep = <20>;
93 };
94
95 qcom,panel-supply-entry@1 {
96 reg = <1>;
97 qcom,supply-name = "vdd";
98 qcom,supply-min-voltage = <3000000>;
99 qcom,supply-max-voltage = <3000000>;
100 qcom,supply-enable-load = <857000>;
101 qcom,supply-disable-load = <0>;
102 qcom,supply-post-on-sleep = <0>;
103 };
104 };
105
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]106 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 qcom,panel-supply-entry@0 {
111 reg = <0>;
112 qcom,supply-name = "wqhd-vddio";
113 qcom,supply-min-voltage = <1800000>;
114 qcom,supply-max-voltage = <1950000>;
115 qcom,supply-enable-load = <32000>;
116 qcom,supply-disable-load = <80>;
117 };
118
119 qcom,panel-supply-entry@1 {
120 reg = <1>;
121 qcom,supply-name = "vdda-3p3";
122 qcom,supply-min-voltage = <3300000>;
123 qcom,supply-max-voltage = <3300000>;
124 qcom,supply-enable-load = <13200>;
125 qcom,supply-disable-load = <80>;
126 };
127
128 qcom,panel-supply-entry@2 {
129 reg = <2>;
130 qcom,supply-name = "lab";
131 qcom,supply-min-voltage = <4600000>;
132 qcom,supply-max-voltage = <6100000>;
133 qcom,supply-enable-load = <100000>;
134 qcom,supply-disable-load = <100>;
135 };
136
137 qcom,panel-supply-entry@3 {
138 reg = <3>;
139 qcom,supply-name = "ibb";
140 qcom,supply-min-voltage = <4000000>;
141 qcom,supply-max-voltage = <6300000>;
142 qcom,supply-enable-load = <100000>;
143 qcom,supply-disable-load = <100>;
144 };
145
146 qcom,panel-supply-entry@4 {
147 reg = <4>;
148 qcom,supply-name = "oledb";
149 qcom,supply-min-voltage = <5000000>;
150 qcom,supply-max-voltage = <8100000>;
151 qcom,supply-enable-load = <100000>;
152 qcom,supply-disable-load = <100>;
153 };
154 };
155
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]156 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
157 compatible = "qcom,dsi-display";
158 label = "dsi_dual_nt35597_truly_video_display";
159 qcom,display-type = "primary";
160
161 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
162 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
163 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
164 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
165 clock-names = "src_byte_clk", "src_pixel_clk";
166
167 pinctrl-names = "panel_active", "panel_suspend";
168 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
169 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
170 qcom,platform-reset-gpio = <&tlmm 75 0>;
171 qcom,panel-mode-gpio = <&tlmm 76 0>;
172
173 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
174 vddio-supply = <&pm660_l11>;
175 lab-supply = <&lcdb_ldo_vreg>;
176 ibb-supply = <&lcdb_ncp_vreg>;
177 };
178
179 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
180 compatible = "qcom,dsi-display";
181 label = "dsi_dual_nt35597_truly_cmd_display";
182 qcom,display-type = "primary";
183
184 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
185 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
186 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
187 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
188 clock-names = "src_byte_clk", "src_pixel_clk";
189
190 pinctrl-names = "panel_active", "panel_suspend";
191 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
192 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
193 qcom,platform-te-gpio = <&tlmm 10 0>;
194 qcom,platform-reset-gpio = <&tlmm 75 0>;
195 qcom,panel-mode-gpio = <&tlmm 76 0>;
196
197 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
198 vddio-supply = <&pm660_l11>;
199 lab-supply = <&lcdb_ldo_vreg>;
200 ibb-supply = <&lcdb_ncp_vreg>;
201 };
202
203 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
204 compatible = "qcom,dsi-display";
205 label = "dsi_nt35597_truly_dsc_cmd_display";
206 qcom,display-type = "primary";
207
208 qcom,dsi-ctrl = <&mdss_dsi1>;
209 qcom,dsi-phy = <&mdss_dsi_phy1>;
210 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
211 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
212 clock-names = "src_byte_clk", "src_pixel_clk";
213
214 pinctrl-names = "panel_active", "panel_suspend";
215 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
216 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
217 qcom,platform-te-gpio = <&tlmm 10 0>;
218 qcom,platform-reset-gpio = <&tlmm 75 0>;
219 qcom,panel-mode-gpio = <&tlmm 76 0>;
220
221 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
222 vddio-supply = <&pm660_l11>;
223 lab-supply = <&lcdb_ldo_vreg>;
224 ibb-supply = <&lcdb_ncp_vreg>;
225 };
226
227 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
228 compatible = "qcom,dsi-display";
229 label = "dsi_nt35597_truly_dsc_video_display";
230 qcom,display-type = "primary";
231
232 qcom,dsi-ctrl = <&mdss_dsi1>;
233 qcom,dsi-phy = <&mdss_dsi_phy1>;
234 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
235 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
236 clock-names = "src_byte_clk", "src_pixel_clk";
237
238 pinctrl-names = "panel_active", "panel_suspend";
239 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
240 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
241 qcom,platform-te-gpio = <&tlmm 10 0>;
242 qcom,platform-reset-gpio = <&tlmm 75 0>;
243 qcom,panel-mode-gpio = <&tlmm 76 0>;
244
245 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
246 vddio-supply = <&pm660_l11>;
247 lab-supply = <&lcdb_ldo_vreg>;
248 ibb-supply = <&lcdb_ncp_vreg>;
249 };
250
251 dsi_sim_vid_display: qcom,dsi-display@4 {
252 compatible = "qcom,dsi-display";
253 label = "dsi_sim_vid_display";
254 qcom,display-type = "primary";
255
256 qcom,dsi-ctrl = <&mdss_dsi0>;
257 qcom,dsi-phy = <&mdss_dsi_phy0>;
258 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
259 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
260 clock-names = "src_byte_clk", "src_pixel_clk";
261
262 pinctrl-names = "panel_active", "panel_suspend";
263 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
264 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
265
266 qcom,dsi-panel = <&dsi_sim_vid>;
267 };
268
269 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
270 compatible = "qcom,dsi-display";
271 label = "dsi_dual_sim_vid_display";
272 qcom,display-type = "primary";
273
274 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
275 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
276 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
277 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
278 clock-names = "src_byte_clk", "src_pixel_clk";
279
280 pinctrl-names = "panel_active", "panel_suspend";
281 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
282 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
283
284 qcom,dsi-panel = <&dsi_dual_sim_vid>;
285 };
286
287 dsi_sim_cmd_display: qcom,dsi-display@6 {
288 compatible = "qcom,dsi-display";
289 label = "dsi_sim_cmd_display";
290 qcom,display-type = "primary";
291
292 qcom,dsi-ctrl = <&mdss_dsi0>;
293 qcom,dsi-phy = <&mdss_dsi_phy0>;
294 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
295 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
296 clock-names = "src_byte_clk", "src_pixel_clk";
297
298 pinctrl-names = "panel_active", "panel_suspend";
299 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
300 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
301
302 qcom,dsi-panel = <&dsi_sim_cmd>;
303 };
304
305 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
306 compatible = "qcom,dsi-display";
307 label = "dsi_dual_sim_cmd_display";
308 qcom,display-type = "primary";
309
310 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
311 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
312 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
313 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
314 clock-names = "src_byte_clk", "src_pixel_clk";
315
316 pinctrl-names = "panel_active", "panel_suspend";
317 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
318 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
319
320 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
321 };
322
323 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
324 compatible = "qcom,dsi-display";
325 label = "dsi_sim_dsc_375_cmd_display";
326 qcom,display-type = "primary";
327
328 qcom,dsi-ctrl = <&mdss_dsi0>;
329 qcom,dsi-phy = <&mdss_dsi_phy0>;
330 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
331 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
332 clock-names = "src_byte_clk", "src_pixel_clk";
333
334 pinctrl-names = "panel_active", "panel_suspend";
335 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
336 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
337
338 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
339 };
340
341 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
342 compatible = "qcom,dsi-display";
343 label = "dsi_dual_sim_dsc_375_cmd_display";
344 qcom,display-type = "primary";
345
346 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
347 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
348 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
349 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
350 clock-names = "src_byte_clk", "src_pixel_clk";
351
352 pinctrl-names = "panel_active", "panel_suspend";
353 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
354 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
355
356 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
357 };
358
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]359 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
360 compatible = "qcom,dsi-display";
361 label = "dsi_dual_nt35597_video_display";
362 qcom,display-type = "primary";
363
364 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
365 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
366 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
367 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
368 clock-names = "src_byte_clk", "src_pixel_clk";
369
370 pinctrl-names = "panel_active", "panel_suspend";
371 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
372 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
373 qcom,platform-reset-gpio = <&tlmm 75 0>;
374 qcom,panel-mode-gpio = <&tlmm 76 0>;
375
376 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
377 vddio-supply = <&pm660_l11>;
378 lab-supply = <&lcdb_ldo_vreg>;
379 ibb-supply = <&lcdb_ncp_vreg>;
380 };
381
382 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
383 compatible = "qcom,dsi-display";
384 label = "dsi_dual_nt35597_cmd_display";
385 qcom,display-type = "primary";
386
387 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
388 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
389 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
390 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
391 clock-names = "src_byte_clk", "src_pixel_clk";
392
393 pinctrl-names = "panel_active", "panel_suspend";
394 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
395 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
396 qcom,platform-reset-gpio = <&tlmm 75 0>;
397 qcom,panel-mode-gpio = <&tlmm 76 0>;
398
399 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
400 vddio-supply = <&pm660_l11>;
401 lab-supply = <&lcdb_ldo_vreg>;
402 ibb-supply = <&lcdb_ncp_vreg>;
403 };
404
405 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
406 compatible = "qcom,dsi-display";
407 label = "dsi_rm67195_amoled_fhd_cmd_display";
408 qcom,display-type = "primary";
409
410 qcom,dsi-ctrl = <&mdss_dsi0>;
411 qcom,dsi-phy = <&mdss_dsi_phy0>;
412 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
413 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
414 clock-names = "src_byte_clk", "src_pixel_clk";
415
416 pinctrl-names = "panel_active", "panel_suspend";
417 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
418 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
419 qcom,platform-te-gpio = <&tlmm 10 0>;
420 qcom,platform-reset-gpio = <&tlmm 75 0>;
421
422 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
423 vddio-supply = <&pm660_l11>;
424 lab-supply = <&lcdb_ldo_vreg>;
425 ibb-supply = <&lcdb_ncp_vreg>;
426 };
427
428 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
429 compatible = "qcom,dsi-display";
430 label = "dsi_nt35695b_truly_fhd_video_display";
431 qcom,display-type = "primary";
432
433 qcom,dsi-ctrl = <&mdss_dsi0>;
434 qcom,dsi-phy = <&mdss_dsi_phy0>;
435 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
436 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
437 clock-names = "src_byte_clk", "src_pixel_clk";
438
439 pinctrl-names = "panel_active", "panel_suspend";
440 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
441 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
442 qcom,platform-reset-gpio = <&tlmm 75 0>;
443
444 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
445 vddio-supply = <&pm660_l11>;
446 lab-supply = <&lcdb_ldo_vreg>;
447 ibb-supply = <&lcdb_ncp_vreg>;
448 };
449
450 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
451 compatible = "qcom,dsi-display";
452 label = "dsi_nt35695b_truly_fhd_cmd_display";
453 qcom,display-type = "primary";
454
455 qcom,dsi-ctrl = <&mdss_dsi0>;
456 qcom,dsi-phy = <&mdss_dsi_phy0>;
457 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
458 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
459 clock-names = "src_byte_clk", "src_pixel_clk";
460
461 pinctrl-names = "panel_active", "panel_suspend";
462 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
463 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
464 qcom,platform-te-gpio = <&tlmm 10 0>;
465 qcom,platform-reset-gpio = <&tlmm 75 0>;
466
467 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
468 vddio-supply = <&pm660_l11>;
469 lab-supply = <&lcdb_ldo_vreg>;
470 ibb-supply = <&lcdb_ncp_vreg>;
471 };
472
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame^]473 dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 {
474 compatible = "qcom,dsi-display";
475 label = "dsi_dual_nt36850_truly_cmd_display";
476 qcom,display-type = "primary";
477
478 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
479 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
480 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
481 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
482 clock-names = "src_byte_clk", "src_pixel_clk";
483
484 pinctrl-names = "panel_active", "panel_suspend";
485 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
486 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
487 qcom,platform-te-gpio = <&tlmm 10 0>;
488 qcom,platform-reset-gpio = <&tlmm 75 0>;
489
490 qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>;
491 vddio-supply = <&pm660_l11>;
492 lab-supply = <&lcdb_ldo_vreg>;
493 ibb-supply = <&lcdb_ncp_vreg>;
494 };
495
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]496 sde_wb: qcom,wb-display@0 {
497 compatible = "qcom,wb-display";
498 cell-index = <0>;
499 label = "wb_display";
500 };
501
502 ext_disp: qcom,msm-ext-disp {
503 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]504
505 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
506 compatible = "qcom,msm-ext-disp-audio-codec-rx";
507 };
508 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]509};
510
511&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530[diff] [blame]512 qcom,dp-usbpd-detection = <&pm660_pdphy>;
513 qcom,ext-disp = <&ext_disp>;
514
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]515 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
516 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
517 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
518 qcom,aux-en-gpio = <&tlmm 50 0>;
519 qcom,aux-sel-gpio = <&tlmm 40 0>;
520 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
521};
522
523&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530[diff] [blame]524 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]525};
526
527&dsi_dual_nt35597_truly_video {
528 qcom,mdss-dsi-t-clk-post = <0x0D>;
529 qcom,mdss-dsi-t-clk-pre = <0x2D>;
530 qcom,mdss-dsi-display-timings {
531 timing@0{
532 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
533 07 05 03 04 00];
534 qcom,display-topology = <2 0 2>,
535 <1 0 2>;
536 qcom,default-topology-index = <0>;
537 };
538 };
539};
540
541&dsi_dual_nt35597_truly_cmd {
542 qcom,mdss-dsi-t-clk-post = <0x0D>;
543 qcom,mdss-dsi-t-clk-pre = <0x2D>;
544 qcom,mdss-dsi-display-timings {
545 timing@0{
546 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
547 07 05 03 04 00];
548 qcom,display-topology = <2 0 2>,
549 <1 0 2>;
550 qcom,default-topology-index = <0>;
551 };
552 };
553};
554
555&dsi_nt35597_truly_dsc_cmd {
556 qcom,mdss-dsi-t-clk-post = <0x0b>;
557 qcom,mdss-dsi-t-clk-pre = <0x23>;
558 qcom,mdss-dsi-display-timings {
559 timing@0{
560 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
561 05 03 03 04 00];
562 qcom,display-topology = <1 1 1>,
563 <2 2 1>, /* dsc merge */
564 <2 1 1>; /* 3d mux */
565 qcom,default-topology-index = <1>;
566 };
567 };
568};
569
570&dsi_nt35597_truly_dsc_video {
571 qcom,mdss-dsi-t-clk-post = <0x0b>;
572 qcom,mdss-dsi-t-clk-pre = <0x23>;
573 qcom,mdss-dsi-display-timings {
574 timing@0{
575 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
576 04 03 03 04 00];
577 qcom,display-topology = <1 1 1>,
578 <2 2 1>, /* dsc merge */
579 <2 1 1>; /* 3d mux */
580 qcom,default-topology-index = <1>;
581 };
582 };
583};
584
585&dsi_sim_vid {
586 qcom,mdss-dsi-t-clk-post = <0x0d>;
587 qcom,mdss-dsi-t-clk-pre = <0x2d>;
588 qcom,mdss-dsi-display-timings {
589 timing@0{
590 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
591 07 05 03 04 00];
592 qcom,display-topology = <1 0 1>,
593 <2 0 1>;
594 qcom,default-topology-index = <0>;
595 };
596 };
597};
598
599&dsi_dual_sim_vid {
600 qcom,mdss-dsi-t-clk-post = <0x0d>;
601 qcom,mdss-dsi-t-clk-pre = <0x2d>;
602 qcom,mdss-dsi-display-timings {
603 timing@0{
604 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
605 07 05 03 04 00];
606 qcom,display-topology = <2 0 2>,
607 <1 0 2>;
608 qcom,default-topology-index = <0>;
609 };
610 };
611};
612
613&dsi_sim_cmd {
614 qcom,mdss-dsi-t-clk-post = <0x0d>;
615 qcom,mdss-dsi-t-clk-pre = <0x2d>;
616 qcom,mdss-dsi-display-timings {
617 timing@0{
618 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
619 07 05 03 04 00];
620 qcom,display-topology = <1 0 1>,
621 <2 0 1>;
622 qcom,default-topology-index = <0>;
623 };
624 };
625};
626
627&dsi_dual_sim_cmd {
628 qcom,mdss-dsi-t-clk-post = <0x0d>;
629 qcom,mdss-dsi-t-clk-pre = <0x2d>;
630 qcom,mdss-dsi-display-timings {
631 timing@0{
632 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
633 09 06 03 04 00];
634 qcom,display-topology = <2 0 2>;
635 qcom,default-topology-index = <0>;
636 };
637 timing@1{
638 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
639 07 05 03 04 00];
640 qcom,display-topology = <2 0 2>,
641 <1 0 2>;
642 qcom,default-topology-index = <0>;
643 };
644 timing@2{
645 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
646 06 04 03 04 00];
647 qcom,display-topology = <2 0 2>;
648 qcom,default-topology-index = <0>;
649 };
650 };
651};
652
653&dsi_sim_dsc_375_cmd {
654 qcom,mdss-dsi-t-clk-post = <0x0d>;
655 qcom,mdss-dsi-t-clk-pre = <0x2d>;
656 qcom,mdss-dsi-display-timings {
657 timing@0 { /* 1080p */
658 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
659 07 04 03 04 00];
660 qcom,display-topology = <1 1 1>;
661 qcom,default-topology-index = <0>;
662 };
663 timing@1 { /* qhd */
664 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
665 05 03 03 04 00];
666 qcom,display-topology = <1 1 1>,
667 <2 2 1>, /* dsc merge */
668 <2 1 1>; /* 3d mux */
669 qcom,default-topology-index = <0>;
670 };
671 };
672};
673
674&dsi_dual_sim_dsc_375_cmd {
675 qcom,mdss-dsi-t-clk-post = <0x0d>;
676 qcom,mdss-dsi-t-clk-pre = <0x2d>;
677 qcom,mdss-dsi-display-timings {
678 timing@0 { /* qhd */
679 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
680 07 05 03 04 00];
681 qcom,display-topology = <2 2 2>;
682 qcom,default-topology-index = <0>;
683 };
684 timing@1 { /* 4k */
685 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
686 06 04 03 04 00];
687 qcom,display-topology = <2 2 2>;
688 qcom,default-topology-index = <0>;
689 };
690 };
691};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]692
693&dsi_dual_nt35597_video {
694 qcom,mdss-dsi-t-clk-post = <0x0d>;
695 qcom,mdss-dsi-t-clk-pre = <0x2d>;
696 qcom,mdss-dsi-display-timings {
697 timing@0 {
698 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
699 05 03 04 00];
700 qcom,display-topology = <2 0 2>,
701 <1 0 2>;
702 qcom,default-topology-index = <0>;
703 };
704 };
705};
706
707&dsi_dual_nt35597_cmd {
708 qcom,mdss-dsi-t-clk-post = <0x0d>;
709 qcom,mdss-dsi-t-clk-pre = <0x2d>;
710 qcom,mdss-dsi-display-timings {
711 timing@0 {
712 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
713 05 03 04 00];
714 qcom,display-topology = <2 0 2>,
715 <1 0 2>;
716 qcom,default-topology-index = <0>;
717 };
718 };
719};
720
721&dsi_rm67195_amoled_fhd_cmd {
722 qcom,mdss-dsi-t-clk-post = <0x07>;
723 qcom,mdss-dsi-t-clk-pre = <0x1c>;
724 qcom,mdss-dsi-display-timings {
725 timing@0 {
726 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
727 05 07 05 03 04 00];
728 qcom,display-topology = <1 0 1>;
729 qcom,default-topology-index = <0>;
730 };
731 };
732};
733
734&dsi_nt35695b_truly_fhd_video {
735 qcom,mdss-dsi-t-clk-post = <0x07>;
736 qcom,mdss-dsi-t-clk-pre = <0x1c>;
737 qcom,mdss-dsi-display-timings {
738 timing@0 {
739 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
740 05 07 05 03 04 00];
741 qcom,display-topology = <1 0 1>;
742 qcom,default-topology-index = <0>;
743 };
744 };
745};
746
747&dsi_nt35695b_truly_fhd_cmd {
748 qcom,mdss-dsi-t-clk-post = <0x07>;
749 qcom,mdss-dsi-t-clk-pre = <0x1c>;
750 qcom,mdss-dsi-display-timings {
751 timing@0 {
752 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
753 05 07 05 03 04 00];
754 qcom,display-topology = <1 0 1>;
755 qcom,default-topology-index = <0>;
756 };
757 };
758};
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame^]759
760&dsi_dual_nt36850_truly_cmd {
761 qcom,mdss-dsi-t-clk-post = <0x0E>;
762 qcom,mdss-dsi-t-clk-pre = <0x30>;
763 qcom,mdss-dsi-display-timings {
764 timing@0{
765 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08
766 08 05 03 04 00];
767 qcom,display-topology = <2 0 2>,
768 <1 0 2>;
769 qcom,default-topology-index = <0>;
770 };
771 };
772};