Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SDE_HW_MDP_CTL_H |
| 14 | #define _SDE_HW_MDP_CTL_H |
| 15 | |
| 16 | #include "sde_hw_mdss.h" |
| 17 | #include "sde_hw_catalog.h" |
| 18 | |
| 19 | struct sde_hw_ctl; |
| 20 | /** |
| 21 | * struct sde_hw_stage_cfg - blending stage cfg |
| 22 | * @stage |
| 23 | * @border_enable |
| 24 | */ |
| 25 | struct sde_hw_stage_cfg { |
| 26 | enum sde_sspp stage[SDE_STAGE_MAX][PIPES_PER_STAGE]; |
| 27 | u8 border_enable; |
| 28 | }; |
| 29 | |
| 30 | /** |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame^] | 31 | * struct sde_hw_intf_cfg :Desbribes how the mdp writes data to |
| 32 | * output interface |
| 33 | * @intf : Interface id |
| 34 | * @wb: writeback id |
| 35 | * @mode_3d: 3d mux configuration |
| 36 | */ |
| 37 | struct sde_hw_intf_cfg { |
| 38 | enum sde_intf intf; |
| 39 | enum sde_wb wb; |
| 40 | enum sde_3d_blend_mode mode_3d; |
| 41 | }; |
| 42 | |
| 43 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 44 | * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions |
| 45 | * Assumption is these functions will be called after clocks are enabled |
| 46 | */ |
| 47 | struct sde_hw_ctl_ops { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame^] | 48 | /** |
| 49 | * kickoff hw operation for Sw controlled interfaces |
| 50 | * DSI cmd mode and WB interface are SW controlled |
| 51 | * @ctx : ctl path ctx pointer |
| 52 | */ |
| 53 | void (*setup_start)(struct sde_hw_ctl *ctx); |
| 54 | |
| 55 | /** |
| 56 | * FLUSH the modules for this control path |
| 57 | * @ctx : ctl path ctx pointer |
| 58 | * @flushbits : module flushmask |
| 59 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 60 | void (*setup_flush)(struct sde_hw_ctl *ctx, |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame^] | 61 | u32 flushbits); |
| 62 | |
| 63 | /** |
| 64 | * Setup ctl_path interface config |
| 65 | * @ctx |
| 66 | * @cfg : interface config structure pointer |
| 67 | */ |
| 68 | void (*setup_intf_cfg)(struct sde_hw_ctl *ctx, |
| 69 | struct sde_hw_intf_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 70 | |
| 71 | int (*reset)(struct sde_hw_ctl *c); |
| 72 | |
| 73 | int (*get_bitmask_sspp)(struct sde_hw_ctl *ctx, |
| 74 | u32 *flushbits, |
| 75 | enum sde_sspp blk); |
| 76 | |
| 77 | int (*get_bitmask_mixer)(struct sde_hw_ctl *ctx, |
| 78 | u32 *flushbits, |
| 79 | enum sde_lm blk); |
| 80 | |
| 81 | int (*get_bitmask_dspp)(struct sde_hw_ctl *ctx, |
| 82 | u32 *flushbits, |
| 83 | enum sde_dspp blk); |
| 84 | |
| 85 | int (*get_bitmask_intf)(struct sde_hw_ctl *ctx, |
| 86 | u32 *flushbits, |
| 87 | enum sde_intf blk); |
| 88 | |
| 89 | int (*get_bitmask_cdm)(struct sde_hw_ctl *ctx, |
| 90 | u32 *flushbits, |
| 91 | enum sde_cdm blk); |
| 92 | |
| 93 | void (*setup_blendstage)(struct sde_hw_ctl *ctx, |
| 94 | enum sde_lm lm, |
| 95 | struct sde_hw_stage_cfg *cfg); |
| 96 | }; |
| 97 | |
| 98 | /** |
| 99 | * struct sde_hw_ctl : CTL PATH driver object |
| 100 | * @struct sde_hw_blk_reg_map *hw; |
| 101 | * @idx |
| 102 | * @ctl_hw_caps |
| 103 | * @mixer_hw_caps |
| 104 | * @ops |
| 105 | */ |
| 106 | struct sde_hw_ctl { |
| 107 | /* base */ |
| 108 | struct sde_hw_blk_reg_map hw; |
| 109 | |
| 110 | /* ctl path */ |
| 111 | int idx; |
| 112 | const struct sde_ctl_cfg *caps; |
| 113 | int mixer_count; |
| 114 | const struct sde_lm_cfg *mixer_hw_caps; |
| 115 | |
| 116 | /* ops */ |
| 117 | struct sde_hw_ctl_ops ops; |
| 118 | }; |
| 119 | |
| 120 | /** |
| 121 | * sde_hw_ctl_init(): Initializes the ctl_path hw driver object. |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame^] | 122 | * should be called before accessing every ctl path registers. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 123 | * @idx: ctl_path index for which driver object is required |
| 124 | * @addr: mapped register io address of MDP |
| 125 | * @m : pointer to mdss catalog data |
| 126 | */ |
| 127 | struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, |
| 128 | void __iomem *addr, |
| 129 | struct sde_mdss_cfg *m); |
| 130 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame^] | 131 | /** |
| 132 | * sde_hw_ctl_destroy(): Destroys ctl driver context |
| 133 | * should be called to free the context |
| 134 | */ |
| 135 | void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx); |
| 136 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 137 | #endif /*_SDE_HW_MDP_CTL_H */ |