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Amit Kucheria088d01b2010-10-07 03:58:12 +03001/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +020021#include <linux/leds.h>
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +020022#include <linux/input.h>
Amit Kucheria088d01b2010-10-07 03:58:12 +030023#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/fsl_devices.h>
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +020026#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
Amit Kucheria088d01b2010-10-07 03:58:12 +030028
29#include <mach/common.h>
30#include <mach/hardware.h>
31#include <mach/iomux-mx51.h>
32#include <mach/i2c.h>
33#include <mach/mxc_ehci.h>
34
35#include <asm/irq.h>
36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40
41#include "devices-imx51.h"
42#include "devices.h"
43
Amit Kucheria81490fc2010-10-07 03:58:25 +030044#define MX51_USB_PLL_DIV_24_MHZ 0x01
45
Arnaud Patard (Rtp)96886c42010-11-26 15:20:52 +010046#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
47#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
48#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +020049
Arnaud Patard (Rtp)96886c42010-11-26 15:20:52 +010050#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
51#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
52#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +020053
Arnaud Patard (Rtp)96886c42010-11-26 15:20:52 +010054#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +020055
Arnaud Patard (Rtp)96886c42010-11-26 15:20:52 +010056#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
57#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +020058
Arnaud Patard (Rtp)c2932bf2010-10-27 14:40:55 +020059/* board 1.1 doesn't have same reset gpio */
Arnaud Patard (Rtp)96886c42010-11-26 15:20:52 +010060#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
61#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
Arnaud Patard (Rtp)c2932bf2010-10-27 14:40:55 +020062
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +020063/* the pci ids pin have pull up. they're driven low according to board id */
64#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
66#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +020067#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +020068
Lothar Waßmann8f5260c2010-10-26 14:28:31 +020069static iomux_v3_cfg_t mx51efikamx_pads[] = {
Amit Kucheria088d01b2010-10-07 03:58:12 +030070 /* UART1 */
71 MX51_PAD_UART1_RXD__UART1_RXD,
72 MX51_PAD_UART1_TXD__UART1_TXD,
73 MX51_PAD_UART1_RTS__UART1_RTS,
74 MX51_PAD_UART1_CTS__UART1_CTS,
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +020075 /* board id */
76 MX51_PAD_PCBID0,
77 MX51_PAD_PCBID1,
78 MX51_PAD_PCBID2,
Arnaud Patard (Rtp)a96eb142010-10-27 14:40:49 +020079
80 /* SD 1 */
81 MX51_PAD_SD1_CMD__SD1_CMD,
82 MX51_PAD_SD1_CLK__SD1_CLK,
83 MX51_PAD_SD1_DATA0__SD1_DATA0,
84 MX51_PAD_SD1_DATA1__SD1_DATA1,
85 MX51_PAD_SD1_DATA2__SD1_DATA2,
86 MX51_PAD_SD1_DATA3__SD1_DATA3,
87
88 /* SD 2 */
89 MX51_PAD_SD2_CMD__SD2_CMD,
90 MX51_PAD_SD2_CLK__SD2_CLK,
91 MX51_PAD_SD2_DATA0__SD2_DATA0,
92 MX51_PAD_SD2_DATA1__SD2_DATA1,
93 MX51_PAD_SD2_DATA2__SD2_DATA2,
94 MX51_PAD_SD2_DATA3__SD2_DATA3,
95
96 /* SD/MMC WP/CD */
Sascha Haueree1ae4d2010-12-15 09:56:35 +010097 MX51_PAD_GPIO1_0__SD1_CD,
98 MX51_PAD_GPIO1_1__SD1_WP,
99 MX51_PAD_GPIO1_7__SD2_WP,
100 MX51_PAD_GPIO1_8__SD2_CD,
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +0200101
102 /* leds */
Sascha Haueree1ae4d2010-12-15 09:56:35 +0100103 MX51_PAD_CSI1_D9__GPIO3_13,
104 MX51_PAD_CSI1_VSYNC__GPIO3_14,
105 MX51_PAD_CSI1_HSYNC__GPIO3_15,
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +0200106
107 /* power key */
108 MX51_PAD_PWRKEY,
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +0200109
110 /* spi */
111 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
112 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
Sascha Haueree1ae4d2010-12-15 09:56:35 +0100113 MX51_PAD_CSPI1_SS0__GPIO4_24,
114 MX51_PAD_CSPI1_SS1__GPIO4_25,
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +0200115 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
116 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
Arnaud Patard (Rtp)c2932bf2010-10-27 14:40:55 +0200117
118 /* reset */
Sascha Haueree1ae4d2010-12-15 09:56:35 +0100119 MX51_PAD_DI1_PIN13__GPIO3_2,
120 MX51_PAD_GPIO1_4__GPIO1_4,
Amit Kucheria088d01b2010-10-07 03:58:12 +0300121};
122
123/* Serial ports */
124#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
125static const struct imxuart_platform_data uart_pdata = {
126 .flags = IMXUART_HAVE_RTSCTS,
127};
128
129static inline void mxc_init_imx_uart(void)
130{
131 imx51_add_imx_uart(0, &uart_pdata);
132 imx51_add_imx_uart(1, &uart_pdata);
133 imx51_add_imx_uart(2, &uart_pdata);
134}
135#else /* !SERIAL_IMX */
136static inline void mxc_init_imx_uart(void)
137{
138}
139#endif /* SERIAL_IMX */
140
Amit Kucheria81490fc2010-10-07 03:58:25 +0300141/* This function is board specific as the bit mask for the plldiv will also
142 * be different for other Freescale SoCs, thus a common bitmask is not
143 * possible and cannot get place in /plat-mxc/ehci.c.
144 */
145static int initialize_otg_port(struct platform_device *pdev)
146{
147 u32 v;
148 void __iomem *usb_base;
149 void __iomem *usbother_base;
150 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
Fabio Estevam28a4f902010-12-13 10:47:05 -0200151 if (!usb_base)
152 return -ENOMEM;
Amit Kucheria81490fc2010-10-07 03:58:25 +0300153 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
154
155 /* Set the PHY clock to 19.2MHz */
156 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
157 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
158 v |= MX51_USB_PLL_DIV_24_MHZ;
159 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
160 iounmap(usb_base);
161 return 0;
162}
163
164static struct mxc_usbh_platform_data dr_utmi_config = {
165 .init = initialize_otg_port,
166 .portsc = MXC_EHCI_UTMI_16BIT,
167 .flags = MXC_EHCI_INTERNAL_PHY,
168};
169
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +0200170/* PCBID2 PCBID1 PCBID0 STATE
171 1 1 1 ER1:rev1.1
172 1 1 0 ER2:rev1.2
173 1 0 1 ER3:rev1.3
174 1 0 0 ER4:rev1.4
175*/
176static void __init mx51_efikamx_board_id(void)
177{
178 int id;
179
180 /* things are taking time to settle */
181 msleep(150);
182
183 gpio_request(EFIKAMX_PCBID0, "pcbid0");
184 gpio_direction_input(EFIKAMX_PCBID0);
185 gpio_request(EFIKAMX_PCBID1, "pcbid1");
186 gpio_direction_input(EFIKAMX_PCBID1);
187 gpio_request(EFIKAMX_PCBID2, "pcbid2");
188 gpio_direction_input(EFIKAMX_PCBID2);
189
190 id = gpio_get_value(EFIKAMX_PCBID0);
191 id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
192 id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
193
194 switch (id) {
195 case 7:
196 system_rev = 0x11;
197 break;
198 case 6:
199 system_rev = 0x12;
200 break;
201 case 5:
202 system_rev = 0x13;
203 break;
204 case 4:
205 system_rev = 0x14;
206 break;
207 default:
208 system_rev = 0x10;
209 break;
210 }
211
212 if ((system_rev == 0x10)
213 || (system_rev == 0x12)
214 || (system_rev == 0x14)) {
215 printk(KERN_WARNING
216 "EfikaMX: Unsupported board revision 1.%u!\n",
217 system_rev & 0xf);
218 }
219}
220
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +0200221static struct gpio_led mx51_efikamx_leds[] = {
222 {
223 .name = "efikamx:green",
224 .default_trigger = "default-on",
225 .gpio = EFIKAMX_GREEN_LED,
226 },
227 {
228 .name = "efikamx:red",
229 .default_trigger = "ide-disk",
230 .gpio = EFIKAMX_RED_LED,
231 },
232 {
233 .name = "efikamx:blue",
234 .default_trigger = "mmc0",
235 .gpio = EFIKAMX_BLUE_LED,
236 },
237};
238
239static struct gpio_led_platform_data mx51_efikamx_leds_data = {
240 .leds = mx51_efikamx_leds,
241 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
242};
243
244static struct platform_device mx51_efikamx_leds_device = {
245 .name = "leds-gpio",
246 .id = -1,
247 .dev = {
248 .platform_data = &mx51_efikamx_leds_data,
249 },
250};
251
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +0200252static struct gpio_keys_button mx51_efikamx_powerkey[] = {
253 {
254 .code = KEY_POWER,
255 .gpio = EFIKAMX_POWER_KEY,
256 .type = EV_PWR,
257 .desc = "Power Button (CM)",
258 .wakeup = 1,
259 .debounce_interval = 10, /* ms */
260 },
261};
262
263static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
264 .buttons = mx51_efikamx_powerkey,
265 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
266};
267
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +0200268static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
269 {
270 .name = "u-boot",
271 .offset = 0,
272 .size = SZ_256K,
273 },
274 {
275 .name = "config",
276 .offset = MTDPART_OFS_APPEND,
277 .size = SZ_64K,
278 },
279};
280
281static struct flash_platform_data mx51_efikamx_spi_flash_data = {
282 .name = "spi_flash",
283 .parts = mx51_efikamx_spi_nor_partitions,
284 .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
285 .type = "sst25vf032b",
286};
287
288static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
289 {
290 .modalias = "m25p80",
291 .max_speed_hz = 25000000,
292 .bus_num = 0,
293 .chip_select = 1,
294 .platform_data = &mx51_efikamx_spi_flash_data,
295 .irq = -1,
296 },
297};
298
299static int mx51_efikamx_spi_cs[] = {
300 EFIKAMX_SPI_CS0,
301 EFIKAMX_SPI_CS1,
302};
303
304static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
305 .chipselect = mx51_efikamx_spi_cs,
306 .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
307};
308
Arnaud Patard (Rtp)c2932bf2010-10-27 14:40:55 +0200309void mx51_efikamx_reset(void)
310{
311 if (system_rev == 0x11)
312 gpio_direction_output(EFIKAMX_RESET1_1, 0);
313 else
314 gpio_direction_output(EFIKAMX_RESET, 0);
315}
316
Amit Kucheria088d01b2010-10-07 03:58:12 +0300317static void __init mxc_board_init(void)
318{
319 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
320 ARRAY_SIZE(mx51efikamx_pads));
Arnaud Patard (Rtp)f1dd3612010-10-27 14:40:46 +0200321 mx51_efikamx_board_id();
Amit Kucheria81490fc2010-10-07 03:58:25 +0300322 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
Amit Kucheria088d01b2010-10-07 03:58:12 +0300323 mxc_init_imx_uart();
Arnaud Patard (Rtp)0ef51952010-11-26 15:27:53 +0100324 imx51_add_sdhci_esdhc_imx(0, NULL);
Arnaud Patard (Rtp)a96eb142010-10-27 14:40:49 +0200325
326 /* on < 1.2 boards both SD controllers are used */
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +0200327 if (system_rev < 0x12) {
Arnaud Patard (Rtp)0ef51952010-11-26 15:27:53 +0100328 imx51_add_sdhci_esdhc_imx(1, NULL);
Arnaud Patard (Rtp)9d2c0ef2010-10-27 14:40:51 +0200329 mx51_efikamx_leds[2].default_trigger = "mmc1";
330 }
331
332 platform_device_register(&mx51_efikamx_leds_device);
Arnaud Patard (Rtp)fcbd0c52010-10-27 14:40:52 +0200333 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
Arnaud Patard (Rtp)c6e34a4c2010-10-27 14:40:54 +0200334
335 spi_register_board_info(mx51_efikamx_spi_board_info,
336 ARRAY_SIZE(mx51_efikamx_spi_board_info));
337 imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
Arnaud Patard (Rtp)c2932bf2010-10-27 14:40:55 +0200338
339 if (system_rev == 0x11) {
340 gpio_request(EFIKAMX_RESET1_1, "reset");
341 gpio_direction_output(EFIKAMX_RESET1_1, 1);
342 } else {
343 gpio_request(EFIKAMX_RESET, "reset");
344 gpio_direction_output(EFIKAMX_RESET, 1);
345 }
Amit Kucheria088d01b2010-10-07 03:58:12 +0300346}
347
348static void __init mx51_efikamx_timer_init(void)
349{
350 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
351}
352
353static struct sys_timer mxc_timer = {
354 .init = mx51_efikamx_timer_init,
355};
356
357MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
358 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
Amit Kucheria088d01b2010-10-07 03:58:12 +0300359 .boot_params = MX51_PHYS_OFFSET + 0x100,
360 .map_io = mx51_map_io,
361 .init_irq = mx51_init_irq,
362 .init_machine = mxc_board_init,
363 .timer = &mxc_timer,
364MACHINE_END