Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Red Hat |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | #ifndef __HDMI_CONNECTOR_H__ |
| 19 | #define __HDMI_CONNECTOR_H__ |
| 20 | |
| 21 | #include <linux/i2c.h> |
| 22 | #include <linux/clk.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/regulator/consumer.h> |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 25 | #include <linux/hdmi.h> |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 26 | |
| 27 | #include "msm_drv.h" |
| 28 | #include "hdmi.xml.h" |
| 29 | |
Archit Taneja | dc50f782 | 2016-02-25 11:22:36 +0530 | [diff] [blame] | 30 | #define HDMI_MAX_NUM_GPIO 6 |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 31 | |
| 32 | struct hdmi_phy; |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 33 | struct hdmi_platform_config; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 34 | |
Archit Taneja | dc50f782 | 2016-02-25 11:22:36 +0530 | [diff] [blame] | 35 | struct hdmi_gpio_data { |
| 36 | int num; |
| 37 | bool output; |
| 38 | int value; |
| 39 | const char *label; |
| 40 | }; |
| 41 | |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 42 | struct hdmi_audio { |
| 43 | bool enabled; |
| 44 | struct hdmi_audio_infoframe infoframe; |
| 45 | int rate; |
| 46 | }; |
| 47 | |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 48 | struct hdmi_hdcp_ctrl; |
| 49 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 50 | struct hdmi { |
| 51 | struct drm_device *dev; |
| 52 | struct platform_device *pdev; |
Srinivas Kandagatla | f142701 | 2016-06-10 10:45:56 +0100 | [diff] [blame] | 53 | struct platform_device *audio_pdev; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 54 | |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 55 | const struct hdmi_platform_config *config; |
| 56 | |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 57 | /* audio state: */ |
| 58 | struct hdmi_audio audio; |
| 59 | |
| 60 | /* video state: */ |
| 61 | bool power_on; |
| 62 | unsigned long int pixclock; |
| 63 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 64 | void __iomem *mmio; |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 65 | void __iomem *qfprom_mmio; |
| 66 | phys_addr_t mmio_phy_addr; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 67 | |
Stephane Viau | 447fa52 | 2015-01-13 14:33:40 -0500 | [diff] [blame] | 68 | struct regulator **hpd_regs; |
| 69 | struct regulator **pwr_regs; |
| 70 | struct clk **hpd_clks; |
| 71 | struct clk **pwr_clks; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 72 | |
| 73 | struct hdmi_phy *phy; |
Archit Taneja | e00012b | 2016-02-25 11:22:40 +0530 | [diff] [blame] | 74 | struct device *phy_dev; |
| 75 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 76 | struct i2c_adapter *i2c; |
| 77 | struct drm_connector *connector; |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 78 | struct drm_bridge *bridge; |
| 79 | |
| 80 | /* the encoder we are hooked to (outside of hdmi block) */ |
| 81 | struct drm_encoder *encoder; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 82 | |
| 83 | bool hdmi_mode; /* are we in hdmi mode? */ |
| 84 | |
| 85 | int irq; |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 86 | struct workqueue_struct *workq; |
| 87 | |
| 88 | struct hdmi_hdcp_ctrl *hdcp_ctrl; |
| 89 | |
| 90 | /* |
| 91 | * spinlock to protect registers shared by different execution |
| 92 | * REG_HDMI_CTRL |
| 93 | * REG_HDMI_DDC_ARBITRATION |
| 94 | * REG_HDMI_HDCP_INT_CTRL |
| 95 | * REG_HDMI_HPD_CTRL |
| 96 | */ |
| 97 | spinlock_t reg_lock; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 98 | }; |
| 99 | |
| 100 | /* platform config data (ie. from DT, or pdata) */ |
| 101 | struct hdmi_platform_config { |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 102 | const char *mmio_name; |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 103 | const char *qfprom_mmio_name; |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 104 | |
| 105 | /* regulators that need to be on for hpd: */ |
| 106 | const char **hpd_reg_names; |
| 107 | int hpd_reg_cnt; |
| 108 | |
| 109 | /* regulators that need to be on for screen pwr: */ |
| 110 | const char **pwr_reg_names; |
| 111 | int pwr_reg_cnt; |
| 112 | |
| 113 | /* clks that need to be on for hpd: */ |
| 114 | const char **hpd_clk_names; |
Stephane Viau | b77f47e | 2014-06-06 10:03:32 -0400 | [diff] [blame] | 115 | const long unsigned *hpd_freq; |
Rob Clark | dada25b | 2013-12-01 12:12:54 -0500 | [diff] [blame] | 116 | int hpd_clk_cnt; |
| 117 | |
| 118 | /* clks that need to be on for screen pwr (ie pixel clk): */ |
| 119 | const char **pwr_clk_names; |
| 120 | int pwr_clk_cnt; |
| 121 | |
| 122 | /* gpio's: */ |
Archit Taneja | dc50f782 | 2016-02-25 11:22:36 +0530 | [diff] [blame] | 123 | struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO]; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 124 | }; |
| 125 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 126 | void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 127 | |
| 128 | static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) |
| 129 | { |
| 130 | msm_writel(data, hdmi->mmio + reg); |
| 131 | } |
| 132 | |
| 133 | static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) |
| 134 | { |
| 135 | return msm_readl(hdmi->mmio + reg); |
| 136 | } |
| 137 | |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 138 | static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg) |
| 139 | { |
| 140 | return msm_readl(hdmi->qfprom_mmio + reg); |
| 141 | } |
| 142 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 143 | /* |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 144 | * hdmi phy: |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 145 | */ |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 146 | |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 147 | enum hdmi_phy_type { |
| 148 | MSM_HDMI_PHY_8x60, |
| 149 | MSM_HDMI_PHY_8960, |
| 150 | MSM_HDMI_PHY_8x74, |
Archit Taneja | e17afdc | 2016-02-25 11:22:44 +0530 | [diff] [blame] | 151 | MSM_HDMI_PHY_8996, |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 152 | MSM_HDMI_PHY_MAX, |
| 153 | }; |
| 154 | |
| 155 | struct hdmi_phy_cfg { |
| 156 | enum hdmi_phy_type type; |
| 157 | void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock); |
| 158 | void (*powerdown)(struct hdmi_phy *phy); |
| 159 | const char * const *reg_names; |
| 160 | int num_regs; |
| 161 | const char * const *clk_names; |
| 162 | int num_clks; |
| 163 | }; |
| 164 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 165 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg; |
| 166 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg; |
| 167 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg; |
| 168 | extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg; |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 169 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 170 | struct hdmi_phy { |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 171 | struct platform_device *pdev; |
| 172 | void __iomem *mmio; |
| 173 | struct hdmi_phy_cfg *cfg; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 174 | const struct hdmi_phy_funcs *funcs; |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 175 | struct regulator **regs; |
| 176 | struct clk **clks; |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 177 | }; |
| 178 | |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 179 | static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data) |
| 180 | { |
| 181 | msm_writel(data, phy->mmio + reg); |
| 182 | } |
| 183 | |
| 184 | static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg) |
| 185 | { |
| 186 | return msm_readl(phy->mmio + reg); |
| 187 | } |
| 188 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 189 | int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy); |
| 190 | void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy); |
| 191 | void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock); |
| 192 | void msm_hdmi_phy_powerdown(struct hdmi_phy *phy); |
| 193 | void __init msm_hdmi_phy_driver_register(void); |
| 194 | void __exit msm_hdmi_phy_driver_unregister(void); |
Archit Taneja | 15b4a45 | 2016-02-25 11:22:38 +0530 | [diff] [blame] | 195 | |
Archit Taneja | ea18489 | 2016-02-25 11:22:39 +0530 | [diff] [blame] | 196 | #ifdef CONFIG_COMMON_CLK |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 197 | int msm_hdmi_pll_8960_init(struct platform_device *pdev); |
| 198 | int msm_hdmi_pll_8996_init(struct platform_device *pdev); |
Archit Taneja | ea18489 | 2016-02-25 11:22:39 +0530 | [diff] [blame] | 199 | #else |
Rob Clark | 0a69509 | 2016-03-23 10:09:00 -0400 | [diff] [blame] | 200 | static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev) |
Archit Taneja | ea18489 | 2016-02-25 11:22:39 +0530 | [diff] [blame] | 201 | { |
| 202 | return -ENODEV; |
| 203 | } |
Archit Taneja | e17afdc | 2016-02-25 11:22:44 +0530 | [diff] [blame] | 204 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 205 | static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev) |
Archit Taneja | e17afdc | 2016-02-25 11:22:44 +0530 | [diff] [blame] | 206 | { |
| 207 | return -ENODEV; |
| 208 | } |
Archit Taneja | ea18489 | 2016-02-25 11:22:39 +0530 | [diff] [blame] | 209 | #endif |
| 210 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 211 | /* |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 212 | * audio: |
| 213 | */ |
Srinivas Kandagatla | f142701 | 2016-06-10 10:45:56 +0100 | [diff] [blame] | 214 | /* Supported HDMI Audio channels and rates */ |
| 215 | #define MSM_HDMI_AUDIO_CHANNEL_2 0 |
| 216 | #define MSM_HDMI_AUDIO_CHANNEL_4 1 |
| 217 | #define MSM_HDMI_AUDIO_CHANNEL_6 2 |
| 218 | #define MSM_HDMI_AUDIO_CHANNEL_8 3 |
| 219 | |
| 220 | #define HDMI_SAMPLE_RATE_32KHZ 0 |
| 221 | #define HDMI_SAMPLE_RATE_44_1KHZ 1 |
| 222 | #define HDMI_SAMPLE_RATE_48KHZ 2 |
| 223 | #define HDMI_SAMPLE_RATE_88_2KHZ 3 |
| 224 | #define HDMI_SAMPLE_RATE_96KHZ 4 |
| 225 | #define HDMI_SAMPLE_RATE_176_4KHZ 5 |
| 226 | #define HDMI_SAMPLE_RATE_192KHZ 6 |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 227 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 228 | int msm_hdmi_audio_update(struct hdmi *hdmi); |
| 229 | int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled, |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 230 | uint32_t num_of_channels, uint32_t channel_allocation, |
| 231 | uint32_t level_shift, bool down_mix); |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 232 | void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate); |
Rob Clark | c0c0d9e | 2013-12-11 14:44:02 -0500 | [diff] [blame] | 233 | |
| 234 | |
| 235 | /* |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 236 | * hdmi bridge: |
| 237 | */ |
| 238 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 239 | struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi); |
| 240 | void msm_hdmi_bridge_destroy(struct drm_bridge *bridge); |
Rob Clark | a3376e3 | 2013-08-30 13:02:15 -0400 | [diff] [blame] | 241 | |
| 242 | /* |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 243 | * hdmi connector: |
| 244 | */ |
| 245 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 246 | void msm_hdmi_connector_irq(struct drm_connector *connector); |
| 247 | struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 248 | |
| 249 | /* |
| 250 | * i2c adapter for ddc: |
| 251 | */ |
| 252 | |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 253 | void msm_hdmi_i2c_irq(struct i2c_adapter *i2c); |
| 254 | void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c); |
| 255 | struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi); |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 256 | |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 257 | /* |
| 258 | * hdcp |
| 259 | */ |
Rob Clark | feb46f0 | 2016-03-20 10:16:29 -0400 | [diff] [blame] | 260 | #ifdef CONFIG_DRM_MSM_HDMI_HDCP |
Arnd Bergmann | fcda50c | 2016-02-22 22:08:35 +0100 | [diff] [blame] | 261 | struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi); |
| 262 | void msm_hdmi_hdcp_destroy(struct hdmi *hdmi); |
| 263 | void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl); |
| 264 | void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl); |
| 265 | void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl); |
Rob Clark | feb46f0 | 2016-03-20 10:16:29 -0400 | [diff] [blame] | 266 | #else |
| 267 | static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi) |
| 268 | { |
| 269 | return ERR_PTR(-ENXIO); |
| 270 | } |
| 271 | static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {} |
| 272 | static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} |
| 273 | static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} |
| 274 | static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} |
| 275 | #endif |
jilai wang | c6a57a5 | 2015-04-02 17:49:01 -0400 | [diff] [blame] | 276 | |
Rob Clark | c8afe68 | 2013-06-26 12:44:06 -0400 | [diff] [blame] | 277 | #endif /* __HDMI_CONNECTOR_H__ */ |