Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 43 | static void |
| 44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 47 | "Device suspended\n"); |
| 48 | } |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 49 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 51 | { |
| 52 | u32 gt_thread_status_mask; |
| 53 | |
| 54 | if (IS_HASWELL(dev_priv->dev)) |
| 55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 56 | else |
| 57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 58 | |
| 59 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 60 | * thread to wake up. |
| 61 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 63 | DRM_ERROR("GT thread status wait timed out\n"); |
| 64 | } |
| 65 | |
| 66 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 67 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 68 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 69 | /* something from same cacheline, but !FORCEWAKE */ |
| 70 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 71 | } |
| 72 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 73 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
| 74 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 75 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 76 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 77 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 78 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 79 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 80 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 81 | /* something from same cacheline, but !FORCEWAKE */ |
| 82 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 83 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 84 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 85 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 86 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 87 | |
| 88 | /* WaRsForcewakeWaitTC0:snb */ |
| 89 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 90 | } |
| 91 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 92 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 93 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 94 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 95 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 96 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 97 | } |
| 98 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 99 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 100 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 101 | { |
| 102 | u32 forcewake_ack; |
| 103 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 106 | else |
| 107 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 108 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 109 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 110 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 111 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 112 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 113 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 114 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 115 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 116 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 117 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 121 | |
| 122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
Ben Widawsky | 0f161f7 | 2013-11-02 21:07:50 -0700 | [diff] [blame] | 123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
| 124 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 128 | { |
| 129 | u32 gtfifodbg; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 130 | |
| 131 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
Ville Syrjälä | 90f256b | 2013-11-14 01:59:59 +0200 | [diff] [blame] | 132 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
| 133 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 134 | } |
| 135 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 136 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
| 137 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 138 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 139 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 140 | /* something from same cacheline, but !FORCEWAKE */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 141 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 142 | gen6_gt_check_fifodbg(dev_priv); |
| 143 | } |
| 144 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 145 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 146 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 147 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 148 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 149 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 150 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 151 | __raw_posting_read(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 152 | |
| 153 | if (IS_GEN7(dev_priv->dev)) |
| 154 | gen6_gt_check_fifodbg(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 158 | { |
| 159 | int ret = 0; |
| 160 | |
Deepak S | 5135d64 | 2013-11-29 15:56:30 +0530 | [diff] [blame] | 161 | /* On VLV, FIFO will be shared by both SW and HW. |
| 162 | * So, we need to read the FREE_ENTRIES everytime */ |
| 163 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 164 | dev_priv->uncore.fifo_count = |
| 165 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 166 | GT_FIFO_FREE_ENTRIES_MASK; |
| 167 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 168 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 169 | int loop = 500; |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 170 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 171 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 172 | udelay(10); |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 173 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 174 | } |
| 175 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 176 | ++ret; |
| 177 | dev_priv->uncore.fifo_count = fifo; |
| 178 | } |
| 179 | dev_priv->uncore.fifo_count--; |
| 180 | |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 185 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 187 | _MASKED_BIT_DISABLE(0xffff)); |
Jani Nikula | 05adaf1 | 2014-05-09 14:52:34 +0300 | [diff] [blame] | 188 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 189 | _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 190 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 191 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 192 | } |
| 193 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 194 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 195 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 196 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 197 | /* Check for Render Engine */ |
| 198 | if (FORCEWAKE_RENDER & fw_engine) { |
| 199 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 200 | FORCEWAKE_ACK_VLV) & |
| 201 | FORCEWAKE_KERNEL) == 0, |
| 202 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 203 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 204 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 205 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 206 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 207 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 208 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 209 | FORCEWAKE_ACK_VLV) & |
| 210 | FORCEWAKE_KERNEL), |
| 211 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 212 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 213 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 214 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 215 | /* Check for Media Engine */ |
| 216 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 217 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 218 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 219 | FORCEWAKE_KERNEL) == 0, |
| 220 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 221 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 222 | |
| 223 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 224 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 225 | |
| 226 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 227 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 228 | FORCEWAKE_KERNEL), |
| 229 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 230 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 231 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 232 | |
| 233 | /* WaRsForcewakeWaitTC0:vlv */ |
Ville Syrjälä | 3f4e349 | 2014-05-23 21:00:18 +0530 | [diff] [blame^] | 234 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 235 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 238 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 239 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 240 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 241 | |
| 242 | /* Check for Render Engine */ |
| 243 | if (FORCEWAKE_RENDER & fw_engine) |
| 244 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 245 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 246 | |
| 247 | |
| 248 | /* Check for Media Engine */ |
| 249 | if (FORCEWAKE_MEDIA & fw_engine) |
| 250 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 251 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 252 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 253 | /* The below doubles as a POSTING_READ */ |
| 254 | gen6_gt_check_fifodbg(dev_priv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 255 | |
| 256 | } |
| 257 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 258 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 259 | { |
| 260 | unsigned long irqflags; |
| 261 | |
| 262 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 263 | |
| 264 | if (fw_engine & FORCEWAKE_RENDER && |
| 265 | dev_priv->uncore.fw_rendercount++ != 0) |
| 266 | fw_engine &= ~FORCEWAKE_RENDER; |
| 267 | if (fw_engine & FORCEWAKE_MEDIA && |
| 268 | dev_priv->uncore.fw_mediacount++ != 0) |
| 269 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 270 | |
| 271 | if (fw_engine) |
| 272 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 273 | |
| 274 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 275 | } |
| 276 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 277 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 278 | { |
| 279 | unsigned long irqflags; |
| 280 | |
| 281 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 282 | |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 283 | if (fw_engine & FORCEWAKE_RENDER) { |
| 284 | WARN_ON(!dev_priv->uncore.fw_rendercount); |
| 285 | if (--dev_priv->uncore.fw_rendercount != 0) |
| 286 | fw_engine &= ~FORCEWAKE_RENDER; |
| 287 | } |
| 288 | |
| 289 | if (fw_engine & FORCEWAKE_MEDIA) { |
| 290 | WARN_ON(!dev_priv->uncore.fw_mediacount); |
| 291 | if (--dev_priv->uncore.fw_mediacount != 0) |
| 292 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 293 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 294 | |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 295 | if (fw_engine) |
| 296 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 297 | |
| 298 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 299 | } |
| 300 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 301 | static void gen6_force_wake_timer(unsigned long arg) |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 302 | { |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 303 | struct drm_i915_private *dev_priv = (void *)arg; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 304 | unsigned long irqflags; |
| 305 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 306 | assert_device_not_suspended(dev_priv); |
| 307 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 308 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 309 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 310 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 311 | if (--dev_priv->uncore.forcewake_count == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 312 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 313 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 314 | |
| 315 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 316 | } |
| 317 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 318 | static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 319 | { |
| 320 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 321 | unsigned long irqflags; |
| 322 | |
| 323 | del_timer_sync(&dev_priv->uncore.force_wake_timer); |
| 324 | |
| 325 | /* Hold uncore.lock across reset to prevent any register access |
| 326 | * with forcewake not set correctly |
| 327 | */ |
| 328 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 329 | |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 330 | if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 331 | vlv_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 332 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 333 | __gen6_gt_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 334 | |
| 335 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 336 | __gen7_gt_force_wake_mt_reset(dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 337 | |
| 338 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 339 | unsigned fw = 0; |
| 340 | |
| 341 | if (IS_VALLEYVIEW(dev)) { |
| 342 | if (dev_priv->uncore.fw_rendercount) |
| 343 | fw |= FORCEWAKE_RENDER; |
| 344 | |
| 345 | if (dev_priv->uncore.fw_mediacount) |
| 346 | fw |= FORCEWAKE_MEDIA; |
| 347 | } else { |
| 348 | if (dev_priv->uncore.forcewake_count) |
| 349 | fw = FORCEWAKE_ALL; |
| 350 | } |
| 351 | |
| 352 | if (fw) |
| 353 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); |
| 354 | |
| 355 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 356 | dev_priv->uncore.fifo_count = |
| 357 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 358 | GT_FIFO_FREE_ENTRIES_MASK; |
| 359 | } else { |
| 360 | dev_priv->uncore.forcewake_count = 0; |
| 361 | dev_priv->uncore.fw_rendercount = 0; |
| 362 | dev_priv->uncore.fw_mediacount = 0; |
| 363 | } |
| 364 | |
| 365 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 366 | } |
| 367 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 368 | void intel_uncore_early_sanitize(struct drm_device *dev) |
| 369 | { |
| 370 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 371 | |
| 372 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 373 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 374 | |
Ben Widawsky | 1d2866b | 2014-04-18 18:04:28 -0300 | [diff] [blame] | 375 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 376 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 377 | /* The docs do not explain exactly how the calculation can be |
| 378 | * made. It is somewhat guessable, but for now, it's always |
| 379 | * 128MB. |
| 380 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 381 | * set up */ |
| 382 | dev_priv->ellc_size = 128; |
| 383 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 384 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 385 | |
Ville Syrjälä | 9705887 | 2013-12-03 11:30:09 +0200 | [diff] [blame] | 386 | /* clear out old GT FIFO errors */ |
| 387 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 388 | __raw_i915_write32(dev_priv, GTFIFODBG, |
| 389 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| 390 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 391 | intel_uncore_forcewake_reset(dev, false); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | void intel_uncore_sanitize(struct drm_device *dev) |
| 395 | { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 396 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 397 | intel_disable_gt_powersave(dev); |
| 398 | } |
| 399 | |
| 400 | /* |
| 401 | * Generally this is called implicitly by the register read function. However, |
| 402 | * if some sequence requires the GT to not power down then this function should |
| 403 | * be called at the beginning of the sequence followed by a call to |
| 404 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 405 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 406 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 407 | { |
| 408 | unsigned long irqflags; |
| 409 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 410 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 411 | return; |
| 412 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 413 | intel_runtime_pm_get(dev_priv); |
| 414 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 415 | /* Redirect to VLV specific routine */ |
| 416 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 417 | return vlv_force_wake_get(dev_priv, fw_engine); |
| 418 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 419 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 420 | if (dev_priv->uncore.forcewake_count++ == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 421 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 422 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 423 | } |
| 424 | |
| 425 | /* |
| 426 | * see gen6_gt_force_wake_get() |
| 427 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 428 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 429 | { |
| 430 | unsigned long irqflags; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 431 | bool delayed = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 432 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 433 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 434 | return; |
| 435 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 436 | /* Redirect to VLV specific routine */ |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 437 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 438 | vlv_force_wake_put(dev_priv, fw_engine); |
| 439 | goto out; |
| 440 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 441 | |
| 442 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 443 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 444 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 445 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 446 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 447 | dev_priv->uncore.forcewake_count++; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 448 | delayed = true; |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 449 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
| 450 | jiffies + 1); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 451 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 452 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 453 | |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 454 | out: |
| 455 | if (!delayed) |
| 456 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 457 | } |
| 458 | |
Paulo Zanoni | e998c40 | 2014-02-21 13:52:26 -0300 | [diff] [blame] | 459 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
| 460 | { |
| 461 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 462 | return; |
| 463 | |
| 464 | WARN_ON(dev_priv->uncore.forcewake_count > 0); |
| 465 | } |
| 466 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 467 | /* We give fast paths for the really cool registers */ |
| 468 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 469 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 470 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 471 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 472 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 473 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 474 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 475 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 476 | REG_RANGE((reg), 0xB000, 0x12000) || \ |
| 477 | REG_RANGE((reg), 0x2E000, 0x30000)) |
| 478 | |
| 479 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ |
| 480 | (REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 481 | REG_RANGE((reg), 0x22000, 0x24000) || \ |
| 482 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 483 | |
| 484 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ |
| 485 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 486 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 487 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
| 488 | REG_RANGE((reg), 0xB000, 0xC000) || \ |
| 489 | REG_RANGE((reg), 0xE000, 0xE800)) |
| 490 | |
| 491 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ |
| 492 | (REG_RANGE((reg), 0x8800, 0x8900) || \ |
| 493 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 494 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 495 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ |
| 496 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ |
| 497 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 498 | |
| 499 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ |
| 500 | (REG_RANGE((reg), 0x4000, 0x5000) || \ |
| 501 | REG_RANGE((reg), 0x8000, 0x8300) || \ |
| 502 | REG_RANGE((reg), 0x8500, 0x8600) || \ |
| 503 | REG_RANGE((reg), 0x9000, 0xB000) || \ |
| 504 | REG_RANGE((reg), 0xC000, 0xC800) || \ |
| 505 | REG_RANGE((reg), 0xF000, 0x10000) || \ |
| 506 | REG_RANGE((reg), 0x14000, 0x14400) || \ |
| 507 | REG_RANGE((reg), 0x22000, 0x24000)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 508 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 509 | static void |
| 510 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 511 | { |
| 512 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 513 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 514 | * hence harmless to write 0 into. */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 515 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 516 | } |
| 517 | |
| 518 | static void |
| 519 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
| 520 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 521 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 522 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
| 523 | reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 524 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 525 | } |
| 526 | } |
| 527 | |
| 528 | static void |
| 529 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| 530 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 531 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 532 | DRM_ERROR("Unclaimed write to %x\n", reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 533 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 537 | #define REG_READ_HEADER(x) \ |
| 538 | unsigned long irqflags; \ |
| 539 | u##x val = 0; \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 540 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 541 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 542 | |
| 543 | #define REG_READ_FOOTER \ |
| 544 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 545 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 546 | return val |
| 547 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 548 | #define __gen4_read(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 549 | static u##x \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 550 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 551 | REG_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 552 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 553 | REG_READ_FOOTER; \ |
| 554 | } |
| 555 | |
| 556 | #define __gen5_read(x) \ |
| 557 | static u##x \ |
| 558 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 559 | REG_READ_HEADER(x); \ |
| 560 | ilk_dummy_write(dev_priv); \ |
| 561 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 562 | REG_READ_FOOTER; \ |
| 563 | } |
| 564 | |
| 565 | #define __gen6_read(x) \ |
| 566 | static u##x \ |
| 567 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 568 | REG_READ_HEADER(x); \ |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 569 | if (dev_priv->uncore.forcewake_count == 0 && \ |
| 570 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 571 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 572 | FORCEWAKE_ALL); \ |
Paulo Zanoni | aa0b3b5 | 2014-04-01 14:55:07 -0300 | [diff] [blame] | 573 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 574 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 575 | FORCEWAKE_ALL); \ |
| 576 | } else { \ |
| 577 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 578 | } \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 579 | REG_READ_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 580 | } |
| 581 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 582 | #define __vlv_read(x) \ |
| 583 | static u##x \ |
| 584 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 585 | unsigned fwengine = 0; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 586 | REG_READ_HEADER(x); \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 587 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
| 588 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 589 | fwengine = FORCEWAKE_RENDER; \ |
| 590 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 591 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 592 | fwengine = FORCEWAKE_MEDIA; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 593 | } \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 594 | if (fwengine) \ |
| 595 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 596 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 597 | if (fwengine) \ |
| 598 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 599 | REG_READ_FOOTER; \ |
| 600 | } |
| 601 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 602 | #define __chv_read(x) \ |
| 603 | static u##x \ |
| 604 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 605 | unsigned fwengine = 0; \ |
| 606 | REG_READ_HEADER(x); \ |
| 607 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 608 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 609 | fwengine = FORCEWAKE_RENDER; \ |
| 610 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 611 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 612 | fwengine = FORCEWAKE_MEDIA; \ |
| 613 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 614 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 615 | fwengine |= FORCEWAKE_RENDER; \ |
| 616 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 617 | fwengine |= FORCEWAKE_MEDIA; \ |
| 618 | } \ |
| 619 | if (fwengine) \ |
| 620 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 621 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 622 | if (fwengine) \ |
| 623 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 624 | REG_READ_FOOTER; \ |
| 625 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 626 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 627 | __chv_read(8) |
| 628 | __chv_read(16) |
| 629 | __chv_read(32) |
| 630 | __chv_read(64) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 631 | __vlv_read(8) |
| 632 | __vlv_read(16) |
| 633 | __vlv_read(32) |
| 634 | __vlv_read(64) |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 635 | __gen6_read(8) |
| 636 | __gen6_read(16) |
| 637 | __gen6_read(32) |
| 638 | __gen6_read(64) |
| 639 | __gen5_read(8) |
| 640 | __gen5_read(16) |
| 641 | __gen5_read(32) |
| 642 | __gen5_read(64) |
| 643 | __gen4_read(8) |
| 644 | __gen4_read(16) |
| 645 | __gen4_read(32) |
| 646 | __gen4_read(64) |
| 647 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 648 | #undef __chv_read |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 649 | #undef __vlv_read |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 650 | #undef __gen6_read |
| 651 | #undef __gen5_read |
| 652 | #undef __gen4_read |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 653 | #undef REG_READ_FOOTER |
| 654 | #undef REG_READ_HEADER |
| 655 | |
| 656 | #define REG_WRITE_HEADER \ |
| 657 | unsigned long irqflags; \ |
| 658 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 659 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 660 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 661 | |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 662 | #define REG_WRITE_FOOTER \ |
| 663 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
| 664 | |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 665 | #define __gen4_write(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 666 | static void \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 667 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 668 | REG_WRITE_HEADER; \ |
| 669 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 670 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | #define __gen5_write(x) \ |
| 674 | static void \ |
| 675 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 676 | REG_WRITE_HEADER; \ |
| 677 | ilk_dummy_write(dev_priv); \ |
| 678 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 679 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 680 | } |
| 681 | |
| 682 | #define __gen6_write(x) \ |
| 683 | static void \ |
| 684 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 685 | u32 __fifo_ret = 0; \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 686 | REG_WRITE_HEADER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 687 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 688 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 689 | } \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 690 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 691 | if (unlikely(__fifo_ret)) { \ |
| 692 | gen6_gt_check_fifodbg(dev_priv); \ |
| 693 | } \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 694 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 695 | } |
| 696 | |
| 697 | #define __hsw_write(x) \ |
| 698 | static void \ |
| 699 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 700 | u32 __fifo_ret = 0; \ |
| 701 | REG_WRITE_HEADER; \ |
| 702 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 703 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 704 | } \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 705 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 706 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 707 | if (unlikely(__fifo_ret)) { \ |
| 708 | gen6_gt_check_fifodbg(dev_priv); \ |
| 709 | } \ |
| 710 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 711 | REG_WRITE_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 712 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 713 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 714 | static const u32 gen8_shadowed_regs[] = { |
| 715 | FORCEWAKE_MT, |
| 716 | GEN6_RPNSWREQ, |
| 717 | GEN6_RC_VIDEO_FREQ, |
| 718 | RING_TAIL(RENDER_RING_BASE), |
| 719 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 720 | RING_TAIL(VEBOX_RING_BASE), |
| 721 | RING_TAIL(BLT_RING_BASE), |
| 722 | /* TODO: Other registers are not yet used */ |
| 723 | }; |
| 724 | |
| 725 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 726 | { |
| 727 | int i; |
| 728 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 729 | if (reg == gen8_shadowed_regs[i]) |
| 730 | return true; |
| 731 | |
| 732 | return false; |
| 733 | } |
| 734 | |
| 735 | #define __gen8_write(x) \ |
| 736 | static void \ |
| 737 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 738 | REG_WRITE_HEADER; \ |
Mika Kuoppala | e9dbd2b | 2014-02-18 19:10:24 +0200 | [diff] [blame] | 739 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
| 740 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 741 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 742 | FORCEWAKE_ALL); \ |
| 743 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 744 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 745 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 746 | FORCEWAKE_ALL); \ |
| 747 | } else { \ |
| 748 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 749 | } \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 750 | REG_WRITE_FOOTER; \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 751 | } |
| 752 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 753 | #define __chv_write(x) \ |
| 754 | static void \ |
| 755 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 756 | unsigned fwengine = 0; \ |
| 757 | bool shadowed = is_gen8_shadowed(dev_priv, reg); \ |
| 758 | REG_WRITE_HEADER; \ |
| 759 | if (!shadowed) { \ |
| 760 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 761 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 762 | fwengine = FORCEWAKE_RENDER; \ |
| 763 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 764 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 765 | fwengine = FORCEWAKE_MEDIA; \ |
| 766 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 767 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 768 | fwengine |= FORCEWAKE_RENDER; \ |
| 769 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 770 | fwengine |= FORCEWAKE_MEDIA; \ |
| 771 | } \ |
| 772 | } \ |
| 773 | if (fwengine) \ |
| 774 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 775 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 776 | if (fwengine) \ |
| 777 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 778 | REG_WRITE_FOOTER; \ |
| 779 | } |
| 780 | |
| 781 | __chv_write(8) |
| 782 | __chv_write(16) |
| 783 | __chv_write(32) |
| 784 | __chv_write(64) |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 785 | __gen8_write(8) |
| 786 | __gen8_write(16) |
| 787 | __gen8_write(32) |
| 788 | __gen8_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 789 | __hsw_write(8) |
| 790 | __hsw_write(16) |
| 791 | __hsw_write(32) |
| 792 | __hsw_write(64) |
| 793 | __gen6_write(8) |
| 794 | __gen6_write(16) |
| 795 | __gen6_write(32) |
| 796 | __gen6_write(64) |
| 797 | __gen5_write(8) |
| 798 | __gen5_write(16) |
| 799 | __gen5_write(32) |
| 800 | __gen5_write(64) |
| 801 | __gen4_write(8) |
| 802 | __gen4_write(16) |
| 803 | __gen4_write(32) |
| 804 | __gen4_write(64) |
| 805 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 806 | #undef __chv_write |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 807 | #undef __gen8_write |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 808 | #undef __hsw_write |
| 809 | #undef __gen6_write |
| 810 | #undef __gen5_write |
| 811 | #undef __gen4_write |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 812 | #undef REG_WRITE_FOOTER |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 813 | #undef REG_WRITE_HEADER |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 814 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 815 | void intel_uncore_init(struct drm_device *dev) |
| 816 | { |
| 817 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 818 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 819 | setup_timer(&dev_priv->uncore.force_wake_timer, |
| 820 | gen6_force_wake_timer, (unsigned long)dev_priv); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 821 | |
Daniel Vetter | 05efeebd | 2014-03-18 16:26:25 +0100 | [diff] [blame] | 822 | intel_uncore_early_sanitize(dev); |
| 823 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 824 | if (IS_VALLEYVIEW(dev)) { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 825 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 826 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
Ben Widawsky | 43d1b64 | 2013-11-07 16:24:31 -0800 | [diff] [blame] | 827 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 828 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
| 829 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 830 | } else if (IS_IVYBRIDGE(dev)) { |
| 831 | u32 ecobus; |
| 832 | |
| 833 | /* IVB configs may use multi-threaded forcewake */ |
| 834 | |
| 835 | /* A small trick here - if the bios hasn't configured |
| 836 | * MT forcewake, and if the device is in RC6, then |
| 837 | * force_wake_mt_get will not wake the device and the |
| 838 | * ECOBUS read will return zero. Which will be |
| 839 | * (correctly) interpreted by the test below as MT |
| 840 | * forcewake being disabled. |
| 841 | */ |
| 842 | mutex_lock(&dev->struct_mutex); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 843 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 844 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 845 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 846 | mutex_unlock(&dev->struct_mutex); |
| 847 | |
| 848 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 849 | dev_priv->uncore.funcs.force_wake_get = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 850 | __gen7_gt_force_wake_mt_get; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 851 | dev_priv->uncore.funcs.force_wake_put = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 852 | __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 853 | } else { |
| 854 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 855 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 856 | dev_priv->uncore.funcs.force_wake_get = |
| 857 | __gen6_gt_force_wake_get; |
| 858 | dev_priv->uncore.funcs.force_wake_put = |
| 859 | __gen6_gt_force_wake_put; |
| 860 | } |
| 861 | } else if (IS_GEN6(dev)) { |
| 862 | dev_priv->uncore.funcs.force_wake_get = |
| 863 | __gen6_gt_force_wake_get; |
| 864 | dev_priv->uncore.funcs.force_wake_put = |
| 865 | __gen6_gt_force_wake_put; |
| 866 | } |
| 867 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 868 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 869 | default: |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 870 | if (IS_CHERRYVIEW(dev)) { |
| 871 | dev_priv->uncore.funcs.mmio_writeb = chv_write8; |
| 872 | dev_priv->uncore.funcs.mmio_writew = chv_write16; |
| 873 | dev_priv->uncore.funcs.mmio_writel = chv_write32; |
| 874 | dev_priv->uncore.funcs.mmio_writeq = chv_write64; |
| 875 | dev_priv->uncore.funcs.mmio_readb = chv_read8; |
| 876 | dev_priv->uncore.funcs.mmio_readw = chv_read16; |
| 877 | dev_priv->uncore.funcs.mmio_readl = chv_read32; |
| 878 | dev_priv->uncore.funcs.mmio_readq = chv_read64; |
| 879 | |
| 880 | } else { |
| 881 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; |
| 882 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; |
| 883 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; |
| 884 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; |
| 885 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 886 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 887 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 888 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 889 | } |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 890 | break; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 891 | case 7: |
| 892 | case 6: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 893 | if (IS_HASWELL(dev)) { |
| 894 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; |
| 895 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; |
| 896 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; |
| 897 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; |
| 898 | } else { |
| 899 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; |
| 900 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; |
| 901 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; |
| 902 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; |
| 903 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 904 | |
| 905 | if (IS_VALLEYVIEW(dev)) { |
| 906 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; |
| 907 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; |
| 908 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; |
| 909 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; |
| 910 | } else { |
| 911 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 912 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 913 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 914 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 915 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 916 | break; |
| 917 | case 5: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 918 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
| 919 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; |
| 920 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; |
| 921 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 922 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
| 923 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; |
| 924 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; |
| 925 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; |
| 926 | break; |
| 927 | case 4: |
| 928 | case 3: |
| 929 | case 2: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 930 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
| 931 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; |
| 932 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; |
| 933 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 934 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
| 935 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; |
| 936 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; |
| 937 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; |
| 938 | break; |
| 939 | } |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 940 | } |
| 941 | |
| 942 | void intel_uncore_fini(struct drm_device *dev) |
| 943 | { |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 944 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 945 | intel_uncore_sanitize(dev); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 946 | intel_uncore_forcewake_reset(dev, false); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 947 | } |
| 948 | |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 949 | #define GEN_RANGE(l, h) GENMASK(h, l) |
| 950 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 951 | static const struct register_whitelist { |
| 952 | uint64_t offset; |
| 953 | uint32_t size; |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 954 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 955 | uint32_t gen_bitmask; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 956 | } whitelist[] = { |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 957 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) }, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 958 | }; |
| 959 | |
| 960 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 961 | void *data, struct drm_file *file) |
| 962 | { |
| 963 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 964 | struct drm_i915_reg_read *reg = data; |
| 965 | struct register_whitelist const *entry = whitelist; |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 966 | int i, ret = 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 967 | |
| 968 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 969 | if (entry->offset == reg->offset && |
| 970 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 971 | break; |
| 972 | } |
| 973 | |
| 974 | if (i == ARRAY_SIZE(whitelist)) |
| 975 | return -EINVAL; |
| 976 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 977 | intel_runtime_pm_get(dev_priv); |
| 978 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 979 | switch (entry->size) { |
| 980 | case 8: |
| 981 | reg->val = I915_READ64(reg->offset); |
| 982 | break; |
| 983 | case 4: |
| 984 | reg->val = I915_READ(reg->offset); |
| 985 | break; |
| 986 | case 2: |
| 987 | reg->val = I915_READ16(reg->offset); |
| 988 | break; |
| 989 | case 1: |
| 990 | reg->val = I915_READ8(reg->offset); |
| 991 | break; |
| 992 | default: |
| 993 | WARN_ON(1); |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 994 | ret = -EINVAL; |
| 995 | goto out; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 996 | } |
| 997 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 998 | out: |
| 999 | intel_runtime_pm_put(dev_priv); |
| 1000 | return ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1001 | } |
| 1002 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1003 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
| 1004 | void *data, struct drm_file *file) |
| 1005 | { |
| 1006 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1007 | struct drm_i915_reset_stats *args = data; |
| 1008 | struct i915_ctx_hang_stats *hs; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1009 | struct intel_context *ctx; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1010 | int ret; |
| 1011 | |
Mika Kuoppala | 661df04 | 2013-11-12 19:49:35 +0200 | [diff] [blame] | 1012 | if (args->flags || args->pad) |
| 1013 | return -EINVAL; |
| 1014 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1015 | if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN)) |
| 1016 | return -EPERM; |
| 1017 | |
| 1018 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1019 | if (ret) |
| 1020 | return ret; |
| 1021 | |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1022 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 1023 | if (IS_ERR(ctx)) { |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1024 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1025 | return PTR_ERR(ctx); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1026 | } |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1027 | hs = &ctx->hang_stats; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1028 | |
| 1029 | if (capable(CAP_SYS_ADMIN)) |
| 1030 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 1031 | else |
| 1032 | args->reset_count = 0; |
| 1033 | |
| 1034 | args->batch_active = hs->batch_active; |
| 1035 | args->batch_pending = hs->batch_pending; |
| 1036 | |
| 1037 | mutex_unlock(&dev->struct_mutex); |
| 1038 | |
| 1039 | return 0; |
| 1040 | } |
| 1041 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1042 | static int i965_reset_complete(struct drm_device *dev) |
| 1043 | { |
| 1044 | u8 gdrst; |
| 1045 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 1046 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 1047 | } |
| 1048 | |
| 1049 | static int i965_do_reset(struct drm_device *dev) |
| 1050 | { |
| 1051 | int ret; |
| 1052 | |
Daniel Vetter | 85ab399 | 2014-05-22 17:56:33 +0200 | [diff] [blame] | 1053 | /* FIXME: i965g/gm need a display save/restore for gpu reset. */ |
| 1054 | return -ENODEV; |
| 1055 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1056 | /* |
| 1057 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 1058 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 1059 | * triggers the reset; when done, the hardware will clear it. |
| 1060 | */ |
| 1061 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1062 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1063 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1064 | if (ret) |
| 1065 | return ret; |
| 1066 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1067 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1068 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1069 | |
| 1070 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1071 | if (ret) |
| 1072 | return ret; |
| 1073 | |
| 1074 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1079 | static int g4x_do_reset(struct drm_device *dev) |
| 1080 | { |
| 1081 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1082 | int ret; |
| 1083 | |
| 1084 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1085 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1086 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1087 | if (ret) |
| 1088 | return ret; |
| 1089 | |
| 1090 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1091 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1092 | POSTING_READ(VDECCLK_GATE_D); |
| 1093 | |
| 1094 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1095 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1096 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1097 | if (ret) |
| 1098 | return ret; |
| 1099 | |
| 1100 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1101 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1102 | POSTING_READ(VDECCLK_GATE_D); |
| 1103 | |
| 1104 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1105 | |
| 1106 | return 0; |
| 1107 | } |
| 1108 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1109 | static int ironlake_do_reset(struct drm_device *dev) |
| 1110 | { |
| 1111 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1112 | int ret; |
| 1113 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1114 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1115 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | f67deb7 | 2014-05-19 19:23:23 +0300 | [diff] [blame] | 1116 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
Ville Syrjälä | b3a3f03 | 2014-05-19 19:23:24 +0300 | [diff] [blame] | 1117 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1118 | if (ret) |
| 1119 | return ret; |
| 1120 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1121 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1122 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | 9aa7250 | 2014-05-19 19:23:26 +0300 | [diff] [blame] | 1123 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
| 1124 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
| 1125 | if (ret) |
| 1126 | return ret; |
| 1127 | |
| 1128 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); |
| 1129 | |
| 1130 | return 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1131 | } |
| 1132 | |
| 1133 | static int gen6_do_reset(struct drm_device *dev) |
| 1134 | { |
| 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1136 | int ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1137 | |
| 1138 | /* Reset the chip */ |
| 1139 | |
| 1140 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 1141 | * for fifo space for the write or forcewake the chip for |
| 1142 | * the read |
| 1143 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1144 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1145 | |
| 1146 | /* Spin waiting for the device to ack the reset request */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1147 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1148 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 1149 | intel_uncore_forcewake_reset(dev, true); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 1150 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1151 | return ret; |
| 1152 | } |
| 1153 | |
| 1154 | int intel_gpu_reset(struct drm_device *dev) |
| 1155 | { |
| 1156 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | 935e8de | 2013-11-07 21:40:47 -0800 | [diff] [blame] | 1157 | case 8: |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1158 | case 7: |
| 1159 | case 6: return gen6_do_reset(dev); |
| 1160 | case 5: return ironlake_do_reset(dev); |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1161 | case 4: |
| 1162 | if (IS_G4X(dev)) |
| 1163 | return g4x_do_reset(dev); |
| 1164 | else |
| 1165 | return i965_do_reset(dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1166 | default: return -ENODEV; |
| 1167 | } |
| 1168 | } |
| 1169 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1170 | void intel_uncore_check_errors(struct drm_device *dev) |
| 1171 | { |
| 1172 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1173 | |
| 1174 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1175 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1176 | DRM_ERROR("Unclaimed register before interrupt\n"); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1177 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1178 | } |
| 1179 | } |