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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +10004#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
Paul Mackerras14cf11a2005-09-26 16:04:21 +10006
Paul Mackerras14cf11a2005-09-26 16:04:21 +10007#include <linux/kernel.h>
8
9#include <asm/hw_irq.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100010#include <asm/atomic.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100011
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
28 * rmb(), though. Note that lwsync is interpreted as sync by
29 * 32-bit and older 64-bit CPUs.
30 *
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight eieio barrier on
34 * SMP since it is only used to order updates to system memory.
35 */
36#define mb() __asm__ __volatile__ ("sync" : : : "memory")
37#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
38#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39#define read_barrier_depends() do { } while(0)
40
41#define set_mb(var, value) do { var = value; mb(); } while (0)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100042
Arnd Bergmann88ced032005-12-16 22:43:46 +010043#ifdef __KERNEL__
Paul Mackerras14cf11a2005-09-26 16:04:21 +100044#ifdef CONFIG_SMP
45#define smp_mb() mb()
46#define smp_rmb() rmb()
47#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
48#define smp_read_barrier_depends() read_barrier_depends()
49#else
50#define smp_mb() barrier()
51#define smp_rmb() barrier()
52#define smp_wmb() barrier()
53#define smp_read_barrier_depends() do { } while(0)
54#endif /* CONFIG_SMP */
55
Nathan Lynch5db9fa92006-08-22 20:36:05 -050056/*
57 * This is a barrier which prevents following instructions from being
58 * started until the value of the argument x is known. For example, if
59 * x is a variable loaded from memory, this prevents following
60 * instructions from being executed until the load has been performed.
61 */
62#define data_barrier(x) \
63 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
64
Paul Mackerras14cf11a2005-09-26 16:04:21 +100065struct task_struct;
66struct pt_regs;
67
68#ifdef CONFIG_DEBUGGER
69
70extern int (*__debugger)(struct pt_regs *regs);
71extern int (*__debugger_ipi)(struct pt_regs *regs);
72extern int (*__debugger_bpt)(struct pt_regs *regs);
73extern int (*__debugger_sstep)(struct pt_regs *regs);
74extern int (*__debugger_iabr_match)(struct pt_regs *regs);
75extern int (*__debugger_dabr_match)(struct pt_regs *regs);
76extern int (*__debugger_fault_handler)(struct pt_regs *regs);
77
78#define DEBUGGER_BOILERPLATE(__NAME) \
79static inline int __NAME(struct pt_regs *regs) \
80{ \
81 if (unlikely(__ ## __NAME)) \
82 return __ ## __NAME(regs); \
83 return 0; \
84}
85
86DEBUGGER_BOILERPLATE(debugger)
87DEBUGGER_BOILERPLATE(debugger_ipi)
88DEBUGGER_BOILERPLATE(debugger_bpt)
89DEBUGGER_BOILERPLATE(debugger_sstep)
90DEBUGGER_BOILERPLATE(debugger_iabr_match)
91DEBUGGER_BOILERPLATE(debugger_dabr_match)
92DEBUGGER_BOILERPLATE(debugger_fault_handler)
93
94#ifdef CONFIG_XMON
95extern void xmon_init(int enable);
96#endif
97
98#else
99static inline int debugger(struct pt_regs *regs) { return 0; }
100static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
101static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
102static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
103static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
104static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
105static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
106#endif
107
108extern int set_dabr(unsigned long dabr);
109extern void print_backtrace(unsigned long *);
110extern void show_regs(struct pt_regs * regs);
111extern void flush_instruction_cache(void);
112extern void hard_reset_now(void);
113extern void poweroff_now(void);
114
115#ifdef CONFIG_6xx
116extern long _get_L2CR(void);
117extern long _get_L3CR(void);
118extern void _set_L2CR(unsigned long);
119extern void _set_L3CR(unsigned long);
120#else
121#define _get_L2CR() 0L
122#define _get_L3CR() 0L
123#define _set_L2CR(val) do { } while(0)
124#define _set_L3CR(val) do { } while(0)
125#endif
126
127extern void via_cuda_init(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000128extern void read_rtc_time(void);
129extern void pmac_find_display(void);
130extern void giveup_fpu(struct task_struct *);
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000131extern void disable_kernel_fp(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000132extern void enable_kernel_fp(void);
133extern void flush_fp_to_thread(struct task_struct *);
134extern void enable_kernel_altivec(void);
135extern void giveup_altivec(struct task_struct *);
136extern void load_up_altivec(struct task_struct *);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000137extern int emulate_altivec(struct pt_regs *);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000138extern void giveup_spe(struct task_struct *);
139extern void load_up_spe(struct task_struct *);
140extern int fix_alignment(struct pt_regs *);
David Gibson25c8a782005-10-27 16:27:25 +1000141extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
142extern void cvt_df(double *from, float *to, struct thread_struct *thread);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000143
Paul Mackerras5388fb12006-01-11 22:11:39 +1100144#ifndef CONFIG_SMP
145extern void discard_lazy_cpu_state(void);
146#else
147static inline void discard_lazy_cpu_state(void)
148{
149}
150#endif
151
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000152#ifdef CONFIG_ALTIVEC
153extern void flush_altivec_to_thread(struct task_struct *);
154#else
155static inline void flush_altivec_to_thread(struct task_struct *t)
156{
157}
158#endif
159
160#ifdef CONFIG_SPE
161extern void flush_spe_to_thread(struct task_struct *);
162#else
163static inline void flush_spe_to_thread(struct task_struct *t)
164{
165}
166#endif
167
168extern int call_rtas(const char *, int, int, unsigned long *, ...);
169extern void cacheable_memzero(void *p, unsigned int nb);
170extern void *cacheable_memcpy(void *, const void *, unsigned int);
171extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
172extern void bad_page_fault(struct pt_regs *, unsigned long, int);
173extern int die(const char *, struct pt_regs *, long);
174extern void _exception(int, struct pt_regs *, int, unsigned long);
175#ifdef CONFIG_BOOKE_WDT
176extern u32 booke_wdt_enabled;
177extern u32 booke_wdt_period;
178#endif /* CONFIG_BOOKE_WDT */
179
180/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
181extern unsigned char e2a(unsigned char);
Michael Ellerman584fc6d2006-03-21 20:46:08 +1100182extern unsigned char* strne2a(unsigned char *dest,
183 const unsigned char *src, size_t n);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000184
185struct device_node;
186extern void note_scsi_host(struct device_node *, void *);
187
188extern struct task_struct *__switch_to(struct task_struct *,
189 struct task_struct *);
190#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
191
192struct thread_struct;
193extern struct task_struct *_switch(struct thread_struct *prev,
194 struct thread_struct *next);
195
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -0800196/*
197 * On SMP systems, when the scheduler does migration-cost autodetection,
198 * it needs a way to flush as much of the CPU's caches as possible.
199 *
200 * TODO: fill this in!
201 */
202static inline void sched_cacheflush(void)
203{
204}
205
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000206extern unsigned int rtas_data;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000207extern int mem_init_done; /* set on boot once kmalloc can be called */
Paul Mackerrascf00a8d2005-10-31 13:07:02 +1100208extern unsigned long memory_limit;
Paul Mackerras49b09852005-11-10 15:53:40 +1100209extern unsigned long klimit;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000210
Paul Mackerras17a63922005-10-20 21:10:09 +1000211extern int powersave_nap; /* set if nap mode can be used in idle loop */
212
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000213/*
214 * Atomic exchange
215 *
216 * Changes the memory location '*ptr' to be val and returns
217 * the previous value stored there.
218 */
219static __inline__ unsigned long
220__xchg_u32(volatile void *p, unsigned long val)
221{
222 unsigned long prev;
223
224 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100225 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000226"1: lwarx %0,0,%2 \n"
227 PPC405_ERR77(0,%2)
228" stwcx. %3,0,%2 \n\
229 bne- 1b"
230 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700231 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
232 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000233 : "cc", "memory");
234
235 return prev;
236}
237
238#ifdef CONFIG_PPC64
239static __inline__ unsigned long
240__xchg_u64(volatile void *p, unsigned long val)
241{
242 unsigned long prev;
243
244 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100245 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000246"1: ldarx %0,0,%2 \n"
247 PPC405_ERR77(0,%2)
248" stdcx. %3,0,%2 \n\
249 bne- 1b"
250 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700251 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
252 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000253 : "cc", "memory");
254
255 return prev;
256}
257#endif
258
259/*
260 * This function doesn't exist, so you'll get a linker error
261 * if something tries to do an invalid xchg().
262 */
263extern void __xchg_called_with_bad_pointer(void);
264
265static __inline__ unsigned long
266__xchg(volatile void *ptr, unsigned long x, unsigned int size)
267{
268 switch (size) {
269 case 4:
270 return __xchg_u32(ptr, x);
271#ifdef CONFIG_PPC64
272 case 8:
273 return __xchg_u64(ptr, x);
274#endif
275 }
276 __xchg_called_with_bad_pointer();
277 return x;
278}
279
280#define xchg(ptr,x) \
281 ({ \
282 __typeof__(*(ptr)) _x_ = (x); \
283 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
284 })
285
286#define tas(ptr) (xchg((ptr),1))
287
288/*
289 * Compare and exchange - if *p == old, set it to new,
290 * and return the old value of *p.
291 */
292#define __HAVE_ARCH_CMPXCHG 1
293
294static __inline__ unsigned long
295__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
296{
297 unsigned int prev;
298
299 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100300 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000301"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
302 cmpw 0,%0,%3\n\
303 bne- 2f\n"
304 PPC405_ERR77(0,%2)
305" stwcx. %4,0,%2\n\
306 bne- 1b"
307 ISYNC_ON_SMP
308 "\n\
3092:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700310 : "=&r" (prev), "+m" (*p)
311 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000312 : "cc", "memory");
313
314 return prev;
315}
316
317#ifdef CONFIG_PPC64
318static __inline__ unsigned long
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100319__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000320{
321 unsigned long prev;
322
323 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100324 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000325"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
326 cmpd 0,%0,%3\n\
327 bne- 2f\n\
328 stdcx. %4,0,%2\n\
329 bne- 1b"
330 ISYNC_ON_SMP
331 "\n\
3322:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700333 : "=&r" (prev), "+m" (*p)
334 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000335 : "cc", "memory");
336
337 return prev;
338}
339#endif
340
341/* This function doesn't exist, so you'll get a linker error
342 if something tries to do an invalid cmpxchg(). */
343extern void __cmpxchg_called_with_bad_pointer(void);
344
345static __inline__ unsigned long
346__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
347 unsigned int size)
348{
349 switch (size) {
350 case 4:
351 return __cmpxchg_u32(ptr, old, new);
352#ifdef CONFIG_PPC64
353 case 8:
354 return __cmpxchg_u64(ptr, old, new);
355#endif
356 }
357 __cmpxchg_called_with_bad_pointer();
358 return old;
359}
360
361#define cmpxchg(ptr,o,n) \
362 ({ \
363 __typeof__(*(ptr)) _o_ = (o); \
364 __typeof__(*(ptr)) _n_ = (n); \
365 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
366 (unsigned long)_n_, sizeof(*(ptr))); \
367 })
368
369#ifdef CONFIG_PPC64
370/*
371 * We handle most unaligned accesses in hardware. On the other hand
372 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
373 * powers of 2 writes until it reaches sufficient alignment).
374 *
375 * Based on this we disable the IP header alignment in network drivers.
Anton Blanchard025be812006-03-31 02:27:06 -0800376 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
377 * cacheline alignment of buffers.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000378 */
Anton Blanchard025be812006-03-31 02:27:06 -0800379#define NET_IP_ALIGN 0
380#define NET_SKB_PAD L1_CACHE_BYTES
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000381#endif
382
383#define arch_align_stack(x) (x)
384
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000385/* Used in very early kernel initialization. */
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000386extern unsigned long reloc_offset(void);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000387extern unsigned long add_reloc_offset(unsigned long);
388extern void reloc_got2(unsigned long);
389
390#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000391
Michael Ellermanc87ef112005-11-03 17:57:53 +1100392static inline void create_instruction(unsigned long addr, unsigned int instr)
393{
394 unsigned int *p;
395 p = (unsigned int *)addr;
396 *p = instr;
397 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
398}
399
400/* Flags for create_branch:
401 * "b" == create_branch(addr, target, 0);
402 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
403 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
404 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
405 */
406#define BRANCH_SET_LINK 0x1
407#define BRANCH_ABSOLUTE 0x2
408
409static inline void create_branch(unsigned long addr,
410 unsigned long target, int flags)
411{
412 unsigned int instruction;
413
414 if (! (flags & BRANCH_ABSOLUTE))
415 target = target - addr;
416
417 /* Mask out the flags and target, so they don't step on each other. */
418 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
419
420 create_instruction(addr, instruction);
421}
422
423static inline void create_function_call(unsigned long addr, void * func)
424{
425 unsigned long func_addr;
426
427#ifdef CONFIG_PPC64
428 /*
429 * On PPC64 the function pointer actually points to the function's
430 * descriptor. The first entry in the descriptor is the address
431 * of the function text.
432 */
433 func_addr = *(unsigned long *)func;
434#else
435 func_addr = (unsigned long)func;
436#endif
437 create_branch(addr, func_addr, BRANCH_SET_LINK);
438}
439
Paul Mackerrasc6622f62006-02-24 10:06:59 +1100440#ifdef CONFIG_VIRT_CPU_ACCOUNTING
441extern void account_system_vtime(struct task_struct *);
442#endif
443
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000444#endif /* __KERNEL__ */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +1000445#endif /* _ASM_POWERPC_SYSTEM_H */