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Sascha Hauer6c7b068502012-03-07 21:01:28 +01001#ifndef __MACH_IMX_CLK_H
2#define __MACH_IMX_CLK_H
3
4#include <linux/spinlock.h>
5#include <linux/clk-provider.h>
Sascha Hauer3a84d172012-09-11 08:50:00 +02006
7extern spinlock_t imx_ccm_lock;
Sascha Hauer6c7b068502012-03-07 21:01:28 +01008
Alexander Shiyan229be9c2014-06-10 19:40:26 +04009void imx_check_clocks(struct clk *clks[], unsigned int count);
Lucas Stach55adc612015-09-21 18:53:57 +020010void imx_register_uart_clocks(struct clk ** const clks[]);
Alexander Shiyan229be9c2014-06-10 19:40:26 +040011
Liu Yingdfd87142013-07-04 17:57:17 +080012extern void imx_cscmr1_fixup(u32 *val);
13
Shawn Guo3bec5f82015-04-26 13:33:39 +080014enum imx_pllv1_type {
15 IMX_PLLV1_IMX1,
16 IMX_PLLV1_IMX21,
17 IMX_PLLV1_IMX25,
18 IMX_PLLV1_IMX27,
19 IMX_PLLV1_IMX31,
20 IMX_PLLV1_IMX35,
21};
22
23struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
24 const char *parent, void __iomem *base);
Sascha Hauer6c7b068502012-03-07 21:01:28 +010025
Sascha Hauera547b812012-03-19 12:36:10 +010026struct clk *imx_clk_pllv2(const char *name, const char *parent,
27 void __iomem *base);
28
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080029enum imx_pllv3_type {
30 IMX_PLLV3_GENERIC,
31 IMX_PLLV3_SYS,
32 IMX_PLLV3_USB,
Stefan Agner60ad8462014-12-02 17:59:42 +010033 IMX_PLLV3_USB_VF610,
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080034 IMX_PLLV3_AV,
35 IMX_PLLV3_ENET,
Frank Lif5394742015-05-19 02:45:02 +080036 IMX_PLLV3_ENET_IMX7,
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080037};
38
39struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
Sascha Hauer2b254692012-11-22 10:18:41 +010040 const char *parent_name, void __iomem *base, u32 div_mask);
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080041
Sascha Hauerb75c0152011-04-19 08:33:45 +020042struct clk *clk_register_gate2(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags,
Stefan Agner45682922016-03-09 18:16:47 -080044 void __iomem *reg, u8 bit_idx, u8 cgr_val,
Shawn Guof9f28cd2014-04-19 10:58:22 +080045 u8 clk_gate_flags, spinlock_t *lock,
46 unsigned int *share_count);
Sascha Hauerb75c0152011-04-19 08:33:45 +020047
Martin Fuzzey75f83d02013-04-23 20:16:59 +080048struct clk * imx_obtain_fixed_clock(
49 const char *name, unsigned long rate);
50
Shawn Guo19d86342014-08-26 15:06:33 +080051struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
52 void __iomem *reg, u8 shift, u32 exclusive_mask);
53
Shawn Guoa10bd672012-04-04 16:07:53 +080054struct clk *imx_clk_pfd(const char *name, const char *parent_name,
55 void __iomem *reg, u8 idx);
56
Shawn Guo32af7a82012-04-04 16:20:56 +080057struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
58 void __iomem *reg, u8 shift, u8 width,
59 void __iomem *busy_reg, u8 busy_shift);
60
61struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
62 u8 width, void __iomem *busy_reg, u8 busy_shift,
63 const char **parent_names, int num_parents);
64
Liu Yingcbe7fc82013-07-04 17:22:26 +080065struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
66 void __iomem *reg, u8 shift, u8 width,
67 void (*fixup)(u32 *val));
68
Liu Yinga49e6c42013-07-04 17:35:46 +080069struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
70 u8 shift, u8 width, const char **parents,
71 int num_parents, void (*fixup)(u32 *val));
72
Sascha Hauer6c7b068502012-03-07 21:01:28 +010073static inline struct clk *imx_clk_fixed(const char *name, int rate)
74{
Stephen Boyd38c70352016-03-01 10:59:49 -080075 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
Sascha Hauer6c7b068502012-03-07 21:01:28 +010076}
77
Dong Aisheng5afc9942016-06-30 17:31:15 +080078static inline struct clk *imx_clk_fixed_factor(const char *name,
79 const char *parent, unsigned int mult, unsigned int div)
80{
81 return clk_register_fixed_factor(NULL, name, parent,
82 CLK_SET_RATE_PARENT, mult, div);
83}
84
Sascha Hauer6c7b068502012-03-07 21:01:28 +010085static inline struct clk *imx_clk_divider(const char *name, const char *parent,
86 void __iomem *reg, u8 shift, u8 width)
87{
88 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
89 reg, shift, width, 0, &imx_ccm_lock);
90}
91
Philipp Zabel3ce92172013-03-27 18:30:40 +010092static inline struct clk *imx_clk_divider_flags(const char *name,
93 const char *parent, void __iomem *reg, u8 shift, u8 width,
94 unsigned long flags)
95{
96 return clk_register_divider(NULL, name, parent, flags,
97 reg, shift, width, 0, &imx_ccm_lock);
98}
99
Dong Aisheng39c29492016-06-30 17:31:16 +0800100static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
101 void __iomem *reg, u8 shift, u8 width)
102{
103 return clk_register_divider(NULL, name, parent,
104 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
105 reg, shift, width, 0, &imx_ccm_lock);
106}
107
Sascha Hauer6c7b068502012-03-07 21:01:28 +0100108static inline struct clk *imx_clk_gate(const char *name, const char *parent,
109 void __iomem *reg, u8 shift)
110{
111 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
112 shift, 0, &imx_ccm_lock);
113}
114
Alexander Shiyan65251692014-06-22 17:17:06 +0400115static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
116 void __iomem *reg, u8 shift)
117{
118 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
119 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
120}
121
Dong Aisheng5afc9942016-06-30 17:31:15 +0800122static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
123 void __iomem *reg, u8 shift)
124{
125 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
126 shift, 0x3, 0, &imx_ccm_lock, NULL);
127}
128
129static inline struct clk *imx_clk_gate2_shared(const char *name,
130 const char *parent, void __iomem *reg, u8 shift,
131 unsigned int *share_count)
132{
133 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
134 shift, 0x3, 0, &imx_ccm_lock, share_count);
135}
136
Fabio Estevamd5ebf5f2016-08-12 15:26:55 -0300137static inline struct clk *imx_clk_gate2_shared2(const char *name,
138 const char *parent, void __iomem *reg, u8 shift,
139 unsigned int *share_count)
140{
141 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
142 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
143 &imx_ccm_lock, share_count);
144}
145
Dong Aisheng5afc9942016-06-30 17:31:15 +0800146static inline struct clk *imx_clk_gate2_cgr(const char *name,
147 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
148{
149 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
150 shift, cgr_val, 0, &imx_ccm_lock, NULL);
151}
152
Dong Aisheng39c29492016-06-30 17:31:16 +0800153static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
154 void __iomem *reg, u8 shift)
155{
156 return clk_register_gate(NULL, name, parent,
157 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
158 reg, shift, 0, &imx_ccm_lock);
159}
160
161static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
162 void __iomem *reg, u8 shift)
163{
164 return clk_register_gate2(NULL, name, parent,
165 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
166 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
167}
168
Sascha Hauer6c7b068502012-03-07 21:01:28 +0100169static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
170 u8 shift, u8 width, const char **parents, int num_parents)
171{
James Hogan819c1de2013-07-29 12:25:01 +0100172 return clk_register_mux(NULL, name, parents, num_parents,
173 CLK_SET_RATE_NO_REPARENT, reg, shift,
Sascha Hauer6c7b068502012-03-07 21:01:28 +0100174 width, 0, &imx_ccm_lock);
175}
176
Dong Aisheng39c29492016-06-30 17:31:16 +0800177static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
178 u8 shift, u8 width, const char **parents, int num_parents)
179{
180 return clk_register_mux(NULL, name, parents, num_parents,
181 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
182 reg, shift, width, 0, &imx_ccm_lock);
183}
184
Philipp Zabel3ce92172013-03-27 18:30:40 +0100185static inline struct clk *imx_clk_mux_flags(const char *name,
186 void __iomem *reg, u8 shift, u8 width, const char **parents,
187 int num_parents, unsigned long flags)
188{
189 return clk_register_mux(NULL, name, parents, num_parents,
James Hogan819c1de2013-07-29 12:25:01 +0100190 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
Philipp Zabel3ce92172013-03-27 18:30:40 +0100191 &imx_ccm_lock);
192}
193
Lucas Stache0fed512014-09-26 15:41:01 +0200194struct clk *imx_clk_cpu(const char *name, const char *parent_name,
195 struct clk *div, struct clk *mux, struct clk *pll,
196 struct clk *step);
197
Sascha Hauer6c7b068502012-03-07 21:01:28 +0100198#endif