Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 28 | /* RS600 / Radeon X1250/X1270 integrated GPU |
| 29 | * |
| 30 | * This file gather function specific to RS600 which is the IGP of |
| 31 | * the X1250/X1270 family supporting intel CPU (while RS690/RS740 |
| 32 | * is the X1250/X1270 supporting AMD CPU). The display engine are |
| 33 | * the avivo one, bios is an atombios, 3D block are the one of the |
| 34 | * R4XX family. The GART is different from the RS400 one and is very |
| 35 | * close to the one of the R600 family (R600 likely being an evolution |
| 36 | * of the RS600 GART block). |
| 37 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 38 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 39 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 40 | #include "radeon_asic.h" |
Slava Grigorev | bfc1f97 | 2014-12-22 17:26:51 -0500 | [diff] [blame] | 41 | #include "radeon_audio.h" |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 42 | #include "atom.h" |
| 43 | #include "rs600d.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 44 | |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 45 | #include "rs600_reg_safe.h" |
| 46 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 47 | static void rs600_gpu_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 48 | int rs600_mc_wait_for_idle(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 49 | |
Alex Deucher | 75104fa | 2012-08-15 17:06:28 -0400 | [diff] [blame] | 50 | static const u32 crtc_offsets[2] = |
| 51 | { |
| 52 | 0, |
| 53 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
| 54 | }; |
| 55 | |
Alex Deucher | bea5497 | 2013-04-09 18:41:15 -0400 | [diff] [blame] | 56 | static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
| 57 | { |
| 58 | if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
| 59 | return true; |
| 60 | else |
| 61 | return false; |
| 62 | } |
| 63 | |
| 64 | static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
| 65 | { |
| 66 | u32 pos1, pos2; |
| 67 | |
| 68 | pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| 69 | pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| 70 | |
| 71 | if (pos1 != pos2) |
| 72 | return true; |
| 73 | else |
| 74 | return false; |
| 75 | } |
| 76 | |
| 77 | /** |
| 78 | * avivo_wait_for_vblank - vblank wait asic callback. |
| 79 | * |
| 80 | * @rdev: radeon_device pointer |
| 81 | * @crtc: crtc to wait for vblank on |
| 82 | * |
| 83 | * Wait for vblank on the requested crtc (r5xx-r7xx). |
| 84 | */ |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 85 | void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
| 86 | { |
Alex Deucher | bea5497 | 2013-04-09 18:41:15 -0400 | [diff] [blame] | 87 | unsigned i = 0; |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 88 | |
Alex Deucher | 75104fa | 2012-08-15 17:06:28 -0400 | [diff] [blame] | 89 | if (crtc >= rdev->num_crtc) |
| 90 | return; |
| 91 | |
Alex Deucher | bea5497 | 2013-04-09 18:41:15 -0400 | [diff] [blame] | 92 | if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
| 93 | return; |
| 94 | |
| 95 | /* depending on when we hit vblank, we may be close to active; if so, |
| 96 | * wait for another frame. |
| 97 | */ |
| 98 | while (avivo_is_in_vblank(rdev, crtc)) { |
| 99 | if (i++ % 100 == 0) { |
| 100 | if (!avivo_is_counter_moving(rdev, crtc)) |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 101 | break; |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 102 | } |
Alex Deucher | bea5497 | 2013-04-09 18:41:15 -0400 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | while (!avivo_is_in_vblank(rdev, crtc)) { |
| 106 | if (i++ % 100 == 0) { |
| 107 | if (!avivo_is_counter_moving(rdev, crtc)) |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 108 | break; |
Alex Deucher | 3ae19b7 | 2012-02-23 17:53:37 -0500 | [diff] [blame] | 109 | } |
| 110 | } |
| 111 | } |
| 112 | |
Michel Dänzer | c63dd75 | 2016-04-01 18:51:34 +0900 | [diff] [blame] | 113 | void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 114 | { |
| 115 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
| 116 | u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 117 | int i; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 118 | |
| 119 | /* Lock the graphics update lock */ |
| 120 | tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
| 121 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
| 122 | |
| 123 | /* update the scanout addresses */ |
Michel Dänzer | c63dd75 | 2016-04-01 18:51:34 +0900 | [diff] [blame] | 124 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, |
| 125 | async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 126 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 127 | (u32)crtc_base); |
| 128 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 129 | (u32)crtc_base); |
| 130 | |
| 131 | /* Wait for update_pending to go high. */ |
Alex Deucher | f649647 | 2011-11-28 14:49:26 -0500 | [diff] [blame] | 132 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 133 | if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) |
| 134 | break; |
| 135 | udelay(1); |
| 136 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 137 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
| 138 | |
| 139 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
| 140 | tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
| 141 | WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) |
| 145 | { |
| 146 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 147 | |
| 148 | /* Return current update_pending status: */ |
Christian König | 157fa14 | 2014-05-27 16:49:20 +0200 | [diff] [blame] | 149 | return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & |
| 150 | AVIVO_D1GRPH_SURFACE_UPDATE_PENDING); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 151 | } |
| 152 | |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 153 | void avivo_program_fmt(struct drm_encoder *encoder) |
| 154 | { |
| 155 | struct drm_device *dev = encoder->dev; |
| 156 | struct radeon_device *rdev = dev->dev_private; |
| 157 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 158 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
| 159 | int bpc = 0; |
| 160 | u32 tmp = 0; |
Alex Deucher | 6214bb7 | 2013-09-24 17:26:26 -0400 | [diff] [blame] | 161 | enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE; |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 162 | |
Alex Deucher | 6214bb7 | 2013-09-24 17:26:26 -0400 | [diff] [blame] | 163 | if (connector) { |
| 164 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 165 | bpc = radeon_get_monitor_bpc(connector); |
Alex Deucher | 6214bb7 | 2013-09-24 17:26:26 -0400 | [diff] [blame] | 166 | dither = radeon_connector->dither; |
| 167 | } |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 168 | |
| 169 | /* LVDS FMT is set up by atom */ |
| 170 | if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
| 171 | return; |
| 172 | |
| 173 | if (bpc == 0) |
| 174 | return; |
| 175 | |
| 176 | switch (bpc) { |
| 177 | case 6: |
Alex Deucher | 6214bb7 | 2013-09-24 17:26:26 -0400 | [diff] [blame] | 178 | if (dither == RADEON_FMT_DITHER_ENABLE) |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 179 | /* XXX sort out optimal dither settings */ |
| 180 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; |
| 181 | else |
| 182 | tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN; |
| 183 | break; |
| 184 | case 8: |
Alex Deucher | 6214bb7 | 2013-09-24 17:26:26 -0400 | [diff] [blame] | 185 | if (dither == RADEON_FMT_DITHER_ENABLE) |
Alex Deucher | 134b480 | 2013-09-23 12:22:11 -0400 | [diff] [blame] | 186 | /* XXX sort out optimal dither settings */ |
| 187 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN | |
| 188 | AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH); |
| 189 | else |
| 190 | tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN | |
| 191 | AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH); |
| 192 | break; |
| 193 | case 10: |
| 194 | default: |
| 195 | /* not needed */ |
| 196 | break; |
| 197 | } |
| 198 | |
| 199 | switch (radeon_encoder->encoder_id) { |
| 200 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 201 | WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp); |
| 202 | break; |
| 203 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 204 | WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp); |
| 205 | break; |
| 206 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 207 | WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp); |
| 208 | break; |
| 209 | case ENCODER_OBJECT_ID_INTERNAL_DDI: |
| 210 | WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp); |
| 211 | break; |
| 212 | default: |
| 213 | break; |
| 214 | } |
| 215 | } |
| 216 | |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 217 | void rs600_pm_misc(struct radeon_device *rdev) |
| 218 | { |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 219 | int requested_index = rdev->pm.requested_power_state_index; |
| 220 | struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; |
| 221 | struct radeon_voltage *voltage = &ps->clock_info[0].voltage; |
| 222 | u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; |
Alex Deucher | 536fcd5 | 2010-04-29 16:33:38 -0400 | [diff] [blame] | 223 | u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 224 | |
| 225 | if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { |
| 226 | if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { |
| 227 | tmp = RREG32(voltage->gpio.reg); |
| 228 | if (voltage->active_high) |
| 229 | tmp |= voltage->gpio.mask; |
| 230 | else |
| 231 | tmp &= ~(voltage->gpio.mask); |
| 232 | WREG32(voltage->gpio.reg, tmp); |
| 233 | if (voltage->delay) |
| 234 | udelay(voltage->delay); |
| 235 | } else { |
| 236 | tmp = RREG32(voltage->gpio.reg); |
| 237 | if (voltage->active_high) |
| 238 | tmp &= ~voltage->gpio.mask; |
| 239 | else |
| 240 | tmp |= voltage->gpio.mask; |
| 241 | WREG32(voltage->gpio.reg, tmp); |
| 242 | if (voltage->delay) |
| 243 | udelay(voltage->delay); |
| 244 | } |
Alex Deucher | 7ac9aa5 | 2010-05-27 19:25:54 -0400 | [diff] [blame] | 245 | } else if (voltage->type == VOLTAGE_VDDC) |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 246 | radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 247 | |
| 248 | dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); |
| 249 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); |
| 250 | dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); |
| 251 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { |
| 252 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { |
| 253 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); |
| 254 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); |
| 255 | } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { |
| 256 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); |
| 257 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); |
| 258 | } |
| 259 | } else { |
| 260 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); |
| 261 | dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); |
| 262 | } |
| 263 | WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); |
| 264 | |
| 265 | dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); |
| 266 | if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { |
| 267 | dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; |
| 268 | if (voltage->delay) { |
| 269 | dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; |
| 270 | dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); |
| 271 | } else |
| 272 | dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; |
| 273 | } else |
| 274 | dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; |
| 275 | WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); |
| 276 | |
| 277 | hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); |
| 278 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) |
| 279 | hdp_dyn_cntl &= ~HDP_FORCEON; |
| 280 | else |
| 281 | hdp_dyn_cntl |= HDP_FORCEON; |
| 282 | WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); |
Alex Deucher | 536fcd5 | 2010-04-29 16:33:38 -0400 | [diff] [blame] | 283 | #if 0 |
| 284 | /* mc_host_dyn seems to cause hangs from time to time */ |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 285 | mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); |
| 286 | if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) |
| 287 | mc_host_dyn_cntl &= ~MC_HOST_FORCEON; |
| 288 | else |
| 289 | mc_host_dyn_cntl |= MC_HOST_FORCEON; |
| 290 | WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); |
Alex Deucher | 536fcd5 | 2010-04-29 16:33:38 -0400 | [diff] [blame] | 291 | #endif |
| 292 | dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); |
| 293 | if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) |
| 294 | dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; |
| 295 | else |
| 296 | dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; |
| 297 | WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 298 | |
| 299 | /* set pcie lanes */ |
| 300 | if ((rdev->flags & RADEON_IS_PCIE) && |
| 301 | !(rdev->flags & RADEON_IS_IGP) && |
Alex Deucher | 798bcf7 | 2012-02-23 17:53:48 -0500 | [diff] [blame] | 302 | rdev->asic->pm.set_pcie_lanes && |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 303 | (ps->pcie_lanes != |
| 304 | rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { |
| 305 | radeon_set_pcie_lanes(rdev, |
| 306 | ps->pcie_lanes); |
Alex Deucher | ce8a3eb | 2010-05-07 16:58:27 -0400 | [diff] [blame] | 307 | DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 308 | } |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 309 | } |
| 310 | |
| 311 | void rs600_pm_prepare(struct radeon_device *rdev) |
| 312 | { |
| 313 | struct drm_device *ddev = rdev->ddev; |
| 314 | struct drm_crtc *crtc; |
| 315 | struct radeon_crtc *radeon_crtc; |
| 316 | u32 tmp; |
| 317 | |
| 318 | /* disable any active CRTCs */ |
| 319 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
| 320 | radeon_crtc = to_radeon_crtc(crtc); |
| 321 | if (radeon_crtc->enabled) { |
| 322 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
| 323 | tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
| 324 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 325 | } |
| 326 | } |
| 327 | } |
| 328 | |
| 329 | void rs600_pm_finish(struct radeon_device *rdev) |
| 330 | { |
| 331 | struct drm_device *ddev = rdev->ddev; |
| 332 | struct drm_crtc *crtc; |
| 333 | struct radeon_crtc *radeon_crtc; |
| 334 | u32 tmp; |
| 335 | |
| 336 | /* enable any active CRTCs */ |
| 337 | list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { |
| 338 | radeon_crtc = to_radeon_crtc(crtc); |
| 339 | if (radeon_crtc->enabled) { |
| 340 | tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); |
| 341 | tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
| 342 | WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 343 | } |
| 344 | } |
| 345 | } |
| 346 | |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 347 | /* hpd for digital panel detect/disconnect */ |
| 348 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) |
| 349 | { |
| 350 | u32 tmp; |
| 351 | bool connected = false; |
| 352 | |
| 353 | switch (hpd) { |
| 354 | case RADEON_HPD_1: |
| 355 | tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); |
| 356 | if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) |
| 357 | connected = true; |
| 358 | break; |
| 359 | case RADEON_HPD_2: |
| 360 | tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); |
| 361 | if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) |
| 362 | connected = true; |
| 363 | break; |
| 364 | default: |
| 365 | break; |
| 366 | } |
| 367 | return connected; |
| 368 | } |
| 369 | |
| 370 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
| 371 | enum radeon_hpd_id hpd) |
| 372 | { |
| 373 | u32 tmp; |
| 374 | bool connected = rs600_hpd_sense(rdev, hpd); |
| 375 | |
| 376 | switch (hpd) { |
| 377 | case RADEON_HPD_1: |
| 378 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 379 | if (connected) |
| 380 | tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
| 381 | else |
| 382 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); |
| 383 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 384 | break; |
| 385 | case RADEON_HPD_2: |
| 386 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 387 | if (connected) |
| 388 | tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
| 389 | else |
| 390 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); |
| 391 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 392 | break; |
| 393 | default: |
| 394 | break; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | void rs600_hpd_init(struct radeon_device *rdev) |
| 399 | { |
| 400 | struct drm_device *dev = rdev->ddev; |
| 401 | struct drm_connector *connector; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 402 | unsigned enable = 0; |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 403 | |
| 404 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 405 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 406 | switch (radeon_connector->hpd.hpd) { |
| 407 | case RADEON_HPD_1: |
| 408 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| 409 | S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 410 | break; |
| 411 | case RADEON_HPD_2: |
| 412 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| 413 | S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 414 | break; |
| 415 | default: |
| 416 | break; |
| 417 | } |
Nicolai Stange | b2c0cbd | 2016-03-22 22:05:27 +0100 | [diff] [blame] | 418 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
| 419 | enable |= 1 << radeon_connector->hpd.hpd; |
Alex Deucher | 64912e9 | 2011-11-03 11:21:39 -0400 | [diff] [blame] | 420 | radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 421 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 422 | radeon_irq_kms_enable_hpd(rdev, enable); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | void rs600_hpd_fini(struct radeon_device *rdev) |
| 426 | { |
| 427 | struct drm_device *dev = rdev->ddev; |
| 428 | struct drm_connector *connector; |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 429 | unsigned disable = 0; |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 430 | |
| 431 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 432 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 433 | switch (radeon_connector->hpd.hpd) { |
| 434 | case RADEON_HPD_1: |
| 435 | WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| 436 | S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 437 | break; |
| 438 | case RADEON_HPD_2: |
| 439 | WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| 440 | S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 441 | break; |
| 442 | default: |
| 443 | break; |
| 444 | } |
Nicolai Stange | b2c0cbd | 2016-03-22 22:05:27 +0100 | [diff] [blame] | 445 | if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) |
| 446 | disable |= 1 << radeon_connector->hpd.hpd; |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 447 | } |
Christian Koenig | fb98257 | 2012-05-17 01:33:30 +0200 | [diff] [blame] | 448 | radeon_irq_kms_disable_hpd(rdev, disable); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 449 | } |
| 450 | |
Jérome Glisse | 71fe289 | 2016-03-18 16:58:38 +0100 | [diff] [blame] | 451 | int rs600_asic_reset(struct radeon_device *rdev, bool hard) |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 452 | { |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 453 | struct rv515_mc_save save; |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 454 | u32 status, tmp; |
| 455 | int ret = 0; |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 456 | |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 457 | status = RREG32(R_000E40_RBBM_STATUS); |
| 458 | if (!G_000E40_GUI_ACTIVE(status)) { |
| 459 | return 0; |
| 460 | } |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 461 | /* Stops all mc clients */ |
| 462 | rv515_mc_stop(rdev, &save); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 463 | status = RREG32(R_000E40_RBBM_STATUS); |
| 464 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 465 | /* stop CP */ |
| 466 | WREG32(RADEON_CP_CSQ_CNTL, 0); |
| 467 | tmp = RREG32(RADEON_CP_RB_CNTL); |
| 468 | WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
| 469 | WREG32(RADEON_CP_RB_RPTR_WR, 0); |
| 470 | WREG32(RADEON_CP_RB_WPTR, 0); |
| 471 | WREG32(RADEON_CP_RB_CNTL, tmp); |
| 472 | pci_save_state(rdev->pdev); |
| 473 | /* disable bus mastering */ |
Michel Dänzer | 642ce52 | 2012-01-12 16:04:11 +0100 | [diff] [blame] | 474 | pci_clear_master(rdev->pdev); |
| 475 | mdelay(1); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 476 | /* reset GA+VAP */ |
| 477 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | |
| 478 | S_0000F0_SOFT_RESET_GA(1)); |
| 479 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 480 | mdelay(500); |
| 481 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 482 | mdelay(1); |
| 483 | status = RREG32(R_000E40_RBBM_STATUS); |
| 484 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 485 | /* reset CP */ |
| 486 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); |
| 487 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 488 | mdelay(500); |
| 489 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 490 | mdelay(1); |
| 491 | status = RREG32(R_000E40_RBBM_STATUS); |
| 492 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 493 | /* reset MC */ |
| 494 | WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); |
| 495 | RREG32(R_0000F0_RBBM_SOFT_RESET); |
| 496 | mdelay(500); |
| 497 | WREG32(R_0000F0_RBBM_SOFT_RESET, 0); |
| 498 | mdelay(1); |
| 499 | status = RREG32(R_000E40_RBBM_STATUS); |
| 500 | dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); |
| 501 | /* restore PCI & busmastering */ |
| 502 | pci_restore_state(rdev->pdev); |
| 503 | /* Check if GPU is idle */ |
| 504 | if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { |
| 505 | dev_err(rdev->dev, "failed to reset GPU\n"); |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 506 | ret = -1; |
| 507 | } else |
| 508 | dev_info(rdev->dev, "GPU reset succeed\n"); |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 509 | rv515_mc_resume(rdev, &save); |
Alex Deucher | 25b2ec5b | 2011-01-11 13:36:55 -0500 | [diff] [blame] | 510 | return ret; |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 511 | } |
| 512 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 513 | /* |
| 514 | * GART. |
| 515 | */ |
| 516 | void rs600_gart_tlb_flush(struct radeon_device *rdev) |
| 517 | { |
| 518 | uint32_t tmp; |
| 519 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 520 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 521 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| 522 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 523 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 524 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
Jerome Glisse | 30f69f3 | 2010-04-16 18:46:35 +0200 | [diff] [blame] | 525 | tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 526 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 527 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 528 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 529 | tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; |
| 530 | WREG32_MC(R_000100_MC_PT0_CNTL, tmp); |
| 531 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 532 | } |
| 533 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 534 | static int rs600_gart_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 535 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 536 | int r; |
| 537 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 538 | if (rdev->gart.robj) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 539 | WARN(1, "RS600 GART already initialized\n"); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 540 | return 0; |
| 541 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 542 | /* Initialize common gart structure */ |
| 543 | r = radeon_gart_init(rdev); |
| 544 | if (r) { |
| 545 | return r; |
| 546 | } |
| 547 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 548 | return radeon_gart_table_vram_alloc(rdev); |
| 549 | } |
| 550 | |
Alex Deucher | e22e6d2 | 2011-07-11 20:27:23 +0000 | [diff] [blame] | 551 | static int rs600_gart_enable(struct radeon_device *rdev) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 552 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 553 | u32 tmp; |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 554 | int r, i; |
| 555 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 556 | if (rdev->gart.robj == NULL) { |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 557 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
| 558 | return -EINVAL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 559 | } |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 560 | r = radeon_gart_table_vram_pin(rdev); |
| 561 | if (r) |
| 562 | return r; |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 563 | /* Enable bus master */ |
Alex Deucher | e22e6d2 | 2011-07-11 20:27:23 +0000 | [diff] [blame] | 564 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
| 565 | WREG32(RADEON_BUS_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 566 | /* FIXME: setup default page */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 567 | WREG32_MC(R_000100_MC_PT0_CNTL, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 568 | (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
| 569 | S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); |
| 570 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 571 | for (i = 0; i < 19; i++) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 572 | WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 573 | S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | |
| 574 | S_00016C_SYSTEM_ACCESS_MODE_MASK( |
| 575 | V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | |
| 576 | S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( |
| 577 | V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | |
| 578 | S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | |
| 579 | S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | |
| 580 | S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 581 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 582 | /* enable first context */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 583 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 584 | S_000102_ENABLE_PAGE_TABLE(1) | |
| 585 | S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); |
| 586 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 587 | /* disable all other contexts */ |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 588 | for (i = 1; i < 8; i++) |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 589 | WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 590 | |
| 591 | /* setup the page table */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 592 | WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 593 | rdev->gart.table_addr); |
| 594 | WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); |
| 595 | WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 596 | WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 597 | |
Alex Deucher | 4f15d24 | 2009-12-05 17:55:37 -0500 | [diff] [blame] | 598 | /* System context maps to VRAM space */ |
| 599 | WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); |
| 600 | WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); |
| 601 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 602 | /* enable page tables */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 603 | tmp = RREG32_MC(R_000100_MC_PT0_CNTL); |
| 604 | WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); |
| 605 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
| 606 | WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 607 | rs600_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 608 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 609 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 610 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 611 | rdev->gart.ready = true; |
| 612 | return 0; |
| 613 | } |
| 614 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 615 | static void rs600_gart_disable(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 616 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 617 | u32 tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 618 | |
| 619 | /* FIXME: disable out of gart access */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 620 | WREG32_MC(R_000100_MC_PT0_CNTL, 0); |
| 621 | tmp = RREG32_MC(R_000009_MC_CNTL1); |
| 622 | WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 623 | radeon_gart_table_vram_unpin(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 624 | } |
| 625 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 626 | static void rs600_gart_fini(struct radeon_device *rdev) |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 627 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 628 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 629 | rs600_gart_disable(rdev); |
| 630 | radeon_gart_table_vram_free(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 631 | } |
| 632 | |
Michel Dänzer | cb65890 | 2015-01-21 17:36:35 +0900 | [diff] [blame] | 633 | uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 634 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 635 | addr = addr & 0xFFFFFFFFFFFFF000ULL; |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 636 | addr |= R600_PTE_SYSTEM; |
| 637 | if (flags & RADEON_GART_PAGE_VALID) |
| 638 | addr |= R600_PTE_VALID; |
| 639 | if (flags & RADEON_GART_PAGE_READ) |
| 640 | addr |= R600_PTE_READABLE; |
| 641 | if (flags & RADEON_GART_PAGE_WRITE) |
| 642 | addr |= R600_PTE_WRITEABLE; |
| 643 | if (flags & RADEON_GART_PAGE_SNOOP) |
| 644 | addr |= R600_PTE_SNOOPED; |
Michel Dänzer | cb65890 | 2015-01-21 17:36:35 +0900 | [diff] [blame] | 645 | return addr; |
| 646 | } |
| 647 | |
| 648 | void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 649 | uint64_t entry) |
| 650 | { |
| 651 | void __iomem *ptr = (void *)rdev->gart.ptr; |
| 652 | writeq(entry, ptr + (i * 8)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 653 | } |
| 654 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 655 | int rs600_irq_set(struct radeon_device *rdev) |
| 656 | { |
| 657 | uint32_t tmp = 0; |
| 658 | uint32_t mode_int = 0; |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 659 | u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & |
| 660 | ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
| 661 | u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & |
| 662 | ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 663 | u32 hdmi0; |
| 664 | if (ASIC_IS_DCE2(rdev)) |
| 665 | hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
| 666 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
| 667 | else |
| 668 | hdmi0 = 0; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 669 | |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 670 | if (!rdev->irq.installed) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 671 | WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
Jerome Glisse | 003e69f | 2010-01-07 15:39:14 +0100 | [diff] [blame] | 672 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 673 | return -EINVAL; |
| 674 | } |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 675 | if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 676 | tmp |= S_000040_SW_INT_EN(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 677 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 678 | if (rdev->irq.crtc_vblank_int[0] || |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 679 | atomic_read(&rdev->irq.pflip[0])) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 680 | mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 681 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 682 | if (rdev->irq.crtc_vblank_int[1] || |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 683 | atomic_read(&rdev->irq.pflip[1])) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 684 | mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 685 | } |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 686 | if (rdev->irq.hpd[0]) { |
| 687 | hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); |
| 688 | } |
| 689 | if (rdev->irq.hpd[1]) { |
| 690 | hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); |
| 691 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 692 | if (rdev->irq.afmt[0]) { |
| 693 | hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
| 694 | } |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 695 | WREG32(R_000040_GEN_INT_CNTL, tmp); |
| 696 | WREG32(R_006540_DxMODE_INT_MASK, mode_int); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 697 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); |
| 698 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 699 | if (ASIC_IS_DCE2(rdev)) |
| 700 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
Alex Deucher | 54acf10 | 2015-03-02 20:39:56 -0500 | [diff] [blame] | 701 | |
| 702 | /* posting read */ |
| 703 | RREG32(R_000040_GEN_INT_CNTL); |
| 704 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 705 | return 0; |
| 706 | } |
| 707 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 708 | static inline u32 rs600_irq_ack(struct radeon_device *rdev) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 709 | { |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 710 | uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 711 | uint32_t irq_mask = S_000044_SW_INT(1); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 712 | u32 tmp; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 713 | |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 714 | if (G_000044_DISPLAY_INT_STAT(irqs)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 715 | rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); |
| 716 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 717 | WREG32(R_006534_D1MODE_VBLANK_STATUS, |
| 718 | S_006534_D1MODE_VBLANK_ACK(1)); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 719 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 720 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 721 | WREG32(R_006D34_D2MODE_VBLANK_STATUS, |
| 722 | S_006D34_D2MODE_VBLANK_ACK(1)); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 723 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 724 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 725 | tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); |
| 726 | tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); |
| 727 | WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); |
| 728 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 729 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 730 | tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); |
| 731 | tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); |
| 732 | WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); |
| 733 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 734 | } else { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 735 | rdev->irq.stat_regs.r500.disp_int = 0; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 736 | } |
| 737 | |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 738 | if (ASIC_IS_DCE2(rdev)) { |
| 739 | rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & |
| 740 | S_007404_HDMI0_AZ_FORMAT_WTRIG(1); |
| 741 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
| 742 | tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); |
| 743 | tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); |
| 744 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); |
| 745 | } |
| 746 | } else |
| 747 | rdev->irq.stat_regs.r500.hdmi0_status = 0; |
| 748 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 749 | if (irqs) { |
Jerome Glisse | 01ceae8 | 2009-10-07 11:08:22 +0200 | [diff] [blame] | 750 | WREG32(R_000044_GEN_INT_STATUS, irqs); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 751 | } |
| 752 | return irqs & irq_mask; |
| 753 | } |
| 754 | |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 755 | void rs600_irq_disable(struct radeon_device *rdev) |
| 756 | { |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 757 | u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & |
| 758 | ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); |
| 759 | WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 760 | WREG32(R_000040_GEN_INT_CNTL, 0); |
| 761 | WREG32(R_006540_DxMODE_INT_MASK, 0); |
| 762 | /* Wait and acknowledge irq */ |
| 763 | mdelay(1); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 764 | rs600_irq_ack(rdev); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 765 | } |
| 766 | |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 767 | int rs600_irq_process(struct radeon_device *rdev) |
| 768 | { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 769 | u32 status, msi_rearm; |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 770 | bool queue_hotplug = false; |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 771 | bool queue_hdmi = false; |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 772 | |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 773 | status = rs600_irq_ack(rdev); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 774 | if (!status && |
| 775 | !rdev->irq.stat_regs.r500.disp_int && |
| 776 | !rdev->irq.stat_regs.r500.hdmi0_status) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 777 | return IRQ_NONE; |
| 778 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 779 | while (status || |
| 780 | rdev->irq.stat_regs.r500.disp_int || |
| 781 | rdev->irq.stat_regs.r500.hdmi0_status) { |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 782 | /* SW interrupt */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 783 | if (G_000044_SW_INT(status)) { |
Alex Deucher | 7465280 | 2011-08-25 13:39:48 -0400 | [diff] [blame] | 784 | radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 785 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 786 | /* Vertical blank interrupts */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 787 | if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 788 | if (rdev->irq.crtc_vblank_int[0]) { |
| 789 | drm_handle_vblank(rdev->ddev, 0); |
| 790 | rdev->pm.vblank_sync = true; |
| 791 | wake_up(&rdev->irq.vblank_queue); |
| 792 | } |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 793 | if (atomic_read(&rdev->irq.pflip[0])) |
Christian König | 1a0e791 | 2014-05-27 16:49:21 +0200 | [diff] [blame] | 794 | radeon_crtc_handle_vblank(rdev, 0); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 795 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 796 | if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 797 | if (rdev->irq.crtc_vblank_int[1]) { |
| 798 | drm_handle_vblank(rdev->ddev, 1); |
| 799 | rdev->pm.vblank_sync = true; |
| 800 | wake_up(&rdev->irq.vblank_queue); |
| 801 | } |
Christian Koenig | 736fc37 | 2012-05-17 19:52:00 +0200 | [diff] [blame] | 802 | if (atomic_read(&rdev->irq.pflip[1])) |
Christian König | 1a0e791 | 2014-05-27 16:49:21 +0200 | [diff] [blame] | 803 | radeon_crtc_handle_vblank(rdev, 1); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 804 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 805 | if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 806 | queue_hotplug = true; |
| 807 | DRM_DEBUG("HPD1\n"); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 808 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 809 | if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 810 | queue_hotplug = true; |
| 811 | DRM_DEBUG("HPD2\n"); |
Alex Deucher | dcfdd40 | 2009-12-04 15:04:19 -0500 | [diff] [blame] | 812 | } |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 813 | if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { |
| 814 | queue_hdmi = true; |
| 815 | DRM_DEBUG("HDMI0\n"); |
| 816 | } |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 817 | status = rs600_irq_ack(rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 818 | } |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 819 | if (queue_hotplug) |
Lyude | cb5d416 | 2015-12-03 18:26:07 -0500 | [diff] [blame] | 820 | schedule_delayed_work(&rdev->hotplug_work, 0); |
Alex Deucher | f122c61 | 2012-03-30 08:59:57 -0400 | [diff] [blame] | 821 | if (queue_hdmi) |
| 822 | schedule_work(&rdev->audio_work); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 823 | if (rdev->msi_enabled) { |
| 824 | switch (rdev->family) { |
| 825 | case CHIP_RS600: |
| 826 | case CHIP_RS690: |
| 827 | case CHIP_RS740: |
| 828 | msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
| 829 | WREG32(RADEON_BUS_CNTL, msi_rearm); |
| 830 | WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
| 831 | break; |
| 832 | default: |
Alex Deucher | b7f5b7d | 2012-02-13 16:36:34 -0500 | [diff] [blame] | 833 | WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 834 | break; |
| 835 | } |
| 836 | } |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 837 | return IRQ_HANDLED; |
| 838 | } |
| 839 | |
| 840 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| 841 | { |
| 842 | if (crtc == 0) |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 843 | return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 844 | else |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 845 | return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 846 | } |
| 847 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 848 | int rs600_mc_wait_for_idle(struct radeon_device *rdev) |
| 849 | { |
| 850 | unsigned i; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 851 | |
| 852 | for (i = 0; i < rdev->usec_timeout; i++) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 853 | if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 854 | return 0; |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 855 | udelay(1); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 856 | } |
| 857 | return -1; |
| 858 | } |
| 859 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 860 | static void rs600_gpu_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 861 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 862 | r420_pipes_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 863 | /* Wait for mc idle */ |
| 864 | if (rs600_mc_wait_for_idle(rdev)) |
| 865 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 866 | } |
| 867 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 868 | static void rs600_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 869 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 870 | u64 base; |
| 871 | |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 872 | rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); |
| 873 | rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 874 | rdev->mc.vram_is_ddr = true; |
| 875 | rdev->mc.vram_width = 128; |
Alex Deucher | 722f294 | 2009-12-03 16:18:19 -0500 | [diff] [blame] | 876 | rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
| 877 | rdev->mc.mc_vram_size = rdev->mc.real_vram_size; |
Jerome Glisse | 51e5fcd | 2010-02-19 14:33:54 +0000 | [diff] [blame] | 878 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 879 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
| 880 | base = RREG32_MC(R_000004_MC_FB_LOCATION); |
| 881 | base = G_000004_MC_FB_START(base) << 16; |
| 882 | radeon_vram_location(rdev, &rdev->mc, base); |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 883 | rdev->mc.gtt_base_align = 0; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 884 | radeon_gtt_location(rdev, &rdev->mc); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 885 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 886 | } |
| 887 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 888 | void rs600_bandwidth_update(struct radeon_device *rdev) |
| 889 | { |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 890 | struct drm_display_mode *mode0 = NULL; |
| 891 | struct drm_display_mode *mode1 = NULL; |
| 892 | u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; |
| 893 | /* FIXME: implement full support */ |
| 894 | |
Alex Deucher | 8efe82c | 2014-11-03 09:57:46 -0500 | [diff] [blame] | 895 | if (!rdev->mode_info.mode_config_initialized) |
| 896 | return; |
| 897 | |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 898 | radeon_update_display_priority(rdev); |
| 899 | |
| 900 | if (rdev->mode_info.crtcs[0]->base.enabled) |
| 901 | mode0 = &rdev->mode_info.crtcs[0]->base.mode; |
| 902 | if (rdev->mode_info.crtcs[1]->base.enabled) |
| 903 | mode1 = &rdev->mode_info.crtcs[1]->base.mode; |
| 904 | |
| 905 | rs690_line_buffer_adjust(rdev, mode0, mode1); |
| 906 | |
| 907 | if (rdev->disp_priority == 2) { |
| 908 | d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); |
| 909 | d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); |
| 910 | d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); |
| 911 | d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); |
| 912 | WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); |
| 913 | WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); |
| 914 | WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); |
| 915 | WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); |
| 916 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 917 | } |
| 918 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 919 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| 920 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 921 | unsigned long flags; |
| 922 | u32 r; |
| 923 | |
| 924 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 925 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| 926 | S_000070_MC_IND_CITF_ARB0(1)); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 927 | r = RREG32(R_000074_MC_IND_DATA); |
| 928 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
| 929 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 933 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 934 | unsigned long flags; |
| 935 | |
| 936 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 937 | WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | |
| 938 | S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); |
| 939 | WREG32(R_000074_MC_IND_DATA, v); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 940 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 941 | } |
| 942 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 943 | static void rs600_debugfs(struct radeon_device *rdev) |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 944 | { |
| 945 | if (r100_debugfs_rbbm_init(rdev)) |
| 946 | DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 947 | } |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 948 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 949 | void rs600_set_safe_registers(struct radeon_device *rdev) |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 950 | { |
| 951 | rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; |
| 952 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 953 | } |
| 954 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 955 | static void rs600_mc_program(struct radeon_device *rdev) |
| 956 | { |
| 957 | struct rv515_mc_save save; |
| 958 | |
| 959 | /* Stops all mc clients */ |
| 960 | rv515_mc_stop(rdev, &save); |
| 961 | |
| 962 | /* Wait for mc idle */ |
| 963 | if (rs600_mc_wait_for_idle(rdev)) |
| 964 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
| 965 | |
| 966 | /* FIXME: What does AGP means for such chipset ? */ |
| 967 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); |
| 968 | WREG32_MC(R_000006_AGP_BASE, 0); |
| 969 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
| 970 | /* Program MC */ |
| 971 | WREG32_MC(R_000004_MC_FB_LOCATION, |
| 972 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 973 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 974 | WREG32(R_000134_HDP_FB_LOCATION, |
| 975 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
| 976 | |
| 977 | rv515_mc_resume(rdev, &save); |
| 978 | } |
| 979 | |
| 980 | static int rs600_startup(struct radeon_device *rdev) |
| 981 | { |
| 982 | int r; |
| 983 | |
| 984 | rs600_mc_program(rdev); |
| 985 | /* Resume clock */ |
| 986 | rv515_clock_startup(rdev); |
| 987 | /* Initialize GPU configuration (# pipes, ...) */ |
| 988 | rs600_gpu_init(rdev); |
| 989 | /* Initialize GART (initialize after TTM so we can allocate |
| 990 | * memory through TTM but finalize after TTM) */ |
| 991 | r = rs600_gart_enable(rdev); |
| 992 | if (r) |
| 993 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 994 | |
| 995 | /* allocate wb buffer */ |
| 996 | r = radeon_wb_init(rdev); |
| 997 | if (r) |
| 998 | return r; |
| 999 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 1000 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 1001 | if (r) { |
| 1002 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 1003 | return r; |
| 1004 | } |
| 1005 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1006 | /* Enable IRQ */ |
Adis Hamzić | e49f395 | 2013-06-02 16:47:54 +0200 | [diff] [blame] | 1007 | if (!rdev->irq.installed) { |
| 1008 | r = radeon_irq_kms_init(rdev); |
| 1009 | if (r) |
| 1010 | return r; |
| 1011 | } |
| 1012 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1013 | rs600_irq_set(rdev); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 1014 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1015 | /* 1M ring buffer */ |
| 1016 | r = r100_cp_init(rdev, 1024 * 1024); |
| 1017 | if (r) { |
Paul Bolle | ec4f2ac | 2011-01-28 23:32:04 +0100 | [diff] [blame] | 1018 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1019 | return r; |
| 1020 | } |
Rafał Miłecki | fe50ac7 | 2010-06-19 12:24:57 +0200 | [diff] [blame] | 1021 | |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1022 | r = radeon_ib_pool_init(rdev); |
| 1023 | if (r) { |
| 1024 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1025 | return r; |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1026 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1027 | |
Slava Grigorev | bfc1f97 | 2014-12-22 17:26:51 -0500 | [diff] [blame] | 1028 | r = radeon_audio_init(rdev); |
Alex Deucher | d4e30ef | 2012-06-04 17:18:51 -0400 | [diff] [blame] | 1029 | if (r) { |
| 1030 | dev_err(rdev->dev, "failed initializing audio\n"); |
| 1031 | return r; |
| 1032 | } |
| 1033 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1034 | return 0; |
| 1035 | } |
| 1036 | |
| 1037 | int rs600_resume(struct radeon_device *rdev) |
| 1038 | { |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 1039 | int r; |
| 1040 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1041 | /* Make sur GART are not working */ |
| 1042 | rs600_gart_disable(rdev); |
| 1043 | /* Resume clock before doing reset */ |
| 1044 | rv515_clock_startup(rdev); |
| 1045 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1046 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1047 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 1048 | RREG32(R_000E40_RBBM_STATUS), |
| 1049 | RREG32(R_0007C0_CP_STAT)); |
| 1050 | } |
| 1051 | /* post */ |
| 1052 | atom_asic_init(rdev->mode_info.atom_context); |
| 1053 | /* Resume clock after posting */ |
| 1054 | rv515_clock_startup(rdev); |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 1055 | /* Initialize surface registers */ |
| 1056 | radeon_surface_init(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1057 | |
| 1058 | rdev->accel_working = true; |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 1059 | r = rs600_startup(rdev); |
| 1060 | if (r) { |
| 1061 | rdev->accel_working = false; |
| 1062 | } |
| 1063 | return r; |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1064 | } |
| 1065 | |
| 1066 | int rs600_suspend(struct radeon_device *rdev) |
| 1067 | { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1068 | radeon_pm_suspend(rdev); |
Slava Grigorev | 7991d66 | 2014-12-03 17:07:01 -0500 | [diff] [blame] | 1069 | radeon_audio_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1070 | r100_cp_disable(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1071 | radeon_wb_disable(rdev); |
Jerome Glisse | ac447df | 2009-09-30 22:18:43 +0200 | [diff] [blame] | 1072 | rs600_irq_disable(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1073 | rs600_gart_disable(rdev); |
| 1074 | return 0; |
| 1075 | } |
| 1076 | |
| 1077 | void rs600_fini(struct radeon_device *rdev) |
| 1078 | { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1079 | radeon_pm_fini(rdev); |
Slava Grigorev | 7991d66 | 2014-12-03 17:07:01 -0500 | [diff] [blame] | 1080 | radeon_audio_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1081 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1082 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1083 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1084 | radeon_gem_fini(rdev); |
| 1085 | rs600_gart_fini(rdev); |
| 1086 | radeon_irq_kms_fini(rdev); |
| 1087 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1088 | radeon_bo_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1089 | radeon_atombios_fini(rdev); |
| 1090 | kfree(rdev->bios); |
| 1091 | rdev->bios = NULL; |
| 1092 | } |
| 1093 | |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 1094 | int rs600_init(struct radeon_device *rdev) |
| 1095 | { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1096 | int r; |
| 1097 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1098 | /* Disable VGA */ |
| 1099 | rv515_vga_render_disable(rdev); |
| 1100 | /* Initialize scratch registers */ |
| 1101 | radeon_scratch_init(rdev); |
| 1102 | /* Initialize surface registers */ |
| 1103 | radeon_surface_init(rdev); |
Dave Airlie | 4c712e6 | 2010-07-15 12:13:50 +1000 | [diff] [blame] | 1104 | /* restore some register to sane defaults */ |
| 1105 | r100_restore_sanity(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1106 | /* BIOS */ |
| 1107 | if (!radeon_get_bios(rdev)) { |
| 1108 | if (ASIC_IS_AVIVO(rdev)) |
| 1109 | return -EINVAL; |
| 1110 | } |
| 1111 | if (rdev->is_atom_bios) { |
| 1112 | r = radeon_atombios_init(rdev); |
| 1113 | if (r) |
| 1114 | return r; |
| 1115 | } else { |
| 1116 | dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); |
| 1117 | return -EINVAL; |
| 1118 | } |
| 1119 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1120 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1121 | dev_warn(rdev->dev, |
| 1122 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 1123 | RREG32(R_000E40_RBBM_STATUS), |
| 1124 | RREG32(R_0007C0_CP_STAT)); |
| 1125 | } |
| 1126 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1127 | if (radeon_boot_test_post_card(rdev) == false) |
| 1128 | return -EINVAL; |
| 1129 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1130 | /* Initialize clocks */ |
| 1131 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1132 | /* initialize memory controller */ |
| 1133 | rs600_mc_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1134 | rs600_debugfs(rdev); |
| 1135 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 1136 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1137 | if (r) |
| 1138 | return r; |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1139 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1140 | r = radeon_bo_init(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1141 | if (r) |
| 1142 | return r; |
| 1143 | r = rs600_gart_init(rdev); |
| 1144 | if (r) |
| 1145 | return r; |
| 1146 | rs600_set_safe_registers(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 1147 | |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 1148 | /* Initialize power management */ |
| 1149 | radeon_pm_init(rdev); |
| 1150 | |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1151 | rdev->accel_working = true; |
| 1152 | r = rs600_startup(rdev); |
| 1153 | if (r) { |
| 1154 | /* Somethings want wront with the accel init stop accel */ |
| 1155 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1156 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1157 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 1158 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 1159 | rs600_gart_fini(rdev); |
| 1160 | radeon_irq_kms_fini(rdev); |
| 1161 | rdev->accel_working = false; |
| 1162 | } |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 1163 | return 0; |
| 1164 | } |