Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1 | /* |
| 2 | * rt5677.c -- RT5677 ALSA SoC audio codec driver |
| 3 | * |
| 4 | * Copyright 2013 Realtek Semiconductor Corp. |
| 5 | * Author: Oder Chiou <oder_chiou@realtek.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 12 | #include <linux/acpi.h> |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 13 | #include <linux/fs.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/moduleparam.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/pm.h> |
| 19 | #include <linux/regmap.h> |
| 20 | #include <linux/i2c.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/spi/spi.h> |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 23 | #include <linux/firmware.h> |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 24 | #include <linux/property.h> |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 25 | #include <sound/core.h> |
| 26 | #include <sound/pcm.h> |
| 27 | #include <sound/pcm_params.h> |
| 28 | #include <sound/soc.h> |
| 29 | #include <sound/soc-dapm.h> |
| 30 | #include <sound/initval.h> |
| 31 | #include <sound/tlv.h> |
| 32 | |
Axel Lin | 30f14b4 | 2014-06-10 08:57:36 +0800 | [diff] [blame] | 33 | #include "rl6231.h" |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 34 | #include "rt5677.h" |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 35 | #include "rt5677-spi.h" |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 36 | |
| 37 | #define RT5677_DEVICE_ID 0x6327 |
| 38 | |
| 39 | #define RT5677_PR_RANGE_BASE (0xff + 1) |
| 40 | #define RT5677_PR_SPACING 0x100 |
| 41 | |
| 42 | #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING)) |
| 43 | |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 44 | /* GPIO indexes defined by ACPI */ |
| 45 | enum { |
| 46 | RT5677_GPIO_PLUG_DET = 0, |
| 47 | RT5677_GPIO_MIC_PRESENT_L = 1, |
| 48 | RT5677_GPIO_HOTWORD_DET_L = 2, |
| 49 | RT5677_GPIO_DSP_INT = 3, |
| 50 | RT5677_GPIO_HP_AMP_SHDN_L = 4, |
| 51 | }; |
| 52 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 53 | static const struct regmap_range_cfg rt5677_ranges[] = { |
| 54 | { |
| 55 | .name = "PR", |
| 56 | .range_min = RT5677_PR_BASE, |
| 57 | .range_max = RT5677_PR_BASE + 0xfd, |
| 58 | .selector_reg = RT5677_PRIV_INDEX, |
| 59 | .selector_mask = 0xff, |
| 60 | .selector_shift = 0x0, |
| 61 | .window_start = RT5677_PRIV_DATA, |
| 62 | .window_len = 0x1, |
| 63 | }, |
| 64 | }; |
| 65 | |
Nariman Poushin | 8019ff6 | 2015-07-16 16:36:21 +0100 | [diff] [blame] | 66 | static const struct reg_sequence init_list[] = { |
Oder Chiou | 2dfe2b0 | 2014-11-19 13:52:18 +0800 | [diff] [blame] | 67 | {RT5677_ASRC_12, 0x0018}, |
| 68 | {RT5677_PR_BASE + 0x3d, 0x364d}, |
| 69 | {RT5677_PR_BASE + 0x17, 0x4fc0}, |
| 70 | {RT5677_PR_BASE + 0x13, 0x0312}, |
| 71 | {RT5677_PR_BASE + 0x1e, 0x0000}, |
| 72 | {RT5677_PR_BASE + 0x12, 0x0eaa}, |
| 73 | {RT5677_PR_BASE + 0x14, 0x018a}, |
Bard Liao | 74d6ea5 | 2015-04-24 15:19:29 +0800 | [diff] [blame] | 74 | {RT5677_PR_BASE + 0x15, 0x0490}, |
| 75 | {RT5677_PR_BASE + 0x38, 0x0f71}, |
| 76 | {RT5677_PR_BASE + 0x39, 0x0f71}, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 77 | }; |
| 78 | #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list) |
| 79 | |
| 80 | static const struct reg_default rt5677_reg[] = { |
| 81 | {RT5677_RESET , 0x0000}, |
| 82 | {RT5677_LOUT1 , 0xa800}, |
| 83 | {RT5677_IN1 , 0x0000}, |
| 84 | {RT5677_MICBIAS , 0x0000}, |
| 85 | {RT5677_SLIMBUS_PARAM , 0x0000}, |
| 86 | {RT5677_SLIMBUS_RX , 0x0000}, |
| 87 | {RT5677_SLIMBUS_CTRL , 0x0000}, |
| 88 | {RT5677_SIDETONE_CTRL , 0x000b}, |
| 89 | {RT5677_ANA_DAC1_2_3_SRC , 0x0000}, |
| 90 | {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111}, |
| 91 | {RT5677_DAC4_DIG_VOL , 0xafaf}, |
| 92 | {RT5677_DAC3_DIG_VOL , 0xafaf}, |
| 93 | {RT5677_DAC1_DIG_VOL , 0xafaf}, |
| 94 | {RT5677_DAC2_DIG_VOL , 0xafaf}, |
| 95 | {RT5677_IF_DSP_DAC2_MIXER , 0x0011}, |
| 96 | {RT5677_STO1_ADC_DIG_VOL , 0x2f2f}, |
| 97 | {RT5677_MONO_ADC_DIG_VOL , 0x2f2f}, |
| 98 | {RT5677_STO1_2_ADC_BST , 0x0000}, |
| 99 | {RT5677_STO2_ADC_DIG_VOL , 0x2f2f}, |
| 100 | {RT5677_ADC_BST_CTRL2 , 0x0000}, |
| 101 | {RT5677_STO3_4_ADC_BST , 0x0000}, |
| 102 | {RT5677_STO3_ADC_DIG_VOL , 0x2f2f}, |
| 103 | {RT5677_STO4_ADC_DIG_VOL , 0x2f2f}, |
| 104 | {RT5677_STO4_ADC_MIXER , 0xd4c0}, |
| 105 | {RT5677_STO3_ADC_MIXER , 0xd4c0}, |
| 106 | {RT5677_STO2_ADC_MIXER , 0xd4c0}, |
| 107 | {RT5677_STO1_ADC_MIXER , 0xd4c0}, |
| 108 | {RT5677_MONO_ADC_MIXER , 0xd4d1}, |
| 109 | {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080}, |
| 110 | {RT5677_STO1_DAC_MIXER , 0xaaaa}, |
| 111 | {RT5677_MONO_DAC_MIXER , 0xaaaa}, |
| 112 | {RT5677_DD1_MIXER , 0xaaaa}, |
| 113 | {RT5677_DD2_MIXER , 0xaaaa}, |
| 114 | {RT5677_IF3_DATA , 0x0000}, |
| 115 | {RT5677_IF4_DATA , 0x0000}, |
| 116 | {RT5677_PDM_OUT_CTRL , 0x8888}, |
| 117 | {RT5677_PDM_DATA_CTRL1 , 0x0000}, |
| 118 | {RT5677_PDM_DATA_CTRL2 , 0x0000}, |
| 119 | {RT5677_PDM1_DATA_CTRL2 , 0x0000}, |
| 120 | {RT5677_PDM1_DATA_CTRL3 , 0x0000}, |
| 121 | {RT5677_PDM1_DATA_CTRL4 , 0x0000}, |
| 122 | {RT5677_PDM2_DATA_CTRL2 , 0x0000}, |
| 123 | {RT5677_PDM2_DATA_CTRL3 , 0x0000}, |
| 124 | {RT5677_PDM2_DATA_CTRL4 , 0x0000}, |
| 125 | {RT5677_TDM1_CTRL1 , 0x0300}, |
| 126 | {RT5677_TDM1_CTRL2 , 0x0000}, |
| 127 | {RT5677_TDM1_CTRL3 , 0x4000}, |
| 128 | {RT5677_TDM1_CTRL4 , 0x0123}, |
| 129 | {RT5677_TDM1_CTRL5 , 0x4567}, |
| 130 | {RT5677_TDM2_CTRL1 , 0x0300}, |
| 131 | {RT5677_TDM2_CTRL2 , 0x0000}, |
| 132 | {RT5677_TDM2_CTRL3 , 0x4000}, |
| 133 | {RT5677_TDM2_CTRL4 , 0x0123}, |
| 134 | {RT5677_TDM2_CTRL5 , 0x4567}, |
| 135 | {RT5677_I2C_MASTER_CTRL1 , 0x0001}, |
| 136 | {RT5677_I2C_MASTER_CTRL2 , 0x0000}, |
| 137 | {RT5677_I2C_MASTER_CTRL3 , 0x0000}, |
| 138 | {RT5677_I2C_MASTER_CTRL4 , 0x0000}, |
| 139 | {RT5677_I2C_MASTER_CTRL5 , 0x0000}, |
| 140 | {RT5677_I2C_MASTER_CTRL6 , 0x0000}, |
| 141 | {RT5677_I2C_MASTER_CTRL7 , 0x0000}, |
| 142 | {RT5677_I2C_MASTER_CTRL8 , 0x0000}, |
| 143 | {RT5677_DMIC_CTRL1 , 0x1505}, |
| 144 | {RT5677_DMIC_CTRL2 , 0x0055}, |
| 145 | {RT5677_HAP_GENE_CTRL1 , 0x0111}, |
| 146 | {RT5677_HAP_GENE_CTRL2 , 0x0064}, |
| 147 | {RT5677_HAP_GENE_CTRL3 , 0xef0e}, |
| 148 | {RT5677_HAP_GENE_CTRL4 , 0xf0f0}, |
| 149 | {RT5677_HAP_GENE_CTRL5 , 0xef0e}, |
| 150 | {RT5677_HAP_GENE_CTRL6 , 0xf0f0}, |
| 151 | {RT5677_HAP_GENE_CTRL7 , 0xef0e}, |
| 152 | {RT5677_HAP_GENE_CTRL8 , 0xf0f0}, |
| 153 | {RT5677_HAP_GENE_CTRL9 , 0xf000}, |
| 154 | {RT5677_HAP_GENE_CTRL10 , 0x0000}, |
| 155 | {RT5677_PWR_DIG1 , 0x0000}, |
| 156 | {RT5677_PWR_DIG2 , 0x0000}, |
| 157 | {RT5677_PWR_ANLG1 , 0x0055}, |
| 158 | {RT5677_PWR_ANLG2 , 0x0000}, |
| 159 | {RT5677_PWR_DSP1 , 0x0001}, |
| 160 | {RT5677_PWR_DSP_ST , 0x0000}, |
| 161 | {RT5677_PWR_DSP2 , 0x0000}, |
| 162 | {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00}, |
| 163 | {RT5677_PRIV_INDEX , 0x0000}, |
| 164 | {RT5677_PRIV_DATA , 0x0000}, |
| 165 | {RT5677_I2S4_SDP , 0x8000}, |
| 166 | {RT5677_I2S1_SDP , 0x8000}, |
| 167 | {RT5677_I2S2_SDP , 0x8000}, |
| 168 | {RT5677_I2S3_SDP , 0x8000}, |
| 169 | {RT5677_CLK_TREE_CTRL1 , 0x1111}, |
| 170 | {RT5677_CLK_TREE_CTRL2 , 0x1111}, |
| 171 | {RT5677_CLK_TREE_CTRL3 , 0x0000}, |
| 172 | {RT5677_PLL1_CTRL1 , 0x0000}, |
| 173 | {RT5677_PLL1_CTRL2 , 0x0000}, |
| 174 | {RT5677_PLL2_CTRL1 , 0x0c60}, |
| 175 | {RT5677_PLL2_CTRL2 , 0x2000}, |
| 176 | {RT5677_GLB_CLK1 , 0x0000}, |
| 177 | {RT5677_GLB_CLK2 , 0x0000}, |
| 178 | {RT5677_ASRC_1 , 0x0000}, |
| 179 | {RT5677_ASRC_2 , 0x0000}, |
| 180 | {RT5677_ASRC_3 , 0x0000}, |
| 181 | {RT5677_ASRC_4 , 0x0000}, |
| 182 | {RT5677_ASRC_5 , 0x0000}, |
| 183 | {RT5677_ASRC_6 , 0x0000}, |
| 184 | {RT5677_ASRC_7 , 0x0000}, |
| 185 | {RT5677_ASRC_8 , 0x0000}, |
| 186 | {RT5677_ASRC_9 , 0x0000}, |
| 187 | {RT5677_ASRC_10 , 0x0000}, |
| 188 | {RT5677_ASRC_11 , 0x0000}, |
Oder Chiou | 86ae04b | 2014-11-17 10:18:11 +0800 | [diff] [blame] | 189 | {RT5677_ASRC_12 , 0x0018}, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 190 | {RT5677_ASRC_13 , 0x0000}, |
| 191 | {RT5677_ASRC_14 , 0x0000}, |
| 192 | {RT5677_ASRC_15 , 0x0000}, |
| 193 | {RT5677_ASRC_16 , 0x0000}, |
| 194 | {RT5677_ASRC_17 , 0x0000}, |
| 195 | {RT5677_ASRC_18 , 0x0000}, |
| 196 | {RT5677_ASRC_19 , 0x0000}, |
| 197 | {RT5677_ASRC_20 , 0x0000}, |
| 198 | {RT5677_ASRC_21 , 0x000c}, |
| 199 | {RT5677_ASRC_22 , 0x0000}, |
| 200 | {RT5677_ASRC_23 , 0x0000}, |
| 201 | {RT5677_VAD_CTRL1 , 0x2184}, |
| 202 | {RT5677_VAD_CTRL2 , 0x010a}, |
| 203 | {RT5677_VAD_CTRL3 , 0x0aea}, |
| 204 | {RT5677_VAD_CTRL4 , 0x000c}, |
| 205 | {RT5677_VAD_CTRL5 , 0x0000}, |
| 206 | {RT5677_DSP_INB_CTRL1 , 0x0000}, |
| 207 | {RT5677_DSP_INB_CTRL2 , 0x0000}, |
| 208 | {RT5677_DSP_IN_OUTB_CTRL , 0x0000}, |
| 209 | {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f}, |
| 210 | {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f}, |
| 211 | {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f}, |
| 212 | {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f}, |
| 213 | {RT5677_ADC_EQ_CTRL1 , 0x6000}, |
| 214 | {RT5677_ADC_EQ_CTRL2 , 0x0000}, |
| 215 | {RT5677_EQ_CTRL1 , 0xc000}, |
| 216 | {RT5677_EQ_CTRL2 , 0x0000}, |
| 217 | {RT5677_EQ_CTRL3 , 0x0000}, |
| 218 | {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009}, |
| 219 | {RT5677_JD_CTRL1 , 0x0000}, |
| 220 | {RT5677_JD_CTRL2 , 0x0000}, |
| 221 | {RT5677_JD_CTRL3 , 0x0000}, |
| 222 | {RT5677_IRQ_CTRL1 , 0x0000}, |
| 223 | {RT5677_IRQ_CTRL2 , 0x0000}, |
| 224 | {RT5677_GPIO_ST , 0x0000}, |
| 225 | {RT5677_GPIO_CTRL1 , 0x0000}, |
| 226 | {RT5677_GPIO_CTRL2 , 0x0000}, |
| 227 | {RT5677_GPIO_CTRL3 , 0x0000}, |
| 228 | {RT5677_STO1_ADC_HI_FILTER1 , 0xb320}, |
| 229 | {RT5677_STO1_ADC_HI_FILTER2 , 0x0000}, |
| 230 | {RT5677_MONO_ADC_HI_FILTER1 , 0xb300}, |
| 231 | {RT5677_MONO_ADC_HI_FILTER2 , 0x0000}, |
| 232 | {RT5677_STO2_ADC_HI_FILTER1 , 0xb300}, |
| 233 | {RT5677_STO2_ADC_HI_FILTER2 , 0x0000}, |
| 234 | {RT5677_STO3_ADC_HI_FILTER1 , 0xb300}, |
| 235 | {RT5677_STO3_ADC_HI_FILTER2 , 0x0000}, |
| 236 | {RT5677_STO4_ADC_HI_FILTER1 , 0xb300}, |
| 237 | {RT5677_STO4_ADC_HI_FILTER2 , 0x0000}, |
| 238 | {RT5677_MB_DRC_CTRL1 , 0x0f20}, |
| 239 | {RT5677_DRC1_CTRL1 , 0x001f}, |
| 240 | {RT5677_DRC1_CTRL2 , 0x020c}, |
| 241 | {RT5677_DRC1_CTRL3 , 0x1f00}, |
| 242 | {RT5677_DRC1_CTRL4 , 0x0000}, |
| 243 | {RT5677_DRC1_CTRL5 , 0x0000}, |
| 244 | {RT5677_DRC1_CTRL6 , 0x0029}, |
| 245 | {RT5677_DRC2_CTRL1 , 0x001f}, |
| 246 | {RT5677_DRC2_CTRL2 , 0x020c}, |
| 247 | {RT5677_DRC2_CTRL3 , 0x1f00}, |
| 248 | {RT5677_DRC2_CTRL4 , 0x0000}, |
| 249 | {RT5677_DRC2_CTRL5 , 0x0000}, |
| 250 | {RT5677_DRC2_CTRL6 , 0x0029}, |
| 251 | {RT5677_DRC1_HL_CTRL1 , 0x8000}, |
| 252 | {RT5677_DRC1_HL_CTRL2 , 0x0200}, |
| 253 | {RT5677_DRC2_HL_CTRL1 , 0x8000}, |
| 254 | {RT5677_DRC2_HL_CTRL2 , 0x0200}, |
| 255 | {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800}, |
| 256 | {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000}, |
| 257 | {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000}, |
| 258 | {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800}, |
| 259 | {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800}, |
| 260 | {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000}, |
| 261 | {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000}, |
| 262 | {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800}, |
| 263 | {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800}, |
| 264 | {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000}, |
| 265 | {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000}, |
| 266 | {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800}, |
| 267 | {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800}, |
| 268 | {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000}, |
| 269 | {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000}, |
| 270 | {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800}, |
| 271 | {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800}, |
| 272 | {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000}, |
| 273 | {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000}, |
| 274 | {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800}, |
| 275 | {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe}, |
| 276 | {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe}, |
| 277 | {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe}, |
| 278 | {RT5677_DIG_MISC , 0x0000}, |
| 279 | {RT5677_GEN_CTRL1 , 0x0000}, |
| 280 | {RT5677_GEN_CTRL2 , 0x0000}, |
| 281 | {RT5677_VENDOR_ID , 0x0000}, |
| 282 | {RT5677_VENDOR_ID1 , 0x10ec}, |
| 283 | {RT5677_VENDOR_ID2 , 0x6327}, |
| 284 | }; |
| 285 | |
| 286 | static bool rt5677_volatile_register(struct device *dev, unsigned int reg) |
| 287 | { |
| 288 | int i; |
| 289 | |
| 290 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { |
| 291 | if (reg >= rt5677_ranges[i].range_min && |
| 292 | reg <= rt5677_ranges[i].range_max) { |
| 293 | return true; |
| 294 | } |
| 295 | } |
| 296 | |
| 297 | switch (reg) { |
| 298 | case RT5677_RESET: |
| 299 | case RT5677_SLIMBUS_PARAM: |
| 300 | case RT5677_PDM_DATA_CTRL1: |
| 301 | case RT5677_PDM_DATA_CTRL2: |
| 302 | case RT5677_PDM1_DATA_CTRL4: |
| 303 | case RT5677_PDM2_DATA_CTRL4: |
| 304 | case RT5677_I2C_MASTER_CTRL1: |
| 305 | case RT5677_I2C_MASTER_CTRL7: |
| 306 | case RT5677_I2C_MASTER_CTRL8: |
| 307 | case RT5677_HAP_GENE_CTRL2: |
| 308 | case RT5677_PWR_DSP_ST: |
| 309 | case RT5677_PRIV_DATA: |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 310 | case RT5677_ASRC_22: |
| 311 | case RT5677_ASRC_23: |
| 312 | case RT5677_VAD_CTRL5: |
| 313 | case RT5677_ADC_EQ_CTRL1: |
| 314 | case RT5677_EQ_CTRL1: |
| 315 | case RT5677_IRQ_CTRL1: |
| 316 | case RT5677_IRQ_CTRL2: |
| 317 | case RT5677_GPIO_ST: |
| 318 | case RT5677_DSP_INB1_SRC_CTRL4: |
| 319 | case RT5677_DSP_INB2_SRC_CTRL4: |
| 320 | case RT5677_DSP_INB3_SRC_CTRL4: |
| 321 | case RT5677_DSP_OUTB1_SRC_CTRL4: |
| 322 | case RT5677_DSP_OUTB2_SRC_CTRL4: |
| 323 | case RT5677_VENDOR_ID: |
| 324 | case RT5677_VENDOR_ID1: |
| 325 | case RT5677_VENDOR_ID2: |
| 326 | return true; |
| 327 | default: |
| 328 | return false; |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | static bool rt5677_readable_register(struct device *dev, unsigned int reg) |
| 333 | { |
| 334 | int i; |
| 335 | |
| 336 | for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) { |
| 337 | if (reg >= rt5677_ranges[i].range_min && |
| 338 | reg <= rt5677_ranges[i].range_max) { |
| 339 | return true; |
| 340 | } |
| 341 | } |
| 342 | |
| 343 | switch (reg) { |
| 344 | case RT5677_RESET: |
| 345 | case RT5677_LOUT1: |
| 346 | case RT5677_IN1: |
| 347 | case RT5677_MICBIAS: |
| 348 | case RT5677_SLIMBUS_PARAM: |
| 349 | case RT5677_SLIMBUS_RX: |
| 350 | case RT5677_SLIMBUS_CTRL: |
| 351 | case RT5677_SIDETONE_CTRL: |
| 352 | case RT5677_ANA_DAC1_2_3_SRC: |
| 353 | case RT5677_IF_DSP_DAC3_4_MIXER: |
| 354 | case RT5677_DAC4_DIG_VOL: |
| 355 | case RT5677_DAC3_DIG_VOL: |
| 356 | case RT5677_DAC1_DIG_VOL: |
| 357 | case RT5677_DAC2_DIG_VOL: |
| 358 | case RT5677_IF_DSP_DAC2_MIXER: |
| 359 | case RT5677_STO1_ADC_DIG_VOL: |
| 360 | case RT5677_MONO_ADC_DIG_VOL: |
| 361 | case RT5677_STO1_2_ADC_BST: |
| 362 | case RT5677_STO2_ADC_DIG_VOL: |
| 363 | case RT5677_ADC_BST_CTRL2: |
| 364 | case RT5677_STO3_4_ADC_BST: |
| 365 | case RT5677_STO3_ADC_DIG_VOL: |
| 366 | case RT5677_STO4_ADC_DIG_VOL: |
| 367 | case RT5677_STO4_ADC_MIXER: |
| 368 | case RT5677_STO3_ADC_MIXER: |
| 369 | case RT5677_STO2_ADC_MIXER: |
| 370 | case RT5677_STO1_ADC_MIXER: |
| 371 | case RT5677_MONO_ADC_MIXER: |
| 372 | case RT5677_ADC_IF_DSP_DAC1_MIXER: |
| 373 | case RT5677_STO1_DAC_MIXER: |
| 374 | case RT5677_MONO_DAC_MIXER: |
| 375 | case RT5677_DD1_MIXER: |
| 376 | case RT5677_DD2_MIXER: |
| 377 | case RT5677_IF3_DATA: |
| 378 | case RT5677_IF4_DATA: |
| 379 | case RT5677_PDM_OUT_CTRL: |
| 380 | case RT5677_PDM_DATA_CTRL1: |
| 381 | case RT5677_PDM_DATA_CTRL2: |
| 382 | case RT5677_PDM1_DATA_CTRL2: |
| 383 | case RT5677_PDM1_DATA_CTRL3: |
| 384 | case RT5677_PDM1_DATA_CTRL4: |
| 385 | case RT5677_PDM2_DATA_CTRL2: |
| 386 | case RT5677_PDM2_DATA_CTRL3: |
| 387 | case RT5677_PDM2_DATA_CTRL4: |
| 388 | case RT5677_TDM1_CTRL1: |
| 389 | case RT5677_TDM1_CTRL2: |
| 390 | case RT5677_TDM1_CTRL3: |
| 391 | case RT5677_TDM1_CTRL4: |
| 392 | case RT5677_TDM1_CTRL5: |
| 393 | case RT5677_TDM2_CTRL1: |
| 394 | case RT5677_TDM2_CTRL2: |
| 395 | case RT5677_TDM2_CTRL3: |
| 396 | case RT5677_TDM2_CTRL4: |
| 397 | case RT5677_TDM2_CTRL5: |
| 398 | case RT5677_I2C_MASTER_CTRL1: |
| 399 | case RT5677_I2C_MASTER_CTRL2: |
| 400 | case RT5677_I2C_MASTER_CTRL3: |
| 401 | case RT5677_I2C_MASTER_CTRL4: |
| 402 | case RT5677_I2C_MASTER_CTRL5: |
| 403 | case RT5677_I2C_MASTER_CTRL6: |
| 404 | case RT5677_I2C_MASTER_CTRL7: |
| 405 | case RT5677_I2C_MASTER_CTRL8: |
| 406 | case RT5677_DMIC_CTRL1: |
| 407 | case RT5677_DMIC_CTRL2: |
| 408 | case RT5677_HAP_GENE_CTRL1: |
| 409 | case RT5677_HAP_GENE_CTRL2: |
| 410 | case RT5677_HAP_GENE_CTRL3: |
| 411 | case RT5677_HAP_GENE_CTRL4: |
| 412 | case RT5677_HAP_GENE_CTRL5: |
| 413 | case RT5677_HAP_GENE_CTRL6: |
| 414 | case RT5677_HAP_GENE_CTRL7: |
| 415 | case RT5677_HAP_GENE_CTRL8: |
| 416 | case RT5677_HAP_GENE_CTRL9: |
| 417 | case RT5677_HAP_GENE_CTRL10: |
| 418 | case RT5677_PWR_DIG1: |
| 419 | case RT5677_PWR_DIG2: |
| 420 | case RT5677_PWR_ANLG1: |
| 421 | case RT5677_PWR_ANLG2: |
| 422 | case RT5677_PWR_DSP1: |
| 423 | case RT5677_PWR_DSP_ST: |
| 424 | case RT5677_PWR_DSP2: |
| 425 | case RT5677_ADC_DAC_HPF_CTRL1: |
| 426 | case RT5677_PRIV_INDEX: |
| 427 | case RT5677_PRIV_DATA: |
| 428 | case RT5677_I2S4_SDP: |
| 429 | case RT5677_I2S1_SDP: |
| 430 | case RT5677_I2S2_SDP: |
| 431 | case RT5677_I2S3_SDP: |
| 432 | case RT5677_CLK_TREE_CTRL1: |
| 433 | case RT5677_CLK_TREE_CTRL2: |
| 434 | case RT5677_CLK_TREE_CTRL3: |
| 435 | case RT5677_PLL1_CTRL1: |
| 436 | case RT5677_PLL1_CTRL2: |
| 437 | case RT5677_PLL2_CTRL1: |
| 438 | case RT5677_PLL2_CTRL2: |
| 439 | case RT5677_GLB_CLK1: |
| 440 | case RT5677_GLB_CLK2: |
| 441 | case RT5677_ASRC_1: |
| 442 | case RT5677_ASRC_2: |
| 443 | case RT5677_ASRC_3: |
| 444 | case RT5677_ASRC_4: |
| 445 | case RT5677_ASRC_5: |
| 446 | case RT5677_ASRC_6: |
| 447 | case RT5677_ASRC_7: |
| 448 | case RT5677_ASRC_8: |
| 449 | case RT5677_ASRC_9: |
| 450 | case RT5677_ASRC_10: |
| 451 | case RT5677_ASRC_11: |
| 452 | case RT5677_ASRC_12: |
| 453 | case RT5677_ASRC_13: |
| 454 | case RT5677_ASRC_14: |
| 455 | case RT5677_ASRC_15: |
| 456 | case RT5677_ASRC_16: |
| 457 | case RT5677_ASRC_17: |
| 458 | case RT5677_ASRC_18: |
| 459 | case RT5677_ASRC_19: |
| 460 | case RT5677_ASRC_20: |
| 461 | case RT5677_ASRC_21: |
| 462 | case RT5677_ASRC_22: |
| 463 | case RT5677_ASRC_23: |
| 464 | case RT5677_VAD_CTRL1: |
| 465 | case RT5677_VAD_CTRL2: |
| 466 | case RT5677_VAD_CTRL3: |
| 467 | case RT5677_VAD_CTRL4: |
| 468 | case RT5677_VAD_CTRL5: |
| 469 | case RT5677_DSP_INB_CTRL1: |
| 470 | case RT5677_DSP_INB_CTRL2: |
| 471 | case RT5677_DSP_IN_OUTB_CTRL: |
| 472 | case RT5677_DSP_OUTB0_1_DIG_VOL: |
| 473 | case RT5677_DSP_OUTB2_3_DIG_VOL: |
| 474 | case RT5677_DSP_OUTB4_5_DIG_VOL: |
| 475 | case RT5677_DSP_OUTB6_7_DIG_VOL: |
| 476 | case RT5677_ADC_EQ_CTRL1: |
| 477 | case RT5677_ADC_EQ_CTRL2: |
| 478 | case RT5677_EQ_CTRL1: |
| 479 | case RT5677_EQ_CTRL2: |
| 480 | case RT5677_EQ_CTRL3: |
| 481 | case RT5677_SOFT_VOL_ZERO_CROSS1: |
| 482 | case RT5677_JD_CTRL1: |
| 483 | case RT5677_JD_CTRL2: |
| 484 | case RT5677_JD_CTRL3: |
| 485 | case RT5677_IRQ_CTRL1: |
| 486 | case RT5677_IRQ_CTRL2: |
| 487 | case RT5677_GPIO_ST: |
| 488 | case RT5677_GPIO_CTRL1: |
| 489 | case RT5677_GPIO_CTRL2: |
| 490 | case RT5677_GPIO_CTRL3: |
| 491 | case RT5677_STO1_ADC_HI_FILTER1: |
| 492 | case RT5677_STO1_ADC_HI_FILTER2: |
| 493 | case RT5677_MONO_ADC_HI_FILTER1: |
| 494 | case RT5677_MONO_ADC_HI_FILTER2: |
| 495 | case RT5677_STO2_ADC_HI_FILTER1: |
| 496 | case RT5677_STO2_ADC_HI_FILTER2: |
| 497 | case RT5677_STO3_ADC_HI_FILTER1: |
| 498 | case RT5677_STO3_ADC_HI_FILTER2: |
| 499 | case RT5677_STO4_ADC_HI_FILTER1: |
| 500 | case RT5677_STO4_ADC_HI_FILTER2: |
| 501 | case RT5677_MB_DRC_CTRL1: |
| 502 | case RT5677_DRC1_CTRL1: |
| 503 | case RT5677_DRC1_CTRL2: |
| 504 | case RT5677_DRC1_CTRL3: |
| 505 | case RT5677_DRC1_CTRL4: |
| 506 | case RT5677_DRC1_CTRL5: |
| 507 | case RT5677_DRC1_CTRL6: |
| 508 | case RT5677_DRC2_CTRL1: |
| 509 | case RT5677_DRC2_CTRL2: |
| 510 | case RT5677_DRC2_CTRL3: |
| 511 | case RT5677_DRC2_CTRL4: |
| 512 | case RT5677_DRC2_CTRL5: |
| 513 | case RT5677_DRC2_CTRL6: |
| 514 | case RT5677_DRC1_HL_CTRL1: |
| 515 | case RT5677_DRC1_HL_CTRL2: |
| 516 | case RT5677_DRC2_HL_CTRL1: |
| 517 | case RT5677_DRC2_HL_CTRL2: |
| 518 | case RT5677_DSP_INB1_SRC_CTRL1: |
| 519 | case RT5677_DSP_INB1_SRC_CTRL2: |
| 520 | case RT5677_DSP_INB1_SRC_CTRL3: |
| 521 | case RT5677_DSP_INB1_SRC_CTRL4: |
| 522 | case RT5677_DSP_INB2_SRC_CTRL1: |
| 523 | case RT5677_DSP_INB2_SRC_CTRL2: |
| 524 | case RT5677_DSP_INB2_SRC_CTRL3: |
| 525 | case RT5677_DSP_INB2_SRC_CTRL4: |
| 526 | case RT5677_DSP_INB3_SRC_CTRL1: |
| 527 | case RT5677_DSP_INB3_SRC_CTRL2: |
| 528 | case RT5677_DSP_INB3_SRC_CTRL3: |
| 529 | case RT5677_DSP_INB3_SRC_CTRL4: |
| 530 | case RT5677_DSP_OUTB1_SRC_CTRL1: |
| 531 | case RT5677_DSP_OUTB1_SRC_CTRL2: |
| 532 | case RT5677_DSP_OUTB1_SRC_CTRL3: |
| 533 | case RT5677_DSP_OUTB1_SRC_CTRL4: |
| 534 | case RT5677_DSP_OUTB2_SRC_CTRL1: |
| 535 | case RT5677_DSP_OUTB2_SRC_CTRL2: |
| 536 | case RT5677_DSP_OUTB2_SRC_CTRL3: |
| 537 | case RT5677_DSP_OUTB2_SRC_CTRL4: |
| 538 | case RT5677_DSP_OUTB_0123_MIXER_CTRL: |
| 539 | case RT5677_DSP_OUTB_45_MIXER_CTRL: |
| 540 | case RT5677_DSP_OUTB_67_MIXER_CTRL: |
| 541 | case RT5677_DIG_MISC: |
| 542 | case RT5677_GEN_CTRL1: |
| 543 | case RT5677_GEN_CTRL2: |
| 544 | case RT5677_VENDOR_ID: |
| 545 | case RT5677_VENDOR_ID1: |
| 546 | case RT5677_VENDOR_ID2: |
| 547 | return true; |
| 548 | default: |
| 549 | return false; |
| 550 | } |
| 551 | } |
| 552 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 553 | /** |
| 554 | * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 555 | * @rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 556 | * @addr: Address index. |
| 557 | * @value: Address data. |
| 558 | * |
| 559 | * |
| 560 | * Returns 0 for success or negative error code. |
| 561 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 562 | static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 563 | unsigned int addr, unsigned int value, unsigned int opcode) |
| 564 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 565 | struct snd_soc_codec *codec = rt5677->codec; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 566 | int ret; |
| 567 | |
| 568 | mutex_lock(&rt5677->dsp_cmd_lock); |
| 569 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 570 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
| 571 | addr >> 16); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 572 | if (ret < 0) { |
| 573 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); |
| 574 | goto err; |
| 575 | } |
| 576 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 577 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 578 | addr & 0xffff); |
| 579 | if (ret < 0) { |
| 580 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); |
| 581 | goto err; |
| 582 | } |
| 583 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 584 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 585 | value >> 16); |
| 586 | if (ret < 0) { |
| 587 | dev_err(codec->dev, "Failed to set data msb value: %d\n", ret); |
| 588 | goto err; |
| 589 | } |
| 590 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 591 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 592 | value & 0xffff); |
| 593 | if (ret < 0) { |
| 594 | dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret); |
| 595 | goto err; |
| 596 | } |
| 597 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 598 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
| 599 | opcode); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 600 | if (ret < 0) { |
| 601 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); |
| 602 | goto err; |
| 603 | } |
| 604 | |
| 605 | err: |
| 606 | mutex_unlock(&rt5677->dsp_cmd_lock); |
| 607 | |
| 608 | return ret; |
| 609 | } |
| 610 | |
| 611 | /** |
| 612 | * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 613 | * rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 614 | * @addr: Address index. |
| 615 | * @value: Address data. |
| 616 | * |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 617 | * |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 618 | * Returns 0 for success or negative error code. |
| 619 | */ |
| 620 | static int rt5677_dsp_mode_i2c_read_addr( |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 621 | struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 622 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 623 | struct snd_soc_codec *codec = rt5677->codec; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 624 | int ret; |
| 625 | unsigned int msb, lsb; |
| 626 | |
| 627 | mutex_lock(&rt5677->dsp_cmd_lock); |
| 628 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 629 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, |
| 630 | addr >> 16); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 631 | if (ret < 0) { |
| 632 | dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret); |
| 633 | goto err; |
| 634 | } |
| 635 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 636 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 637 | addr & 0xffff); |
| 638 | if (ret < 0) { |
| 639 | dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret); |
| 640 | goto err; |
| 641 | } |
| 642 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 643 | ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, |
| 644 | 0x0002); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 645 | if (ret < 0) { |
| 646 | dev_err(codec->dev, "Failed to set op code value: %d\n", ret); |
| 647 | goto err; |
| 648 | } |
| 649 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 650 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); |
| 651 | regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 652 | *value = (msb << 16) | lsb; |
| 653 | |
| 654 | err: |
| 655 | mutex_unlock(&rt5677->dsp_cmd_lock); |
| 656 | |
| 657 | return ret; |
| 658 | } |
| 659 | |
| 660 | /** |
| 661 | * rt5677_dsp_mode_i2c_write - Write register on DSP mode. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 662 | * rt5677: Private Data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 663 | * @reg: Register index. |
| 664 | * @value: Register data. |
| 665 | * |
| 666 | * |
| 667 | * Returns 0 for success or negative error code. |
| 668 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 669 | static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 670 | unsigned int reg, unsigned int value) |
| 671 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 672 | return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2, |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 673 | value, 0x0001); |
| 674 | } |
| 675 | |
| 676 | /** |
| 677 | * rt5677_dsp_mode_i2c_read - Read register on DSP mode. |
| 678 | * @codec: SoC audio codec device. |
| 679 | * @reg: Register index. |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 680 | * @value: Register data. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 681 | * |
| 682 | * |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 683 | * Returns 0 for success or negative error code. |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 684 | */ |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 685 | static int rt5677_dsp_mode_i2c_read( |
| 686 | struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 687 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 688 | int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2, |
| 689 | value); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 690 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 691 | *value &= 0xffff; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 692 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 693 | return ret; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 694 | } |
| 695 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 696 | static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 697 | { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 698 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 699 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 700 | if (on) { |
| 701 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); |
| 702 | rt5677->is_dsp_mode = true; |
| 703 | } else { |
| 704 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); |
| 705 | rt5677->is_dsp_mode = false; |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 706 | } |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on) |
| 710 | { |
| 711 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 712 | static bool activity; |
| 713 | int ret; |
| 714 | |
Arnd Bergmann | 4c12112 | 2015-01-28 22:31:30 +0100 | [diff] [blame] | 715 | if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI)) |
| 716 | return -ENXIO; |
| 717 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 718 | if (on && !activity) { |
| 719 | activity = true; |
| 720 | |
| 721 | regcache_cache_only(rt5677->regmap, false); |
| 722 | regcache_cache_bypass(rt5677->regmap, true); |
| 723 | |
| 724 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); |
| 725 | regmap_update_bits(rt5677->regmap, |
| 726 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00); |
| 727 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 728 | RT5677_LDO1_SEL_MASK, 0x0); |
| 729 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 730 | RT5677_PWR_LDO1, RT5677_PWR_LDO1); |
Oder Chiou | ab1f709 | 2015-02-11 19:18:51 +0800 | [diff] [blame] | 731 | switch (rt5677->type) { |
| 732 | case RT5677: |
| 733 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 734 | RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC); |
| 735 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, |
| 736 | RT5677_PLL2_PR_SRC_MASK | |
| 737 | RT5677_DSP_CLK_SRC_MASK, |
| 738 | RT5677_PLL2_PR_SRC_MCLK2 | |
| 739 | RT5677_DSP_CLK_SRC_BYPASS); |
| 740 | break; |
| 741 | case RT5676: |
| 742 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, |
| 743 | RT5677_DSP_CLK_SRC_MASK, |
| 744 | RT5677_DSP_CLK_SRC_BYPASS); |
| 745 | break; |
| 746 | default: |
| 747 | break; |
| 748 | } |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 749 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 750 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); |
| 751 | rt5677_set_dsp_mode(codec, true); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 752 | |
| 753 | ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, |
| 754 | codec->dev); |
| 755 | if (ret == 0) { |
Ben Zhang | 7d4d443 | 2015-08-21 21:17:00 -0700 | [diff] [blame] | 756 | rt5677_spi_write_firmware(0x50000000, rt5677->fw1); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 757 | release_firmware(rt5677->fw1); |
| 758 | } |
| 759 | |
| 760 | ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, |
| 761 | codec->dev); |
| 762 | if (ret == 0) { |
Ben Zhang | 7d4d443 | 2015-08-21 21:17:00 -0700 | [diff] [blame] | 763 | rt5677_spi_write_firmware(0x60000000, rt5677->fw2); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 764 | release_firmware(rt5677->fw2); |
| 765 | } |
| 766 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 767 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 768 | |
| 769 | regcache_cache_bypass(rt5677->regmap, false); |
| 770 | regcache_cache_only(rt5677->regmap, true); |
| 771 | } else if (!on && activity) { |
| 772 | activity = false; |
| 773 | |
| 774 | regcache_cache_only(rt5677->regmap, false); |
| 775 | regcache_cache_bypass(rt5677->regmap, true); |
| 776 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 777 | regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); |
| 778 | rt5677_set_dsp_mode(codec, false); |
| 779 | regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 780 | |
| 781 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
| 782 | |
| 783 | regcache_cache_bypass(rt5677->regmap, false); |
| 784 | regcache_mark_dirty(rt5677->regmap); |
| 785 | regcache_sync(rt5677->regmap); |
| 786 | } |
| 787 | |
| 788 | return 0; |
| 789 | } |
| 790 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 791 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 792 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 793 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 794 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 795 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 796 | static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 797 | |
| 798 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ |
Lars-Peter Clausen | 53f2860 | 2015-08-02 17:19:52 +0200 | [diff] [blame] | 799 | static const DECLARE_TLV_DB_RANGE(bst_tlv, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 800 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
| 801 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), |
| 802 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), |
| 803 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), |
| 804 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), |
| 805 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), |
Lars-Peter Clausen | 53f2860 | 2015-08-02 17:19:52 +0200 | [diff] [blame] | 806 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) |
| 807 | ); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 808 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 809 | static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol, |
| 810 | struct snd_ctl_elem_value *ucontrol) |
| 811 | { |
Fang, Yang A | 6087fca | 2014-12-23 23:49:05 -0400 | [diff] [blame] | 812 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
| 813 | struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 814 | |
| 815 | ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol, |
| 821 | struct snd_ctl_elem_value *ucontrol) |
| 822 | { |
Fang, Yang A | 6087fca | 2014-12-23 23:49:05 -0400 | [diff] [blame] | 823 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); |
| 824 | struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component); |
| 825 | struct snd_soc_codec *codec = snd_soc_component_to_codec(component); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 826 | |
| 827 | rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; |
| 828 | |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 829 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 830 | rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en); |
| 831 | |
| 832 | return 0; |
| 833 | } |
| 834 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 835 | static const struct snd_kcontrol_new rt5677_snd_controls[] = { |
| 836 | /* OUTPUT Control */ |
| 837 | SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1, |
| 838 | RT5677_LOUT1_L_MUTE_SFT, 1, 1), |
| 839 | SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1, |
| 840 | RT5677_LOUT2_L_MUTE_SFT, 1, 1), |
| 841 | SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1, |
| 842 | RT5677_LOUT3_L_MUTE_SFT, 1, 1), |
| 843 | |
| 844 | /* DAC Digital Volume */ |
| 845 | SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 846 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 847 | SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 848 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 849 | SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 850 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 851 | SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 852 | RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 853 | |
| 854 | /* IN1/IN2 Control */ |
| 855 | SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv), |
| 856 | SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv), |
| 857 | |
| 858 | /* ADC Digital Volume Control */ |
| 859 | SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL, |
| 860 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 861 | SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL, |
| 862 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 863 | SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL, |
| 864 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 865 | SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL, |
| 866 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 867 | SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL, |
| 868 | RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1), |
| 869 | |
| 870 | SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 871 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 872 | adc_vol_tlv), |
| 873 | SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 874 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 875 | adc_vol_tlv), |
| 876 | SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 877 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 878 | adc_vol_tlv), |
| 879 | SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 880 | RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 881 | adc_vol_tlv), |
| 882 | SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL, |
Dylan Reid | 40e3262 | 2014-12-04 17:00:13 -0800 | [diff] [blame] | 883 | RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 884 | adc_vol_tlv), |
| 885 | |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 886 | /* Sidetone Control */ |
| 887 | SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL, |
| 888 | RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv), |
| 889 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 890 | /* ADC Boost Volume Control */ |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 891 | SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 892 | RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0, |
| 893 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 894 | SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 895 | RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0, |
| 896 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 897 | SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 898 | RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0, |
| 899 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 900 | SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 901 | RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0, |
| 902 | adc_bst_tlv), |
Oder Chiou | 80220f2 | 2014-06-10 14:35:25 +0800 | [diff] [blame] | 903 | SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 904 | RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0, |
| 905 | adc_bst_tlv), |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 906 | |
| 907 | SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0, |
| 908 | rt5677_dsp_vad_get, rt5677_dsp_vad_put), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 909 | }; |
| 910 | |
| 911 | /** |
| 912 | * set_dmic_clk - Set parameter of dmic. |
| 913 | * |
| 914 | * @w: DAPM widget. |
| 915 | * @kcontrol: The kcontrol of this widget. |
| 916 | * @event: Event id. |
| 917 | * |
| 918 | * Choose dmic clock between 1MHz and 3MHz. |
| 919 | * It is better for clock to approximate 3MHz. |
| 920 | */ |
| 921 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, |
| 922 | struct snd_kcontrol *kcontrol, int event) |
| 923 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 924 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 925 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | 00a6d6e5 | 2015-08-05 10:03:18 +0800 | [diff] [blame] | 926 | int idx, rate; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 927 | |
Oder Chiou | 00a6d6e5 | 2015-08-05 10:03:18 +0800 | [diff] [blame] | 928 | rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, |
| 929 | RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT); |
| 930 | idx = rl6231_calc_dmic_clk(rate); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 931 | if (idx < 0) |
| 932 | dev_err(codec->dev, "Failed to set DMIC clock\n"); |
| 933 | else |
| 934 | regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, |
| 935 | RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT); |
| 936 | return idx; |
| 937 | } |
| 938 | |
| 939 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, |
| 940 | struct snd_soc_dapm_widget *sink) |
| 941 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 942 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
| 943 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 944 | unsigned int val; |
| 945 | |
| 946 | regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); |
| 947 | val &= RT5677_SCLK_SRC_MASK; |
| 948 | if (val == RT5677_SCLK_SRC_PLL1) |
| 949 | return 1; |
| 950 | else |
| 951 | return 0; |
| 952 | } |
| 953 | |
Oder Chiou | 5a8c7c2 | 2014-12-23 10:27:55 +0800 | [diff] [blame] | 954 | static int is_using_asrc(struct snd_soc_dapm_widget *source, |
| 955 | struct snd_soc_dapm_widget *sink) |
| 956 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 957 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
Oder Chiou | e4b7e6a | 2015-01-13 11:13:14 +0800 | [diff] [blame] | 958 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | 5a8c7c2 | 2014-12-23 10:27:55 +0800 | [diff] [blame] | 959 | unsigned int reg, shift, val; |
| 960 | |
| 961 | if (source->reg == RT5677_ASRC_1) { |
| 962 | switch (source->shift) { |
| 963 | case 12: |
| 964 | reg = RT5677_ASRC_4; |
| 965 | shift = 0; |
| 966 | break; |
| 967 | case 13: |
| 968 | reg = RT5677_ASRC_4; |
| 969 | shift = 4; |
| 970 | break; |
| 971 | case 14: |
| 972 | reg = RT5677_ASRC_4; |
| 973 | shift = 8; |
| 974 | break; |
| 975 | case 15: |
| 976 | reg = RT5677_ASRC_4; |
| 977 | shift = 12; |
| 978 | break; |
| 979 | default: |
| 980 | return 0; |
| 981 | } |
| 982 | } else { |
| 983 | switch (source->shift) { |
| 984 | case 0: |
| 985 | reg = RT5677_ASRC_6; |
| 986 | shift = 8; |
| 987 | break; |
| 988 | case 1: |
| 989 | reg = RT5677_ASRC_6; |
| 990 | shift = 12; |
| 991 | break; |
| 992 | case 2: |
| 993 | reg = RT5677_ASRC_5; |
| 994 | shift = 0; |
| 995 | break; |
| 996 | case 3: |
| 997 | reg = RT5677_ASRC_5; |
| 998 | shift = 4; |
| 999 | break; |
| 1000 | case 4: |
| 1001 | reg = RT5677_ASRC_5; |
| 1002 | shift = 8; |
| 1003 | break; |
| 1004 | case 5: |
| 1005 | reg = RT5677_ASRC_5; |
| 1006 | shift = 12; |
| 1007 | break; |
| 1008 | case 12: |
| 1009 | reg = RT5677_ASRC_3; |
| 1010 | shift = 0; |
| 1011 | break; |
| 1012 | case 13: |
| 1013 | reg = RT5677_ASRC_3; |
| 1014 | shift = 4; |
| 1015 | break; |
| 1016 | case 14: |
| 1017 | reg = RT5677_ASRC_3; |
| 1018 | shift = 12; |
| 1019 | break; |
| 1020 | default: |
| 1021 | return 0; |
| 1022 | } |
| 1023 | } |
| 1024 | |
Oder Chiou | e4b7e6a | 2015-01-13 11:13:14 +0800 | [diff] [blame] | 1025 | regmap_read(rt5677->regmap, reg, &val); |
| 1026 | val = (val >> shift) & 0xf; |
| 1027 | |
Oder Chiou | 5a8c7c2 | 2014-12-23 10:27:55 +0800 | [diff] [blame] | 1028 | switch (val) { |
| 1029 | case 1 ... 6: |
| 1030 | return 1; |
| 1031 | default: |
| 1032 | return 0; |
| 1033 | } |
| 1034 | |
| 1035 | } |
| 1036 | |
| 1037 | static int can_use_asrc(struct snd_soc_dapm_widget *source, |
| 1038 | struct snd_soc_dapm_widget *sink) |
| 1039 | { |
| 1040 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
| 1041 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 1042 | |
| 1043 | if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) |
| 1044 | return 1; |
| 1045 | |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
Oder Chiou | c36aa0a | 2015-03-16 14:39:57 +0800 | [diff] [blame] | 1049 | /** |
| 1050 | * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters |
| 1051 | * @codec: SoC audio codec device. |
| 1052 | * @filter_mask: mask of filters. |
| 1053 | * @clk_src: clock source |
| 1054 | * |
| 1055 | * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can |
| 1056 | * only support standard 32fs or 64fs i2s format, ASRC should be enabled to |
| 1057 | * support special i2s clock format such as Intel's 100fs(100 * sampling rate). |
| 1058 | * ASRC function will track i2s clock and generate a corresponding system clock |
| 1059 | * for codec. This function provides an API to select the clock source for a |
| 1060 | * set of filters specified by the mask. And the codec driver will turn on ASRC |
| 1061 | * for these filters if ASRC is selected as their clock source. |
| 1062 | */ |
| 1063 | int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec, |
| 1064 | unsigned int filter_mask, unsigned int clk_src) |
| 1065 | { |
| 1066 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 1067 | unsigned int asrc3_mask = 0, asrc3_value = 0; |
| 1068 | unsigned int asrc4_mask = 0, asrc4_value = 0; |
| 1069 | unsigned int asrc5_mask = 0, asrc5_value = 0; |
| 1070 | unsigned int asrc6_mask = 0, asrc6_value = 0; |
| 1071 | unsigned int asrc7_mask = 0, asrc7_value = 0; |
Bard Liao | 16ab6e1 | 2015-04-28 11:27:40 +0800 | [diff] [blame] | 1072 | unsigned int asrc8_mask = 0, asrc8_value = 0; |
Oder Chiou | c36aa0a | 2015-03-16 14:39:57 +0800 | [diff] [blame] | 1073 | |
| 1074 | switch (clk_src) { |
| 1075 | case RT5677_CLK_SEL_SYS: |
| 1076 | case RT5677_CLK_SEL_I2S1_ASRC: |
| 1077 | case RT5677_CLK_SEL_I2S2_ASRC: |
| 1078 | case RT5677_CLK_SEL_I2S3_ASRC: |
| 1079 | case RT5677_CLK_SEL_I2S4_ASRC: |
| 1080 | case RT5677_CLK_SEL_I2S5_ASRC: |
| 1081 | case RT5677_CLK_SEL_I2S6_ASRC: |
| 1082 | case RT5677_CLK_SEL_SYS2: |
| 1083 | case RT5677_CLK_SEL_SYS3: |
| 1084 | case RT5677_CLK_SEL_SYS4: |
| 1085 | case RT5677_CLK_SEL_SYS5: |
| 1086 | case RT5677_CLK_SEL_SYS6: |
| 1087 | case RT5677_CLK_SEL_SYS7: |
| 1088 | break; |
| 1089 | |
| 1090 | default: |
| 1091 | return -EINVAL; |
| 1092 | } |
| 1093 | |
| 1094 | /* ASRC 3 */ |
| 1095 | if (filter_mask & RT5677_DA_STEREO_FILTER) { |
| 1096 | asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK; |
| 1097 | asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK) |
| 1098 | | (clk_src << RT5677_DA_STO_CLK_SEL_SFT); |
| 1099 | } |
| 1100 | |
| 1101 | if (filter_mask & RT5677_DA_MONO2_L_FILTER) { |
| 1102 | asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK; |
| 1103 | asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK) |
| 1104 | | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT); |
| 1105 | } |
| 1106 | |
| 1107 | if (filter_mask & RT5677_DA_MONO2_R_FILTER) { |
| 1108 | asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK; |
| 1109 | asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK) |
| 1110 | | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT); |
| 1111 | } |
| 1112 | |
| 1113 | if (asrc3_mask) |
| 1114 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, |
| 1115 | asrc3_value); |
| 1116 | |
| 1117 | /* ASRC 4 */ |
| 1118 | if (filter_mask & RT5677_DA_MONO3_L_FILTER) { |
| 1119 | asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK; |
| 1120 | asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK) |
| 1121 | | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT); |
| 1122 | } |
| 1123 | |
| 1124 | if (filter_mask & RT5677_DA_MONO3_R_FILTER) { |
| 1125 | asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK; |
| 1126 | asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK) |
| 1127 | | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT); |
| 1128 | } |
| 1129 | |
| 1130 | if (filter_mask & RT5677_DA_MONO4_L_FILTER) { |
| 1131 | asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK; |
| 1132 | asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK) |
| 1133 | | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT); |
| 1134 | } |
| 1135 | |
| 1136 | if (filter_mask & RT5677_DA_MONO4_R_FILTER) { |
| 1137 | asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK; |
| 1138 | asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK) |
| 1139 | | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT); |
| 1140 | } |
| 1141 | |
| 1142 | if (asrc4_mask) |
| 1143 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, |
| 1144 | asrc4_value); |
| 1145 | |
| 1146 | /* ASRC 5 */ |
| 1147 | if (filter_mask & RT5677_AD_STEREO1_FILTER) { |
| 1148 | asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK; |
| 1149 | asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK) |
| 1150 | | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT); |
| 1151 | } |
| 1152 | |
| 1153 | if (filter_mask & RT5677_AD_STEREO2_FILTER) { |
| 1154 | asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK; |
| 1155 | asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK) |
| 1156 | | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT); |
| 1157 | } |
| 1158 | |
| 1159 | if (filter_mask & RT5677_AD_STEREO3_FILTER) { |
| 1160 | asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK; |
| 1161 | asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK) |
| 1162 | | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT); |
| 1163 | } |
| 1164 | |
| 1165 | if (filter_mask & RT5677_AD_STEREO4_FILTER) { |
| 1166 | asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK; |
| 1167 | asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK) |
| 1168 | | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT); |
| 1169 | } |
| 1170 | |
| 1171 | if (asrc5_mask) |
| 1172 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, |
| 1173 | asrc5_value); |
| 1174 | |
| 1175 | /* ASRC 6 */ |
| 1176 | if (filter_mask & RT5677_AD_MONO_L_FILTER) { |
| 1177 | asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK; |
| 1178 | asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK) |
| 1179 | | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT); |
| 1180 | } |
| 1181 | |
| 1182 | if (filter_mask & RT5677_AD_MONO_R_FILTER) { |
| 1183 | asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK; |
| 1184 | asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK) |
| 1185 | | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT); |
| 1186 | } |
| 1187 | |
| 1188 | if (asrc6_mask) |
| 1189 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, |
| 1190 | asrc6_value); |
| 1191 | |
| 1192 | /* ASRC 7 */ |
| 1193 | if (filter_mask & RT5677_DSP_OB_0_3_FILTER) { |
| 1194 | asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK; |
| 1195 | asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK) |
| 1196 | | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT); |
| 1197 | } |
| 1198 | |
| 1199 | if (filter_mask & RT5677_DSP_OB_4_7_FILTER) { |
| 1200 | asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK; |
| 1201 | asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK) |
| 1202 | | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT); |
| 1203 | } |
| 1204 | |
| 1205 | if (asrc7_mask) |
| 1206 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, |
| 1207 | asrc7_value); |
| 1208 | |
Bard Liao | 16ab6e1 | 2015-04-28 11:27:40 +0800 | [diff] [blame] | 1209 | /* ASRC 8 */ |
| 1210 | if (filter_mask & RT5677_I2S1_SOURCE) { |
| 1211 | asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK; |
| 1212 | asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK) |
| 1213 | | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); |
| 1214 | } |
| 1215 | |
| 1216 | if (filter_mask & RT5677_I2S2_SOURCE) { |
| 1217 | asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK; |
| 1218 | asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK) |
| 1219 | | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); |
| 1220 | } |
| 1221 | |
| 1222 | if (filter_mask & RT5677_I2S3_SOURCE) { |
| 1223 | asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK; |
| 1224 | asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK) |
| 1225 | | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); |
| 1226 | } |
| 1227 | |
| 1228 | if (filter_mask & RT5677_I2S4_SOURCE) { |
| 1229 | asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK; |
| 1230 | asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK) |
| 1231 | | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); |
| 1232 | } |
| 1233 | |
| 1234 | if (asrc8_mask) |
| 1235 | regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, |
| 1236 | asrc8_value); |
| 1237 | |
Oder Chiou | c36aa0a | 2015-03-16 14:39:57 +0800 | [diff] [blame] | 1238 | return 0; |
| 1239 | } |
| 1240 | EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src); |
| 1241 | |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1242 | static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source, |
| 1243 | struct snd_soc_dapm_widget *sink) |
| 1244 | { |
| 1245 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
| 1246 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 1247 | unsigned int asrc_setting; |
| 1248 | |
| 1249 | switch (source->shift) { |
| 1250 | case 11: |
| 1251 | regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); |
| 1252 | asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >> |
| 1253 | RT5677_AD_STO1_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1254 | break; |
| 1255 | |
| 1256 | case 10: |
| 1257 | regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); |
| 1258 | asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >> |
| 1259 | RT5677_AD_STO2_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1260 | break; |
| 1261 | |
| 1262 | case 9: |
| 1263 | regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); |
| 1264 | asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >> |
| 1265 | RT5677_AD_STO3_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1266 | break; |
| 1267 | |
| 1268 | case 8: |
| 1269 | regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); |
| 1270 | asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >> |
| 1271 | RT5677_AD_STO4_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1272 | break; |
| 1273 | |
| 1274 | case 7: |
| 1275 | regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); |
| 1276 | asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >> |
| 1277 | RT5677_AD_MONOL_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1278 | break; |
| 1279 | |
| 1280 | case 6: |
| 1281 | regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); |
| 1282 | asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >> |
| 1283 | RT5677_AD_MONOR_CLK_SEL_SFT; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1284 | break; |
| 1285 | |
| 1286 | default: |
Axel Lin | 2dfadff | 2016-03-30 18:25:07 +0800 | [diff] [blame] | 1287 | return 0; |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1288 | } |
| 1289 | |
Axel Lin | 2dfadff | 2016-03-30 18:25:07 +0800 | [diff] [blame] | 1290 | if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC && |
| 1291 | asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC) |
| 1292 | return 1; |
| 1293 | |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 1294 | return 0; |
| 1295 | } |
| 1296 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1297 | /* Digital Mixer */ |
| 1298 | static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = { |
| 1299 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, |
| 1300 | RT5677_M_STO1_ADC_L1_SFT, 1, 1), |
| 1301 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, |
| 1302 | RT5677_M_STO1_ADC_L2_SFT, 1, 1), |
| 1303 | }; |
| 1304 | |
| 1305 | static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = { |
| 1306 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER, |
| 1307 | RT5677_M_STO1_ADC_R1_SFT, 1, 1), |
| 1308 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER, |
| 1309 | RT5677_M_STO1_ADC_R2_SFT, 1, 1), |
| 1310 | }; |
| 1311 | |
| 1312 | static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = { |
| 1313 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, |
| 1314 | RT5677_M_STO2_ADC_L1_SFT, 1, 1), |
| 1315 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, |
| 1316 | RT5677_M_STO2_ADC_L2_SFT, 1, 1), |
| 1317 | }; |
| 1318 | |
| 1319 | static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = { |
| 1320 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER, |
| 1321 | RT5677_M_STO2_ADC_R1_SFT, 1, 1), |
| 1322 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER, |
| 1323 | RT5677_M_STO2_ADC_R2_SFT, 1, 1), |
| 1324 | }; |
| 1325 | |
| 1326 | static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = { |
| 1327 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, |
| 1328 | RT5677_M_STO3_ADC_L1_SFT, 1, 1), |
| 1329 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, |
| 1330 | RT5677_M_STO3_ADC_L2_SFT, 1, 1), |
| 1331 | }; |
| 1332 | |
| 1333 | static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = { |
| 1334 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER, |
| 1335 | RT5677_M_STO3_ADC_R1_SFT, 1, 1), |
| 1336 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER, |
| 1337 | RT5677_M_STO3_ADC_R2_SFT, 1, 1), |
| 1338 | }; |
| 1339 | |
| 1340 | static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = { |
| 1341 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, |
| 1342 | RT5677_M_STO4_ADC_L1_SFT, 1, 1), |
| 1343 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, |
| 1344 | RT5677_M_STO4_ADC_L2_SFT, 1, 1), |
| 1345 | }; |
| 1346 | |
| 1347 | static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = { |
| 1348 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER, |
| 1349 | RT5677_M_STO4_ADC_R1_SFT, 1, 1), |
| 1350 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER, |
| 1351 | RT5677_M_STO4_ADC_R2_SFT, 1, 1), |
| 1352 | }; |
| 1353 | |
| 1354 | static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = { |
| 1355 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, |
| 1356 | RT5677_M_MONO_ADC_L1_SFT, 1, 1), |
| 1357 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, |
| 1358 | RT5677_M_MONO_ADC_L2_SFT, 1, 1), |
| 1359 | }; |
| 1360 | |
| 1361 | static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = { |
| 1362 | SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER, |
| 1363 | RT5677_M_MONO_ADC_R1_SFT, 1, 1), |
| 1364 | SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER, |
| 1365 | RT5677_M_MONO_ADC_R2_SFT, 1, 1), |
| 1366 | }; |
| 1367 | |
| 1368 | static const struct snd_kcontrol_new rt5677_dac_l_mix[] = { |
| 1369 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1370 | RT5677_M_ADDA_MIXER1_L_SFT, 1, 1), |
| 1371 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1372 | RT5677_M_DAC1_L_SFT, 1, 1), |
| 1373 | }; |
| 1374 | |
| 1375 | static const struct snd_kcontrol_new rt5677_dac_r_mix[] = { |
| 1376 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1377 | RT5677_M_ADDA_MIXER1_R_SFT, 1, 1), |
| 1378 | SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1379 | RT5677_M_DAC1_R_SFT, 1, 1), |
| 1380 | }; |
| 1381 | |
| 1382 | static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1383 | SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1384 | RT5677_M_ST_DAC1_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1385 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1386 | RT5677_M_DAC1_L_STO_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1387 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1388 | RT5677_M_DAC2_L_STO_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1389 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1390 | RT5677_M_DAC1_R_STO_L_SFT, 1, 1), |
| 1391 | }; |
| 1392 | |
| 1393 | static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1394 | SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1395 | RT5677_M_ST_DAC1_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1396 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1397 | RT5677_M_DAC1_R_STO_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1398 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1399 | RT5677_M_DAC2_R_STO_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1400 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1401 | RT5677_M_DAC1_L_STO_R_SFT, 1, 1), |
| 1402 | }; |
| 1403 | |
| 1404 | static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1405 | SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1406 | RT5677_M_ST_DAC2_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1407 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1408 | RT5677_M_DAC1_L_MONO_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1409 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1410 | RT5677_M_DAC2_L_MONO_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1411 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1412 | RT5677_M_DAC2_R_MONO_L_SFT, 1, 1), |
| 1413 | }; |
| 1414 | |
| 1415 | static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1416 | SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1417 | RT5677_M_ST_DAC2_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1418 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1419 | RT5677_M_DAC1_R_MONO_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1420 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1421 | RT5677_M_DAC2_R_MONO_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1422 | SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1423 | RT5677_M_DAC2_L_MONO_R_SFT, 1, 1), |
| 1424 | }; |
| 1425 | |
| 1426 | static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1427 | SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1428 | RT5677_M_STO_L_DD1_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1429 | SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1430 | RT5677_M_MONO_L_DD1_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1431 | SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1432 | RT5677_M_DAC3_L_DD1_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1433 | SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1434 | RT5677_M_DAC3_R_DD1_L_SFT, 1, 1), |
| 1435 | }; |
| 1436 | |
| 1437 | static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1438 | SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1439 | RT5677_M_STO_R_DD1_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1440 | SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1441 | RT5677_M_MONO_R_DD1_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1442 | SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1443 | RT5677_M_DAC3_R_DD1_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1444 | SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1445 | RT5677_M_DAC3_L_DD1_R_SFT, 1, 1), |
| 1446 | }; |
| 1447 | |
| 1448 | static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1449 | SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1450 | RT5677_M_STO_L_DD2_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1451 | SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1452 | RT5677_M_MONO_L_DD2_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1453 | SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1454 | RT5677_M_DAC4_L_DD2_L_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1455 | SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1456 | RT5677_M_DAC4_R_DD2_L_SFT, 1, 1), |
| 1457 | }; |
| 1458 | |
| 1459 | static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = { |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1460 | SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1461 | RT5677_M_STO_R_DD2_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1462 | SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1463 | RT5677_M_MONO_R_DD2_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1464 | SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1465 | RT5677_M_DAC4_R_DD2_R_SFT, 1, 1), |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 1466 | SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1467 | RT5677_M_DAC4_L_DD2_R_SFT, 1, 1), |
| 1468 | }; |
| 1469 | |
| 1470 | static const struct snd_kcontrol_new rt5677_ob_01_mix[] = { |
| 1471 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1472 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1473 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1474 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1475 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1476 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1477 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1478 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1479 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1480 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1481 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1482 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1483 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1484 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1485 | }; |
| 1486 | |
| 1487 | static const struct snd_kcontrol_new rt5677_ob_23_mix[] = { |
| 1488 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1489 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1490 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1491 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1492 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1493 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1494 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1495 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1496 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1497 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1498 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1499 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1500 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL, |
| 1501 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1502 | }; |
| 1503 | |
| 1504 | static const struct snd_kcontrol_new rt5677_ob_4_mix[] = { |
| 1505 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1506 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1507 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1508 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1509 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1510 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1511 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1512 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1513 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1514 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1515 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1516 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1517 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1518 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1519 | }; |
| 1520 | |
| 1521 | static const struct snd_kcontrol_new rt5677_ob_5_mix[] = { |
| 1522 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1523 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1524 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1525 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1526 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1527 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1528 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1529 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1530 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1531 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1532 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1533 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1534 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL, |
| 1535 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1536 | }; |
| 1537 | |
| 1538 | static const struct snd_kcontrol_new rt5677_ob_6_mix[] = { |
| 1539 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1540 | RT5677_DSP_IB_01_H_SFT, 1, 1), |
| 1541 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1542 | RT5677_DSP_IB_23_H_SFT, 1, 1), |
| 1543 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1544 | RT5677_DSP_IB_45_H_SFT, 1, 1), |
| 1545 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1546 | RT5677_DSP_IB_6_H_SFT, 1, 1), |
| 1547 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1548 | RT5677_DSP_IB_7_H_SFT, 1, 1), |
| 1549 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1550 | RT5677_DSP_IB_8_H_SFT, 1, 1), |
| 1551 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1552 | RT5677_DSP_IB_9_H_SFT, 1, 1), |
| 1553 | }; |
| 1554 | |
| 1555 | static const struct snd_kcontrol_new rt5677_ob_7_mix[] = { |
| 1556 | SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1557 | RT5677_DSP_IB_01_L_SFT, 1, 1), |
| 1558 | SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1559 | RT5677_DSP_IB_23_L_SFT, 1, 1), |
| 1560 | SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1561 | RT5677_DSP_IB_45_L_SFT, 1, 1), |
| 1562 | SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1563 | RT5677_DSP_IB_6_L_SFT, 1, 1), |
| 1564 | SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1565 | RT5677_DSP_IB_7_L_SFT, 1, 1), |
| 1566 | SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1567 | RT5677_DSP_IB_8_L_SFT, 1, 1), |
| 1568 | SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL, |
| 1569 | RT5677_DSP_IB_9_L_SFT, 1, 1), |
| 1570 | }; |
| 1571 | |
| 1572 | |
| 1573 | /* Mux */ |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1574 | /* DAC1 L/R Source */ /* MX-29 [10:8] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1575 | static const char * const rt5677_dac1_src[] = { |
| 1576 | "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01", |
| 1577 | "OB 01" |
| 1578 | }; |
| 1579 | |
| 1580 | static SOC_ENUM_SINGLE_DECL( |
| 1581 | rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1582 | RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src); |
| 1583 | |
| 1584 | static const struct snd_kcontrol_new rt5677_dac1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1585 | SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1586 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1587 | /* ADDA1 L/R Source */ /* MX-29 [1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1588 | static const char * const rt5677_adda1_src[] = { |
| 1589 | "STO1 ADC MIX", "STO2 ADC MIX", "OB 67", |
| 1590 | }; |
| 1591 | |
| 1592 | static SOC_ENUM_SINGLE_DECL( |
| 1593 | rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER, |
| 1594 | RT5677_ADDA1_SEL_SFT, rt5677_adda1_src); |
| 1595 | |
| 1596 | static const struct snd_kcontrol_new rt5677_adda1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1597 | SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1598 | |
| 1599 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1600 | /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1601 | static const char * const rt5677_dac2l_src[] = { |
| 1602 | "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2", |
| 1603 | "OB 2", |
| 1604 | }; |
| 1605 | |
| 1606 | static SOC_ENUM_SINGLE_DECL( |
| 1607 | rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER, |
| 1608 | RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src); |
| 1609 | |
| 1610 | static const struct snd_kcontrol_new rt5677_dac2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1611 | SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1612 | |
| 1613 | static const char * const rt5677_dac2r_src[] = { |
| 1614 | "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3", |
| 1615 | "OB 3", "Haptic Generator", "VAD ADC" |
| 1616 | }; |
| 1617 | |
| 1618 | static SOC_ENUM_SINGLE_DECL( |
| 1619 | rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER, |
| 1620 | RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src); |
| 1621 | |
| 1622 | static const struct snd_kcontrol_new rt5677_dac2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1623 | SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1624 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1625 | /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1626 | static const char * const rt5677_dac3l_src[] = { |
| 1627 | "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L", |
| 1628 | "SLB DAC 4", "OB 4" |
| 1629 | }; |
| 1630 | |
| 1631 | static SOC_ENUM_SINGLE_DECL( |
| 1632 | rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1633 | RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src); |
| 1634 | |
| 1635 | static const struct snd_kcontrol_new rt5677_dac3_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1636 | SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1637 | |
| 1638 | static const char * const rt5677_dac3r_src[] = { |
| 1639 | "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R", |
| 1640 | "SLB DAC 5", "OB 5" |
| 1641 | }; |
| 1642 | |
| 1643 | static SOC_ENUM_SINGLE_DECL( |
| 1644 | rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1645 | RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src); |
| 1646 | |
| 1647 | static const struct snd_kcontrol_new rt5677_dac3_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1648 | SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1649 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1650 | /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1651 | static const char * const rt5677_dac4l_src[] = { |
| 1652 | "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L", |
| 1653 | "SLB DAC 6", "OB 6" |
| 1654 | }; |
| 1655 | |
| 1656 | static SOC_ENUM_SINGLE_DECL( |
| 1657 | rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1658 | RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src); |
| 1659 | |
| 1660 | static const struct snd_kcontrol_new rt5677_dac4_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1661 | SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1662 | |
| 1663 | static const char * const rt5677_dac4r_src[] = { |
| 1664 | "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R", |
| 1665 | "SLB DAC 7", "OB 7" |
| 1666 | }; |
| 1667 | |
| 1668 | static SOC_ENUM_SINGLE_DECL( |
| 1669 | rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER, |
| 1670 | RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src); |
| 1671 | |
| 1672 | static const struct snd_kcontrol_new rt5677_dac4_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1673 | SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1674 | |
| 1675 | /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */ |
| 1676 | static const char * const rt5677_iob_bypass_src[] = { |
| 1677 | "Bypass", "Pass SRC" |
| 1678 | }; |
| 1679 | |
| 1680 | static SOC_ENUM_SINGLE_DECL( |
| 1681 | rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1682 | RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src); |
| 1683 | |
| 1684 | static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1685 | SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1686 | |
| 1687 | static SOC_ENUM_SINGLE_DECL( |
| 1688 | rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1689 | RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src); |
| 1690 | |
| 1691 | static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1692 | SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1693 | |
| 1694 | static SOC_ENUM_SINGLE_DECL( |
| 1695 | rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1696 | RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src); |
| 1697 | |
| 1698 | static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1699 | SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1700 | |
| 1701 | static SOC_ENUM_SINGLE_DECL( |
| 1702 | rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1703 | RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src); |
| 1704 | |
| 1705 | static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1706 | SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1707 | |
| 1708 | static SOC_ENUM_SINGLE_DECL( |
| 1709 | rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL, |
| 1710 | RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src); |
| 1711 | |
| 1712 | static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1713 | SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1714 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1715 | /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1716 | static const char * const rt5677_stereo_adc2_src[] = { |
| 1717 | "DD MIX1", "DMIC", "Stereo DAC MIX" |
| 1718 | }; |
| 1719 | |
| 1720 | static SOC_ENUM_SINGLE_DECL( |
| 1721 | rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER, |
| 1722 | RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1723 | |
| 1724 | static const struct snd_kcontrol_new rt5677_sto1_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1725 | SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1726 | |
| 1727 | static SOC_ENUM_SINGLE_DECL( |
| 1728 | rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER, |
| 1729 | RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1730 | |
| 1731 | static const struct snd_kcontrol_new rt5677_sto2_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1732 | SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1733 | |
| 1734 | static SOC_ENUM_SINGLE_DECL( |
| 1735 | rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER, |
| 1736 | RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src); |
| 1737 | |
| 1738 | static const struct snd_kcontrol_new rt5677_sto3_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1739 | SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1740 | |
| 1741 | /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */ |
| 1742 | static const char * const rt5677_dmic_src[] = { |
| 1743 | "DMIC1", "DMIC2", "DMIC3", "DMIC4" |
| 1744 | }; |
| 1745 | |
| 1746 | static SOC_ENUM_SINGLE_DECL( |
| 1747 | rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER, |
| 1748 | RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src); |
| 1749 | |
| 1750 | static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1751 | SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1752 | |
| 1753 | static SOC_ENUM_SINGLE_DECL( |
| 1754 | rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER, |
| 1755 | RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src); |
| 1756 | |
| 1757 | static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1758 | SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1759 | |
| 1760 | static SOC_ENUM_SINGLE_DECL( |
| 1761 | rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER, |
| 1762 | RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src); |
| 1763 | |
| 1764 | static const struct snd_kcontrol_new rt5677_sto1_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1765 | SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1766 | |
| 1767 | static SOC_ENUM_SINGLE_DECL( |
| 1768 | rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER, |
| 1769 | RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src); |
| 1770 | |
| 1771 | static const struct snd_kcontrol_new rt5677_sto2_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1772 | SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1773 | |
| 1774 | static SOC_ENUM_SINGLE_DECL( |
| 1775 | rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER, |
| 1776 | RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src); |
| 1777 | |
| 1778 | static const struct snd_kcontrol_new rt5677_sto3_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1779 | SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1780 | |
| 1781 | static SOC_ENUM_SINGLE_DECL( |
| 1782 | rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER, |
| 1783 | RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src); |
| 1784 | |
| 1785 | static const struct snd_kcontrol_new rt5677_sto4_dmic_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1786 | SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1787 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1788 | /* Stereo2 ADC Source */ /* MX-26 [0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1789 | static const char * const rt5677_stereo2_adc_lr_src[] = { |
| 1790 | "L", "LR" |
| 1791 | }; |
| 1792 | |
| 1793 | static SOC_ENUM_SINGLE_DECL( |
| 1794 | rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER, |
| 1795 | RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src); |
| 1796 | |
| 1797 | static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1798 | SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1799 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 1800 | /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1801 | static const char * const rt5677_stereo_adc1_src[] = { |
| 1802 | "DD MIX1", "ADC1/2", "Stereo DAC MIX" |
| 1803 | }; |
| 1804 | |
| 1805 | static SOC_ENUM_SINGLE_DECL( |
| 1806 | rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER, |
| 1807 | RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1808 | |
| 1809 | static const struct snd_kcontrol_new rt5677_sto1_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1810 | SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1811 | |
| 1812 | static SOC_ENUM_SINGLE_DECL( |
| 1813 | rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER, |
| 1814 | RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1815 | |
| 1816 | static const struct snd_kcontrol_new rt5677_sto2_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1817 | SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1818 | |
| 1819 | static SOC_ENUM_SINGLE_DECL( |
| 1820 | rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER, |
| 1821 | RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src); |
| 1822 | |
| 1823 | static const struct snd_kcontrol_new rt5677_sto3_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1824 | SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1825 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1826 | /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1827 | static const char * const rt5677_mono_adc2_l_src[] = { |
| 1828 | "DD MIX1L", "DMIC", "MONO DAC MIXL" |
| 1829 | }; |
| 1830 | |
| 1831 | static SOC_ENUM_SINGLE_DECL( |
| 1832 | rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER, |
| 1833 | RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src); |
| 1834 | |
| 1835 | static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1836 | SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1837 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1838 | /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1839 | static const char * const rt5677_mono_adc1_l_src[] = { |
| 1840 | "DD MIX1L", "ADC1", "MONO DAC MIXL" |
| 1841 | }; |
| 1842 | |
| 1843 | static SOC_ENUM_SINGLE_DECL( |
| 1844 | rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER, |
| 1845 | RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src); |
| 1846 | |
| 1847 | static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1848 | SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1849 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1850 | /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1851 | static const char * const rt5677_mono_adc2_r_src[] = { |
| 1852 | "DD MIX1R", "DMIC", "MONO DAC MIXR" |
| 1853 | }; |
| 1854 | |
| 1855 | static SOC_ENUM_SINGLE_DECL( |
| 1856 | rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER, |
| 1857 | RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src); |
| 1858 | |
| 1859 | static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1860 | SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1861 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1862 | /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1863 | static const char * const rt5677_mono_adc1_r_src[] = { |
| 1864 | "DD MIX1R", "ADC2", "MONO DAC MIXR" |
| 1865 | }; |
| 1866 | |
| 1867 | static SOC_ENUM_SINGLE_DECL( |
| 1868 | rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER, |
| 1869 | RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src); |
| 1870 | |
| 1871 | static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1872 | SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1873 | |
| 1874 | /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */ |
| 1875 | static const char * const rt5677_stereo4_adc2_src[] = { |
| 1876 | "DD MIX1", "DMIC", "DD MIX2" |
| 1877 | }; |
| 1878 | |
| 1879 | static SOC_ENUM_SINGLE_DECL( |
| 1880 | rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER, |
| 1881 | RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src); |
| 1882 | |
| 1883 | static const struct snd_kcontrol_new rt5677_sto4_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1884 | SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1885 | |
| 1886 | |
| 1887 | /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */ |
| 1888 | static const char * const rt5677_stereo4_adc1_src[] = { |
| 1889 | "DD MIX1", "ADC1/2", "DD MIX2" |
| 1890 | }; |
| 1891 | |
| 1892 | static SOC_ENUM_SINGLE_DECL( |
| 1893 | rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER, |
| 1894 | RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src); |
| 1895 | |
| 1896 | static const struct snd_kcontrol_new rt5677_sto4_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 1897 | SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 1898 | |
| 1899 | /* InBound0/1 Source */ /* MX-A3 [14:12] */ |
| 1900 | static const char * const rt5677_inbound01_src[] = { |
| 1901 | "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX", |
| 1902 | "VAD ADC/DAC1 FS" |
| 1903 | }; |
| 1904 | |
| 1905 | static SOC_ENUM_SINGLE_DECL( |
| 1906 | rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1, |
| 1907 | RT5677_IB01_SRC_SFT, rt5677_inbound01_src); |
| 1908 | |
| 1909 | static const struct snd_kcontrol_new rt5677_ib01_src_mux = |
| 1910 | SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum); |
| 1911 | |
| 1912 | /* InBound2/3 Source */ /* MX-A3 [10:8] */ |
| 1913 | static const char * const rt5677_inbound23_src[] = { |
| 1914 | "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX", |
| 1915 | "DAC1 FS", "IF4 DAC" |
| 1916 | }; |
| 1917 | |
| 1918 | static SOC_ENUM_SINGLE_DECL( |
| 1919 | rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1, |
| 1920 | RT5677_IB23_SRC_SFT, rt5677_inbound23_src); |
| 1921 | |
| 1922 | static const struct snd_kcontrol_new rt5677_ib23_src_mux = |
| 1923 | SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum); |
| 1924 | |
| 1925 | /* InBound4/5 Source */ /* MX-A3 [6:4] */ |
| 1926 | static const char * const rt5677_inbound45_src[] = { |
| 1927 | "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX", |
| 1928 | "IF3 DAC" |
| 1929 | }; |
| 1930 | |
| 1931 | static SOC_ENUM_SINGLE_DECL( |
| 1932 | rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1, |
| 1933 | RT5677_IB45_SRC_SFT, rt5677_inbound45_src); |
| 1934 | |
| 1935 | static const struct snd_kcontrol_new rt5677_ib45_src_mux = |
| 1936 | SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum); |
| 1937 | |
| 1938 | /* InBound6 Source */ /* MX-A3 [2:0] */ |
| 1939 | static const char * const rt5677_inbound6_src[] = { |
| 1940 | "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L", |
| 1941 | "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L" |
| 1942 | }; |
| 1943 | |
| 1944 | static SOC_ENUM_SINGLE_DECL( |
| 1945 | rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1, |
| 1946 | RT5677_IB6_SRC_SFT, rt5677_inbound6_src); |
| 1947 | |
| 1948 | static const struct snd_kcontrol_new rt5677_ib6_src_mux = |
| 1949 | SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum); |
| 1950 | |
| 1951 | /* InBound7 Source */ /* MX-A4 [14:12] */ |
| 1952 | static const char * const rt5677_inbound7_src[] = { |
| 1953 | "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R", |
| 1954 | "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R" |
| 1955 | }; |
| 1956 | |
| 1957 | static SOC_ENUM_SINGLE_DECL( |
| 1958 | rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2, |
| 1959 | RT5677_IB7_SRC_SFT, rt5677_inbound7_src); |
| 1960 | |
| 1961 | static const struct snd_kcontrol_new rt5677_ib7_src_mux = |
| 1962 | SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum); |
| 1963 | |
| 1964 | /* InBound8 Source */ /* MX-A4 [10:8] */ |
| 1965 | static const char * const rt5677_inbound8_src[] = { |
| 1966 | "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L", |
| 1967 | "MONO ADC MIX L", "DACL1 FS" |
| 1968 | }; |
| 1969 | |
| 1970 | static SOC_ENUM_SINGLE_DECL( |
| 1971 | rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2, |
| 1972 | RT5677_IB8_SRC_SFT, rt5677_inbound8_src); |
| 1973 | |
| 1974 | static const struct snd_kcontrol_new rt5677_ib8_src_mux = |
| 1975 | SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum); |
| 1976 | |
| 1977 | /* InBound9 Source */ /* MX-A4 [6:4] */ |
| 1978 | static const char * const rt5677_inbound9_src[] = { |
| 1979 | "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R", |
| 1980 | "MONO ADC MIX R", "DACR1 FS", "DAC1 FS" |
| 1981 | }; |
| 1982 | |
| 1983 | static SOC_ENUM_SINGLE_DECL( |
| 1984 | rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2, |
| 1985 | RT5677_IB9_SRC_SFT, rt5677_inbound9_src); |
| 1986 | |
| 1987 | static const struct snd_kcontrol_new rt5677_ib9_src_mux = |
| 1988 | SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum); |
| 1989 | |
| 1990 | /* VAD Source */ /* MX-9F [6:4] */ |
| 1991 | static const char * const rt5677_vad_src[] = { |
| 1992 | "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L", |
| 1993 | "STO3 ADC MIX L" |
| 1994 | }; |
| 1995 | |
| 1996 | static SOC_ENUM_SINGLE_DECL( |
| 1997 | rt5677_vad_enum, RT5677_VAD_CTRL4, |
| 1998 | RT5677_VAD_SRC_SFT, rt5677_vad_src); |
| 1999 | |
| 2000 | static const struct snd_kcontrol_new rt5677_vad_src_mux = |
| 2001 | SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum); |
| 2002 | |
| 2003 | /* Sidetone Source */ /* MX-13 [11:9] */ |
| 2004 | static const char * const rt5677_sidetone_src[] = { |
| 2005 | "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2" |
| 2006 | }; |
| 2007 | |
| 2008 | static SOC_ENUM_SINGLE_DECL( |
| 2009 | rt5677_sidetone_enum, RT5677_SIDETONE_CTRL, |
| 2010 | RT5677_ST_SEL_SFT, rt5677_sidetone_src); |
| 2011 | |
| 2012 | static const struct snd_kcontrol_new rt5677_sidetone_mux = |
| 2013 | SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum); |
| 2014 | |
| 2015 | /* DAC1/2 Source */ /* MX-15 [1:0] */ |
| 2016 | static const char * const rt5677_dac12_src[] = { |
| 2017 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" |
| 2018 | }; |
| 2019 | |
| 2020 | static SOC_ENUM_SINGLE_DECL( |
| 2021 | rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC, |
| 2022 | RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src); |
| 2023 | |
| 2024 | static const struct snd_kcontrol_new rt5677_dac12_mux = |
| 2025 | SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum); |
| 2026 | |
| 2027 | /* DAC3 Source */ /* MX-15 [5:4] */ |
| 2028 | static const char * const rt5677_dac3_src[] = { |
| 2029 | "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L" |
| 2030 | }; |
| 2031 | |
| 2032 | static SOC_ENUM_SINGLE_DECL( |
| 2033 | rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC, |
| 2034 | RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src); |
| 2035 | |
| 2036 | static const struct snd_kcontrol_new rt5677_dac3_mux = |
| 2037 | SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum); |
| 2038 | |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2039 | /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2040 | static const char * const rt5677_pdm_src[] = { |
| 2041 | "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2" |
| 2042 | }; |
| 2043 | |
| 2044 | static SOC_ENUM_SINGLE_DECL( |
| 2045 | rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL, |
| 2046 | RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src); |
| 2047 | |
| 2048 | static const struct snd_kcontrol_new rt5677_pdm1_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2049 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2050 | |
| 2051 | static SOC_ENUM_SINGLE_DECL( |
| 2052 | rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL, |
| 2053 | RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src); |
| 2054 | |
| 2055 | static const struct snd_kcontrol_new rt5677_pdm2_l_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2056 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2057 | |
| 2058 | static SOC_ENUM_SINGLE_DECL( |
| 2059 | rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL, |
| 2060 | RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src); |
| 2061 | |
| 2062 | static const struct snd_kcontrol_new rt5677_pdm1_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2063 | SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2064 | |
| 2065 | static SOC_ENUM_SINGLE_DECL( |
| 2066 | rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL, |
| 2067 | RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src); |
| 2068 | |
| 2069 | static const struct snd_kcontrol_new rt5677_pdm2_r_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2070 | SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2071 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 2072 | /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2073 | static const char * const rt5677_if12_adc1_src[] = { |
| 2074 | "STO1 ADC MIX", "OB01", "VAD ADC" |
| 2075 | }; |
| 2076 | |
| 2077 | static SOC_ENUM_SINGLE_DECL( |
| 2078 | rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2, |
| 2079 | RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src); |
| 2080 | |
| 2081 | static const struct snd_kcontrol_new rt5677_if1_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2082 | SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2083 | |
| 2084 | static SOC_ENUM_SINGLE_DECL( |
| 2085 | rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2, |
| 2086 | RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src); |
| 2087 | |
| 2088 | static const struct snd_kcontrol_new rt5677_if2_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2089 | SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2090 | |
| 2091 | static SOC_ENUM_SINGLE_DECL( |
| 2092 | rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX, |
| 2093 | RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src); |
| 2094 | |
| 2095 | static const struct snd_kcontrol_new rt5677_slb_adc1_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2096 | SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2097 | |
| 2098 | /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */ |
| 2099 | static const char * const rt5677_if12_adc2_src[] = { |
| 2100 | "STO2 ADC MIX", "OB23" |
| 2101 | }; |
| 2102 | |
| 2103 | static SOC_ENUM_SINGLE_DECL( |
| 2104 | rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2, |
| 2105 | RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src); |
| 2106 | |
| 2107 | static const struct snd_kcontrol_new rt5677_if1_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2108 | SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2109 | |
| 2110 | static SOC_ENUM_SINGLE_DECL( |
| 2111 | rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2, |
| 2112 | RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src); |
| 2113 | |
| 2114 | static const struct snd_kcontrol_new rt5677_if2_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2115 | SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2116 | |
| 2117 | static SOC_ENUM_SINGLE_DECL( |
| 2118 | rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX, |
| 2119 | RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src); |
| 2120 | |
| 2121 | static const struct snd_kcontrol_new rt5677_slb_adc2_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2122 | SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2123 | |
| 2124 | /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */ |
| 2125 | static const char * const rt5677_if12_adc3_src[] = { |
| 2126 | "STO3 ADC MIX", "MONO ADC MIX", "OB45" |
| 2127 | }; |
| 2128 | |
| 2129 | static SOC_ENUM_SINGLE_DECL( |
| 2130 | rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2, |
| 2131 | RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src); |
| 2132 | |
| 2133 | static const struct snd_kcontrol_new rt5677_if1_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2134 | SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2135 | |
| 2136 | static SOC_ENUM_SINGLE_DECL( |
| 2137 | rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2, |
| 2138 | RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src); |
| 2139 | |
| 2140 | static const struct snd_kcontrol_new rt5677_if2_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2141 | SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2142 | |
| 2143 | static SOC_ENUM_SINGLE_DECL( |
| 2144 | rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX, |
| 2145 | RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src); |
| 2146 | |
| 2147 | static const struct snd_kcontrol_new rt5677_slb_adc3_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2148 | SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2149 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 2150 | /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2151 | static const char * const rt5677_if12_adc4_src[] = { |
| 2152 | "STO4 ADC MIX", "OB67", "OB01" |
| 2153 | }; |
| 2154 | |
| 2155 | static SOC_ENUM_SINGLE_DECL( |
| 2156 | rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2, |
| 2157 | RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src); |
| 2158 | |
| 2159 | static const struct snd_kcontrol_new rt5677_if1_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2160 | SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2161 | |
| 2162 | static SOC_ENUM_SINGLE_DECL( |
| 2163 | rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2, |
| 2164 | RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src); |
| 2165 | |
| 2166 | static const struct snd_kcontrol_new rt5677_if2_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2167 | SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2168 | |
| 2169 | static SOC_ENUM_SINGLE_DECL( |
| 2170 | rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX, |
| 2171 | RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src); |
| 2172 | |
| 2173 | static const struct snd_kcontrol_new rt5677_slb_adc4_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2174 | SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2175 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 2176 | /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2177 | static const char * const rt5677_if34_adc_src[] = { |
| 2178 | "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX", |
| 2179 | "MONO ADC MIX", "OB01", "OB23", "VAD ADC" |
| 2180 | }; |
| 2181 | |
| 2182 | static SOC_ENUM_SINGLE_DECL( |
| 2183 | rt5677_if3_adc_enum, RT5677_IF3_DATA, |
| 2184 | RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src); |
| 2185 | |
| 2186 | static const struct snd_kcontrol_new rt5677_if3_adc_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2187 | SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2188 | |
| 2189 | static SOC_ENUM_SINGLE_DECL( |
| 2190 | rt5677_if4_adc_enum, RT5677_IF4_DATA, |
| 2191 | RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src); |
| 2192 | |
| 2193 | static const struct snd_kcontrol_new rt5677_if4_adc_mux = |
Oder Chiou | 1b7fd76 | 2014-06-10 14:35:24 +0800 | [diff] [blame] | 2194 | SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2195 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2196 | /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */ |
| 2197 | static const char * const rt5677_if12_adc_swap_src[] = { |
| 2198 | "L/R", "R/L", "L/L", "R/R" |
| 2199 | }; |
| 2200 | |
| 2201 | static SOC_ENUM_SINGLE_DECL( |
| 2202 | rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1, |
| 2203 | RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2204 | |
| 2205 | static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux = |
| 2206 | SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum); |
| 2207 | |
| 2208 | static SOC_ENUM_SINGLE_DECL( |
| 2209 | rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1, |
| 2210 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2211 | |
| 2212 | static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux = |
| 2213 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum); |
| 2214 | |
| 2215 | static SOC_ENUM_SINGLE_DECL( |
| 2216 | rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1, |
| 2217 | RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2218 | |
| 2219 | static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux = |
| 2220 | SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum); |
| 2221 | |
| 2222 | static SOC_ENUM_SINGLE_DECL( |
| 2223 | rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1, |
| 2224 | RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2225 | |
| 2226 | static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux = |
| 2227 | SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum); |
| 2228 | |
| 2229 | static SOC_ENUM_SINGLE_DECL( |
| 2230 | rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1, |
| 2231 | RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2232 | |
| 2233 | static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux = |
| 2234 | SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum); |
| 2235 | |
| 2236 | static SOC_ENUM_SINGLE_DECL( |
| 2237 | rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1, |
| 2238 | RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2239 | |
| 2240 | static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux = |
| 2241 | SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum); |
| 2242 | |
| 2243 | static SOC_ENUM_SINGLE_DECL( |
| 2244 | rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1, |
| 2245 | RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2246 | |
| 2247 | static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux = |
| 2248 | SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum); |
| 2249 | |
| 2250 | static SOC_ENUM_SINGLE_DECL( |
| 2251 | rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1, |
| 2252 | RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src); |
| 2253 | |
| 2254 | static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux = |
| 2255 | SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum); |
| 2256 | |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 2257 | /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */ |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2258 | static const char * const rt5677_if1_adc_tdm_swap_src[] = { |
| 2259 | "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", |
| 2260 | "3/1/2/4", "3/4/1/2" |
| 2261 | }; |
| 2262 | |
| 2263 | static SOC_ENUM_SINGLE_DECL( |
| 2264 | rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2, |
| 2265 | RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src); |
| 2266 | |
| 2267 | static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux = |
| 2268 | SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum); |
| 2269 | |
| 2270 | /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */ |
| 2271 | static const char * const rt5677_if2_adc_tdm_swap_src[] = { |
| 2272 | "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3", |
| 2273 | "2/3/1/4", "3/4/1/2" |
| 2274 | }; |
| 2275 | |
| 2276 | static SOC_ENUM_SINGLE_DECL( |
| 2277 | rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2, |
| 2278 | RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src); |
| 2279 | |
| 2280 | static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux = |
| 2281 | SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum); |
| 2282 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame] | 2283 | /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0] |
| 2284 | MX-3F[14:12][10:8][6:4][2:0] |
| 2285 | MX-43[14:12][10:8][6:4][2:0] |
| 2286 | MX-44[14:12][10:8][6:4][2:0] */ |
| 2287 | static const char * const rt5677_if12_dac_tdm_sel_src[] = { |
| 2288 | "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7" |
| 2289 | }; |
| 2290 | |
| 2291 | static SOC_ENUM_SINGLE_DECL( |
| 2292 | rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 2293 | RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2294 | |
| 2295 | static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux = |
| 2296 | SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum); |
| 2297 | |
| 2298 | static SOC_ENUM_SINGLE_DECL( |
| 2299 | rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 2300 | RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2301 | |
| 2302 | static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux = |
| 2303 | SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum); |
| 2304 | |
| 2305 | static SOC_ENUM_SINGLE_DECL( |
| 2306 | rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 2307 | RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2308 | |
| 2309 | static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux = |
| 2310 | SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum); |
| 2311 | |
| 2312 | static SOC_ENUM_SINGLE_DECL( |
| 2313 | rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4, |
| 2314 | RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2315 | |
| 2316 | static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux = |
| 2317 | SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum); |
| 2318 | |
| 2319 | static SOC_ENUM_SINGLE_DECL( |
| 2320 | rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 2321 | RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2322 | |
| 2323 | static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux = |
| 2324 | SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum); |
| 2325 | |
| 2326 | static SOC_ENUM_SINGLE_DECL( |
| 2327 | rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 2328 | RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2329 | |
| 2330 | static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux = |
| 2331 | SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum); |
| 2332 | |
| 2333 | static SOC_ENUM_SINGLE_DECL( |
| 2334 | rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 2335 | RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2336 | |
| 2337 | static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux = |
| 2338 | SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum); |
| 2339 | |
| 2340 | static SOC_ENUM_SINGLE_DECL( |
| 2341 | rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5, |
| 2342 | RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2343 | |
| 2344 | static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux = |
| 2345 | SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum); |
| 2346 | |
| 2347 | static SOC_ENUM_SINGLE_DECL( |
| 2348 | rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 2349 | RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2350 | |
| 2351 | static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux = |
| 2352 | SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum); |
| 2353 | |
| 2354 | static SOC_ENUM_SINGLE_DECL( |
| 2355 | rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 2356 | RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2357 | |
| 2358 | static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux = |
| 2359 | SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum); |
| 2360 | |
| 2361 | static SOC_ENUM_SINGLE_DECL( |
| 2362 | rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 2363 | RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2364 | |
| 2365 | static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux = |
| 2366 | SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum); |
| 2367 | |
| 2368 | static SOC_ENUM_SINGLE_DECL( |
| 2369 | rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4, |
| 2370 | RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2371 | |
| 2372 | static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux = |
| 2373 | SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum); |
| 2374 | |
| 2375 | static SOC_ENUM_SINGLE_DECL( |
| 2376 | rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2377 | RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2378 | |
| 2379 | static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux = |
| 2380 | SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum); |
| 2381 | |
| 2382 | static SOC_ENUM_SINGLE_DECL( |
| 2383 | rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2384 | RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2385 | |
| 2386 | static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux = |
| 2387 | SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum); |
| 2388 | |
| 2389 | static SOC_ENUM_SINGLE_DECL( |
| 2390 | rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2391 | RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2392 | |
| 2393 | static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux = |
| 2394 | SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum); |
| 2395 | |
| 2396 | static SOC_ENUM_SINGLE_DECL( |
| 2397 | rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5, |
| 2398 | RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src); |
| 2399 | |
| 2400 | static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux = |
| 2401 | SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum); |
| 2402 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2403 | static int rt5677_bst1_event(struct snd_soc_dapm_widget *w, |
| 2404 | struct snd_kcontrol *kcontrol, int event) |
| 2405 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2406 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2407 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2408 | |
| 2409 | switch (event) { |
| 2410 | case SND_SOC_DAPM_POST_PMU: |
| 2411 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2412 | RT5677_PWR_BST1_P, RT5677_PWR_BST1_P); |
| 2413 | break; |
| 2414 | |
| 2415 | case SND_SOC_DAPM_PRE_PMD: |
| 2416 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2417 | RT5677_PWR_BST1_P, 0); |
| 2418 | break; |
| 2419 | |
| 2420 | default: |
| 2421 | return 0; |
| 2422 | } |
| 2423 | |
| 2424 | return 0; |
| 2425 | } |
| 2426 | |
| 2427 | static int rt5677_bst2_event(struct snd_soc_dapm_widget *w, |
| 2428 | struct snd_kcontrol *kcontrol, int event) |
| 2429 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2430 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2431 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2432 | |
| 2433 | switch (event) { |
| 2434 | case SND_SOC_DAPM_POST_PMU: |
| 2435 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2436 | RT5677_PWR_BST2_P, RT5677_PWR_BST2_P); |
| 2437 | break; |
| 2438 | |
| 2439 | case SND_SOC_DAPM_PRE_PMD: |
| 2440 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2441 | RT5677_PWR_BST2_P, 0); |
| 2442 | break; |
| 2443 | |
| 2444 | default: |
| 2445 | return 0; |
| 2446 | } |
| 2447 | |
| 2448 | return 0; |
| 2449 | } |
| 2450 | |
| 2451 | static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w, |
| 2452 | struct snd_kcontrol *kcontrol, int event) |
| 2453 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2454 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2455 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2456 | |
| 2457 | switch (event) { |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2458 | case SND_SOC_DAPM_PRE_PMU: |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2459 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2460 | break; |
| 2461 | |
| 2462 | case SND_SOC_DAPM_POST_PMU: |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2463 | regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); |
| 2464 | break; |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2465 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2466 | default: |
| 2467 | return 0; |
| 2468 | } |
| 2469 | |
| 2470 | return 0; |
| 2471 | } |
| 2472 | |
| 2473 | static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w, |
| 2474 | struct snd_kcontrol *kcontrol, int event) |
| 2475 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2476 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2477 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2478 | |
| 2479 | switch (event) { |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2480 | case SND_SOC_DAPM_PRE_PMU: |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2481 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2482 | break; |
| 2483 | |
| 2484 | case SND_SOC_DAPM_POST_PMU: |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2485 | regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); |
| 2486 | break; |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2487 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2488 | default: |
| 2489 | return 0; |
| 2490 | } |
| 2491 | |
| 2492 | return 0; |
| 2493 | } |
| 2494 | |
| 2495 | static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w, |
| 2496 | struct snd_kcontrol *kcontrol, int event) |
| 2497 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2498 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2499 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2500 | |
| 2501 | switch (event) { |
| 2502 | case SND_SOC_DAPM_POST_PMU: |
| 2503 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2504 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | |
| 2505 | RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 | |
| 2506 | RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB); |
| 2507 | break; |
Oder Chiou | f58c3b9 | 2014-06-10 14:35:26 +0800 | [diff] [blame] | 2508 | |
| 2509 | case SND_SOC_DAPM_PRE_PMD: |
| 2510 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 2511 | RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 | |
| 2512 | RT5677_PWR_CLK_MB, 0); |
| 2513 | break; |
| 2514 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2515 | default: |
| 2516 | return 0; |
| 2517 | } |
| 2518 | |
| 2519 | return 0; |
| 2520 | } |
| 2521 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2522 | static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w, |
| 2523 | struct snd_kcontrol *kcontrol, int event) |
| 2524 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2525 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2526 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2527 | unsigned int value; |
| 2528 | |
| 2529 | switch (event) { |
| 2530 | case SND_SOC_DAPM_PRE_PMU: |
| 2531 | regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); |
| 2532 | if (value & RT5677_IF1_ADC_CTRL_MASK) |
| 2533 | regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, |
| 2534 | RT5677_IF1_ADC_MODE_MASK, |
| 2535 | RT5677_IF1_ADC_MODE_TDM); |
| 2536 | break; |
| 2537 | |
| 2538 | default: |
| 2539 | return 0; |
| 2540 | } |
| 2541 | |
| 2542 | return 0; |
| 2543 | } |
| 2544 | |
| 2545 | static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w, |
| 2546 | struct snd_kcontrol *kcontrol, int event) |
| 2547 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2548 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2549 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2550 | unsigned int value; |
| 2551 | |
| 2552 | switch (event) { |
| 2553 | case SND_SOC_DAPM_PRE_PMU: |
| 2554 | regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); |
| 2555 | if (value & RT5677_IF2_ADC_CTRL_MASK) |
| 2556 | regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, |
| 2557 | RT5677_IF2_ADC_MODE_MASK, |
| 2558 | RT5677_IF2_ADC_MODE_TDM); |
| 2559 | break; |
| 2560 | |
| 2561 | default: |
| 2562 | return 0; |
| 2563 | } |
| 2564 | |
| 2565 | return 0; |
| 2566 | } |
| 2567 | |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 2568 | static int rt5677_vref_event(struct snd_soc_dapm_widget *w, |
| 2569 | struct snd_kcontrol *kcontrol, int event) |
| 2570 | { |
Lars-Peter Clausen | 46f2087 | 2015-01-15 12:52:16 +0100 | [diff] [blame] | 2571 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 2572 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 2573 | |
| 2574 | switch (event) { |
| 2575 | case SND_SOC_DAPM_POST_PMU: |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 2576 | if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON && |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 2577 | !rt5677->is_vref_slow) { |
| 2578 | mdelay(20); |
| 2579 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 2580 | RT5677_PWR_FV1 | RT5677_PWR_FV2, |
| 2581 | RT5677_PWR_FV1 | RT5677_PWR_FV2); |
| 2582 | rt5677->is_vref_slow = true; |
| 2583 | } |
| 2584 | break; |
| 2585 | |
| 2586 | default: |
| 2587 | return 0; |
| 2588 | } |
| 2589 | |
| 2590 | return 0; |
| 2591 | } |
| 2592 | |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 2593 | static int rt5677_filter_power_event(struct snd_soc_dapm_widget *w, |
| 2594 | struct snd_kcontrol *kcontrol, int event) |
| 2595 | { |
| 2596 | switch (event) { |
| 2597 | case SND_SOC_DAPM_POST_PMU: |
| 2598 | msleep(50); |
| 2599 | break; |
| 2600 | |
| 2601 | default: |
| 2602 | return 0; |
| 2603 | } |
| 2604 | |
| 2605 | return 0; |
| 2606 | } |
| 2607 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2608 | static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = { |
| 2609 | SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT, |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2610 | 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU | |
| 2611 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2612 | SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT, |
Oder Chiou | bdfbf25 | 2015-01-08 10:31:05 +0800 | [diff] [blame] | 2613 | 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU | |
| 2614 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2615 | |
Oder Chiou | 5a8c7c2 | 2014-12-23 10:27:55 +0800 | [diff] [blame] | 2616 | /* ASRC */ |
| 2617 | SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0), |
| 2618 | SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0), |
| 2619 | SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0), |
| 2620 | SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0), |
| 2621 | SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0), |
| 2622 | SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL, |
| 2623 | 0), |
| 2624 | SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL, |
| 2625 | 0), |
| 2626 | SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL, |
| 2627 | 0), |
| 2628 | SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL, |
| 2629 | 0), |
| 2630 | SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL, |
| 2631 | 0), |
| 2632 | SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL, |
| 2633 | 0), |
| 2634 | SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL, |
| 2635 | 0), |
| 2636 | SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL, |
| 2637 | 0), |
| 2638 | SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL, |
| 2639 | 0), |
| 2640 | SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL, |
| 2641 | 0), |
| 2642 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL, |
| 2643 | 0), |
| 2644 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL, |
| 2645 | 0), |
| 2646 | SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0), |
| 2647 | SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0), |
| 2648 | SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0), |
| 2649 | SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0), |
| 2650 | SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL, |
| 2651 | 0), |
| 2652 | SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL, |
| 2653 | 0), |
| 2654 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2655 | /* Input Side */ |
| 2656 | /* micbias */ |
Oder Chiou | 3d0c03d | 2014-06-10 14:35:23 +0800 | [diff] [blame] | 2657 | SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT, |
Oder Chiou | f58c3b9 | 2014-06-10 14:35:26 +0800 | [diff] [blame] | 2658 | 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD | |
| 2659 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2660 | |
| 2661 | /* Input Lines */ |
| 2662 | SND_SOC_DAPM_INPUT("DMIC L1"), |
| 2663 | SND_SOC_DAPM_INPUT("DMIC R1"), |
| 2664 | SND_SOC_DAPM_INPUT("DMIC L2"), |
| 2665 | SND_SOC_DAPM_INPUT("DMIC R2"), |
| 2666 | SND_SOC_DAPM_INPUT("DMIC L3"), |
| 2667 | SND_SOC_DAPM_INPUT("DMIC R3"), |
| 2668 | SND_SOC_DAPM_INPUT("DMIC L4"), |
| 2669 | SND_SOC_DAPM_INPUT("DMIC R4"), |
| 2670 | |
| 2671 | SND_SOC_DAPM_INPUT("IN1P"), |
| 2672 | SND_SOC_DAPM_INPUT("IN1N"), |
| 2673 | SND_SOC_DAPM_INPUT("IN2P"), |
| 2674 | SND_SOC_DAPM_INPUT("IN2N"), |
| 2675 | |
| 2676 | SND_SOC_DAPM_INPUT("Haptic Generator"), |
| 2677 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 2678 | SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2679 | SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2680 | SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2681 | SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2682 | |
| 2683 | SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1, |
| 2684 | RT5677_DMIC_1_EN_SFT, 0, NULL, 0), |
| 2685 | SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1, |
| 2686 | RT5677_DMIC_2_EN_SFT, 0, NULL, 0), |
| 2687 | SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1, |
| 2688 | RT5677_DMIC_3_EN_SFT, 0, NULL, 0), |
| 2689 | SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2, |
| 2690 | RT5677_DMIC_4_EN_SFT, 0, NULL, 0), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2691 | |
| 2692 | SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, |
| 2693 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), |
| 2694 | |
| 2695 | /* Boost */ |
| 2696 | SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2, |
| 2697 | RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event, |
| 2698 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
| 2699 | SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2, |
| 2700 | RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event, |
| 2701 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), |
| 2702 | |
| 2703 | /* ADCs */ |
| 2704 | SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, |
| 2705 | 0, 0), |
| 2706 | SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM, |
| 2707 | 0, 0), |
| 2708 | SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2709 | |
| 2710 | SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1, |
| 2711 | RT5677_PWR_ADC_L_BIT, 0, NULL, 0), |
| 2712 | SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1, |
| 2713 | RT5677_PWR_ADC_R_BIT, 0, NULL, 0), |
| 2714 | SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1, |
| 2715 | RT5677_PWR_ADCFED1_BIT, 0, NULL, 0), |
| 2716 | SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1, |
| 2717 | RT5677_PWR_ADCFED2_BIT, 0, NULL, 0), |
| 2718 | |
| 2719 | /* ADC Mux */ |
| 2720 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2721 | &rt5677_sto1_dmic_mux), |
| 2722 | SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2723 | &rt5677_sto1_adc1_mux), |
| 2724 | SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2725 | &rt5677_sto1_adc2_mux), |
| 2726 | SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2727 | &rt5677_sto2_dmic_mux), |
| 2728 | SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2729 | &rt5677_sto2_adc1_mux), |
| 2730 | SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2731 | &rt5677_sto2_adc2_mux), |
| 2732 | SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0, |
| 2733 | &rt5677_sto2_adc_lr_mux), |
| 2734 | SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2735 | &rt5677_sto3_dmic_mux), |
| 2736 | SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2737 | &rt5677_sto3_adc1_mux), |
| 2738 | SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2739 | &rt5677_sto3_adc2_mux), |
| 2740 | SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0, |
| 2741 | &rt5677_sto4_dmic_mux), |
| 2742 | SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2743 | &rt5677_sto4_adc1_mux), |
| 2744 | SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2745 | &rt5677_sto4_adc2_mux), |
| 2746 | SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, |
| 2747 | &rt5677_mono_dmic_l_mux), |
| 2748 | SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, |
| 2749 | &rt5677_mono_dmic_r_mux), |
| 2750 | SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0, |
| 2751 | &rt5677_mono_adc2_l_mux), |
| 2752 | SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0, |
| 2753 | &rt5677_mono_adc1_l_mux), |
| 2754 | SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0, |
| 2755 | &rt5677_mono_adc1_r_mux), |
| 2756 | SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0, |
| 2757 | &rt5677_mono_adc2_r_mux), |
| 2758 | |
| 2759 | /* ADC Mixer */ |
| 2760 | SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2, |
| 2761 | RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0), |
| 2762 | SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2, |
| 2763 | RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0), |
| 2764 | SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2, |
| 2765 | RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0), |
| 2766 | SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2, |
| 2767 | RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0), |
| 2768 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2769 | rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)), |
| 2770 | SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2771 | rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)), |
| 2772 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2773 | rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)), |
| 2774 | SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2775 | rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)), |
| 2776 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2777 | rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)), |
| 2778 | SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2779 | rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)), |
| 2780 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2781 | rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)), |
| 2782 | SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2783 | rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)), |
| 2784 | SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2, |
| 2785 | RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0), |
| 2786 | SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, |
| 2787 | rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)), |
| 2788 | SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2, |
| 2789 | RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0), |
| 2790 | SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, |
| 2791 | rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)), |
| 2792 | |
| 2793 | /* ADC PGA */ |
| 2794 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2795 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2796 | SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2797 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2798 | SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2799 | SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2800 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2801 | SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2802 | SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2803 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2804 | SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2805 | SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2806 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2807 | SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2808 | SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2809 | SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2810 | |
| 2811 | /* DSP */ |
| 2812 | SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0, |
| 2813 | &rt5677_ib9_src_mux), |
| 2814 | SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0, |
| 2815 | &rt5677_ib8_src_mux), |
| 2816 | SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0, |
| 2817 | &rt5677_ib7_src_mux), |
| 2818 | SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0, |
| 2819 | &rt5677_ib6_src_mux), |
| 2820 | SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0, |
| 2821 | &rt5677_ib45_src_mux), |
| 2822 | SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0, |
| 2823 | &rt5677_ib23_src_mux), |
| 2824 | SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0, |
| 2825 | &rt5677_ib01_src_mux), |
| 2826 | SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2827 | &rt5677_ib45_bypass_src_mux), |
| 2828 | SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2829 | &rt5677_ib23_bypass_src_mux), |
| 2830 | SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2831 | &rt5677_ib01_bypass_src_mux), |
| 2832 | SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2833 | &rt5677_ob23_bypass_src_mux), |
| 2834 | SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0, |
| 2835 | &rt5677_ob01_bypass_src_mux), |
| 2836 | |
| 2837 | SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2838 | SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2839 | |
| 2840 | SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2841 | SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2842 | SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2843 | SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2844 | SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2845 | SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2846 | |
| 2847 | /* Digital Interface */ |
| 2848 | SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1, |
| 2849 | RT5677_PWR_I2S1_BIT, 0, NULL, 0), |
| 2850 | SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2851 | SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2852 | SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2853 | SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2854 | SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2855 | SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2856 | SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2857 | SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2858 | SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2859 | SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2860 | SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2861 | SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2862 | SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2863 | SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2864 | SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2865 | SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2866 | |
| 2867 | SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1, |
| 2868 | RT5677_PWR_I2S2_BIT, 0, NULL, 0), |
| 2869 | SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2870 | SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2871 | SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2872 | SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2873 | SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2874 | SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2875 | SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2876 | SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2877 | SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2878 | SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2879 | SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2880 | SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2881 | SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2882 | SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2883 | SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2884 | SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2885 | |
| 2886 | SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1, |
| 2887 | RT5677_PWR_I2S3_BIT, 0, NULL, 0), |
| 2888 | SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2889 | SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2890 | SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2891 | SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2892 | SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2893 | SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2894 | |
| 2895 | SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1, |
| 2896 | RT5677_PWR_I2S4_BIT, 0, NULL, 0), |
| 2897 | SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2898 | SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2899 | SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2900 | SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2901 | SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2902 | SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2903 | |
| 2904 | SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1, |
| 2905 | RT5677_PWR_SLB_BIT, 0, NULL, 0), |
| 2906 | SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2907 | SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2908 | SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2909 | SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2910 | SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2911 | SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2912 | SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2913 | SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2914 | SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2915 | SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2916 | SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2917 | SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2918 | SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2919 | SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2920 | SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2921 | SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2922 | |
| 2923 | /* Digital Interface Select */ |
| 2924 | SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2925 | &rt5677_if1_adc1_mux), |
| 2926 | SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2927 | &rt5677_if1_adc2_mux), |
| 2928 | SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2929 | &rt5677_if1_adc3_mux), |
| 2930 | SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2931 | &rt5677_if1_adc4_mux), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2932 | SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2933 | &rt5677_if1_adc1_swap_mux), |
| 2934 | SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2935 | &rt5677_if1_adc2_swap_mux), |
| 2936 | SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2937 | &rt5677_if1_adc3_swap_mux), |
| 2938 | SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2939 | &rt5677_if1_adc4_swap_mux), |
| 2940 | SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2941 | &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event, |
| 2942 | SND_SOC_DAPM_PRE_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2943 | SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2944 | &rt5677_if2_adc1_mux), |
| 2945 | SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2946 | &rt5677_if2_adc2_mux), |
| 2947 | SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2948 | &rt5677_if2_adc3_mux), |
| 2949 | SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2950 | &rt5677_if2_adc4_mux), |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 2951 | SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2952 | &rt5677_if2_adc1_swap_mux), |
| 2953 | SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2954 | &rt5677_if2_adc2_swap_mux), |
| 2955 | SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2956 | &rt5677_if2_adc3_swap_mux), |
| 2957 | SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2958 | &rt5677_if2_adc4_swap_mux), |
| 2959 | SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0, |
| 2960 | &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event, |
| 2961 | SND_SOC_DAPM_PRE_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 2962 | SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0, |
| 2963 | &rt5677_if3_adc_mux), |
| 2964 | SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0, |
| 2965 | &rt5677_if4_adc_mux), |
| 2966 | SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2967 | &rt5677_slb_adc1_mux), |
| 2968 | SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2969 | &rt5677_slb_adc2_mux), |
| 2970 | SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2971 | &rt5677_slb_adc3_mux), |
| 2972 | SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2973 | &rt5677_slb_adc4_mux), |
| 2974 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame] | 2975 | SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0, |
| 2976 | &rt5677_if1_dac0_tdm_sel_mux), |
| 2977 | SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2978 | &rt5677_if1_dac1_tdm_sel_mux), |
| 2979 | SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2980 | &rt5677_if1_dac2_tdm_sel_mux), |
| 2981 | SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2982 | &rt5677_if1_dac3_tdm_sel_mux), |
| 2983 | SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0, |
| 2984 | &rt5677_if1_dac4_tdm_sel_mux), |
| 2985 | SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0, |
| 2986 | &rt5677_if1_dac5_tdm_sel_mux), |
| 2987 | SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0, |
| 2988 | &rt5677_if1_dac6_tdm_sel_mux), |
| 2989 | SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0, |
| 2990 | &rt5677_if1_dac7_tdm_sel_mux), |
| 2991 | |
| 2992 | SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0, |
| 2993 | &rt5677_if2_dac0_tdm_sel_mux), |
| 2994 | SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 2995 | &rt5677_if2_dac1_tdm_sel_mux), |
| 2996 | SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0, |
| 2997 | &rt5677_if2_dac2_tdm_sel_mux), |
| 2998 | SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0, |
| 2999 | &rt5677_if2_dac3_tdm_sel_mux), |
| 3000 | SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0, |
| 3001 | &rt5677_if2_dac4_tdm_sel_mux), |
| 3002 | SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0, |
| 3003 | &rt5677_if2_dac5_tdm_sel_mux), |
| 3004 | SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0, |
| 3005 | &rt5677_if2_dac6_tdm_sel_mux), |
| 3006 | SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0, |
| 3007 | &rt5677_if2_dac7_tdm_sel_mux), |
| 3008 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3009 | /* Audio Interface */ |
| 3010 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 3011 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 3012 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 3013 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 3014 | SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 3015 | SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 3016 | SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 3017 | SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 3018 | SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0), |
| 3019 | SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0), |
| 3020 | |
| 3021 | /* Sidetone Mux */ |
| 3022 | SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0, |
| 3023 | &rt5677_sidetone_mux), |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 3024 | SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL, |
| 3025 | RT5677_ST_EN_SFT, 0, NULL, 0), |
| 3026 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3027 | /* VAD Mux*/ |
| 3028 | SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0, |
| 3029 | &rt5677_vad_src_mux), |
| 3030 | |
| 3031 | /* Tensilica DSP */ |
| 3032 | SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3033 | SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0, |
| 3034 | rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)), |
| 3035 | SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0, |
| 3036 | rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)), |
| 3037 | SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0, |
| 3038 | rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)), |
| 3039 | SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0, |
| 3040 | rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)), |
| 3041 | SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0, |
| 3042 | rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)), |
| 3043 | SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0, |
| 3044 | rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)), |
| 3045 | |
| 3046 | /* Output Side */ |
Oder Chiou | d65fd3a | 2014-11-05 13:42:52 +0800 | [diff] [blame] | 3047 | /* DAC mixer before sound effect */ |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3048 | SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, |
| 3049 | rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)), |
| 3050 | SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, |
| 3051 | rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)), |
| 3052 | SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3053 | |
| 3054 | /* DAC Mux */ |
| 3055 | SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0, |
| 3056 | &rt5677_dac1_mux), |
| 3057 | SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0, |
| 3058 | &rt5677_adda1_mux), |
| 3059 | SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0, |
| 3060 | &rt5677_dac12_mux), |
| 3061 | SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0, |
| 3062 | &rt5677_dac3_mux), |
| 3063 | |
| 3064 | /* DAC2 channel Mux */ |
| 3065 | SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0, |
| 3066 | &rt5677_dac2_l_mux), |
| 3067 | SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0, |
| 3068 | &rt5677_dac2_r_mux), |
| 3069 | |
| 3070 | /* DAC3 channel Mux */ |
| 3071 | SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0, |
| 3072 | &rt5677_dac3_l_mux), |
| 3073 | SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0, |
| 3074 | &rt5677_dac3_r_mux), |
| 3075 | |
| 3076 | /* DAC4 channel Mux */ |
| 3077 | SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0, |
| 3078 | &rt5677_dac4_l_mux), |
| 3079 | SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0, |
| 3080 | &rt5677_dac4_r_mux), |
| 3081 | |
| 3082 | /* DAC Mixer */ |
| 3083 | SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3084 | RT5677_PWR_DAC_S1F_BIT, 0, rt5677_filter_power_event, |
| 3085 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3086 | SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3087 | RT5677_PWR_DAC_M2F_L_BIT, 0, rt5677_filter_power_event, |
| 3088 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3089 | SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3090 | RT5677_PWR_DAC_M2F_R_BIT, 0, rt5677_filter_power_event, |
| 3091 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3092 | SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3093 | RT5677_PWR_DAC_M3F_L_BIT, 0, rt5677_filter_power_event, |
| 3094 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3095 | SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3096 | RT5677_PWR_DAC_M3F_R_BIT, 0, rt5677_filter_power_event, |
| 3097 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3098 | SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3099 | RT5677_PWR_DAC_M4F_L_BIT, 0, rt5677_filter_power_event, |
| 3100 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 3101 | SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2, |
Oder Chiou | c22d766 | 2015-11-09 18:01:04 +0800 | [diff] [blame] | 3102 | RT5677_PWR_DAC_M4F_R_BIT, 0, rt5677_filter_power_event, |
| 3103 | SND_SOC_DAPM_POST_PMU), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3104 | |
| 3105 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, |
| 3106 | rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)), |
| 3107 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, |
| 3108 | rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)), |
| 3109 | SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, |
| 3110 | rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)), |
| 3111 | SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, |
| 3112 | rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)), |
| 3113 | SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0, |
| 3114 | rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)), |
| 3115 | SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0, |
| 3116 | rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)), |
| 3117 | SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0, |
| 3118 | rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)), |
| 3119 | SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0, |
| 3120 | rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)), |
| 3121 | SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3122 | SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3123 | SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3124 | SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 3125 | |
| 3126 | /* DACs */ |
| 3127 | SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1, |
| 3128 | RT5677_PWR_DAC1_BIT, 0), |
| 3129 | SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1, |
| 3130 | RT5677_PWR_DAC2_BIT, 0), |
| 3131 | SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1, |
| 3132 | RT5677_PWR_DAC3_BIT, 0), |
| 3133 | |
| 3134 | /* PDM */ |
| 3135 | SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2, |
| 3136 | RT5677_PWR_PDM1_BIT, 0, NULL, 0), |
| 3137 | SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2, |
| 3138 | RT5677_PWR_PDM2_BIT, 0, NULL, 0), |
| 3139 | |
| 3140 | SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT, |
| 3141 | 1, &rt5677_pdm1_l_mux), |
| 3142 | SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT, |
| 3143 | 1, &rt5677_pdm1_r_mux), |
| 3144 | SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT, |
| 3145 | 1, &rt5677_pdm2_l_mux), |
| 3146 | SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT, |
| 3147 | 1, &rt5677_pdm2_r_mux), |
| 3148 | |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 3149 | SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3150 | 0, NULL, 0), |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 3151 | SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3152 | 0, NULL, 0), |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 3153 | SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3154 | 0, NULL, 0), |
| 3155 | |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 3156 | SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0, |
| 3157 | rt5677_vref_event, SND_SOC_DAPM_POST_PMU), |
| 3158 | SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0, |
| 3159 | rt5677_vref_event, SND_SOC_DAPM_POST_PMU), |
| 3160 | SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0, |
| 3161 | rt5677_vref_event, SND_SOC_DAPM_POST_PMU), |
| 3162 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3163 | /* Output Lines */ |
| 3164 | SND_SOC_DAPM_OUTPUT("LOUT1"), |
| 3165 | SND_SOC_DAPM_OUTPUT("LOUT2"), |
| 3166 | SND_SOC_DAPM_OUTPUT("LOUT3"), |
| 3167 | SND_SOC_DAPM_OUTPUT("PDM1L"), |
| 3168 | SND_SOC_DAPM_OUTPUT("PDM1R"), |
| 3169 | SND_SOC_DAPM_OUTPUT("PDM2L"), |
| 3170 | SND_SOC_DAPM_OUTPUT("PDM2R"), |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 3171 | |
| 3172 | SND_SOC_DAPM_POST("vref", rt5677_vref_event), |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3173 | }; |
| 3174 | |
| 3175 | static const struct snd_soc_dapm_route rt5677_dapm_routes[] = { |
Oder Chiou | 5220f7f | 2015-05-08 13:24:02 +0800 | [diff] [blame] | 3176 | { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc }, |
| 3177 | { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc }, |
| 3178 | { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc }, |
| 3179 | { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc }, |
| 3180 | { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc }, |
| 3181 | { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc }, |
Oder Chiou | 5a8c7c2 | 2014-12-23 10:27:55 +0800 | [diff] [blame] | 3182 | { "I2S1", NULL, "I2S1 ASRC", can_use_asrc}, |
| 3183 | { "I2S2", NULL, "I2S2 ASRC", can_use_asrc}, |
| 3184 | { "I2S3", NULL, "I2S3 ASRC", can_use_asrc}, |
| 3185 | { "I2S4", NULL, "I2S4 ASRC", can_use_asrc}, |
| 3186 | |
| 3187 | { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, |
| 3188 | { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc }, |
| 3189 | { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc }, |
| 3190 | { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc }, |
| 3191 | { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc }, |
| 3192 | { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc }, |
| 3193 | { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc }, |
| 3194 | { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, |
| 3195 | { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc }, |
| 3196 | { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc }, |
| 3197 | { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc }, |
| 3198 | { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, |
| 3199 | { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, |
| 3200 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3201 | { "DMIC1", NULL, "DMIC L1" }, |
| 3202 | { "DMIC1", NULL, "DMIC R1" }, |
| 3203 | { "DMIC2", NULL, "DMIC L2" }, |
| 3204 | { "DMIC2", NULL, "DMIC R2" }, |
| 3205 | { "DMIC3", NULL, "DMIC L3" }, |
| 3206 | { "DMIC3", NULL, "DMIC R3" }, |
| 3207 | { "DMIC4", NULL, "DMIC L4" }, |
| 3208 | { "DMIC4", NULL, "DMIC R4" }, |
| 3209 | |
| 3210 | { "DMIC L1", NULL, "DMIC CLK" }, |
| 3211 | { "DMIC R1", NULL, "DMIC CLK" }, |
| 3212 | { "DMIC L2", NULL, "DMIC CLK" }, |
| 3213 | { "DMIC R2", NULL, "DMIC CLK" }, |
| 3214 | { "DMIC L3", NULL, "DMIC CLK" }, |
| 3215 | { "DMIC R3", NULL, "DMIC CLK" }, |
| 3216 | { "DMIC L4", NULL, "DMIC CLK" }, |
| 3217 | { "DMIC R4", NULL, "DMIC CLK" }, |
| 3218 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 3219 | { "DMIC L1", NULL, "DMIC1 power" }, |
| 3220 | { "DMIC R1", NULL, "DMIC1 power" }, |
| 3221 | { "DMIC L3", NULL, "DMIC3 power" }, |
| 3222 | { "DMIC R3", NULL, "DMIC3 power" }, |
| 3223 | { "DMIC L4", NULL, "DMIC4 power" }, |
| 3224 | { "DMIC R4", NULL, "DMIC4 power" }, |
| 3225 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3226 | { "BST1", NULL, "IN1P" }, |
| 3227 | { "BST1", NULL, "IN1N" }, |
| 3228 | { "BST2", NULL, "IN2P" }, |
| 3229 | { "BST2", NULL, "IN2N" }, |
| 3230 | |
Bard Liao | 22e5134 | 2014-08-27 19:50:33 +0800 | [diff] [blame] | 3231 | { "IN1P", NULL, "MICBIAS1" }, |
| 3232 | { "IN1N", NULL, "MICBIAS1" }, |
| 3233 | { "IN2P", NULL, "MICBIAS1" }, |
| 3234 | { "IN2N", NULL, "MICBIAS1" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3235 | |
| 3236 | { "ADC 1", NULL, "BST1" }, |
| 3237 | { "ADC 1", NULL, "ADC 1 power" }, |
| 3238 | { "ADC 1", NULL, "ADC1 clock" }, |
| 3239 | { "ADC 2", NULL, "BST2" }, |
| 3240 | { "ADC 2", NULL, "ADC 2 power" }, |
| 3241 | { "ADC 2", NULL, "ADC2 clock" }, |
| 3242 | |
| 3243 | { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, |
| 3244 | { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, |
| 3245 | { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" }, |
| 3246 | { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" }, |
| 3247 | |
| 3248 | { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" }, |
| 3249 | { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" }, |
| 3250 | { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" }, |
| 3251 | { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" }, |
| 3252 | |
| 3253 | { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" }, |
| 3254 | { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" }, |
| 3255 | { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" }, |
| 3256 | { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" }, |
| 3257 | |
| 3258 | { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" }, |
| 3259 | { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" }, |
| 3260 | { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" }, |
| 3261 | { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" }, |
| 3262 | |
| 3263 | { "Mono DMIC L Mux", "DMIC1", "DMIC1" }, |
| 3264 | { "Mono DMIC L Mux", "DMIC2", "DMIC2" }, |
| 3265 | { "Mono DMIC L Mux", "DMIC3", "DMIC3" }, |
| 3266 | { "Mono DMIC L Mux", "DMIC4", "DMIC4" }, |
| 3267 | |
| 3268 | { "Mono DMIC R Mux", "DMIC1", "DMIC1" }, |
| 3269 | { "Mono DMIC R Mux", "DMIC2", "DMIC2" }, |
| 3270 | { "Mono DMIC R Mux", "DMIC3", "DMIC3" }, |
| 3271 | { "Mono DMIC R Mux", "DMIC4", "DMIC4" }, |
| 3272 | |
| 3273 | { "ADC 1_2", NULL, "ADC 1" }, |
| 3274 | { "ADC 1_2", NULL, "ADC 2" }, |
| 3275 | |
| 3276 | { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 3277 | { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 3278 | { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3279 | |
| 3280 | { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 3281 | { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" }, |
| 3282 | { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3283 | |
| 3284 | { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 3285 | { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 3286 | { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3287 | |
| 3288 | { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 3289 | { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" }, |
| 3290 | { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3291 | |
| 3292 | { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 3293 | { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 3294 | { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3295 | |
| 3296 | { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 3297 | { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, |
| 3298 | { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" }, |
| 3299 | |
| 3300 | { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" }, |
| 3301 | { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" }, |
| 3302 | { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" }, |
| 3303 | |
| 3304 | { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" }, |
| 3305 | { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" }, |
| 3306 | { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" }, |
| 3307 | |
| 3308 | { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" }, |
| 3309 | { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" }, |
| 3310 | { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 3311 | |
| 3312 | { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" }, |
| 3313 | { "Mono ADC1 L Mux", "ADC1", "ADC 1" }, |
| 3314 | { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 3315 | |
| 3316 | { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" }, |
| 3317 | { "Mono ADC1 R Mux", "ADC2", "ADC 2" }, |
| 3318 | { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 3319 | |
| 3320 | { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" }, |
| 3321 | { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" }, |
| 3322 | { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 3323 | |
| 3324 | { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" }, |
| 3325 | { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" }, |
| 3326 | { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" }, |
| 3327 | { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" }, |
| 3328 | |
| 3329 | { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, |
| 3330 | { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3331 | { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, |
| 3332 | { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, |
| 3333 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3334 | |
| 3335 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" }, |
| 3336 | { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" }, |
| 3337 | |
| 3338 | { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" }, |
| 3339 | { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" }, |
| 3340 | { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" }, |
| 3341 | { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" }, |
| 3342 | |
| 3343 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" }, |
| 3344 | { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" }, |
| 3345 | |
| 3346 | { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" }, |
| 3347 | { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" }, |
| 3348 | |
| 3349 | { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" }, |
| 3350 | { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3351 | { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" }, |
| 3352 | { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" }, |
| 3353 | { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3354 | |
| 3355 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" }, |
| 3356 | { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" }, |
| 3357 | |
| 3358 | { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" }, |
| 3359 | { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" }, |
| 3360 | { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" }, |
| 3361 | { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" }, |
| 3362 | |
| 3363 | { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" }, |
| 3364 | { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3365 | { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" }, |
| 3366 | { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" }, |
| 3367 | { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3368 | |
| 3369 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" }, |
| 3370 | { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" }, |
| 3371 | |
| 3372 | { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" }, |
| 3373 | { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" }, |
| 3374 | { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" }, |
| 3375 | { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" }, |
| 3376 | |
| 3377 | { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" }, |
| 3378 | { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3379 | { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" }, |
| 3380 | { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" }, |
| 3381 | { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3382 | |
| 3383 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" }, |
| 3384 | { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" }, |
| 3385 | |
| 3386 | { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" }, |
| 3387 | { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" }, |
| 3388 | { "Mono ADC MIXL", NULL, "adc mono left filter" }, |
| 3389 | { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3390 | |
| 3391 | { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" }, |
| 3392 | { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" }, |
| 3393 | { "Mono ADC MIXR", NULL, "adc mono right filter" }, |
| 3394 | { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, |
| 3395 | |
| 3396 | { "Mono ADC MIX", NULL, "Mono ADC MIXL" }, |
| 3397 | { "Mono ADC MIX", NULL, "Mono ADC MIXR" }, |
| 3398 | |
| 3399 | { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 3400 | { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, |
| 3401 | { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, |
| 3402 | { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 3403 | { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 3404 | |
| 3405 | { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3406 | { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3407 | { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3408 | |
| 3409 | { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3410 | { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 3411 | |
| 3412 | { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3413 | { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3414 | { "IF1 ADC3 Mux", "OB45", "OB45" }, |
| 3415 | |
| 3416 | { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3417 | { "IF1 ADC4 Mux", "OB67", "OB67" }, |
| 3418 | { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3419 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 3420 | { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" }, |
| 3421 | { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" }, |
| 3422 | { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" }, |
| 3423 | { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" }, |
| 3424 | |
| 3425 | { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" }, |
| 3426 | { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" }, |
| 3427 | { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" }, |
| 3428 | { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" }, |
| 3429 | |
| 3430 | { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" }, |
| 3431 | { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" }, |
| 3432 | { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" }, |
| 3433 | { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" }, |
| 3434 | |
| 3435 | { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" }, |
| 3436 | { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" }, |
| 3437 | { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" }, |
| 3438 | { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" }, |
| 3439 | |
| 3440 | { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" }, |
| 3441 | { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" }, |
| 3442 | { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" }, |
| 3443 | { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" }, |
| 3444 | |
| 3445 | { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" }, |
| 3446 | { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" }, |
| 3447 | { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" }, |
| 3448 | { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" }, |
| 3449 | { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" }, |
| 3450 | { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" }, |
| 3451 | { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" }, |
| 3452 | { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" }, |
| 3453 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3454 | { "AIF1TX", NULL, "I2S1" }, |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 3455 | { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3456 | |
| 3457 | { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3458 | { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3459 | { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3460 | |
| 3461 | { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3462 | { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 3463 | |
| 3464 | { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3465 | { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3466 | { "IF2 ADC3 Mux", "OB45", "OB45" }, |
| 3467 | |
| 3468 | { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3469 | { "IF2 ADC4 Mux", "OB67", "OB67" }, |
| 3470 | { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3471 | |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 3472 | { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" }, |
| 3473 | { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" }, |
| 3474 | { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" }, |
| 3475 | { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" }, |
| 3476 | |
| 3477 | { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" }, |
| 3478 | { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" }, |
| 3479 | { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" }, |
| 3480 | { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" }, |
| 3481 | |
| 3482 | { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" }, |
| 3483 | { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" }, |
| 3484 | { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" }, |
| 3485 | { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" }, |
| 3486 | |
| 3487 | { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" }, |
| 3488 | { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" }, |
| 3489 | { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" }, |
| 3490 | { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" }, |
| 3491 | |
| 3492 | { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" }, |
| 3493 | { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" }, |
| 3494 | { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" }, |
| 3495 | { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" }, |
| 3496 | |
| 3497 | { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" }, |
| 3498 | { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" }, |
| 3499 | { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" }, |
| 3500 | { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" }, |
| 3501 | { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" }, |
| 3502 | { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" }, |
| 3503 | { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" }, |
| 3504 | { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" }, |
| 3505 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3506 | { "AIF2TX", NULL, "I2S2" }, |
Oder Chiou | e6f6ebc | 2014-10-22 16:11:39 +0800 | [diff] [blame] | 3507 | { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3508 | |
| 3509 | { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3510 | { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3511 | { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3512 | { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3513 | { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3514 | { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" }, |
| 3515 | { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" }, |
| 3516 | { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3517 | |
| 3518 | { "AIF3TX", NULL, "I2S3" }, |
| 3519 | { "AIF3TX", NULL, "IF3 ADC Mux" }, |
| 3520 | |
| 3521 | { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3522 | { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3523 | { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3524 | { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3525 | { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3526 | { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" }, |
| 3527 | { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" }, |
| 3528 | { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3529 | |
| 3530 | { "AIF4TX", NULL, "I2S4" }, |
| 3531 | { "AIF4TX", NULL, "IF4 ADC Mux" }, |
| 3532 | |
| 3533 | { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3534 | { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3535 | { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3536 | |
| 3537 | { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3538 | { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" }, |
| 3539 | |
| 3540 | { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3541 | { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" }, |
| 3542 | { "SLB ADC3 Mux", "OB45", "OB45" }, |
| 3543 | |
| 3544 | { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" }, |
| 3545 | { "SLB ADC4 Mux", "OB67", "OB67" }, |
| 3546 | { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" }, |
| 3547 | |
| 3548 | { "SLBTX", NULL, "SLB" }, |
| 3549 | { "SLBTX", NULL, "SLB ADC1 Mux" }, |
| 3550 | { "SLBTX", NULL, "SLB ADC2 Mux" }, |
| 3551 | { "SLBTX", NULL, "SLB ADC3 Mux" }, |
| 3552 | { "SLBTX", NULL, "SLB ADC4 Mux" }, |
| 3553 | |
| 3554 | { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" }, |
| 3555 | { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" }, |
| 3556 | { "IB01 Mux", "SLB DAC 01", "SLB DAC01" }, |
| 3557 | { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3558 | { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" }, |
| 3559 | |
| 3560 | { "IB01 Bypass Mux", "Bypass", "IB01 Mux" }, |
| 3561 | { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" }, |
| 3562 | |
| 3563 | { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" }, |
| 3564 | { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" }, |
| 3565 | { "IB23 Mux", "SLB DAC 23", "SLB DAC23" }, |
| 3566 | { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3567 | { "IB23 Mux", "DAC1 FS", "DAC1 FS" }, |
| 3568 | { "IB23 Mux", "IF4 DAC", "IF4 DAC" }, |
| 3569 | |
| 3570 | { "IB23 Bypass Mux", "Bypass", "IB23 Mux" }, |
| 3571 | { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" }, |
| 3572 | |
| 3573 | { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" }, |
| 3574 | { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" }, |
| 3575 | { "IB45 Mux", "SLB DAC 45", "SLB DAC45" }, |
| 3576 | { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" }, |
| 3577 | { "IB45 Mux", "IF3 DAC", "IF3 DAC" }, |
| 3578 | |
| 3579 | { "IB45 Bypass Mux", "Bypass", "IB45 Mux" }, |
| 3580 | { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" }, |
| 3581 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3582 | { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, |
| 3583 | { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3584 | { "IB6 Mux", "SLB DAC 6", "SLB DAC6" }, |
| 3585 | { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, |
| 3586 | { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3587 | { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 3588 | { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 3589 | { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 3590 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3591 | { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, |
| 3592 | { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3593 | { "IB7 Mux", "SLB DAC 7", "SLB DAC7" }, |
| 3594 | { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, |
| 3595 | { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3596 | { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, |
| 3597 | { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, |
| 3598 | { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, |
| 3599 | |
| 3600 | { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" }, |
| 3601 | { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" }, |
| 3602 | { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" }, |
| 3603 | { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" }, |
| 3604 | { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" }, |
| 3605 | { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" }, |
| 3606 | |
| 3607 | { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" }, |
| 3608 | { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" }, |
| 3609 | { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" }, |
| 3610 | { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" }, |
| 3611 | { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" }, |
| 3612 | { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" }, |
| 3613 | { "IB9 Mux", "DAC1 FS", "DAC1 FS" }, |
| 3614 | |
| 3615 | { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3616 | { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3617 | { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3618 | { "OB01 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3619 | { "OB01 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3620 | { "OB01 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3621 | { "OB01 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3622 | |
| 3623 | { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3624 | { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3625 | { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3626 | { "OB23 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3627 | { "OB23 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3628 | { "OB23 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3629 | { "OB23 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3630 | |
| 3631 | { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3632 | { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3633 | { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3634 | { "OB4 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3635 | { "OB4 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3636 | { "OB4 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3637 | { "OB4 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3638 | |
| 3639 | { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3640 | { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3641 | { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3642 | { "OB5 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3643 | { "OB5 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3644 | { "OB5 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3645 | { "OB5 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3646 | |
| 3647 | { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3648 | { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3649 | { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3650 | { "OB6 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3651 | { "OB6 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3652 | { "OB6 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3653 | { "OB6 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3654 | |
| 3655 | { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" }, |
| 3656 | { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" }, |
| 3657 | { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" }, |
| 3658 | { "OB7 MIX", "IB6 Switch", "IB6 Mux" }, |
| 3659 | { "OB7 MIX", "IB7 Switch", "IB7 Mux" }, |
| 3660 | { "OB7 MIX", "IB8 Switch", "IB8 Mux" }, |
| 3661 | { "OB7 MIX", "IB9 Switch", "IB9 Mux" }, |
| 3662 | |
| 3663 | { "OB01 Bypass Mux", "Bypass", "OB01 MIX" }, |
| 3664 | { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" }, |
| 3665 | { "OB23 Bypass Mux", "Bypass", "OB23 MIX" }, |
| 3666 | { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" }, |
| 3667 | |
| 3668 | { "OutBound2", NULL, "OB23 Bypass Mux" }, |
| 3669 | { "OutBound3", NULL, "OB23 Bypass Mux" }, |
| 3670 | { "OutBound4", NULL, "OB4 MIX" }, |
| 3671 | { "OutBound5", NULL, "OB5 MIX" }, |
| 3672 | { "OutBound6", NULL, "OB6 MIX" }, |
| 3673 | { "OutBound7", NULL, "OB7 MIX" }, |
| 3674 | |
| 3675 | { "OB45", NULL, "OutBound4" }, |
| 3676 | { "OB45", NULL, "OutBound5" }, |
| 3677 | { "OB67", NULL, "OutBound6" }, |
| 3678 | { "OB67", NULL, "OutBound7" }, |
| 3679 | |
| 3680 | { "IF1 DAC0", NULL, "AIF1RX" }, |
| 3681 | { "IF1 DAC1", NULL, "AIF1RX" }, |
| 3682 | { "IF1 DAC2", NULL, "AIF1RX" }, |
| 3683 | { "IF1 DAC3", NULL, "AIF1RX" }, |
| 3684 | { "IF1 DAC4", NULL, "AIF1RX" }, |
| 3685 | { "IF1 DAC5", NULL, "AIF1RX" }, |
| 3686 | { "IF1 DAC6", NULL, "AIF1RX" }, |
| 3687 | { "IF1 DAC7", NULL, "AIF1RX" }, |
| 3688 | { "IF1 DAC0", NULL, "I2S1" }, |
| 3689 | { "IF1 DAC1", NULL, "I2S1" }, |
| 3690 | { "IF1 DAC2", NULL, "I2S1" }, |
| 3691 | { "IF1 DAC3", NULL, "I2S1" }, |
| 3692 | { "IF1 DAC4", NULL, "I2S1" }, |
| 3693 | { "IF1 DAC5", NULL, "I2S1" }, |
| 3694 | { "IF1 DAC6", NULL, "I2S1" }, |
| 3695 | { "IF1 DAC7", NULL, "I2S1" }, |
| 3696 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame] | 3697 | { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" }, |
| 3698 | { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" }, |
| 3699 | { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" }, |
| 3700 | { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" }, |
| 3701 | { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" }, |
| 3702 | { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" }, |
| 3703 | { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" }, |
| 3704 | { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" }, |
| 3705 | |
| 3706 | { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" }, |
| 3707 | { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" }, |
| 3708 | { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" }, |
| 3709 | { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" }, |
| 3710 | { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" }, |
| 3711 | { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" }, |
| 3712 | { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" }, |
| 3713 | { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" }, |
| 3714 | |
| 3715 | { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" }, |
| 3716 | { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" }, |
| 3717 | { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" }, |
| 3718 | { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" }, |
| 3719 | { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" }, |
| 3720 | { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" }, |
| 3721 | { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" }, |
| 3722 | { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" }, |
| 3723 | |
| 3724 | { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" }, |
| 3725 | { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" }, |
| 3726 | { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" }, |
| 3727 | { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" }, |
| 3728 | { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" }, |
| 3729 | { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" }, |
| 3730 | { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" }, |
| 3731 | { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" }, |
| 3732 | |
| 3733 | { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" }, |
| 3734 | { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" }, |
| 3735 | { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" }, |
| 3736 | { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" }, |
| 3737 | { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" }, |
| 3738 | { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" }, |
| 3739 | { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" }, |
| 3740 | { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" }, |
| 3741 | |
| 3742 | { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" }, |
| 3743 | { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" }, |
| 3744 | { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" }, |
| 3745 | { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" }, |
| 3746 | { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" }, |
| 3747 | { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" }, |
| 3748 | { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" }, |
| 3749 | { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" }, |
| 3750 | |
| 3751 | { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" }, |
| 3752 | { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" }, |
| 3753 | { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" }, |
| 3754 | { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" }, |
| 3755 | { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" }, |
| 3756 | { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" }, |
| 3757 | { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" }, |
| 3758 | { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" }, |
| 3759 | |
| 3760 | { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" }, |
| 3761 | { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" }, |
| 3762 | { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" }, |
| 3763 | { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" }, |
| 3764 | { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" }, |
| 3765 | { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" }, |
| 3766 | { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" }, |
| 3767 | { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" }, |
| 3768 | |
| 3769 | { "IF1 DAC01", NULL, "IF1 DAC0 Mux" }, |
| 3770 | { "IF1 DAC01", NULL, "IF1 DAC1 Mux" }, |
| 3771 | { "IF1 DAC23", NULL, "IF1 DAC2 Mux" }, |
| 3772 | { "IF1 DAC23", NULL, "IF1 DAC3 Mux" }, |
| 3773 | { "IF1 DAC45", NULL, "IF1 DAC4 Mux" }, |
| 3774 | { "IF1 DAC45", NULL, "IF1 DAC5 Mux" }, |
| 3775 | { "IF1 DAC67", NULL, "IF1 DAC6 Mux" }, |
| 3776 | { "IF1 DAC67", NULL, "IF1 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3777 | |
| 3778 | { "IF2 DAC0", NULL, "AIF2RX" }, |
| 3779 | { "IF2 DAC1", NULL, "AIF2RX" }, |
| 3780 | { "IF2 DAC2", NULL, "AIF2RX" }, |
| 3781 | { "IF2 DAC3", NULL, "AIF2RX" }, |
| 3782 | { "IF2 DAC4", NULL, "AIF2RX" }, |
| 3783 | { "IF2 DAC5", NULL, "AIF2RX" }, |
| 3784 | { "IF2 DAC6", NULL, "AIF2RX" }, |
| 3785 | { "IF2 DAC7", NULL, "AIF2RX" }, |
| 3786 | { "IF2 DAC0", NULL, "I2S2" }, |
| 3787 | { "IF2 DAC1", NULL, "I2S2" }, |
| 3788 | { "IF2 DAC2", NULL, "I2S2" }, |
| 3789 | { "IF2 DAC3", NULL, "I2S2" }, |
| 3790 | { "IF2 DAC4", NULL, "I2S2" }, |
| 3791 | { "IF2 DAC5", NULL, "I2S2" }, |
| 3792 | { "IF2 DAC6", NULL, "I2S2" }, |
| 3793 | { "IF2 DAC7", NULL, "I2S2" }, |
| 3794 | |
Oder Chiou | 91159ec | 2014-11-11 15:31:19 +0800 | [diff] [blame] | 3795 | { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" }, |
| 3796 | { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" }, |
| 3797 | { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" }, |
| 3798 | { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" }, |
| 3799 | { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" }, |
| 3800 | { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" }, |
| 3801 | { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" }, |
| 3802 | { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" }, |
| 3803 | |
| 3804 | { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" }, |
| 3805 | { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" }, |
| 3806 | { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" }, |
| 3807 | { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" }, |
| 3808 | { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" }, |
| 3809 | { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" }, |
| 3810 | { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" }, |
| 3811 | { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" }, |
| 3812 | |
| 3813 | { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" }, |
| 3814 | { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" }, |
| 3815 | { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" }, |
| 3816 | { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" }, |
| 3817 | { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" }, |
| 3818 | { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" }, |
| 3819 | { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" }, |
| 3820 | { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" }, |
| 3821 | |
| 3822 | { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" }, |
| 3823 | { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" }, |
| 3824 | { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" }, |
| 3825 | { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" }, |
| 3826 | { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" }, |
| 3827 | { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" }, |
| 3828 | { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" }, |
| 3829 | { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" }, |
| 3830 | |
| 3831 | { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" }, |
| 3832 | { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" }, |
| 3833 | { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" }, |
| 3834 | { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" }, |
| 3835 | { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" }, |
| 3836 | { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" }, |
| 3837 | { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" }, |
| 3838 | { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" }, |
| 3839 | |
| 3840 | { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" }, |
| 3841 | { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" }, |
| 3842 | { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" }, |
| 3843 | { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" }, |
| 3844 | { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" }, |
| 3845 | { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" }, |
| 3846 | { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" }, |
| 3847 | { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" }, |
| 3848 | |
| 3849 | { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" }, |
| 3850 | { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" }, |
| 3851 | { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" }, |
| 3852 | { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" }, |
| 3853 | { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" }, |
| 3854 | { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" }, |
| 3855 | { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" }, |
| 3856 | { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" }, |
| 3857 | |
| 3858 | { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" }, |
| 3859 | { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" }, |
| 3860 | { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" }, |
| 3861 | { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" }, |
| 3862 | { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" }, |
| 3863 | { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" }, |
| 3864 | { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" }, |
| 3865 | { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" }, |
| 3866 | |
| 3867 | { "IF2 DAC01", NULL, "IF2 DAC0 Mux" }, |
| 3868 | { "IF2 DAC01", NULL, "IF2 DAC1 Mux" }, |
| 3869 | { "IF2 DAC23", NULL, "IF2 DAC2 Mux" }, |
| 3870 | { "IF2 DAC23", NULL, "IF2 DAC3 Mux" }, |
| 3871 | { "IF2 DAC45", NULL, "IF2 DAC4 Mux" }, |
| 3872 | { "IF2 DAC45", NULL, "IF2 DAC5 Mux" }, |
| 3873 | { "IF2 DAC67", NULL, "IF2 DAC6 Mux" }, |
| 3874 | { "IF2 DAC67", NULL, "IF2 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3875 | |
| 3876 | { "IF3 DAC", NULL, "AIF3RX" }, |
| 3877 | { "IF3 DAC", NULL, "I2S3" }, |
| 3878 | |
| 3879 | { "IF4 DAC", NULL, "AIF4RX" }, |
| 3880 | { "IF4 DAC", NULL, "I2S4" }, |
| 3881 | |
| 3882 | { "IF3 DAC L", NULL, "IF3 DAC" }, |
| 3883 | { "IF3 DAC R", NULL, "IF3 DAC" }, |
| 3884 | |
| 3885 | { "IF4 DAC L", NULL, "IF4 DAC" }, |
| 3886 | { "IF4 DAC R", NULL, "IF4 DAC" }, |
| 3887 | |
| 3888 | { "SLB DAC0", NULL, "SLBRX" }, |
| 3889 | { "SLB DAC1", NULL, "SLBRX" }, |
| 3890 | { "SLB DAC2", NULL, "SLBRX" }, |
| 3891 | { "SLB DAC3", NULL, "SLBRX" }, |
| 3892 | { "SLB DAC4", NULL, "SLBRX" }, |
| 3893 | { "SLB DAC5", NULL, "SLBRX" }, |
| 3894 | { "SLB DAC6", NULL, "SLBRX" }, |
| 3895 | { "SLB DAC7", NULL, "SLBRX" }, |
| 3896 | { "SLB DAC0", NULL, "SLB" }, |
| 3897 | { "SLB DAC1", NULL, "SLB" }, |
| 3898 | { "SLB DAC2", NULL, "SLB" }, |
| 3899 | { "SLB DAC3", NULL, "SLB" }, |
| 3900 | { "SLB DAC4", NULL, "SLB" }, |
| 3901 | { "SLB DAC5", NULL, "SLB" }, |
| 3902 | { "SLB DAC6", NULL, "SLB" }, |
| 3903 | { "SLB DAC7", NULL, "SLB" }, |
| 3904 | |
| 3905 | { "SLB DAC01", NULL, "SLB DAC0" }, |
| 3906 | { "SLB DAC01", NULL, "SLB DAC1" }, |
| 3907 | { "SLB DAC23", NULL, "SLB DAC2" }, |
| 3908 | { "SLB DAC23", NULL, "SLB DAC3" }, |
| 3909 | { "SLB DAC45", NULL, "SLB DAC4" }, |
| 3910 | { "SLB DAC45", NULL, "SLB DAC5" }, |
| 3911 | { "SLB DAC67", NULL, "SLB DAC6" }, |
| 3912 | { "SLB DAC67", NULL, "SLB DAC7" }, |
| 3913 | |
| 3914 | { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" }, |
| 3915 | { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" }, |
| 3916 | { "ADDA1 Mux", "OB 67", "OB67" }, |
| 3917 | |
| 3918 | { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" }, |
| 3919 | { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" }, |
| 3920 | { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" }, |
| 3921 | { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" }, |
| 3922 | { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" }, |
| 3923 | { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" }, |
| 3924 | |
| 3925 | { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" }, |
| 3926 | { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3927 | { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" }, |
| 3928 | { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3929 | |
| 3930 | { "DAC1 FS", NULL, "DAC1 MIXL" }, |
| 3931 | { "DAC1 FS", NULL, "DAC1 MIXR" }, |
| 3932 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3933 | { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" }, |
| 3934 | { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3935 | { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3936 | { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3937 | { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" }, |
| 3938 | { "DAC2 L Mux", "OB 2", "OutBound2" }, |
| 3939 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3940 | { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" }, |
| 3941 | { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3942 | { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3943 | { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3944 | { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" }, |
| 3945 | { "DAC2 R Mux", "OB 3", "OutBound3" }, |
| 3946 | { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" }, |
| 3947 | { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" }, |
| 3948 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3949 | { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" }, |
| 3950 | { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3951 | { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3952 | { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3953 | { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" }, |
| 3954 | { "DAC3 L Mux", "OB 4", "OutBound4" }, |
| 3955 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3956 | { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" }, |
| 3957 | { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3958 | { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3959 | { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3960 | { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" }, |
| 3961 | { "DAC3 R Mux", "OB 5", "OutBound5" }, |
| 3962 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3963 | { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" }, |
| 3964 | { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3965 | { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" }, |
| 3966 | { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" }, |
| 3967 | { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" }, |
| 3968 | { "DAC4 L Mux", "OB 6", "OutBound6" }, |
| 3969 | |
Oder Chiou | 7006877 | 2015-02-25 17:36:13 +0800 | [diff] [blame] | 3970 | { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" }, |
| 3971 | { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3972 | { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" }, |
| 3973 | { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" }, |
| 3974 | { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" }, |
| 3975 | { "DAC4 R Mux", "OB 7", "OutBound7" }, |
| 3976 | |
| 3977 | { "Sidetone Mux", "DMIC1 L", "DMIC L1" }, |
| 3978 | { "Sidetone Mux", "DMIC2 L", "DMIC L2" }, |
| 3979 | { "Sidetone Mux", "DMIC3 L", "DMIC L3" }, |
| 3980 | { "Sidetone Mux", "DMIC4 L", "DMIC L4" }, |
| 3981 | { "Sidetone Mux", "ADC1", "ADC 1" }, |
| 3982 | { "Sidetone Mux", "ADC2", "ADC 2" }, |
Oder Chiou | 90bdbb4 | 2014-09-18 14:45:59 +0800 | [diff] [blame] | 3983 | { "Sidetone Mux", NULL, "Sidetone Power" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3984 | |
| 3985 | { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" }, |
| 3986 | { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3987 | { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, |
| 3988 | { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" }, |
| 3989 | { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, |
| 3990 | { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" }, |
| 3991 | { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, |
| 3992 | { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, |
| 3993 | { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3994 | { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 3995 | { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 3996 | |
| 3997 | { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" }, |
| 3998 | { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" }, |
| 3999 | { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" }, |
| 4000 | { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4001 | { "Mono DAC MIXL", NULL, "dac mono2 left filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4002 | { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4003 | { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" }, |
| 4004 | { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" }, |
| 4005 | { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" }, |
| 4006 | { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4007 | { "Mono DAC MIXR", NULL, "dac mono2 right filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4008 | { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4009 | |
| 4010 | { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, |
| 4011 | { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, |
| 4012 | { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" }, |
| 4013 | { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4014 | { "DD1 MIXL", NULL, "dac mono3 left filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4015 | { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4016 | { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, |
| 4017 | { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, |
| 4018 | { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" }, |
| 4019 | { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4020 | { "DD1 MIXR", NULL, "dac mono3 right filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4021 | { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4022 | |
| 4023 | { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, |
| 4024 | { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" }, |
| 4025 | { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" }, |
| 4026 | { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4027 | { "DD2 MIXL", NULL, "dac mono4 left filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4028 | { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4029 | { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, |
| 4030 | { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" }, |
| 4031 | { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" }, |
| 4032 | { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" }, |
Oder Chiou | 6800b5b | 2014-12-23 10:27:54 +0800 | [diff] [blame] | 4033 | { "DD2 MIXR", NULL, "dac mono4 right filter" }, |
Oder Chiou | 38d595e | 2014-12-23 10:27:56 +0800 | [diff] [blame] | 4034 | { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4035 | |
| 4036 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" }, |
| 4037 | { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" }, |
| 4038 | { "Mono DAC MIX", NULL, "Mono DAC MIXL" }, |
| 4039 | { "Mono DAC MIX", NULL, "Mono DAC MIXR" }, |
| 4040 | { "DD1 MIX", NULL, "DD1 MIXL" }, |
| 4041 | { "DD1 MIX", NULL, "DD1 MIXR" }, |
| 4042 | { "DD2 MIX", NULL, "DD2 MIXL" }, |
| 4043 | { "DD2 MIX", NULL, "DD2 MIXR" }, |
| 4044 | |
| 4045 | { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" }, |
| 4046 | { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" }, |
| 4047 | { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" }, |
| 4048 | { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" }, |
| 4049 | |
| 4050 | { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" }, |
| 4051 | { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" }, |
| 4052 | { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" }, |
| 4053 | { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" }, |
| 4054 | |
| 4055 | { "DAC 1", NULL, "DAC12 SRC Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4056 | { "DAC 2", NULL, "DAC12 SRC Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4057 | { "DAC 3", NULL, "DAC3 SRC Mux" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4058 | |
| 4059 | { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, |
| 4060 | { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, |
| 4061 | { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" }, |
| 4062 | { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" }, |
| 4063 | { "PDM1 L Mux", NULL, "PDM1 Power" }, |
| 4064 | { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, |
| 4065 | { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, |
| 4066 | { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" }, |
| 4067 | { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" }, |
| 4068 | { "PDM1 R Mux", NULL, "PDM1 Power" }, |
| 4069 | { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" }, |
| 4070 | { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" }, |
| 4071 | { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" }, |
| 4072 | { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" }, |
| 4073 | { "PDM2 L Mux", NULL, "PDM2 Power" }, |
| 4074 | { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" }, |
| 4075 | { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" }, |
| 4076 | { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" }, |
| 4077 | { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" }, |
| 4078 | { "PDM2 R Mux", NULL, "PDM2 Power" }, |
| 4079 | |
| 4080 | { "LOUT1 amp", NULL, "DAC 1" }, |
| 4081 | { "LOUT2 amp", NULL, "DAC 2" }, |
| 4082 | { "LOUT3 amp", NULL, "DAC 3" }, |
| 4083 | |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 4084 | { "LOUT1 vref", NULL, "LOUT1 amp" }, |
| 4085 | { "LOUT2 vref", NULL, "LOUT2 amp" }, |
| 4086 | { "LOUT3 vref", NULL, "LOUT3 amp" }, |
| 4087 | |
| 4088 | { "LOUT1", NULL, "LOUT1 vref" }, |
| 4089 | { "LOUT2", NULL, "LOUT2 vref" }, |
| 4090 | { "LOUT3", NULL, "LOUT3 vref" }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4091 | |
| 4092 | { "PDM1L", NULL, "PDM1 L Mux" }, |
| 4093 | { "PDM1R", NULL, "PDM1 R Mux" }, |
| 4094 | { "PDM2L", NULL, "PDM2 L Mux" }, |
| 4095 | { "PDM2R", NULL, "PDM2 R Mux" }, |
| 4096 | }; |
| 4097 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4098 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = { |
| 4099 | { "DMIC L2", NULL, "DMIC1 power" }, |
| 4100 | { "DMIC R2", NULL, "DMIC1 power" }, |
| 4101 | }; |
| 4102 | |
| 4103 | static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = { |
| 4104 | { "DMIC L2", NULL, "DMIC2 power" }, |
| 4105 | { "DMIC R2", NULL, "DMIC2 power" }, |
| 4106 | }; |
| 4107 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4108 | static int rt5677_hw_params(struct snd_pcm_substream *substream, |
| 4109 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) |
| 4110 | { |
| 4111 | struct snd_soc_codec *codec = dai->codec; |
| 4112 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4113 | unsigned int val_len = 0, val_clk, mask_clk; |
| 4114 | int pre_div, bclk_ms, frame_size; |
| 4115 | |
| 4116 | rt5677->lrck[dai->id] = params_rate(params); |
Axel Lin | 30f14b4 | 2014-06-10 08:57:36 +0800 | [diff] [blame] | 4117 | pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4118 | if (pre_div < 0) { |
Anatol Pomozov | 8a4bd60 | 2014-10-15 13:55:32 -0700 | [diff] [blame] | 4119 | dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", |
| 4120 | rt5677->sysclk, rt5677->lrck[dai->id]); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4121 | return -EINVAL; |
| 4122 | } |
| 4123 | frame_size = snd_soc_params_to_frame_size(params); |
| 4124 | if (frame_size < 0) { |
| 4125 | dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); |
| 4126 | return -EINVAL; |
| 4127 | } |
| 4128 | bclk_ms = frame_size > 32; |
| 4129 | rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); |
| 4130 | |
| 4131 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", |
| 4132 | rt5677->bclk[dai->id], rt5677->lrck[dai->id]); |
| 4133 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", |
| 4134 | bclk_ms, pre_div, dai->id); |
| 4135 | |
| 4136 | switch (params_width(params)) { |
| 4137 | case 16: |
| 4138 | break; |
| 4139 | case 20: |
| 4140 | val_len |= RT5677_I2S_DL_20; |
| 4141 | break; |
| 4142 | case 24: |
| 4143 | val_len |= RT5677_I2S_DL_24; |
| 4144 | break; |
| 4145 | case 8: |
| 4146 | val_len |= RT5677_I2S_DL_8; |
| 4147 | break; |
| 4148 | default: |
| 4149 | return -EINVAL; |
| 4150 | } |
| 4151 | |
| 4152 | switch (dai->id) { |
| 4153 | case RT5677_AIF1: |
| 4154 | mask_clk = RT5677_I2S_PD1_MASK; |
| 4155 | val_clk = pre_div << RT5677_I2S_PD1_SFT; |
| 4156 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, |
| 4157 | RT5677_I2S_DL_MASK, val_len); |
| 4158 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 4159 | mask_clk, val_clk); |
| 4160 | break; |
| 4161 | case RT5677_AIF2: |
| 4162 | mask_clk = RT5677_I2S_PD2_MASK; |
| 4163 | val_clk = pre_div << RT5677_I2S_PD2_SFT; |
| 4164 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, |
| 4165 | RT5677_I2S_DL_MASK, val_len); |
| 4166 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 4167 | mask_clk, val_clk); |
| 4168 | break; |
| 4169 | case RT5677_AIF3: |
| 4170 | mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK; |
| 4171 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT | |
| 4172 | pre_div << RT5677_I2S_PD3_SFT; |
| 4173 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, |
| 4174 | RT5677_I2S_DL_MASK, val_len); |
| 4175 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 4176 | mask_clk, val_clk); |
| 4177 | break; |
| 4178 | case RT5677_AIF4: |
| 4179 | mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK; |
| 4180 | val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT | |
| 4181 | pre_div << RT5677_I2S_PD4_SFT; |
| 4182 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, |
| 4183 | RT5677_I2S_DL_MASK, val_len); |
| 4184 | regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, |
| 4185 | mask_clk, val_clk); |
| 4186 | break; |
| 4187 | default: |
| 4188 | break; |
| 4189 | } |
| 4190 | |
| 4191 | return 0; |
| 4192 | } |
| 4193 | |
| 4194 | static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
| 4195 | { |
| 4196 | struct snd_soc_codec *codec = dai->codec; |
| 4197 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4198 | unsigned int reg_val = 0; |
| 4199 | |
| 4200 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
| 4201 | case SND_SOC_DAIFMT_CBM_CFM: |
| 4202 | rt5677->master[dai->id] = 1; |
| 4203 | break; |
| 4204 | case SND_SOC_DAIFMT_CBS_CFS: |
| 4205 | reg_val |= RT5677_I2S_MS_S; |
| 4206 | rt5677->master[dai->id] = 0; |
| 4207 | break; |
| 4208 | default: |
| 4209 | return -EINVAL; |
| 4210 | } |
| 4211 | |
| 4212 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
| 4213 | case SND_SOC_DAIFMT_NB_NF: |
| 4214 | break; |
| 4215 | case SND_SOC_DAIFMT_IB_NF: |
| 4216 | reg_val |= RT5677_I2S_BP_INV; |
| 4217 | break; |
| 4218 | default: |
| 4219 | return -EINVAL; |
| 4220 | } |
| 4221 | |
| 4222 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
| 4223 | case SND_SOC_DAIFMT_I2S: |
| 4224 | break; |
| 4225 | case SND_SOC_DAIFMT_LEFT_J: |
| 4226 | reg_val |= RT5677_I2S_DF_LEFT; |
| 4227 | break; |
| 4228 | case SND_SOC_DAIFMT_DSP_A: |
| 4229 | reg_val |= RT5677_I2S_DF_PCM_A; |
| 4230 | break; |
| 4231 | case SND_SOC_DAIFMT_DSP_B: |
| 4232 | reg_val |= RT5677_I2S_DF_PCM_B; |
| 4233 | break; |
| 4234 | default: |
| 4235 | return -EINVAL; |
| 4236 | } |
| 4237 | |
| 4238 | switch (dai->id) { |
| 4239 | case RT5677_AIF1: |
| 4240 | regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, |
| 4241 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 4242 | RT5677_I2S_DF_MASK, reg_val); |
| 4243 | break; |
| 4244 | case RT5677_AIF2: |
| 4245 | regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, |
| 4246 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 4247 | RT5677_I2S_DF_MASK, reg_val); |
| 4248 | break; |
| 4249 | case RT5677_AIF3: |
| 4250 | regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, |
| 4251 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 4252 | RT5677_I2S_DF_MASK, reg_val); |
| 4253 | break; |
| 4254 | case RT5677_AIF4: |
| 4255 | regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, |
| 4256 | RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK | |
| 4257 | RT5677_I2S_DF_MASK, reg_val); |
| 4258 | break; |
| 4259 | default: |
| 4260 | break; |
| 4261 | } |
| 4262 | |
| 4263 | |
| 4264 | return 0; |
| 4265 | } |
| 4266 | |
| 4267 | static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai, |
| 4268 | int clk_id, unsigned int freq, int dir) |
| 4269 | { |
| 4270 | struct snd_soc_codec *codec = dai->codec; |
| 4271 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4272 | unsigned int reg_val = 0; |
| 4273 | |
| 4274 | if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) |
| 4275 | return 0; |
| 4276 | |
| 4277 | switch (clk_id) { |
| 4278 | case RT5677_SCLK_S_MCLK: |
| 4279 | reg_val |= RT5677_SCLK_SRC_MCLK; |
| 4280 | break; |
| 4281 | case RT5677_SCLK_S_PLL1: |
| 4282 | reg_val |= RT5677_SCLK_SRC_PLL1; |
| 4283 | break; |
| 4284 | case RT5677_SCLK_S_RCCLK: |
| 4285 | reg_val |= RT5677_SCLK_SRC_RCCLK; |
| 4286 | break; |
| 4287 | default: |
| 4288 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); |
| 4289 | return -EINVAL; |
| 4290 | } |
| 4291 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4292 | RT5677_SCLK_SRC_MASK, reg_val); |
| 4293 | rt5677->sysclk = freq; |
| 4294 | rt5677->sysclk_src = clk_id; |
| 4295 | |
| 4296 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); |
| 4297 | |
| 4298 | return 0; |
| 4299 | } |
| 4300 | |
| 4301 | /** |
| 4302 | * rt5677_pll_calc - Calcualte PLL M/N/K code. |
| 4303 | * @freq_in: external clock provided to codec. |
| 4304 | * @freq_out: target clock which codec works on. |
| 4305 | * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag. |
| 4306 | * |
| 4307 | * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec. |
| 4308 | * |
| 4309 | * Returns 0 for success or negative error code. |
| 4310 | */ |
| 4311 | static int rt5677_pll_calc(const unsigned int freq_in, |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4312 | const unsigned int freq_out, struct rl6231_pll_code *pll_code) |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4313 | { |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4314 | if (RT5677_PLL_INP_MIN > freq_in) |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4315 | return -EINVAL; |
| 4316 | |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4317 | return rl6231_pll_calc(freq_in, freq_out, pll_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4318 | } |
| 4319 | |
| 4320 | static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, |
| 4321 | unsigned int freq_in, unsigned int freq_out) |
| 4322 | { |
| 4323 | struct snd_soc_codec *codec = dai->codec; |
| 4324 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4325 | struct rl6231_pll_code pll_code; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4326 | int ret; |
| 4327 | |
| 4328 | if (source == rt5677->pll_src && freq_in == rt5677->pll_in && |
| 4329 | freq_out == rt5677->pll_out) |
| 4330 | return 0; |
| 4331 | |
| 4332 | if (!freq_in || !freq_out) { |
| 4333 | dev_dbg(codec->dev, "PLL disabled\n"); |
| 4334 | |
| 4335 | rt5677->pll_in = 0; |
| 4336 | rt5677->pll_out = 0; |
| 4337 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4338 | RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK); |
| 4339 | return 0; |
| 4340 | } |
| 4341 | |
| 4342 | switch (source) { |
| 4343 | case RT5677_PLL1_S_MCLK: |
| 4344 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4345 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK); |
| 4346 | break; |
| 4347 | case RT5677_PLL1_S_BCLK1: |
| 4348 | case RT5677_PLL1_S_BCLK2: |
| 4349 | case RT5677_PLL1_S_BCLK3: |
| 4350 | case RT5677_PLL1_S_BCLK4: |
| 4351 | switch (dai->id) { |
| 4352 | case RT5677_AIF1: |
| 4353 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4354 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1); |
| 4355 | break; |
| 4356 | case RT5677_AIF2: |
| 4357 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4358 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2); |
| 4359 | break; |
| 4360 | case RT5677_AIF3: |
| 4361 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4362 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3); |
| 4363 | break; |
| 4364 | case RT5677_AIF4: |
| 4365 | regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, |
| 4366 | RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4); |
| 4367 | break; |
| 4368 | default: |
| 4369 | break; |
| 4370 | } |
| 4371 | break; |
| 4372 | default: |
| 4373 | dev_err(codec->dev, "Unknown PLL source %d\n", source); |
| 4374 | return -EINVAL; |
| 4375 | } |
| 4376 | |
| 4377 | ret = rt5677_pll_calc(freq_in, freq_out, &pll_code); |
| 4378 | if (ret < 0) { |
| 4379 | dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); |
| 4380 | return ret; |
| 4381 | } |
| 4382 | |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4383 | dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n", |
| 4384 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), |
| 4385 | pll_code.n_code, pll_code.k_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4386 | |
| 4387 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, |
Axel Lin | 099d334 | 2014-06-17 12:41:31 +0800 | [diff] [blame] | 4388 | pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4389 | regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, |
| 4390 | (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT | |
| 4391 | pll_code.m_bp << RT5677_PLL_M_BP_SFT); |
| 4392 | |
| 4393 | rt5677->pll_in = freq_in; |
| 4394 | rt5677->pll_out = freq_out; |
| 4395 | rt5677->pll_src = source; |
| 4396 | |
| 4397 | return 0; |
| 4398 | } |
| 4399 | |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4400 | static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
| 4401 | unsigned int rx_mask, int slots, int slot_width) |
| 4402 | { |
| 4403 | struct snd_soc_codec *codec = dai->codec; |
Oder Chiou | e4b7e6a | 2015-01-13 11:13:14 +0800 | [diff] [blame] | 4404 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Oder Chiou | 9913b9f | 2015-01-13 11:13:15 +0800 | [diff] [blame] | 4405 | unsigned int val = 0, slot_width_25 = 0; |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4406 | |
| 4407 | if (rx_mask || tx_mask) |
| 4408 | val |= (1 << 12); |
| 4409 | |
| 4410 | switch (slots) { |
| 4411 | case 4: |
| 4412 | val |= (1 << 10); |
| 4413 | break; |
| 4414 | case 6: |
| 4415 | val |= (2 << 10); |
| 4416 | break; |
| 4417 | case 8: |
| 4418 | val |= (3 << 10); |
| 4419 | break; |
| 4420 | case 2: |
| 4421 | default: |
| 4422 | break; |
| 4423 | } |
| 4424 | |
| 4425 | switch (slot_width) { |
| 4426 | case 20: |
| 4427 | val |= (1 << 8); |
| 4428 | break; |
Oder Chiou | 9913b9f | 2015-01-13 11:13:15 +0800 | [diff] [blame] | 4429 | case 25: |
| 4430 | slot_width_25 = 0x8080; |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4431 | case 24: |
| 4432 | val |= (2 << 8); |
| 4433 | break; |
| 4434 | case 32: |
| 4435 | val |= (3 << 8); |
| 4436 | break; |
| 4437 | case 16: |
| 4438 | default: |
| 4439 | break; |
| 4440 | } |
| 4441 | |
| 4442 | switch (dai->id) { |
| 4443 | case RT5677_AIF1: |
Oder Chiou | e4b7e6a | 2015-01-13 11:13:14 +0800 | [diff] [blame] | 4444 | regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, |
| 4445 | val); |
Oder Chiou | 9913b9f | 2015-01-13 11:13:15 +0800 | [diff] [blame] | 4446 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, |
| 4447 | slot_width_25); |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4448 | break; |
| 4449 | case RT5677_AIF2: |
Oder Chiou | e4b7e6a | 2015-01-13 11:13:14 +0800 | [diff] [blame] | 4450 | regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, |
| 4451 | val); |
Oder Chiou | 9913b9f | 2015-01-13 11:13:15 +0800 | [diff] [blame] | 4452 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, |
| 4453 | slot_width_25); |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4454 | break; |
| 4455 | default: |
| 4456 | break; |
| 4457 | } |
| 4458 | |
| 4459 | return 0; |
| 4460 | } |
| 4461 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4462 | static int rt5677_set_bias_level(struct snd_soc_codec *codec, |
| 4463 | enum snd_soc_bias_level level) |
| 4464 | { |
| 4465 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4466 | |
| 4467 | switch (level) { |
| 4468 | case SND_SOC_BIAS_ON: |
| 4469 | break; |
| 4470 | |
| 4471 | case SND_SOC_BIAS_PREPARE: |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 4472 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) { |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4473 | rt5677_set_dsp_vad(codec, false); |
| 4474 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4475 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
| 4476 | RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK, |
| 4477 | 0x0055); |
| 4478 | regmap_update_bits(rt5677->regmap, |
| 4479 | RT5677_PR_BASE + RT5677_BIAS_CUR4, |
| 4480 | 0x0f00, 0x0f00); |
| 4481 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 4482 | RT5677_PWR_FV1 | RT5677_PWR_FV2 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4483 | RT5677_PWR_VREF1 | RT5677_PWR_MB | |
| 4484 | RT5677_PWR_BG | RT5677_PWR_VREF2, |
| 4485 | RT5677_PWR_VREF1 | RT5677_PWR_MB | |
| 4486 | RT5677_PWR_BG | RT5677_PWR_VREF2); |
Oder Chiou | 683996c | 2014-11-19 13:52:20 +0800 | [diff] [blame] | 4487 | rt5677->is_vref_slow = false; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4488 | regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, |
| 4489 | RT5677_PWR_CORE, RT5677_PWR_CORE); |
| 4490 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, |
| 4491 | 0x1, 0x1); |
| 4492 | } |
| 4493 | break; |
| 4494 | |
| 4495 | case SND_SOC_BIAS_STANDBY: |
| 4496 | break; |
| 4497 | |
| 4498 | case SND_SOC_BIAS_OFF: |
| 4499 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); |
| 4500 | regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); |
| 4501 | regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); |
Oder Chiou | f18803a | 2014-07-07 15:37:00 +0800 | [diff] [blame] | 4502 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4503 | regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); |
| 4504 | regmap_update_bits(rt5677->regmap, |
| 4505 | RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4506 | |
| 4507 | if (rt5677->dsp_vad_en) |
| 4508 | rt5677_set_dsp_vad(codec, true); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4509 | break; |
| 4510 | |
| 4511 | default: |
| 4512 | break; |
| 4513 | } |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4514 | |
| 4515 | return 0; |
| 4516 | } |
| 4517 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4518 | #ifdef CONFIG_GPIOLIB |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4519 | static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
| 4520 | { |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4521 | struct rt5677_priv *rt5677 = gpiochip_get_data(chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4522 | |
| 4523 | switch (offset) { |
| 4524 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4525 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4526 | 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1)); |
| 4527 | break; |
| 4528 | |
| 4529 | case RT5677_GPIO6: |
| 4530 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4531 | RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT); |
| 4532 | break; |
| 4533 | |
| 4534 | default: |
| 4535 | break; |
| 4536 | } |
| 4537 | } |
| 4538 | |
| 4539 | static int rt5677_gpio_direction_out(struct gpio_chip *chip, |
| 4540 | unsigned offset, int value) |
| 4541 | { |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4542 | struct rt5677_priv *rt5677 = gpiochip_get_data(chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4543 | |
| 4544 | switch (offset) { |
| 4545 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4546 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4547 | 0x3 << (offset * 3 + 1), |
| 4548 | (0x2 | !!value) << (offset * 3 + 1)); |
| 4549 | break; |
| 4550 | |
| 4551 | case RT5677_GPIO6: |
| 4552 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4553 | RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK, |
| 4554 | RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT); |
| 4555 | break; |
| 4556 | |
| 4557 | default: |
| 4558 | break; |
| 4559 | } |
| 4560 | |
| 4561 | return 0; |
| 4562 | } |
| 4563 | |
| 4564 | static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 4565 | { |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4566 | struct rt5677_priv *rt5677 = gpiochip_get_data(chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4567 | int value, ret; |
| 4568 | |
| 4569 | ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); |
| 4570 | if (ret < 0) |
| 4571 | return ret; |
| 4572 | |
| 4573 | return (value & (0x1 << offset)) >> offset; |
| 4574 | } |
| 4575 | |
| 4576 | static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset) |
| 4577 | { |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4578 | struct rt5677_priv *rt5677 = gpiochip_get_data(chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4579 | |
| 4580 | switch (offset) { |
| 4581 | case RT5677_GPIO1 ... RT5677_GPIO5: |
| 4582 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 4583 | 0x1 << (offset * 3 + 2), 0x0); |
| 4584 | break; |
| 4585 | |
| 4586 | case RT5677_GPIO6: |
| 4587 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, |
| 4588 | RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN); |
| 4589 | break; |
| 4590 | |
| 4591 | default: |
| 4592 | break; |
| 4593 | } |
| 4594 | |
| 4595 | return 0; |
| 4596 | } |
| 4597 | |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4598 | /** Configures the gpio as |
| 4599 | * 0 - floating |
| 4600 | * 1 - pull down |
| 4601 | * 2 - pull up |
| 4602 | */ |
| 4603 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, |
| 4604 | int value) |
| 4605 | { |
| 4606 | int shift; |
| 4607 | |
| 4608 | switch (offset) { |
| 4609 | case RT5677_GPIO1 ... RT5677_GPIO2: |
| 4610 | shift = 2 * (1 - offset); |
| 4611 | regmap_update_bits(rt5677->regmap, |
| 4612 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2, |
| 4613 | 0x3 << shift, |
| 4614 | (value & 0x3) << shift); |
| 4615 | break; |
| 4616 | |
| 4617 | case RT5677_GPIO3 ... RT5677_GPIO6: |
| 4618 | shift = 2 * (9 - offset); |
| 4619 | regmap_update_bits(rt5677->regmap, |
| 4620 | RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3, |
| 4621 | 0x3 << shift, |
| 4622 | (value & 0x3) << shift); |
| 4623 | break; |
| 4624 | |
| 4625 | default: |
| 4626 | break; |
| 4627 | } |
| 4628 | } |
| 4629 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4630 | static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset) |
| 4631 | { |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4632 | struct rt5677_priv *rt5677 = gpiochip_get_data(chip); |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4633 | struct regmap_irq_chip_data *data = rt5677->irq_data; |
| 4634 | int irq; |
| 4635 | |
| 4636 | if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) { |
| 4637 | if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || |
| 4638 | (rt5677->pdata.jd1_gpio == 2 && |
| 4639 | offset == RT5677_GPIO2) || |
| 4640 | (rt5677->pdata.jd1_gpio == 3 && |
| 4641 | offset == RT5677_GPIO3)) { |
| 4642 | irq = RT5677_IRQ_JD1; |
| 4643 | } else { |
| 4644 | return -ENXIO; |
| 4645 | } |
| 4646 | } |
| 4647 | |
| 4648 | if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) { |
| 4649 | if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || |
| 4650 | (rt5677->pdata.jd2_gpio == 2 && |
| 4651 | offset == RT5677_GPIO5) || |
| 4652 | (rt5677->pdata.jd2_gpio == 3 && |
| 4653 | offset == RT5677_GPIO6)) { |
| 4654 | irq = RT5677_IRQ_JD2; |
| 4655 | } else if ((rt5677->pdata.jd3_gpio == 1 && |
| 4656 | offset == RT5677_GPIO4) || |
| 4657 | (rt5677->pdata.jd3_gpio == 2 && |
| 4658 | offset == RT5677_GPIO5) || |
| 4659 | (rt5677->pdata.jd3_gpio == 3 && |
| 4660 | offset == RT5677_GPIO6)) { |
| 4661 | irq = RT5677_IRQ_JD3; |
| 4662 | } else { |
| 4663 | return -ENXIO; |
| 4664 | } |
| 4665 | } |
| 4666 | |
| 4667 | return regmap_irq_get_virq(data, irq); |
| 4668 | } |
| 4669 | |
Julia Lawall | c59b24f | 2016-09-11 14:14:42 +0200 | [diff] [blame] | 4670 | static const struct gpio_chip rt5677_template_chip = { |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4671 | .label = "rt5677", |
| 4672 | .owner = THIS_MODULE, |
| 4673 | .direction_output = rt5677_gpio_direction_out, |
| 4674 | .set = rt5677_gpio_set, |
| 4675 | .direction_input = rt5677_gpio_direction_in, |
| 4676 | .get = rt5677_gpio_get, |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4677 | .to_irq = rt5677_to_irq, |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4678 | .can_sleep = 1, |
| 4679 | }; |
| 4680 | |
| 4681 | static void rt5677_init_gpio(struct i2c_client *i2c) |
| 4682 | { |
| 4683 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 4684 | int ret; |
| 4685 | |
| 4686 | rt5677->gpio_chip = rt5677_template_chip; |
| 4687 | rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; |
Linus Walleij | 58383c7 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 4688 | rt5677->gpio_chip.parent = &i2c->dev; |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4689 | rt5677->gpio_chip.base = -1; |
| 4690 | |
Linus Walleij | 1490036 | 2015-12-08 23:27:09 +0100 | [diff] [blame] | 4691 | ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4692 | if (ret != 0) |
| 4693 | dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); |
| 4694 | } |
| 4695 | |
| 4696 | static void rt5677_free_gpio(struct i2c_client *i2c) |
| 4697 | { |
| 4698 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4699 | |
Axel Lin | 5d5e63a | 2014-09-17 20:58:02 +0800 | [diff] [blame] | 4700 | gpiochip_remove(&rt5677->gpio_chip); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4701 | } |
| 4702 | #else |
Anatol Pomozov | 45b6e1d | 2014-10-16 09:40:58 -0700 | [diff] [blame] | 4703 | static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset, |
| 4704 | int value) |
| 4705 | { |
| 4706 | } |
| 4707 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 4708 | static void rt5677_init_gpio(struct i2c_client *i2c) |
| 4709 | { |
| 4710 | } |
| 4711 | |
| 4712 | static void rt5677_free_gpio(struct i2c_client *i2c) |
| 4713 | { |
| 4714 | } |
| 4715 | #endif |
| 4716 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4717 | static int rt5677_probe(struct snd_soc_codec *codec) |
| 4718 | { |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 4719 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4720 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4721 | int i; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4722 | |
| 4723 | rt5677->codec = codec; |
| 4724 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4725 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 4726 | snd_soc_dapm_add_routes(dapm, |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4727 | rt5677_dmic2_clk_2, |
| 4728 | ARRAY_SIZE(rt5677_dmic2_clk_2)); |
| 4729 | } else { /*use dmic1 clock by default*/ |
Lars-Peter Clausen | 6b43c2e | 2015-05-19 21:49:11 +0200 | [diff] [blame] | 4730 | snd_soc_dapm_add_routes(dapm, |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 4731 | rt5677_dmic2_clk_1, |
| 4732 | ARRAY_SIZE(rt5677_dmic2_clk_1)); |
| 4733 | } |
| 4734 | |
Lars-Peter Clausen | bd1204c | 2015-04-27 22:13:24 +0200 | [diff] [blame] | 4735 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4736 | |
| 4737 | regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); |
| 4738 | regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); |
| 4739 | |
Anatol Pomozov | 40eb90a | 2014-10-10 20:46:36 -0700 | [diff] [blame] | 4740 | for (i = 0; i < RT5677_GPIO_NUM; i++) |
| 4741 | rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); |
| 4742 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 4743 | if (rt5677->irq_data) { |
| 4744 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, |
| 4745 | 0x8000); |
| 4746 | regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, |
| 4747 | 0x0008); |
| 4748 | |
| 4749 | if (rt5677->pdata.jd1_gpio) |
| 4750 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4751 | RT5677_SEL_GPIO_JD1_MASK, |
| 4752 | rt5677->pdata.jd1_gpio << |
| 4753 | RT5677_SEL_GPIO_JD1_SFT); |
| 4754 | |
| 4755 | if (rt5677->pdata.jd2_gpio) |
| 4756 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4757 | RT5677_SEL_GPIO_JD2_MASK, |
| 4758 | rt5677->pdata.jd2_gpio << |
| 4759 | RT5677_SEL_GPIO_JD2_SFT); |
| 4760 | |
| 4761 | if (rt5677->pdata.jd3_gpio) |
| 4762 | regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, |
| 4763 | RT5677_SEL_GPIO_JD3_MASK, |
| 4764 | rt5677->pdata.jd3_gpio << |
| 4765 | RT5677_SEL_GPIO_JD3_SFT); |
| 4766 | } |
| 4767 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4768 | mutex_init(&rt5677->dsp_cmd_lock); |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 4769 | mutex_init(&rt5677->dsp_pri_lock); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4770 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4771 | return 0; |
| 4772 | } |
| 4773 | |
| 4774 | static int rt5677_remove(struct snd_soc_codec *codec) |
| 4775 | { |
| 4776 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4777 | |
| 4778 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
Axel Lin | f285f16 | 2015-07-23 23:32:04 +0800 | [diff] [blame] | 4779 | gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); |
Anatol Pomozov | cdab0d4 | 2015-10-29 15:31:59 -0700 | [diff] [blame] | 4780 | gpiod_set_value_cansleep(rt5677->reset_pin, 1); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4781 | |
| 4782 | return 0; |
| 4783 | } |
| 4784 | |
| 4785 | #ifdef CONFIG_PM |
| 4786 | static int rt5677_suspend(struct snd_soc_codec *codec) |
| 4787 | { |
| 4788 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4789 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4790 | if (!rt5677->dsp_vad_en) { |
| 4791 | regcache_cache_only(rt5677->regmap, true); |
| 4792 | regcache_mark_dirty(rt5677->regmap); |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4793 | |
Axel Lin | f285f16 | 2015-07-23 23:32:04 +0800 | [diff] [blame] | 4794 | gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); |
Anatol Pomozov | cdab0d4 | 2015-10-29 15:31:59 -0700 | [diff] [blame] | 4795 | gpiod_set_value_cansleep(rt5677->reset_pin, 1); |
Oder Chiou | cbca407 | 2015-02-25 17:36:14 +0800 | [diff] [blame] | 4796 | } |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4797 | |
| 4798 | return 0; |
| 4799 | } |
| 4800 | |
| 4801 | static int rt5677_resume(struct snd_soc_codec *codec) |
| 4802 | { |
| 4803 | struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); |
| 4804 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4805 | if (!rt5677->dsp_vad_en) { |
Ben Zhang | 1aa844c | 2015-12-15 13:51:25 -0800 | [diff] [blame] | 4806 | rt5677->pll_src = 0; |
| 4807 | rt5677->pll_in = 0; |
| 4808 | rt5677->pll_out = 0; |
Axel Lin | f285f16 | 2015-07-23 23:32:04 +0800 | [diff] [blame] | 4809 | gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); |
Anatol Pomozov | cdab0d4 | 2015-10-29 15:31:59 -0700 | [diff] [blame] | 4810 | gpiod_set_value_cansleep(rt5677->reset_pin, 0); |
Ben Zhang | efd901e | 2015-06-22 11:12:59 -0700 | [diff] [blame] | 4811 | if (rt5677->pow_ldo2 || rt5677->reset_pin) |
Oder Chiou | cbca407 | 2015-02-25 17:36:14 +0800 | [diff] [blame] | 4812 | msleep(10); |
Oder Chiou | cbca407 | 2015-02-25 17:36:14 +0800 | [diff] [blame] | 4813 | |
Oder Chiou | af48f1d | 2014-10-06 16:30:51 +0800 | [diff] [blame] | 4814 | regcache_cache_only(rt5677->regmap, false); |
| 4815 | regcache_sync(rt5677->regmap); |
| 4816 | } |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4817 | |
| 4818 | return 0; |
| 4819 | } |
| 4820 | #else |
| 4821 | #define rt5677_suspend NULL |
| 4822 | #define rt5677_resume NULL |
| 4823 | #endif |
| 4824 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4825 | static int rt5677_read(void *context, unsigned int reg, unsigned int *val) |
| 4826 | { |
| 4827 | struct i2c_client *client = context; |
| 4828 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); |
| 4829 | |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 4830 | if (rt5677->is_dsp_mode) { |
| 4831 | if (reg > 0xff) { |
| 4832 | mutex_lock(&rt5677->dsp_pri_lock); |
| 4833 | rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, |
| 4834 | reg & 0xff); |
| 4835 | rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val); |
| 4836 | mutex_unlock(&rt5677->dsp_pri_lock); |
| 4837 | } else { |
| 4838 | rt5677_dsp_mode_i2c_read(rt5677, reg, val); |
| 4839 | } |
| 4840 | } else { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4841 | regmap_read(rt5677->regmap_physical, reg, val); |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 4842 | } |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4843 | |
| 4844 | return 0; |
| 4845 | } |
| 4846 | |
| 4847 | static int rt5677_write(void *context, unsigned int reg, unsigned int val) |
| 4848 | { |
| 4849 | struct i2c_client *client = context; |
| 4850 | struct rt5677_priv *rt5677 = i2c_get_clientdata(client); |
| 4851 | |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 4852 | if (rt5677->is_dsp_mode) { |
| 4853 | if (reg > 0xff) { |
| 4854 | mutex_lock(&rt5677->dsp_pri_lock); |
| 4855 | rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX, |
| 4856 | reg & 0xff); |
| 4857 | rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA, |
| 4858 | val); |
| 4859 | mutex_unlock(&rt5677->dsp_pri_lock); |
| 4860 | } else { |
| 4861 | rt5677_dsp_mode_i2c_write(rt5677, reg, val); |
| 4862 | } |
| 4863 | } else { |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4864 | regmap_write(rt5677->regmap_physical, reg, val); |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 4865 | } |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4866 | |
| 4867 | return 0; |
| 4868 | } |
| 4869 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4870 | #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000 |
| 4871 | #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
| 4872 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) |
| 4873 | |
Axel Lin | 6479304 | 2015-07-15 15:38:14 +0800 | [diff] [blame] | 4874 | static const struct snd_soc_dai_ops rt5677_aif_dai_ops = { |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4875 | .hw_params = rt5677_hw_params, |
| 4876 | .set_fmt = rt5677_set_dai_fmt, |
| 4877 | .set_sysclk = rt5677_set_dai_sysclk, |
| 4878 | .set_pll = rt5677_set_dai_pll, |
Oder Chiou | 48561af | 2014-09-17 15:12:33 +0800 | [diff] [blame] | 4879 | .set_tdm_slot = rt5677_set_tdm_slot, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4880 | }; |
| 4881 | |
| 4882 | static struct snd_soc_dai_driver rt5677_dai[] = { |
| 4883 | { |
| 4884 | .name = "rt5677-aif1", |
| 4885 | .id = RT5677_AIF1, |
| 4886 | .playback = { |
| 4887 | .stream_name = "AIF1 Playback", |
| 4888 | .channels_min = 1, |
| 4889 | .channels_max = 2, |
| 4890 | .rates = RT5677_STEREO_RATES, |
| 4891 | .formats = RT5677_FORMATS, |
| 4892 | }, |
| 4893 | .capture = { |
| 4894 | .stream_name = "AIF1 Capture", |
| 4895 | .channels_min = 1, |
| 4896 | .channels_max = 2, |
| 4897 | .rates = RT5677_STEREO_RATES, |
| 4898 | .formats = RT5677_FORMATS, |
| 4899 | }, |
| 4900 | .ops = &rt5677_aif_dai_ops, |
| 4901 | }, |
| 4902 | { |
| 4903 | .name = "rt5677-aif2", |
| 4904 | .id = RT5677_AIF2, |
| 4905 | .playback = { |
| 4906 | .stream_name = "AIF2 Playback", |
| 4907 | .channels_min = 1, |
| 4908 | .channels_max = 2, |
| 4909 | .rates = RT5677_STEREO_RATES, |
| 4910 | .formats = RT5677_FORMATS, |
| 4911 | }, |
| 4912 | .capture = { |
| 4913 | .stream_name = "AIF2 Capture", |
| 4914 | .channels_min = 1, |
| 4915 | .channels_max = 2, |
| 4916 | .rates = RT5677_STEREO_RATES, |
| 4917 | .formats = RT5677_FORMATS, |
| 4918 | }, |
| 4919 | .ops = &rt5677_aif_dai_ops, |
| 4920 | }, |
| 4921 | { |
| 4922 | .name = "rt5677-aif3", |
| 4923 | .id = RT5677_AIF3, |
| 4924 | .playback = { |
| 4925 | .stream_name = "AIF3 Playback", |
| 4926 | .channels_min = 1, |
| 4927 | .channels_max = 2, |
| 4928 | .rates = RT5677_STEREO_RATES, |
| 4929 | .formats = RT5677_FORMATS, |
| 4930 | }, |
| 4931 | .capture = { |
| 4932 | .stream_name = "AIF3 Capture", |
| 4933 | .channels_min = 1, |
| 4934 | .channels_max = 2, |
| 4935 | .rates = RT5677_STEREO_RATES, |
| 4936 | .formats = RT5677_FORMATS, |
| 4937 | }, |
| 4938 | .ops = &rt5677_aif_dai_ops, |
| 4939 | }, |
| 4940 | { |
| 4941 | .name = "rt5677-aif4", |
| 4942 | .id = RT5677_AIF4, |
| 4943 | .playback = { |
| 4944 | .stream_name = "AIF4 Playback", |
| 4945 | .channels_min = 1, |
| 4946 | .channels_max = 2, |
| 4947 | .rates = RT5677_STEREO_RATES, |
| 4948 | .formats = RT5677_FORMATS, |
| 4949 | }, |
| 4950 | .capture = { |
| 4951 | .stream_name = "AIF4 Capture", |
| 4952 | .channels_min = 1, |
| 4953 | .channels_max = 2, |
| 4954 | .rates = RT5677_STEREO_RATES, |
| 4955 | .formats = RT5677_FORMATS, |
| 4956 | }, |
| 4957 | .ops = &rt5677_aif_dai_ops, |
| 4958 | }, |
| 4959 | { |
| 4960 | .name = "rt5677-slimbus", |
| 4961 | .id = RT5677_AIF5, |
| 4962 | .playback = { |
| 4963 | .stream_name = "SLIMBus Playback", |
| 4964 | .channels_min = 1, |
| 4965 | .channels_max = 2, |
| 4966 | .rates = RT5677_STEREO_RATES, |
| 4967 | .formats = RT5677_FORMATS, |
| 4968 | }, |
| 4969 | .capture = { |
| 4970 | .stream_name = "SLIMBus Capture", |
| 4971 | .channels_min = 1, |
| 4972 | .channels_max = 2, |
| 4973 | .rates = RT5677_STEREO_RATES, |
| 4974 | .formats = RT5677_FORMATS, |
| 4975 | }, |
| 4976 | .ops = &rt5677_aif_dai_ops, |
| 4977 | }, |
| 4978 | }; |
| 4979 | |
| 4980 | static struct snd_soc_codec_driver soc_codec_dev_rt5677 = { |
| 4981 | .probe = rt5677_probe, |
| 4982 | .remove = rt5677_remove, |
| 4983 | .suspend = rt5677_suspend, |
| 4984 | .resume = rt5677_resume, |
| 4985 | .set_bias_level = rt5677_set_bias_level, |
| 4986 | .idle_bias_off = true, |
Kuninori Morimoto | 1ec95a5 | 2016-08-08 09:23:46 +0000 | [diff] [blame] | 4987 | .component_driver = { |
| 4988 | .controls = rt5677_snd_controls, |
| 4989 | .num_controls = ARRAY_SIZE(rt5677_snd_controls), |
| 4990 | .dapm_widgets = rt5677_dapm_widgets, |
| 4991 | .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets), |
| 4992 | .dapm_routes = rt5677_dapm_routes, |
| 4993 | .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes), |
| 4994 | }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 4995 | }; |
| 4996 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 4997 | static const struct regmap_config rt5677_regmap_physical = { |
| 4998 | .name = "physical", |
| 4999 | .reg_bits = 8, |
| 5000 | .val_bits = 16, |
| 5001 | |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 5002 | .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * |
| 5003 | RT5677_PR_SPACING), |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 5004 | .readable_reg = rt5677_readable_register, |
| 5005 | |
| 5006 | .cache_type = REGCACHE_NONE, |
Oder Chiou | 6fe17da | 2014-11-25 09:51:41 +0800 | [diff] [blame] | 5007 | .ranges = rt5677_ranges, |
| 5008 | .num_ranges = ARRAY_SIZE(rt5677_ranges), |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 5009 | }; |
| 5010 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5011 | static const struct regmap_config rt5677_regmap = { |
| 5012 | .reg_bits = 8, |
| 5013 | .val_bits = 16, |
| 5014 | |
| 5015 | .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) * |
| 5016 | RT5677_PR_SPACING), |
| 5017 | |
| 5018 | .volatile_reg = rt5677_volatile_register, |
| 5019 | .readable_reg = rt5677_readable_register, |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 5020 | .reg_read = rt5677_read, |
| 5021 | .reg_write = rt5677_write, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5022 | |
| 5023 | .cache_type = REGCACHE_RBTREE, |
| 5024 | .reg_defaults = rt5677_reg, |
| 5025 | .num_reg_defaults = ARRAY_SIZE(rt5677_reg), |
| 5026 | .ranges = rt5677_ranges, |
| 5027 | .num_ranges = ARRAY_SIZE(rt5677_ranges), |
| 5028 | }; |
| 5029 | |
| 5030 | static const struct i2c_device_id rt5677_i2c_id[] = { |
Oder Chiou | ab1f709 | 2015-02-11 19:18:51 +0800 | [diff] [blame] | 5031 | { "rt5677", RT5677 }, |
| 5032 | { "rt5676", RT5676 }, |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 5033 | { "RT5677CE:00", RT5677 }, |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5034 | { } |
| 5035 | }; |
| 5036 | MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id); |
| 5037 | |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 5038 | static const struct acpi_gpio_params plug_det_gpio = { RT5677_GPIO_PLUG_DET, 0, false }; |
| 5039 | static const struct acpi_gpio_params mic_present_gpio = { RT5677_GPIO_MIC_PRESENT_L, 0, false }; |
| 5040 | static const struct acpi_gpio_params headphone_enable_gpio = { RT5677_GPIO_HP_AMP_SHDN_L, 0, false }; |
| 5041 | |
| 5042 | static const struct acpi_gpio_mapping bdw_rt5677_gpios[] = { |
| 5043 | { "plug-det-gpios", &plug_det_gpio, 1 }, |
| 5044 | { "mic-present-gpios", &mic_present_gpio, 1 }, |
| 5045 | { "headphone-enable-gpios", &headphone_enable_gpio, 1 }, |
| 5046 | { NULL }, |
| 5047 | }; |
| 5048 | |
| 5049 | static void rt5677_read_acpi_properties(struct rt5677_priv *rt5677, |
| 5050 | struct device *dev) |
| 5051 | { |
| 5052 | int ret; |
| 5053 | u32 val; |
| 5054 | |
| 5055 | ret = acpi_dev_add_driver_gpios(ACPI_COMPANION(dev), |
| 5056 | bdw_rt5677_gpios); |
| 5057 | if (ret) |
| 5058 | dev_warn(dev, "Failed to add driver gpios\n"); |
| 5059 | |
| 5060 | if (!device_property_read_u32(dev, "DCLK", &val)) |
| 5061 | rt5677->pdata.dmic2_clk_pin = val; |
| 5062 | |
| 5063 | rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1"); |
| 5064 | rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2"); |
| 5065 | rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1"); |
| 5066 | rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2"); |
| 5067 | rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3"); |
| 5068 | |
| 5069 | device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio); |
| 5070 | device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio); |
| 5071 | device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio); |
| 5072 | } |
| 5073 | |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 5074 | static void rt5677_read_device_properties(struct rt5677_priv *rt5677, |
| 5075 | struct device *dev) |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 5076 | { |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 5077 | rt5677->pdata.in1_diff = device_property_read_bool(dev, |
| 5078 | "realtek,in1-differential"); |
| 5079 | rt5677->pdata.in2_diff = device_property_read_bool(dev, |
| 5080 | "realtek,in2-differential"); |
| 5081 | rt5677->pdata.lout1_diff = device_property_read_bool(dev, |
| 5082 | "realtek,lout1-differential"); |
| 5083 | rt5677->pdata.lout2_diff = device_property_read_bool(dev, |
| 5084 | "realtek,lout2-differential"); |
| 5085 | rt5677->pdata.lout3_diff = device_property_read_bool(dev, |
| 5086 | "realtek,lout3-differential"); |
Anatol Pomozov | 6f67c38 | 2014-09-26 09:57:27 -0700 | [diff] [blame] | 5087 | |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 5088 | device_property_read_u8_array(dev, "realtek,gpio-config", |
| 5089 | rt5677->pdata.gpio_config, RT5677_GPIO_NUM); |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 5090 | |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 5091 | device_property_read_u32(dev, "realtek,jd1-gpio", |
| 5092 | &rt5677->pdata.jd1_gpio); |
| 5093 | device_property_read_u32(dev, "realtek,jd2-gpio", |
| 5094 | &rt5677->pdata.jd2_gpio); |
| 5095 | device_property_read_u32(dev, "realtek,jd3-gpio", |
| 5096 | &rt5677->pdata.jd3_gpio); |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 5097 | } |
| 5098 | |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 5099 | static struct regmap_irq rt5677_irqs[] = { |
| 5100 | [RT5677_IRQ_JD1] = { |
| 5101 | .reg_offset = 0, |
| 5102 | .mask = RT5677_EN_IRQ_GPIO_JD1, |
| 5103 | }, |
| 5104 | [RT5677_IRQ_JD2] = { |
| 5105 | .reg_offset = 0, |
| 5106 | .mask = RT5677_EN_IRQ_GPIO_JD2, |
| 5107 | }, |
| 5108 | [RT5677_IRQ_JD3] = { |
| 5109 | .reg_offset = 0, |
| 5110 | .mask = RT5677_EN_IRQ_GPIO_JD3, |
| 5111 | }, |
| 5112 | }; |
| 5113 | |
| 5114 | static struct regmap_irq_chip rt5677_irq_chip = { |
| 5115 | .name = "rt5677", |
| 5116 | .irqs = rt5677_irqs, |
| 5117 | .num_irqs = ARRAY_SIZE(rt5677_irqs), |
| 5118 | |
| 5119 | .num_regs = 1, |
| 5120 | .status_base = RT5677_IRQ_CTRL1, |
| 5121 | .mask_base = RT5677_IRQ_CTRL1, |
| 5122 | .mask_invert = 1, |
| 5123 | }; |
| 5124 | |
Oder Chiou | 35d40d1 | 2014-11-19 13:52:19 +0800 | [diff] [blame] | 5125 | static int rt5677_init_irq(struct i2c_client *i2c) |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 5126 | { |
| 5127 | int ret; |
| 5128 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 5129 | |
| 5130 | if (!rt5677->pdata.jd1_gpio && |
| 5131 | !rt5677->pdata.jd2_gpio && |
| 5132 | !rt5677->pdata.jd3_gpio) |
| 5133 | return 0; |
| 5134 | |
| 5135 | if (!i2c->irq) { |
| 5136 | dev_err(&i2c->dev, "No interrupt specified\n"); |
| 5137 | return -EINVAL; |
| 5138 | } |
| 5139 | |
| 5140 | ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, |
| 5141 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0, |
| 5142 | &rt5677_irq_chip, &rt5677->irq_data); |
| 5143 | |
| 5144 | if (ret != 0) { |
| 5145 | dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); |
| 5146 | return ret; |
| 5147 | } |
| 5148 | |
| 5149 | return 0; |
| 5150 | } |
| 5151 | |
Oder Chiou | 35d40d1 | 2014-11-19 13:52:19 +0800 | [diff] [blame] | 5152 | static void rt5677_free_irq(struct i2c_client *i2c) |
Oder Chiou | 5e3363a | 2014-10-16 11:24:26 -0700 | [diff] [blame] | 5153 | { |
| 5154 | struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c); |
| 5155 | |
| 5156 | if (rt5677->irq_data) |
| 5157 | regmap_del_irq_chip(i2c->irq, rt5677->irq_data); |
| 5158 | } |
| 5159 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5160 | static int rt5677_i2c_probe(struct i2c_client *i2c, |
| 5161 | const struct i2c_device_id *id) |
| 5162 | { |
| 5163 | struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev); |
| 5164 | struct rt5677_priv *rt5677; |
| 5165 | int ret; |
| 5166 | unsigned int val; |
| 5167 | |
| 5168 | rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), |
| 5169 | GFP_KERNEL); |
| 5170 | if (rt5677 == NULL) |
| 5171 | return -ENOMEM; |
| 5172 | |
| 5173 | i2c_set_clientdata(i2c, rt5677); |
| 5174 | |
Oder Chiou | ab1f709 | 2015-02-11 19:18:51 +0800 | [diff] [blame] | 5175 | rt5677->type = id->driver_data; |
| 5176 | |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5177 | if (pdata) |
| 5178 | rt5677->pdata = *pdata; |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 5179 | else if (i2c->dev.of_node) |
Ben Zhang | 9bfde72 | 2015-06-22 11:13:00 -0700 | [diff] [blame] | 5180 | rt5677_read_device_properties(rt5677, &i2c->dev); |
John Keeping | 8912853 | 2016-08-24 22:06:35 +0100 | [diff] [blame] | 5181 | else if (ACPI_HANDLE(&i2c->dev)) |
| 5182 | rt5677_read_acpi_properties(rt5677, &i2c->dev); |
| 5183 | else |
| 5184 | return -EINVAL; |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5185 | |
Ben Zhang | efd901e | 2015-06-22 11:12:59 -0700 | [diff] [blame] | 5186 | /* pow-ldo2 and reset are optional. The codec pins may be statically |
| 5187 | * connected on the board without gpios. If the gpio device property |
| 5188 | * isn't specified, devm_gpiod_get_optional returns NULL. |
| 5189 | */ |
| 5190 | rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, |
| 5191 | "realtek,pow-ldo2", GPIOD_OUT_HIGH); |
| 5192 | if (IS_ERR(rt5677->pow_ldo2)) { |
| 5193 | ret = PTR_ERR(rt5677->pow_ldo2); |
| 5194 | dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); |
Axel Lin | f8163c8 | 2015-07-25 10:23:40 +0800 | [diff] [blame] | 5195 | return ret; |
Ben Zhang | efd901e | 2015-06-22 11:12:59 -0700 | [diff] [blame] | 5196 | } |
| 5197 | rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, |
Anatol Pomozov | cdab0d4 | 2015-10-29 15:31:59 -0700 | [diff] [blame] | 5198 | "realtek,reset", GPIOD_OUT_LOW); |
Ben Zhang | efd901e | 2015-06-22 11:12:59 -0700 | [diff] [blame] | 5199 | if (IS_ERR(rt5677->reset_pin)) { |
| 5200 | ret = PTR_ERR(rt5677->reset_pin); |
| 5201 | dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); |
Axel Lin | f8163c8 | 2015-07-25 10:23:40 +0800 | [diff] [blame] | 5202 | return ret; |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 5203 | } |
| 5204 | |
Ben Zhang | efd901e | 2015-06-22 11:12:59 -0700 | [diff] [blame] | 5205 | if (rt5677->pow_ldo2 || rt5677->reset_pin) { |
Anatol Pomozov | f9f6a59 | 2014-09-17 13:14:20 -0700 | [diff] [blame] | 5206 | /* Wait a while until I2C bus becomes available. The datasheet |
| 5207 | * does not specify the exact we should wait but startup |
| 5208 | * sequence mentiones at least a few milliseconds. |
| 5209 | */ |
| 5210 | msleep(10); |
| 5211 | } |
| 5212 | |
Oder Chiou | 19ba484 | 2014-11-05 13:42:53 +0800 | [diff] [blame] | 5213 | rt5677->regmap_physical = devm_regmap_init_i2c(i2c, |
| 5214 | &rt5677_regmap_physical); |
| 5215 | if (IS_ERR(rt5677->regmap_physical)) { |
| 5216 | ret = PTR_ERR(rt5677->regmap_physical); |
| 5217 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 5218 | ret); |
| 5219 | return ret; |
| 5220 | } |
| 5221 | |
| 5222 | rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5223 | if (IS_ERR(rt5677->regmap)) { |
| 5224 | ret = PTR_ERR(rt5677->regmap); |
| 5225 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", |
| 5226 | ret); |
| 5227 | return ret; |
| 5228 | } |
| 5229 | |
| 5230 | regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); |
| 5231 | if (val != RT5677_DEVICE_ID) { |
| 5232 | dev_err(&i2c->dev, |
Jarkko Nikula | aa0bcc5 | 2015-06-25 13:59:01 +0300 | [diff] [blame] | 5233 | "Device with ID register %#x is not rt5677\n", val); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5234 | return -ENODEV; |
| 5235 | } |
| 5236 | |
| 5237 | regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); |
| 5238 | |
| 5239 | ret = regmap_register_patch(rt5677->regmap, init_list, |
| 5240 | ARRAY_SIZE(init_list)); |
| 5241 | if (ret != 0) |
| 5242 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); |
| 5243 | |
| 5244 | if (rt5677->pdata.in1_diff) |
| 5245 | regmap_update_bits(rt5677->regmap, RT5677_IN1, |
| 5246 | RT5677_IN_DF1, RT5677_IN_DF1); |
| 5247 | |
| 5248 | if (rt5677->pdata.in2_diff) |
| 5249 | regmap_update_bits(rt5677->regmap, RT5677_IN1, |
| 5250 | RT5677_IN_DF2, RT5677_IN_DF2); |
| 5251 | |
Anatol Pomozov | 6f67c38 | 2014-09-26 09:57:27 -0700 | [diff] [blame] | 5252 | if (rt5677->pdata.lout1_diff) |
| 5253 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 5254 | RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF); |
| 5255 | |
| 5256 | if (rt5677->pdata.lout2_diff) |
| 5257 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 5258 | RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF); |
| 5259 | |
| 5260 | if (rt5677->pdata.lout3_diff) |
| 5261 | regmap_update_bits(rt5677->regmap, RT5677_LOUT1, |
| 5262 | RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF); |
| 5263 | |
Bard Liao | 2d15d97 | 2014-08-27 19:50:34 +0800 | [diff] [blame] | 5264 | if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { |
| 5265 | regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, |
| 5266 | RT5677_GPIO5_FUNC_MASK, |
| 5267 | RT5677_GPIO5_FUNC_DMIC); |
| 5268 | regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, |
| 5269 | RT5677_GPIO5_DIR_MASK, |
| 5270 | RT5677_GPIO5_DIR_OUT); |
| 5271 | } |
| 5272 | |
Oder Chiou | 277880a | 2015-01-08 10:31:06 +0800 | [diff] [blame] | 5273 | if (rt5677->pdata.micbias1_vdd_3v3) |
| 5274 | regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, |
| 5275 | RT5677_MICBIAS1_CTRL_VDD_MASK, |
| 5276 | RT5677_MICBIAS1_CTRL_VDD_3_3V); |
| 5277 | |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 5278 | rt5677_init_gpio(i2c); |
Oder Chiou | 35d40d1 | 2014-11-19 13:52:19 +0800 | [diff] [blame] | 5279 | rt5677_init_irq(i2c); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 5280 | |
Axel Lin | d0bdcb9 | 2014-06-10 11:37:24 +0800 | [diff] [blame] | 5281 | return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677, |
| 5282 | rt5677_dai, ARRAY_SIZE(rt5677_dai)); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5283 | } |
| 5284 | |
| 5285 | static int rt5677_i2c_remove(struct i2c_client *i2c) |
| 5286 | { |
| 5287 | snd_soc_unregister_codec(&i2c->dev); |
Oder Chiou | 35d40d1 | 2014-11-19 13:52:19 +0800 | [diff] [blame] | 5288 | rt5677_free_irq(i2c); |
Oder Chiou | 44caf76 | 2014-09-16 11:37:39 +0800 | [diff] [blame] | 5289 | rt5677_free_gpio(i2c); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5290 | |
| 5291 | return 0; |
| 5292 | } |
| 5293 | |
| 5294 | static struct i2c_driver rt5677_i2c_driver = { |
| 5295 | .driver = { |
| 5296 | .name = "rt5677", |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5297 | }, |
| 5298 | .probe = rt5677_i2c_probe, |
| 5299 | .remove = rt5677_i2c_remove, |
| 5300 | .id_table = rt5677_i2c_id, |
| 5301 | }; |
Axel Lin | c8cfbec | 2014-06-03 10:56:41 +0800 | [diff] [blame] | 5302 | module_i2c_driver(rt5677_i2c_driver); |
Oder Chiou | 0e826e8 | 2014-05-26 20:32:33 +0800 | [diff] [blame] | 5303 | |
| 5304 | MODULE_DESCRIPTION("ASoC RT5677 driver"); |
| 5305 | MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>"); |
| 5306 | MODULE_LICENSE("GPL v2"); |